1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD$"); 35 36/* 37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 39 */ 40 41#include "opt_ofw_pci.h" 42#include "opt_psycho.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/endian.h> 48#include <sys/kdb.h> 49#include <sys/kernel.h> 50#include <sys/lock.h> 51#include <sys/malloc.h> 52#include <sys/module.h> 53#include <sys/mutex.h> 54#include <sys/pcpu.h> 55#include <sys/reboot.h> 56#include <sys/rman.h> 57#include <sys/sysctl.h> 58 59#include <dev/ofw/ofw_bus.h> 60#include <dev/ofw/ofw_pci.h> 61#include <dev/ofw/openfirm.h> 62 63#include <machine/bus.h> 64#include <machine/bus_common.h> 65#include <machine/bus_private.h> 66#include <machine/iommureg.h> 67#include <machine/iommuvar.h> 68#include <machine/resource.h> 69#include <machine/ver.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sparc64/pci/ofw_pci.h> 75#include <sparc64/pci/psychoreg.h> 76#include <sparc64/pci/psychovar.h> 77 78#include "pcib_if.h" 79 80static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 81 const char *); 82static const struct psycho_desc *psycho_get_desc(device_t); 83static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t, 84 driver_filter_t, driver_intr_t); 85static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *, 86 bus_addr_t *, u_long *); 87static void sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 88 bus_dmasync_op_t op); 89static void psycho_intr_enable(void *); 90static void psycho_intr_disable(void *); 91static void psycho_intr_assign(void *); 92static void psycho_intr_clear(void *); 93 94/* Interrupt handlers */ 95static driver_filter_t psycho_ue; 96static driver_filter_t psycho_ce; 97static driver_filter_t psycho_pci_bus; 98static driver_filter_t psycho_powerdebug; 99static driver_intr_t psycho_powerdown; 100static driver_intr_t psycho_overtemp; 101#ifdef PSYCHO_MAP_WAKEUP 102static driver_filter_t psycho_wakeup; 103#endif 104 105/* IOMMU support */ 106static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 107 108/* 109 * Methods 110 */ 111static device_probe_t psycho_probe; 112static device_attach_t psycho_attach; 113static bus_read_ivar_t psycho_read_ivar; 114static bus_setup_intr_t psycho_setup_intr; 115static bus_alloc_resource_t psycho_alloc_resource; 116static bus_activate_resource_t psycho_activate_resource; 117static bus_adjust_resource_t psycho_adjust_resource; 118static bus_get_dma_tag_t psycho_get_dma_tag; 119static pcib_maxslots_t psycho_maxslots; 120static pcib_read_config_t psycho_read_config; 121static pcib_write_config_t psycho_write_config; 122static pcib_route_interrupt_t psycho_route_interrupt; 123static ofw_bus_get_node_t psycho_get_node; 124static ofw_pci_setup_device_t psycho_setup_device; 125 126static device_method_t psycho_methods[] = { 127 /* Device interface */ 128 DEVMETHOD(device_probe, psycho_probe), 129 DEVMETHOD(device_attach, psycho_attach), 130 DEVMETHOD(device_shutdown, bus_generic_shutdown), 131 DEVMETHOD(device_suspend, bus_generic_suspend), 132 DEVMETHOD(device_resume, bus_generic_resume), 133 134 /* Bus interface */ 135 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 136 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 137 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 138 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 139 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 140 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 141 DEVMETHOD(bus_adjust_resource, psycho_adjust_resource), 142 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 143 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag), 144 145 /* pcib interface */ 146 DEVMETHOD(pcib_maxslots, psycho_maxslots), 147 DEVMETHOD(pcib_read_config, psycho_read_config), 148 DEVMETHOD(pcib_write_config, psycho_write_config), 149 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 150 151 /* ofw_bus interface */ 152 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 153 154 /* ofw_pci interface */ 155 DEVMETHOD(ofw_pci_setup_device, psycho_setup_device), 156 157 DEVMETHOD_END 158}; 159 160static devclass_t psycho_devclass; 161 162DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods, 163 sizeof(struct psycho_softc)); 164EARLY_DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, NULL, NULL, 165 BUS_PASS_BUS); 166 167static SYSCTL_NODE(_hw, OID_AUTO, psycho, CTLFLAG_RD, 0, "psycho parameters"); 168 169static u_int psycho_powerfail = 1; 170TUNABLE_INT("hw.psycho.powerfail", &psycho_powerfail); 171SYSCTL_UINT(_hw_psycho, OID_AUTO, powerfail, CTLFLAG_RDTUN, &psycho_powerfail, 172 0, "powerfail action (0: none, 1: shutdown (default), 2: debugger)"); 173 174static SLIST_HEAD(, psycho_softc) psycho_softcs = 175 SLIST_HEAD_INITIALIZER(psycho_softcs); 176 177static const struct intr_controller psycho_ic = { 178 psycho_intr_enable, 179 psycho_intr_disable, 180 psycho_intr_assign, 181 psycho_intr_clear 182}; 183 184struct psycho_icarg { 185 struct psycho_softc *pica_sc; 186 bus_addr_t pica_map; 187 bus_addr_t pica_clr; 188}; 189 190#define PSYCHO_READ8(sc, off) \ 191 bus_read_8((sc)->sc_mem_res, (off)) 192#define PSYCHO_WRITE8(sc, off, v) \ 193 bus_write_8((sc)->sc_mem_res, (off), (v)) 194#define PCICTL_READ8(sc, off) \ 195 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 196#define PCICTL_WRITE8(sc, off, v) \ 197 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 198 199/* 200 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 201 * single PCI bus and does not have a streaming buffer. It often has an APB 202 * (advanced PCI bridge) connected to it, which was designed specifically for 203 * the IIi. The APB lets the IIi handle two independent PCI buses, and 204 * appears as two "Simba"'s underneath the Sabre. 205 * 206 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 207 * basically the same as Sabre but without an APB underneath it. 208 * 209 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA 210 * bus and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 211 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 212 * will usually find a "Psycho+" since I don't think the original "Psycho" 213 * ever shipped, and if it did it would be in the U30. 214 * 215 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 216 * both part of the same IC, they only have a single register space. As such, 217 * they need to be configured together, even though the autoconfiguration will 218 * attach them separately. 219 * 220 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 221 * as pci1 and pci2, although they have been implemented with other PCI bus 222 * numbers on some machines. 223 * 224 * On UltraII machines, there can be any number of "Psycho+" ICs, each 225 * providing two PCI buses. 226 */ 227 228struct psycho_desc { 229 const char *pd_string; 230 int pd_mode; 231 const char *pd_name; 232}; 233 234static const struct psycho_desc psycho_compats[] = { 235 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 236 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 237 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 238 { NULL, 0, NULL } 239}; 240 241static const struct psycho_desc psycho_models[] = { 242 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 243 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 244 { NULL, 0, NULL } 245}; 246 247static const struct psycho_desc * 248psycho_find_desc(const struct psycho_desc *table, const char *string) 249{ 250 const struct psycho_desc *desc; 251 252 if (string == NULL) 253 return (NULL); 254 for (desc = table; desc->pd_string != NULL; desc++) 255 if (strcmp(desc->pd_string, string) == 0) 256 return (desc); 257 return (NULL); 258} 259 260static const struct psycho_desc * 261psycho_get_desc(device_t dev) 262{ 263 const struct psycho_desc *rv; 264 265 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev)); 266 if (rv == NULL) 267 rv = psycho_find_desc(psycho_compats, 268 ofw_bus_get_compat(dev)); 269 return (rv); 270} 271 272static int 273psycho_probe(device_t dev) 274{ 275 const char *dtype; 276 277 dtype = ofw_bus_get_type(dev); 278 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 279 psycho_get_desc(dev) != NULL) { 280 device_set_desc(dev, "U2P UPA-PCI bridge"); 281 return (0); 282 } 283 return (ENXIO); 284} 285 286static int 287psycho_attach(device_t dev) 288{ 289 struct psycho_icarg *pica; 290 struct psycho_softc *asc, *sc, *osc; 291 struct ofw_pci_ranges *range; 292 const struct psycho_desc *desc; 293 bus_addr_t intrclr, intrmap; 294 uint64_t csr, dr; 295 phandle_t node; 296 uint32_t dvmabase, prop, prop_array[2]; 297 u_int rerun, ver; 298 int i, j; 299 300 node = ofw_bus_get_node(dev); 301 sc = device_get_softc(dev); 302 desc = psycho_get_desc(dev); 303 304 sc->sc_node = node; 305 sc->sc_dev = dev; 306 sc->sc_mode = desc->pd_mode; 307 308 /* 309 * The Psycho gets three register banks: 310 * (0) per-PBM configuration and status registers 311 * (1) per-PBM PCI configuration space, containing only the 312 * PBM 256-byte PCI header 313 * (2) the shared Psycho configuration registers 314 */ 315 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 316 i = 2; 317 sc->sc_pcictl = 318 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) - 319 bus_get_resource_start(dev, SYS_RES_MEMORY, 2); 320 switch (sc->sc_pcictl) { 321 case PSR_PCICTL0: 322 sc->sc_half = 0; 323 break; 324 case PSR_PCICTL1: 325 sc->sc_half = 1; 326 break; 327 default: 328 panic("%s: bogus PCI control register location", 329 __func__); 330 /* NOTREACHED */ 331 } 332 } else { 333 i = 0; 334 sc->sc_pcictl = PSR_PCICTL0; 335 sc->sc_half = 0; 336 } 337 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, 338 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) | 339 RF_ACTIVE); 340 if (sc->sc_mem_res == NULL) 341 panic("%s: could not allocate registers", __func__); 342 343 /* 344 * Match other Psychos that are already configured against 345 * the base physical address. This will be the same for a 346 * pair of devices that share register space. 347 */ 348 osc = NULL; 349 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 350 if (rman_get_start(asc->sc_mem_res) == 351 rman_get_start(sc->sc_mem_res)) { 352 /* Found partner. */ 353 osc = asc; 354 break; 355 } 356 } 357 if (osc == NULL) { 358 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 359 M_NOWAIT | M_ZERO); 360 if (sc->sc_mtx == NULL) 361 panic("%s: could not malloc mutex", __func__); 362 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 363 } else { 364 if (sc->sc_mode != PSYCHO_MODE_PSYCHO) 365 panic("%s: no partner expected", __func__); 366 if (mtx_initialized(osc->sc_mtx) == 0) 367 panic("%s: mutex not initialized", __func__); 368 sc->sc_mtx = osc->sc_mtx; 369 } 370 371 csr = PSYCHO_READ8(sc, PSR_CS); 372 ver = PSYCHO_GCSR_VERS(csr); 373 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */ 374 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 375 sc->sc_ign = PSYCHO_GCSR_IGN(csr); 376 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 377 prop = 33000000; 378 379 device_printf(dev, 380 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n", 381 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, 382 'A' + sc->sc_half, prop / 1000 / 1000); 383 384 /* Set up the PCI control and PCI diagnostic registers. */ 385 386 csr = PCICTL_READ8(sc, PCR_CS); 387 csr &= ~PCICTL_ARB_PARK; 388 if (OF_getproplen(node, "no-bus-parking") < 0) 389 csr |= PCICTL_ARB_PARK; 390 391 /* Workarounds for version specific bugs. */ 392 dr = PCICTL_READ8(sc, PCR_DIAG); 393 switch (ver) { 394 case 0: 395 dr |= DIAG_RTRY_DIS; 396 dr &= ~DIAG_DWSYNC_DIS; 397 rerun = 0; 398 break; 399 case 1: 400 csr &= ~PCICTL_ARB_PARK; 401 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS; 402 rerun = 0; 403 break; 404 default: 405 dr |= DIAG_DWSYNC_DIS; 406 dr &= ~DIAG_RTRY_DIS; 407 rerun = 1; 408 break; 409 } 410 411 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4; 412 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); 413#ifdef PSYCHO_DEBUG 414 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 415 (unsigned long long)PCICTL_READ8(sc, PCR_CS), 416 (unsigned long long)csr); 417#endif 418 PCICTL_WRITE8(sc, PCR_CS, csr); 419 420 dr &= ~DIAG_ISYNC_DIS; 421#ifdef PSYCHO_DEBUG 422 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 423 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG), 424 (unsigned long long)dr); 425#endif 426 PCICTL_WRITE8(sc, PCR_DIAG, dr); 427 428 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 429 /* Use the PROM preset for now. */ 430 csr = PCICTL_READ8(sc, PCR_TAS); 431 if (csr == 0) 432 panic("%s: Hummingbird/Sabre TAS not initialized.", 433 __func__); 434 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 435 } else 436 dvmabase = -1; 437 438 /* Initialize memory and I/O rmans. */ 439 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 440 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 441 if (rman_init(&sc->sc_pci_io_rman) != 0 || 442 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 443 panic("%s: failed to set up I/O rman", __func__); 444 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 445 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 446 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 447 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 448 panic("%s: failed to set up memory rman", __func__); 449 450 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 451 /* 452 * Make sure that the expected ranges are present. The 453 * OFW_PCI_CS_MEM64 one is not currently used though. 454 */ 455 if (i != PSYCHO_NRANGE) 456 panic("%s: unsupported number of ranges", __func__); 457 /* 458 * Find the addresses of the various bus spaces. 459 * There should not be multiple ones of one kind. 460 * The physical start addresses of the ranges are the configuration, 461 * memory and I/O handles. 462 */ 463 for (i = 0; i < PSYCHO_NRANGE; i++) { 464 j = OFW_PCI_RANGE_CS(&range[i]); 465 if (sc->sc_pci_bh[j] != 0) 466 panic("%s: duplicate range for space %d", 467 __func__, j); 468 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 469 } 470 free(range, M_OFWPROP); 471 472 /* Register the softc, this is needed for paired Psychos. */ 473 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 474 475 /* 476 * If we're a Hummingbird/Sabre or the first of a pair of Psychos 477 * to arrive here, do the interrupt setup and start up the IOMMU. 478 */ 479 if (osc == NULL) { 480 /* 481 * Hunt through all the interrupt mapping regs and register 482 * our interrupt controller for the corresponding interrupt 483 * vectors. We do this early in order to be able to catch 484 * stray interrupts. 485 */ 486 for (i = 0; i <= PSYCHO_MAX_INO; i++) { 487 if (psycho_find_intrmap(sc, i, &intrmap, &intrclr, 488 NULL) == 0) 489 continue; 490 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT); 491 if (pica == NULL) 492 panic("%s: could not allocate interrupt " 493 "controller argument", __func__); 494 pica->pica_sc = sc; 495 pica->pica_map = intrmap; 496 pica->pica_clr = intrclr; 497#ifdef PSYCHO_DEBUG 498 /* 499 * Enable all interrupts and clear all interrupt 500 * states. This aids the debugging of interrupt 501 * routing problems. 502 */ 503 device_printf(dev, 504 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n", 505 i, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO", 506 (u_long)intrmap, (u_long)PSYCHO_READ8(sc, 507 intrmap), (u_long)intrclr); 508 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, i)); 509 PSYCHO_WRITE8(sc, intrclr, INTCLR_IDLE); 510 PSYCHO_WRITE8(sc, intrmap, 511 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, i), 512 PCPU_GET(mid))); 513#endif 514 j = intr_controller_register(INTMAP_VEC(sc->sc_ign, 515 i), &psycho_ic, pica); 516 if (j != 0) 517 device_printf(dev, "could not register " 518 "interrupt controller for INO %d (%d)\n", 519 i, j); 520 } 521 522 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 523 sparc64_counter_init(device_get_nameunit(dev), 524 rman_get_bustag(sc->sc_mem_res), 525 rman_get_bushandle(sc->sc_mem_res), PSR_TC0); 526 527 /* 528 * Set up IOMMU and PCI configuration if we're the first 529 * of a pair of Psychos to arrive here or a Hummingbird 530 * or Sabre. 531 * 532 * We should calculate a TSB size based on amount of RAM 533 * and number of bus controllers and number and type of 534 * child devices. 535 * 536 * For the moment, 32KB should be more than enough. 537 */ 538 sc->sc_is = malloc(sizeof(*sc->sc_is), M_DEVBUF, M_NOWAIT | 539 M_ZERO); 540 if (sc->sc_is == NULL) 541 panic("%s: could not malloc IOMMU state", __func__); 542 sc->sc_is->is_flags = IOMMU_PRESERVE_PROM; 543 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 544 sc->sc_dma_methods = 545 malloc(sizeof(*sc->sc_dma_methods), M_DEVBUF, 546 M_NOWAIT); 547 if (sc->sc_dma_methods == NULL) 548 panic("%s: could not malloc DMA methods", 549 __func__); 550 memcpy(sc->sc_dma_methods, &iommu_dma_methods, 551 sizeof(*sc->sc_dma_methods)); 552 sc->sc_dma_methods->dm_dmamap_sync = 553 sabre_dmamap_sync; 554 sc->sc_is->is_pmaxaddr = 555 IOMMU_MAXADDR(SABRE_IOMMU_BITS); 556 } else { 557 sc->sc_dma_methods = &iommu_dma_methods; 558 sc->sc_is->is_pmaxaddr = 559 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS); 560 } 561 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0; 562 if (OF_getproplen(node, "no-streaming-cache") < 0) 563 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 564 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0; 565 psycho_iommu_init(sc, 3, dvmabase); 566 } else { 567 /* Just copy IOMMU state, config tag and address. */ 568 sc->sc_dma_methods = &iommu_dma_methods; 569 sc->sc_is = osc->sc_is; 570 if (OF_getproplen(node, "no-streaming-cache") < 0) 571 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 572 iommu_reset(sc->sc_is); 573 } 574 575 /* Allocate our tags. */ 576 sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, rman_get_bustag( 577 sc->sc_mem_res), PCI_IO_BUS_SPACE, NULL); 578 if (sc->sc_pci_iot == NULL) 579 panic("%s: could not allocate PCI I/O tag", __func__); 580 sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, rman_get_bustag( 581 sc->sc_mem_res), PCI_CONFIG_BUS_SPACE, NULL); 582 if (sc->sc_pci_cfgt == NULL) 583 panic("%s: could not allocate PCI configuration space tag", 584 __func__); 585 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 586 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr, 587 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 588 panic("%s: could not create PCI DMA tag", __func__); 589 /* Customize the tag. */ 590 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 591 sc->sc_pci_dmat->dt_mt = sc->sc_dma_methods; 592 593 i = OF_getprop(node, "bus-range", (void *)prop_array, 594 sizeof(prop_array)); 595 if (i == -1) 596 panic("%s: could not get bus-range", __func__); 597 if (i != sizeof(prop_array)) 598 panic("%s: broken bus-range (%d)", __func__, i); 599 sc->sc_pci_secbus = prop_array[0]; 600 sc->sc_pci_subbus = prop_array[1]; 601 if (bootverbose) 602 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 603 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 604 605 /* Clear any pending PCI error bits. */ 606 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 607 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 608 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2); 609 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS)); 610 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS)); 611 612 if (osc == NULL) { 613 /* 614 * Establish handlers for interesting interrupts... 615 * 616 * XXX We need to remember these and remove this to support 617 * hotplug on the UPA/FHC bus. 618 * 619 * XXX Not all controllers have these, but installing them 620 * is better than trying to sort through this mess. 621 */ 622 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); 623 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); 624 switch (psycho_powerfail) { 625 case 0: 626 break; 627 case 2: 628 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, 629 psycho_powerdebug, NULL); 630 break; 631 default: 632 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, 633 psycho_powerdown); 634 break; 635 } 636 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 637 /* 638 * Hummingbirds/Sabres do not have the following two 639 * interrupts. 640 */ 641 642 /* 643 * The spare hardware interrupt is used for the 644 * over-temperature interrupt. 645 */ 646 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, NULL, 647 psycho_overtemp); 648#ifdef PSYCHO_MAP_WAKEUP 649 /* 650 * psycho_wakeup() doesn't do anything useful right 651 * now. 652 */ 653 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, 654 psycho_wakeup, NULL); 655#endif /* PSYCHO_MAP_WAKEUP */ 656 } 657 } 658 /* 659 * Register a PCI bus error interrupt handler according to which 660 * half this is. Hummingbird/Sabre don't have a PCI bus B error 661 * interrupt but they are also only used for PCI bus A. 662 */ 663 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 664 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); 665 666 /* 667 * Set the latency timer register as this isn't always done by the 668 * firmware. 669 */ 670 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 671 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 672 673 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t)) 674 le16enc(&sc->sc_pci_hpbcfg[i], bus_space_read_2( 675 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG], 676 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE, 677 PCS_FUNC, i))); 678 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t)) 679 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_pci_cfgt, 680 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF( 681 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i)); 682 683 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 684 /* 685 * On E250 the interrupt map entry for the EBus bridge is wrong, 686 * causing incorrect interrupts to be assigned to some devices on 687 * the EBus. Work around it by changing our copy of the interrupt 688 * map mask to perform a full comparison of the INO. That way 689 * the interrupt map entry for the EBus bridge won't match at all 690 * and the INOs specified in the "interrupts" properties of the 691 * EBus devices will be used directly instead. 692 */ 693 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 694 sc->sc_pci_iinfo.opi_imapmsk != NULL) 695 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 696 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 697 698 device_add_child(dev, "pci", -1); 699 return (bus_generic_attach(dev)); 700} 701 702static void 703psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap, 704 driver_filter_t filt, driver_intr_t intr) 705{ 706 u_long vec; 707 int rid; 708 709 rid = index; 710 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 711 SYS_RES_IRQ, &rid, RF_ACTIVE); 712 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) { 713 /* 714 * These interrupts aren't mandatory and not available 715 * with all controllers (not even Psychos). 716 */ 717 return; 718 } 719 if (sc->sc_irq_res[index] == NULL || 720 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != 721 sc->sc_ign || 722 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec || 723 intr_vectors[vec].iv_ic != &psycho_ic || 724 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 725 INTR_TYPE_MISC | INTR_BRIDGE, filt, intr, sc, 726 &sc->sc_ihand[index]) != 0) 727 panic("%s: failed to set up interrupt %d", __func__, index); 728} 729 730static int 731psycho_find_intrmap(struct psycho_softc *sc, u_int ino, 732 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 733{ 734 bus_addr_t intrclr, intrmap; 735 uint64_t diag; 736 int found; 737 738 /* 739 * XXX we only compare INOs rather than INRs since the firmware may 740 * not provide the IGN and the IGN is constant for all devices on 741 * that PCI controller. 742 * This could cause problems for the FFB/external interrupt which 743 * has a full vector that can be set arbitrarily. 744 */ 745 746 if (ino > PSYCHO_MAX_INO) { 747 device_printf(sc->sc_dev, "out of range INO %d requested\n", 748 ino); 749 return (0); 750 } 751 752 found = 0; 753 /* Hunt through OBIO first. */ 754 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 755 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 756 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8, 757 diag >>= 2) { 758 if (sc->sc_mode == PSYCHO_MODE_SABRE && 759 (intrmap == PSR_TIMER0_INT_MAP || 760 intrmap == PSR_TIMER1_INT_MAP || 761 intrmap == PSR_PCIBERR_INT_MAP || 762 intrmap == PSR_PWRMGT_INT_MAP)) 763 continue; 764 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) { 765 diag &= 2; 766 found = 1; 767 break; 768 } 769 } 770 771 if (!found) { 772 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 773 /* Now do PCI interrupts. */ 774 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 775 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 776 diag >>= 8) { 777 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 778 (intrmap == PSR_PCIA2_INT_MAP || 779 intrmap == PSR_PCIA3_INT_MAP)) 780 continue; 781 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) { 782 intrclr += 8 * (ino & 3); 783 diag = (diag >> ((ino & 3) * 2)) & 2; 784 found = 1; 785 break; 786 } 787 } 788 } 789 if (intrmapptr != NULL) 790 *intrmapptr = intrmap; 791 if (intrclrptr != NULL) 792 *intrclrptr = intrclr; 793 if (intrdiagptr != NULL) 794 *intrdiagptr = diag; 795 return (found); 796} 797 798/* 799 * Interrupt handlers 800 */ 801static int 802psycho_ue(void *arg) 803{ 804 struct psycho_softc *sc = arg; 805 uint64_t afar, afsr; 806 807 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 808 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 809 /* 810 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 811 * the AFAR to be set to the physical address of the TTE entry that 812 * was invalid/write protected. Call into the IOMMU code to have 813 * them decoded to virtual I/O addresses. 814 */ 815 if ((afsr & UEAFSR_P_DTE) != 0) 816 iommu_decode_fault(sc->sc_is, afar); 817 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 818 device_get_nameunit(sc->sc_dev), (u_long)afar, (u_long)afsr); 819 return (FILTER_HANDLED); 820} 821 822static int 823psycho_ce(void *arg) 824{ 825 struct psycho_softc *sc = arg; 826 uint64_t afar, afsr; 827 828 mtx_lock_spin(sc->sc_mtx); 829 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 830 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 831 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 832 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 833 /* Clear the error bits that we caught. */ 834 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr); 835 mtx_unlock_spin(sc->sc_mtx); 836 return (FILTER_HANDLED); 837} 838 839static int 840psycho_pci_bus(void *arg) 841{ 842 struct psycho_softc *sc = arg; 843 uint64_t afar, afsr; 844 845 afar = PCICTL_READ8(sc, PCR_AFA); 846 afsr = PCICTL_READ8(sc, PCR_AFS); 847 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 848 device_get_nameunit(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 849 (u_long)afsr); 850 return (FILTER_HANDLED); 851} 852 853static int 854psycho_powerdebug(void *arg __unused) 855{ 856 857 kdb_enter(KDB_WHY_POWERFAIL, "powerfail"); 858 return (FILTER_HANDLED); 859} 860 861static void 862psycho_powerdown(void *arg __unused) 863{ 864 static int shutdown; 865 866 /* As the interrupt is cleared we may be called multiple times. */ 867 if (shutdown != 0) 868 return; 869 shutdown++; 870 printf("Power Failure Detected: Shutting down NOW.\n"); 871 shutdown_nice(RB_POWEROFF); 872} 873 874static void 875psycho_overtemp(void *arg __unused) 876{ 877 static int shutdown; 878 879 /* As the interrupt is cleared we may be called multiple times. */ 880 if (shutdown != 0) 881 return; 882 shutdown++; 883 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 884 shutdown_nice(RB_POWEROFF); 885} 886 887#ifdef PSYCHO_MAP_WAKEUP 888static int 889psycho_wakeup(void *arg) 890{ 891 struct psycho_softc *sc = arg; 892 893 /* We don't really have a framework to deal with this properly. */ 894 device_printf(sc->sc_dev, "power management wakeup\n"); 895 return (FILTER_HANDLED); 896} 897#endif /* PSYCHO_MAP_WAKEUP */ 898 899static void 900psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 901{ 902 struct iommu_state *is = sc->sc_is; 903 904 /* Punch in our copies. */ 905 is->is_bustag = rman_get_bustag(sc->sc_mem_res); 906 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res); 907 is->is_iommu = PSR_IOMMU; 908 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 909 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 910 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 911 is->is_dva = PSR_IOMMU_SVADIAG; 912 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 913 914 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0); 915} 916 917static int 918psycho_maxslots(device_t dev) 919{ 920 921 /* XXX: is this correct? */ 922 return (PCI_SLOTMAX); 923} 924 925static uint32_t 926psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 927 int width) 928{ 929 struct psycho_softc *sc; 930 bus_space_handle_t bh; 931 u_long offset = 0; 932 uint8_t byte; 933 uint16_t shrt; 934 uint32_t r, wrd; 935 int i; 936 937 sc = device_get_softc(dev); 938 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 939 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 940 return (-1); 941 942 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 943 944 /* 945 * The Hummingbird and Sabre bridges are picky in that they 946 * only allow their config space to be accessed using the 947 * "native" width of the respective register being accessed 948 * and return semi-random other content of their config space 949 * otherwise. Given that the PCI specs don't say anything 950 * about such a (unusual) limitation and lots of stuff expects 951 * to be able to access the contents of the config space at 952 * any width we allow just that. We do this by using a copy 953 * of the header of the bridge (the rest is all zero anyway) 954 * read during attach (expect for PCIR_STATUS) in order to 955 * simplify things. 956 * The Psycho bridges contain a dupe of their header at 0x80 957 * which we nullify that way also. 958 */ 959 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE && 960 func == PCS_FUNC) { 961 if (offset % width != 0) 962 return (-1); 963 964 if (reg >= sizeof(sc->sc_pci_hpbcfg)) 965 return (0); 966 967 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) || 968 reg == PCIR_STATUS || reg == PCIR_STATUS + 1) 969 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS], 970 bus_space_read_2(sc->sc_pci_cfgt, bh, 971 PSYCHO_CONF_OFF(sc->sc_pci_secbus, 972 PCS_DEVICE, PCS_FUNC, PCIR_STATUS))); 973 974 switch (width) { 975 case 1: 976 return (sc->sc_pci_hpbcfg[reg]); 977 case 2: 978 return (le16dec(&sc->sc_pci_hpbcfg[reg])); 979 case 4: 980 return (le32dec(&sc->sc_pci_hpbcfg[reg])); 981 } 982 } 983 984 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 985 switch (width) { 986 case 1: 987 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 988 r = byte; 989 break; 990 case 2: 991 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 992 r = shrt; 993 break; 994 case 4: 995 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 996 r = wrd; 997 break; 998 default: 999 panic("%s: bad width", __func__); 1000 /* NOTREACHED */ 1001 } 1002 1003 if (i) { 1004#ifdef PSYCHO_DEBUG 1005 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 1006 __func__, bus, slot, func, reg); 1007#endif 1008 r = -1; 1009 } 1010 return (r); 1011} 1012 1013static void 1014psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1015 u_int reg, uint32_t val, int width) 1016{ 1017 struct psycho_softc *sc; 1018 bus_space_handle_t bh; 1019 u_long offset = 0; 1020 1021 sc = device_get_softc(dev); 1022 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1023 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1024 return; 1025 1026 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 1027 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1028 switch (width) { 1029 case 1: 1030 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1031 break; 1032 case 2: 1033 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1034 break; 1035 case 4: 1036 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1037 break; 1038 default: 1039 panic("%s: bad width", __func__); 1040 /* NOTREACHED */ 1041 } 1042} 1043 1044static int 1045psycho_route_interrupt(device_t bridge, device_t dev, int pin) 1046{ 1047 struct psycho_softc *sc; 1048 struct ofw_pci_register reg; 1049 bus_addr_t intrmap; 1050 ofw_pci_intr_t pintr, mintr; 1051 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1052 1053 sc = device_get_softc(bridge); 1054 pintr = pin; 1055 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1056 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1057 NULL, maskbuf)) 1058 return (mintr); 1059 /* 1060 * If this is outside of the range for an intpin, it's likely a full 1061 * INO, and no mapping is required at all; this happens on the U30, 1062 * where there's no interrupt map at the Psycho node. Fortunately, 1063 * there seem to be no INOs in the intpin range on this boxen, so 1064 * this easy heuristics will do. 1065 */ 1066 if (pin > 4) 1067 return (pin); 1068 /* 1069 * Guess the INO; we always assume that this is a non-OBIO 1070 * device, and that pin is a "real" intpin number. Determine 1071 * the mapping register to be used by the slot number. 1072 * We only need to do this on E450s, it seems; here, the slot numbers 1073 * for bus A are one-based, while those for bus B seemingly have an 1074 * offset of 2 (hence the factor of 3 below). 1075 */ 1076 intrmap = PSR_PCIA0_INT_MAP + 1077 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 1078 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 1079 device_printf(bridge, 1080 "guessing interrupt %d for device %d.%d pin %d\n", 1081 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 1082 return (mintr); 1083} 1084 1085static int 1086psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1087{ 1088 struct psycho_softc *sc; 1089 1090 sc = device_get_softc(dev); 1091 switch (which) { 1092 case PCIB_IVAR_DOMAIN: 1093 *result = device_get_unit(dev); 1094 return (0); 1095 case PCIB_IVAR_BUS: 1096 *result = sc->sc_pci_secbus; 1097 return (0); 1098 } 1099 return (ENOENT); 1100} 1101 1102static void 1103sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1104{ 1105 struct iommu_state *is = dt->dt_cookie; 1106 1107 if ((map->dm_flags & DMF_LOADED) == 0) 1108 return; 1109 1110 if ((op & BUS_DMASYNC_POSTREAD) != 0) 1111 (void)bus_space_read_8(is->is_bustag, is->is_bushandle, 1112 PSR_DMA_WRITE_SYNC); 1113 1114 if ((op & BUS_DMASYNC_PREWRITE) != 0) 1115 membar(Sync); 1116} 1117 1118static void 1119psycho_intr_enable(void *arg) 1120{ 1121 struct intr_vector *iv = arg; 1122 struct psycho_icarg *pica = iv->iv_icarg; 1123 1124 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, 1125 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1126} 1127 1128static void 1129psycho_intr_disable(void *arg) 1130{ 1131 struct intr_vector *iv = arg; 1132 struct psycho_icarg *pica = iv->iv_icarg; 1133 1134 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec); 1135} 1136 1137static void 1138psycho_intr_assign(void *arg) 1139{ 1140 struct intr_vector *iv = arg; 1141 struct psycho_icarg *pica = iv->iv_icarg; 1142 1143 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID( 1144 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid)); 1145} 1146 1147static void 1148psycho_intr_clear(void *arg) 1149{ 1150 struct intr_vector *iv = arg; 1151 struct psycho_icarg *pica = iv->iv_icarg; 1152 1153 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, INTCLR_IDLE); 1154} 1155 1156static int 1157psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 1158 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1159 void **cookiep) 1160{ 1161 struct psycho_softc *sc; 1162 u_long vec; 1163 1164 sc = device_get_softc(dev); 1165 /* 1166 * Make sure the vector is fully specified and we registered 1167 * our interrupt controller for it. 1168 */ 1169 vec = rman_get_start(ires); 1170 if (INTIGN(vec) != sc->sc_ign || 1171 intr_vectors[vec].iv_ic != &psycho_ic) { 1172 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1173 return (EINVAL); 1174 } 1175 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1176 arg, cookiep)); 1177} 1178 1179static struct resource * 1180psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1181 u_long start, u_long end, u_long count, u_int flags) 1182{ 1183 struct psycho_softc *sc; 1184 struct resource *rv; 1185 struct rman *rm; 1186 1187 sc = device_get_softc(bus); 1188 switch (type) { 1189 case SYS_RES_IRQ: 1190 /* 1191 * XXX: Don't accept blank ranges for now, only single 1192 * interrupts. The other case should not happen with 1193 * the MI PCI code... 1194 * XXX: This may return a resource that is out of the 1195 * range that was specified. Is this correct...? 1196 */ 1197 if (start != end) 1198 panic("%s: XXX: interrupt range", __func__); 1199 start = end = INTMAP_VEC(sc->sc_ign, end); 1200 return (bus_generic_alloc_resource(bus, child, type, rid, 1201 start, end, count, flags)); 1202 case SYS_RES_MEMORY: 1203 rm = &sc->sc_pci_mem_rman; 1204 break; 1205 case SYS_RES_IOPORT: 1206 rm = &sc->sc_pci_io_rman; 1207 break; 1208 default: 1209 return (NULL); 1210 } 1211 1212 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 1213 child); 1214 if (rv == NULL) 1215 return (NULL); 1216 rman_set_rid(rv, *rid); 1217 1218 if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type, 1219 *rid, rv) != 0) { 1220 rman_release_resource(rv); 1221 return (NULL); 1222 } 1223 return (rv); 1224} 1225 1226static int 1227psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1228 struct resource *r) 1229{ 1230 struct psycho_softc *sc; 1231 struct bus_space_tag *tag; 1232 1233 sc = device_get_softc(bus); 1234 switch (type) { 1235 case SYS_RES_IRQ: 1236 return (bus_generic_activate_resource(bus, child, type, rid, 1237 r)); 1238 case SYS_RES_MEMORY: 1239 tag = sparc64_alloc_bus_tag(r, rman_get_bustag( 1240 sc->sc_mem_res), PCI_MEMORY_BUS_SPACE, NULL); 1241 if (tag == NULL) 1242 return (ENOMEM); 1243 rman_set_bustag(r, tag); 1244 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] + 1245 rman_get_start(r)); 1246 break; 1247 case SYS_RES_IOPORT: 1248 rman_set_bustag(r, sc->sc_pci_iot); 1249 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] + 1250 rman_get_start(r)); 1251 break; 1252 } 1253 return (rman_activate_resource(r)); 1254} 1255 1256static int 1257psycho_adjust_resource(device_t bus, device_t child, int type, 1258 struct resource *r, u_long start, u_long end) 1259{ 1260 struct psycho_softc *sc; 1261 struct rman *rm; 1262 1263 sc = device_get_softc(bus); 1264 switch (type) { 1265 case SYS_RES_IRQ: 1266 return (bus_generic_adjust_resource(bus, child, type, r, 1267 start, end)); 1268 case SYS_RES_MEMORY: 1269 rm = &sc->sc_pci_mem_rman; 1270 break; 1271 case SYS_RES_IOPORT: 1272 rm = &sc->sc_pci_io_rman; 1273 break; 1274 default: 1275 return (EINVAL); 1276 } 1277 if (rman_is_region_manager(r, rm) == 0) 1278 return (EINVAL); 1279 return (rman_adjust_resource(r, start, end)); 1280} 1281 1282static bus_dma_tag_t 1283psycho_get_dma_tag(device_t bus, device_t child __unused) 1284{ 1285 struct psycho_softc *sc; 1286 1287 sc = device_get_softc(bus); 1288 return (sc->sc_pci_dmat); 1289} 1290 1291static phandle_t 1292psycho_get_node(device_t bus, device_t child __unused) 1293{ 1294 struct psycho_softc *sc; 1295 1296 sc = device_get_softc(bus); 1297 /* We only have one child, the PCI bus, which needs our own node. */ 1298 return (sc->sc_node); 1299} 1300 1301static void 1302psycho_setup_device(device_t bus, device_t child) 1303{ 1304 struct psycho_softc *sc; 1305 uint32_t rev; 1306 1307 sc = device_get_softc(bus); 1308 /* 1309 * Revision 0 EBus bridges have a bug which prevents them from 1310 * working when bus parking is enabled. 1311 */ 1312 if ((strcmp(ofw_bus_get_name(child), "ebus") == 0 || 1313 strcmp(ofw_bus_get_name(child), "pci108e,1000") == 0) && 1314 OF_getprop(ofw_bus_get_node(child), "revision-id", &rev, 1315 sizeof(rev)) > 0 && rev == 0) 1316 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS) & 1317 ~PCICTL_ARB_PARK); 1318} 1319