mmu_oea64.c revision 248508
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#include <sys/cdefs.h> 94__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea64.c 248508 2013-03-19 14:13:12Z kib $"); 95 96/* 97 * Manages physical address maps. 98 * 99 * Since the information managed by this module is also stored by the 100 * logical address mapping module, this module may throw away valid virtual 101 * to physical mappings at almost any time. However, invalidations of 102 * mappings must be done as requested. 103 * 104 * In order to cope with hardware architectures which make virtual to 105 * physical map invalidates expensive, this module may delay invalidate 106 * reduced protection operations until such time as they are actually 107 * necessary. This module is given full information as to which processors 108 * are currently using which maps, and to when physical maps must be made 109 * correct. 110 */ 111 112#include "opt_compat.h" 113#include "opt_kstack_pages.h" 114 115#include <sys/param.h> 116#include <sys/kernel.h> 117#include <sys/queue.h> 118#include <sys/cpuset.h> 119#include <sys/ktr.h> 120#include <sys/lock.h> 121#include <sys/msgbuf.h> 122#include <sys/malloc.h> 123#include <sys/mutex.h> 124#include <sys/proc.h> 125#include <sys/rwlock.h> 126#include <sys/sched.h> 127#include <sys/sysctl.h> 128#include <sys/systm.h> 129#include <sys/vmmeter.h> 130 131#include <sys/kdb.h> 132 133#include <dev/ofw/openfirm.h> 134 135#include <vm/vm.h> 136#include <vm/vm_param.h> 137#include <vm/vm_kern.h> 138#include <vm/vm_page.h> 139#include <vm/vm_map.h> 140#include <vm/vm_object.h> 141#include <vm/vm_extern.h> 142#include <vm/vm_pageout.h> 143#include <vm/uma.h> 144 145#include <machine/_inttypes.h> 146#include <machine/cpu.h> 147#include <machine/platform.h> 148#include <machine/frame.h> 149#include <machine/md_var.h> 150#include <machine/psl.h> 151#include <machine/bat.h> 152#include <machine/hid.h> 153#include <machine/pte.h> 154#include <machine/sr.h> 155#include <machine/trap.h> 156#include <machine/mmuvar.h> 157 158#include "mmu_oea64.h" 159#include "mmu_if.h" 160#include "moea64_if.h" 161 162void moea64_release_vsid(uint64_t vsid); 163uintptr_t moea64_get_unique_vsid(void); 164 165#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 166#define ENABLE_TRANS(msr) mtmsr(msr) 167 168#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 169#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 170#define VSID_HASH_MASK 0x0000007fffffffffULL 171 172/* 173 * Locking semantics: 174 * -- Read lock: if no modifications are being made to either the PVO lists 175 * or page table or if any modifications being made result in internal 176 * changes (e.g. wiring, protection) such that the existence of the PVOs 177 * is unchanged and they remain associated with the same pmap (in which 178 * case the changes should be protected by the pmap lock) 179 * -- Write lock: required if PTEs/PVOs are being inserted or removed. 180 */ 181 182#define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock) 183#define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock) 184#define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock) 185#define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock) 186 187struct ofw_map { 188 cell_t om_va; 189 cell_t om_len; 190 cell_t om_pa_hi; 191 cell_t om_pa_lo; 192 cell_t om_mode; 193}; 194 195/* 196 * Map of physical memory regions. 197 */ 198static struct mem_region *regions; 199static struct mem_region *pregions; 200static u_int phys_avail_count; 201static int regions_sz, pregions_sz; 202 203extern void bs_remap_earlyboot(void); 204 205/* 206 * Lock for the pteg and pvo tables. 207 */ 208struct rwlock moea64_table_lock; 209struct mtx moea64_slb_mutex; 210 211/* 212 * PTEG data. 213 */ 214u_int moea64_pteg_count; 215u_int moea64_pteg_mask; 216 217/* 218 * PVO data. 219 */ 220struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 221 222uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 223uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 224 225#define BPVO_POOL_SIZE 327680 226static struct pvo_entry *moea64_bpvo_pool; 227static int moea64_bpvo_pool_index = 0; 228 229#define VSID_NBPW (sizeof(u_int32_t) * 8) 230#ifdef __powerpc64__ 231#define NVSIDS (NPMAPS * 16) 232#define VSID_HASHMASK 0xffffffffUL 233#else 234#define NVSIDS NPMAPS 235#define VSID_HASHMASK 0xfffffUL 236#endif 237static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 238 239static boolean_t moea64_initialized = FALSE; 240 241/* 242 * Statistics. 243 */ 244u_int moea64_pte_valid = 0; 245u_int moea64_pte_overflow = 0; 246u_int moea64_pvo_entries = 0; 247u_int moea64_pvo_enter_calls = 0; 248u_int moea64_pvo_remove_calls = 0; 249SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 250 &moea64_pte_valid, 0, ""); 251SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 252 &moea64_pte_overflow, 0, ""); 253SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 254 &moea64_pvo_entries, 0, ""); 255SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 256 &moea64_pvo_enter_calls, 0, ""); 257SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 258 &moea64_pvo_remove_calls, 0, ""); 259 260vm_offset_t moea64_scratchpage_va[2]; 261struct pvo_entry *moea64_scratchpage_pvo[2]; 262uintptr_t moea64_scratchpage_pte[2]; 263struct mtx moea64_scratchpage_mtx; 264 265uint64_t moea64_large_page_mask = 0; 266int moea64_large_page_size = 0; 267int moea64_large_page_shift = 0; 268 269/* 270 * PVO calls. 271 */ 272static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 273 vm_offset_t, vm_offset_t, uint64_t, int); 274static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 275static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 276 277/* 278 * Utility routines. 279 */ 280static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 281static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 282static void moea64_kremove(mmu_t, vm_offset_t); 283static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 284 vm_offset_t pa, vm_size_t sz); 285 286/* 287 * Kernel MMU interface 288 */ 289void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 290void moea64_clear_modify(mmu_t, vm_page_t); 291void moea64_clear_reference(mmu_t, vm_page_t); 292void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 293void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 294 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 295void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 296void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 297 vm_prot_t); 298void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 299vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 300vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 301void moea64_init(mmu_t); 302boolean_t moea64_is_modified(mmu_t, vm_page_t); 303boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 304boolean_t moea64_is_referenced(mmu_t, vm_page_t); 305int moea64_ts_referenced(mmu_t, vm_page_t); 306vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 307boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 308int moea64_page_wired_mappings(mmu_t, vm_page_t); 309void moea64_pinit(mmu_t, pmap_t); 310void moea64_pinit0(mmu_t, pmap_t); 311void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 312void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 313void moea64_qremove(mmu_t, vm_offset_t, int); 314void moea64_release(mmu_t, pmap_t); 315void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 316void moea64_remove_pages(mmu_t, pmap_t); 317void moea64_remove_all(mmu_t, vm_page_t); 318void moea64_remove_write(mmu_t, vm_page_t); 319void moea64_zero_page(mmu_t, vm_page_t); 320void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 321void moea64_zero_page_idle(mmu_t, vm_page_t); 322void moea64_activate(mmu_t, struct thread *); 323void moea64_deactivate(mmu_t, struct thread *); 324void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 325void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 326void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 327vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 328void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 329void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 330void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 331boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 332static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 333 334static mmu_method_t moea64_methods[] = { 335 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 336 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 337 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 338 MMUMETHOD(mmu_copy_page, moea64_copy_page), 339 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 340 MMUMETHOD(mmu_enter, moea64_enter), 341 MMUMETHOD(mmu_enter_object, moea64_enter_object), 342 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 343 MMUMETHOD(mmu_extract, moea64_extract), 344 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 345 MMUMETHOD(mmu_init, moea64_init), 346 MMUMETHOD(mmu_is_modified, moea64_is_modified), 347 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 348 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 349 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 350 MMUMETHOD(mmu_map, moea64_map), 351 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 352 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 353 MMUMETHOD(mmu_pinit, moea64_pinit), 354 MMUMETHOD(mmu_pinit0, moea64_pinit0), 355 MMUMETHOD(mmu_protect, moea64_protect), 356 MMUMETHOD(mmu_qenter, moea64_qenter), 357 MMUMETHOD(mmu_qremove, moea64_qremove), 358 MMUMETHOD(mmu_release, moea64_release), 359 MMUMETHOD(mmu_remove, moea64_remove), 360 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 361 MMUMETHOD(mmu_remove_all, moea64_remove_all), 362 MMUMETHOD(mmu_remove_write, moea64_remove_write), 363 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 364 MMUMETHOD(mmu_zero_page, moea64_zero_page), 365 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 366 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 367 MMUMETHOD(mmu_activate, moea64_activate), 368 MMUMETHOD(mmu_deactivate, moea64_deactivate), 369 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 370 371 /* Internal interfaces */ 372 MMUMETHOD(mmu_mapdev, moea64_mapdev), 373 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 374 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 375 MMUMETHOD(mmu_kextract, moea64_kextract), 376 MMUMETHOD(mmu_kenter, moea64_kenter), 377 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 378 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 379 380 { 0, 0 } 381}; 382 383MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 384 385static __inline u_int 386va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 387{ 388 uint64_t hash; 389 int shift; 390 391 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 392 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 393 shift); 394 return (hash & moea64_pteg_mask); 395} 396 397static __inline struct pvo_head * 398vm_page_to_pvoh(vm_page_t m) 399{ 400 401 return (&m->md.mdpg_pvoh); 402} 403 404static __inline void 405moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 406 uint64_t pte_lo, int flags) 407{ 408 409 /* 410 * Construct a PTE. Default to IMB initially. Valid bit only gets 411 * set when the real pte is set in memory. 412 * 413 * Note: Don't set the valid bit for correct operation of tlb update. 414 */ 415 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 416 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 417 418 if (flags & PVO_LARGE) 419 pt->pte_hi |= LPTE_BIG; 420 421 pt->pte_lo = pte_lo; 422} 423 424static __inline uint64_t 425moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 426{ 427 uint64_t pte_lo; 428 int i; 429 430 if (ma != VM_MEMATTR_DEFAULT) { 431 switch (ma) { 432 case VM_MEMATTR_UNCACHEABLE: 433 return (LPTE_I | LPTE_G); 434 case VM_MEMATTR_WRITE_COMBINING: 435 case VM_MEMATTR_WRITE_BACK: 436 case VM_MEMATTR_PREFETCHABLE: 437 return (LPTE_I); 438 case VM_MEMATTR_WRITE_THROUGH: 439 return (LPTE_W | LPTE_M); 440 } 441 } 442 443 /* 444 * Assume the page is cache inhibited and access is guarded unless 445 * it's in our available memory array. 446 */ 447 pte_lo = LPTE_I | LPTE_G; 448 for (i = 0; i < pregions_sz; i++) { 449 if ((pa >= pregions[i].mr_start) && 450 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 451 pte_lo &= ~(LPTE_I | LPTE_G); 452 pte_lo |= LPTE_M; 453 break; 454 } 455 } 456 457 return pte_lo; 458} 459 460/* 461 * Quick sort callout for comparing memory regions. 462 */ 463static int om_cmp(const void *a, const void *b); 464 465static int 466om_cmp(const void *a, const void *b) 467{ 468 const struct ofw_map *mapa; 469 const struct ofw_map *mapb; 470 471 mapa = a; 472 mapb = b; 473 if (mapa->om_pa_hi < mapb->om_pa_hi) 474 return (-1); 475 else if (mapa->om_pa_hi > mapb->om_pa_hi) 476 return (1); 477 else if (mapa->om_pa_lo < mapb->om_pa_lo) 478 return (-1); 479 else if (mapa->om_pa_lo > mapb->om_pa_lo) 480 return (1); 481 else 482 return (0); 483} 484 485static void 486moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 487{ 488 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 489 register_t msr; 490 vm_offset_t off; 491 vm_paddr_t pa_base; 492 int i; 493 494 bzero(translations, sz); 495 if (OF_getprop(mmu, "translations", translations, sz) == -1) 496 panic("moea64_bootstrap: can't get ofw translations"); 497 498 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 499 sz /= sizeof(*translations); 500 qsort(translations, sz, sizeof (*translations), om_cmp); 501 502 for (i = 0; i < sz; i++) { 503 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 504 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 505 translations[i].om_len); 506 507 if (translations[i].om_pa_lo % PAGE_SIZE) 508 panic("OFW translation not page-aligned!"); 509 510 pa_base = translations[i].om_pa_lo; 511 512 #ifdef __powerpc64__ 513 pa_base += (vm_offset_t)translations[i].om_pa_hi << 32; 514 #else 515 if (translations[i].om_pa_hi) 516 panic("OFW translations above 32-bit boundary!"); 517 #endif 518 519 /* Now enter the pages for this mapping */ 520 521 DISABLE_TRANS(msr); 522 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 523 if (moea64_pvo_find_va(kernel_pmap, 524 translations[i].om_va + off) != NULL) 525 continue; 526 527 moea64_kenter(mmup, translations[i].om_va + off, 528 pa_base + off); 529 } 530 ENABLE_TRANS(msr); 531 } 532} 533 534#ifdef __powerpc64__ 535static void 536moea64_probe_large_page(void) 537{ 538 uint16_t pvr = mfpvr() >> 16; 539 540 switch (pvr) { 541 case IBM970: 542 case IBM970FX: 543 case IBM970MP: 544 powerpc_sync(); isync(); 545 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 546 powerpc_sync(); isync(); 547 548 /* FALLTHROUGH */ 549 case IBMCELLBE: 550 moea64_large_page_size = 0x1000000; /* 16 MB */ 551 moea64_large_page_shift = 24; 552 break; 553 default: 554 moea64_large_page_size = 0; 555 } 556 557 moea64_large_page_mask = moea64_large_page_size - 1; 558} 559 560static void 561moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 562{ 563 struct slb *cache; 564 struct slb entry; 565 uint64_t esid, slbe; 566 uint64_t i; 567 568 cache = PCPU_GET(slb); 569 esid = va >> ADDR_SR_SHFT; 570 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 571 572 for (i = 0; i < 64; i++) { 573 if (cache[i].slbe == (slbe | i)) 574 return; 575 } 576 577 entry.slbe = slbe; 578 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 579 if (large) 580 entry.slbv |= SLBV_L; 581 582 slb_insert_kernel(entry.slbe, entry.slbv); 583} 584#endif 585 586static void 587moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 588 vm_offset_t kernelend) 589{ 590 register_t msr; 591 vm_paddr_t pa; 592 vm_offset_t size, off; 593 uint64_t pte_lo; 594 int i; 595 596 if (moea64_large_page_size == 0) 597 hw_direct_map = 0; 598 599 DISABLE_TRANS(msr); 600 if (hw_direct_map) { 601 LOCK_TABLE_WR(); 602 PMAP_LOCK(kernel_pmap); 603 for (i = 0; i < pregions_sz; i++) { 604 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 605 pregions[i].mr_size; pa += moea64_large_page_size) { 606 pte_lo = LPTE_M; 607 608 /* 609 * Set memory access as guarded if prefetch within 610 * the page could exit the available physmem area. 611 */ 612 if (pa & moea64_large_page_mask) { 613 pa &= moea64_large_page_mask; 614 pte_lo |= LPTE_G; 615 } 616 if (pa + moea64_large_page_size > 617 pregions[i].mr_start + pregions[i].mr_size) 618 pte_lo |= LPTE_G; 619 620 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 621 NULL, pa, pa, pte_lo, 622 PVO_WIRED | PVO_LARGE); 623 } 624 } 625 PMAP_UNLOCK(kernel_pmap); 626 UNLOCK_TABLE_WR(); 627 } else { 628 size = sizeof(struct pvo_head) * moea64_pteg_count; 629 off = (vm_offset_t)(moea64_pvo_table); 630 for (pa = off; pa < off + size; pa += PAGE_SIZE) 631 moea64_kenter(mmup, pa, pa); 632 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 633 off = (vm_offset_t)(moea64_bpvo_pool); 634 for (pa = off; pa < off + size; pa += PAGE_SIZE) 635 moea64_kenter(mmup, pa, pa); 636 637 /* 638 * Map certain important things, like ourselves. 639 * 640 * NOTE: We do not map the exception vector space. That code is 641 * used only in real mode, and leaving it unmapped allows us to 642 * catch NULL pointer deferences, instead of making NULL a valid 643 * address. 644 */ 645 646 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 647 pa += PAGE_SIZE) 648 moea64_kenter(mmup, pa, pa); 649 } 650 ENABLE_TRANS(msr); 651 652 /* 653 * Allow user to override unmapped_buf_allowed for testing. 654 * XXXKIB Only direct map implementation was tested. 655 */ 656 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 657 &unmapped_buf_allowed)) 658 unmapped_buf_allowed = hw_direct_map; 659} 660 661void 662moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 663{ 664 int i, j; 665 vm_size_t physsz, hwphyssz; 666 667#ifndef __powerpc64__ 668 /* We don't have a direct map since there is no BAT */ 669 hw_direct_map = 0; 670 671 /* Make sure battable is zero, since we have no BAT */ 672 for (i = 0; i < 16; i++) { 673 battable[i].batu = 0; 674 battable[i].batl = 0; 675 } 676#else 677 moea64_probe_large_page(); 678 679 /* Use a direct map if we have large page support */ 680 if (moea64_large_page_size > 0) 681 hw_direct_map = 1; 682 else 683 hw_direct_map = 0; 684#endif 685 686 /* Get physical memory regions from firmware */ 687 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 688 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 689 690 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 691 panic("moea64_bootstrap: phys_avail too small"); 692 693 phys_avail_count = 0; 694 physsz = 0; 695 hwphyssz = 0; 696 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 697 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 698 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 699 regions[i].mr_start + regions[i].mr_size, 700 regions[i].mr_size); 701 if (hwphyssz != 0 && 702 (physsz + regions[i].mr_size) >= hwphyssz) { 703 if (physsz < hwphyssz) { 704 phys_avail[j] = regions[i].mr_start; 705 phys_avail[j + 1] = regions[i].mr_start + 706 hwphyssz - physsz; 707 physsz = hwphyssz; 708 phys_avail_count++; 709 } 710 break; 711 } 712 phys_avail[j] = regions[i].mr_start; 713 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 714 phys_avail_count++; 715 physsz += regions[i].mr_size; 716 } 717 718 /* Check for overlap with the kernel and exception vectors */ 719 for (j = 0; j < 2*phys_avail_count; j+=2) { 720 if (phys_avail[j] < EXC_LAST) 721 phys_avail[j] += EXC_LAST; 722 723 if (kernelstart >= phys_avail[j] && 724 kernelstart < phys_avail[j+1]) { 725 if (kernelend < phys_avail[j+1]) { 726 phys_avail[2*phys_avail_count] = 727 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 728 phys_avail[2*phys_avail_count + 1] = 729 phys_avail[j+1]; 730 phys_avail_count++; 731 } 732 733 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 734 } 735 736 if (kernelend >= phys_avail[j] && 737 kernelend < phys_avail[j+1]) { 738 if (kernelstart > phys_avail[j]) { 739 phys_avail[2*phys_avail_count] = phys_avail[j]; 740 phys_avail[2*phys_avail_count + 1] = 741 kernelstart & ~PAGE_MASK; 742 phys_avail_count++; 743 } 744 745 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 746 } 747 } 748 749 physmem = btoc(physsz); 750 751#ifdef PTEGCOUNT 752 moea64_pteg_count = PTEGCOUNT; 753#else 754 moea64_pteg_count = 0x1000; 755 756 while (moea64_pteg_count < physmem) 757 moea64_pteg_count <<= 1; 758 759 moea64_pteg_count >>= 1; 760#endif /* PTEGCOUNT */ 761} 762 763void 764moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 765{ 766 vm_size_t size; 767 register_t msr; 768 int i; 769 770 /* 771 * Set PTEG mask 772 */ 773 moea64_pteg_mask = moea64_pteg_count - 1; 774 775 /* 776 * Allocate pv/overflow lists. 777 */ 778 size = sizeof(struct pvo_head) * moea64_pteg_count; 779 780 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 781 PAGE_SIZE); 782 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 783 784 DISABLE_TRANS(msr); 785 for (i = 0; i < moea64_pteg_count; i++) 786 LIST_INIT(&moea64_pvo_table[i]); 787 ENABLE_TRANS(msr); 788 789 /* 790 * Initialize the lock that synchronizes access to the pteg and pvo 791 * tables. 792 */ 793 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE); 794 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 795 796 /* 797 * Initialise the unmanaged pvo pool. 798 */ 799 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 800 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 801 moea64_bpvo_pool_index = 0; 802 803 /* 804 * Make sure kernel vsid is allocated as well as VSID 0. 805 */ 806 #ifndef __powerpc64__ 807 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 808 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 809 moea64_vsid_bitmap[0] |= 1; 810 #endif 811 812 /* 813 * Initialize the kernel pmap (which is statically allocated). 814 */ 815 #ifdef __powerpc64__ 816 for (i = 0; i < 64; i++) { 817 pcpup->pc_slb[i].slbv = 0; 818 pcpup->pc_slb[i].slbe = 0; 819 } 820 #else 821 for (i = 0; i < 16; i++) 822 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 823 #endif 824 825 kernel_pmap->pmap_phys = kernel_pmap; 826 CPU_FILL(&kernel_pmap->pm_active); 827 RB_INIT(&kernel_pmap->pmap_pvo); 828 829 PMAP_LOCK_INIT(kernel_pmap); 830 831 /* 832 * Now map in all the other buffers we allocated earlier 833 */ 834 835 moea64_setup_direct_map(mmup, kernelstart, kernelend); 836} 837 838void 839moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 840{ 841 ihandle_t mmui; 842 phandle_t chosen; 843 phandle_t mmu; 844 size_t sz; 845 int i; 846 vm_offset_t pa, va; 847 void *dpcpu; 848 849 /* 850 * Set up the Open Firmware pmap and add its mappings if not in real 851 * mode. 852 */ 853 854 chosen = OF_finddevice("/chosen"); 855 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 856 mmu = OF_instance_to_package(mmui); 857 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1) 858 sz = 0; 859 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 860 panic("moea64_bootstrap: too many ofw translations"); 861 862 if (sz > 0) 863 moea64_add_ofw_mappings(mmup, mmu, sz); 864 } 865 866 /* 867 * Calculate the last available physical address. 868 */ 869 for (i = 0; phys_avail[i + 2] != 0; i += 2) 870 ; 871 Maxmem = powerpc_btop(phys_avail[i + 1]); 872 873 /* 874 * Initialize MMU and remap early physical mappings 875 */ 876 MMU_CPU_BOOTSTRAP(mmup,0); 877 mtmsr(mfmsr() | PSL_DR | PSL_IR); 878 pmap_bootstrapped++; 879 bs_remap_earlyboot(); 880 881 /* 882 * Set the start and end of kva. 883 */ 884 virtual_avail = VM_MIN_KERNEL_ADDRESS; 885 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 886 887 /* 888 * Map the entire KVA range into the SLB. We must not fault there. 889 */ 890 #ifdef __powerpc64__ 891 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 892 moea64_bootstrap_slb_prefault(va, 0); 893 #endif 894 895 /* 896 * Figure out how far we can extend virtual_end into segment 16 897 * without running into existing mappings. Segment 16 is guaranteed 898 * to contain neither RAM nor devices (at least on Apple hardware), 899 * but will generally contain some OFW mappings we should not 900 * step on. 901 */ 902 903 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 904 PMAP_LOCK(kernel_pmap); 905 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 906 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 907 virtual_end += PAGE_SIZE; 908 PMAP_UNLOCK(kernel_pmap); 909 #endif 910 911 /* 912 * Allocate a kernel stack with a guard page for thread0 and map it 913 * into the kernel page map. 914 */ 915 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 916 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 917 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 918 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 919 thread0.td_kstack = va; 920 thread0.td_kstack_pages = KSTACK_PAGES; 921 for (i = 0; i < KSTACK_PAGES; i++) { 922 moea64_kenter(mmup, va, pa); 923 pa += PAGE_SIZE; 924 va += PAGE_SIZE; 925 } 926 927 /* 928 * Allocate virtual address space for the message buffer. 929 */ 930 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 931 msgbufp = (struct msgbuf *)virtual_avail; 932 va = virtual_avail; 933 virtual_avail += round_page(msgbufsize); 934 while (va < virtual_avail) { 935 moea64_kenter(mmup, va, pa); 936 pa += PAGE_SIZE; 937 va += PAGE_SIZE; 938 } 939 940 /* 941 * Allocate virtual address space for the dynamic percpu area. 942 */ 943 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 944 dpcpu = (void *)virtual_avail; 945 va = virtual_avail; 946 virtual_avail += DPCPU_SIZE; 947 while (va < virtual_avail) { 948 moea64_kenter(mmup, va, pa); 949 pa += PAGE_SIZE; 950 va += PAGE_SIZE; 951 } 952 dpcpu_init(dpcpu, 0); 953 954 /* 955 * Allocate some things for page zeroing. We put this directly 956 * in the page table, marked with LPTE_LOCKED, to avoid any 957 * of the PVO book-keeping or other parts of the VM system 958 * from even knowing that this hack exists. 959 */ 960 961 if (!hw_direct_map) { 962 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 963 MTX_DEF); 964 for (i = 0; i < 2; i++) { 965 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 966 virtual_end -= PAGE_SIZE; 967 968 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 969 970 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 971 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 972 LOCK_TABLE_RD(); 973 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 974 mmup, moea64_scratchpage_pvo[i]); 975 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 976 |= LPTE_LOCKED; 977 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 978 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 979 moea64_scratchpage_pvo[i]->pvo_vpn); 980 UNLOCK_TABLE_RD(); 981 } 982 } 983} 984 985/* 986 * Activate a user pmap. The pmap must be activated before its address 987 * space can be accessed in any way. 988 */ 989void 990moea64_activate(mmu_t mmu, struct thread *td) 991{ 992 pmap_t pm; 993 994 pm = &td->td_proc->p_vmspace->vm_pmap; 995 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 996 997 #ifdef __powerpc64__ 998 PCPU_SET(userslb, pm->pm_slb); 999 #else 1000 PCPU_SET(curpmap, pm->pmap_phys); 1001 #endif 1002} 1003 1004void 1005moea64_deactivate(mmu_t mmu, struct thread *td) 1006{ 1007 pmap_t pm; 1008 1009 pm = &td->td_proc->p_vmspace->vm_pmap; 1010 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1011 #ifdef __powerpc64__ 1012 PCPU_SET(userslb, NULL); 1013 #else 1014 PCPU_SET(curpmap, NULL); 1015 #endif 1016} 1017 1018void 1019moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1020{ 1021 struct pvo_entry *pvo; 1022 uintptr_t pt; 1023 uint64_t vsid; 1024 int i, ptegidx; 1025 1026 LOCK_TABLE_WR(); 1027 PMAP_LOCK(pm); 1028 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 1029 1030 if (pvo != NULL) { 1031 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1032 1033 if (wired) { 1034 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1035 pm->pm_stats.wired_count++; 1036 pvo->pvo_vaddr |= PVO_WIRED; 1037 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 1038 } else { 1039 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1040 pm->pm_stats.wired_count--; 1041 pvo->pvo_vaddr &= ~PVO_WIRED; 1042 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1043 } 1044 1045 if (pt != -1) { 1046 /* Update wiring flag in page table. */ 1047 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1048 pvo->pvo_vpn); 1049 } else if (wired) { 1050 /* 1051 * If we are wiring the page, and it wasn't in the 1052 * page table before, add it. 1053 */ 1054 vsid = PVO_VSID(pvo); 1055 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 1056 pvo->pvo_vaddr & PVO_LARGE); 1057 1058 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 1059 1060 if (i >= 0) { 1061 PVO_PTEGIDX_CLR(pvo); 1062 PVO_PTEGIDX_SET(pvo, i); 1063 } 1064 } 1065 1066 } 1067 UNLOCK_TABLE_WR(); 1068 PMAP_UNLOCK(pm); 1069} 1070 1071/* 1072 * This goes through and sets the physical address of our 1073 * special scratch PTE to the PA we want to zero or copy. Because 1074 * of locking issues (this can get called in pvo_enter() by 1075 * the UMA allocator), we can't use most other utility functions here 1076 */ 1077 1078static __inline 1079void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1080 1081 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1082 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1083 1084 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1085 ~(LPTE_WIMG | LPTE_RPGN); 1086 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1087 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1088 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1089 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1090 moea64_scratchpage_pvo[which]->pvo_vpn); 1091 isync(); 1092} 1093 1094void 1095moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1096{ 1097 vm_offset_t dst; 1098 vm_offset_t src; 1099 1100 dst = VM_PAGE_TO_PHYS(mdst); 1101 src = VM_PAGE_TO_PHYS(msrc); 1102 1103 if (hw_direct_map) { 1104 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1105 } else { 1106 mtx_lock(&moea64_scratchpage_mtx); 1107 1108 moea64_set_scratchpage_pa(mmu, 0, src); 1109 moea64_set_scratchpage_pa(mmu, 1, dst); 1110 1111 bcopy((void *)moea64_scratchpage_va[0], 1112 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1113 1114 mtx_unlock(&moea64_scratchpage_mtx); 1115 } 1116} 1117 1118static inline void 1119moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1120 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1121{ 1122 void *a_cp, *b_cp; 1123 vm_offset_t a_pg_offset, b_pg_offset; 1124 int cnt; 1125 1126 while (xfersize > 0) { 1127 a_pg_offset = a_offset & PAGE_MASK; 1128 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1129 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1130 a_pg_offset; 1131 b_pg_offset = b_offset & PAGE_MASK; 1132 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1133 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1134 b_pg_offset; 1135 bcopy(a_cp, b_cp, cnt); 1136 a_offset += cnt; 1137 b_offset += cnt; 1138 xfersize -= cnt; 1139 } 1140} 1141 1142static inline void 1143moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1144 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1145{ 1146 void *a_cp, *b_cp; 1147 vm_offset_t a_pg_offset, b_pg_offset; 1148 int cnt; 1149 1150 mtx_lock(&moea64_scratchpage_mtx); 1151 while (xfersize > 0) { 1152 a_pg_offset = a_offset & PAGE_MASK; 1153 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1154 moea64_set_scratchpage_pa(mmu, 0, 1155 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1156 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1157 b_pg_offset = b_offset & PAGE_MASK; 1158 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1159 moea64_set_scratchpage_pa(mmu, 1, 1160 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1161 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1162 bcopy(a_cp, b_cp, cnt); 1163 a_offset += cnt; 1164 b_offset += cnt; 1165 xfersize -= cnt; 1166 } 1167 mtx_unlock(&moea64_scratchpage_mtx); 1168} 1169 1170void 1171moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1172 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1173{ 1174 1175 if (hw_direct_map) { 1176 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1177 xfersize); 1178 } else { 1179 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1180 xfersize); 1181 } 1182} 1183 1184void 1185moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1186{ 1187 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1188 1189 if (size + off > PAGE_SIZE) 1190 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1191 1192 if (hw_direct_map) { 1193 bzero((caddr_t)pa + off, size); 1194 } else { 1195 mtx_lock(&moea64_scratchpage_mtx); 1196 moea64_set_scratchpage_pa(mmu, 0, pa); 1197 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1198 mtx_unlock(&moea64_scratchpage_mtx); 1199 } 1200} 1201 1202/* 1203 * Zero a page of physical memory by temporarily mapping it 1204 */ 1205void 1206moea64_zero_page(mmu_t mmu, vm_page_t m) 1207{ 1208 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1209 vm_offset_t va, off; 1210 1211 if (!hw_direct_map) { 1212 mtx_lock(&moea64_scratchpage_mtx); 1213 1214 moea64_set_scratchpage_pa(mmu, 0, pa); 1215 va = moea64_scratchpage_va[0]; 1216 } else { 1217 va = pa; 1218 } 1219 1220 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1221 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1222 1223 if (!hw_direct_map) 1224 mtx_unlock(&moea64_scratchpage_mtx); 1225} 1226 1227void 1228moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1229{ 1230 1231 moea64_zero_page(mmu, m); 1232} 1233 1234/* 1235 * Map the given physical page at the specified virtual address in the 1236 * target pmap with the protection requested. If specified the page 1237 * will be wired down. 1238 */ 1239 1240void 1241moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1242 vm_prot_t prot, boolean_t wired) 1243{ 1244 struct pvo_head *pvo_head; 1245 uma_zone_t zone; 1246 vm_page_t pg; 1247 uint64_t pte_lo; 1248 u_int pvo_flags; 1249 int error; 1250 1251 if (!moea64_initialized) { 1252 pvo_head = NULL; 1253 pg = NULL; 1254 zone = moea64_upvo_zone; 1255 pvo_flags = 0; 1256 } else { 1257 pvo_head = vm_page_to_pvoh(m); 1258 pg = m; 1259 zone = moea64_mpvo_zone; 1260 pvo_flags = PVO_MANAGED; 1261 } 1262 1263 if ((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) == 0) 1264 VM_OBJECT_ASSERT_WLOCKED(m->object); 1265 1266 /* XXX change the pvo head for fake pages */ 1267 if ((m->oflags & VPO_UNMANAGED) != 0) { 1268 pvo_flags &= ~PVO_MANAGED; 1269 pvo_head = NULL; 1270 zone = moea64_upvo_zone; 1271 } 1272 1273 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1274 1275 if (prot & VM_PROT_WRITE) { 1276 pte_lo |= LPTE_BW; 1277 if (pmap_bootstrapped && 1278 (m->oflags & VPO_UNMANAGED) == 0) 1279 vm_page_aflag_set(m, PGA_WRITEABLE); 1280 } else 1281 pte_lo |= LPTE_BR; 1282 1283 if ((prot & VM_PROT_EXECUTE) == 0) 1284 pte_lo |= LPTE_NOEXEC; 1285 1286 if (wired) 1287 pvo_flags |= PVO_WIRED; 1288 1289 LOCK_TABLE_WR(); 1290 PMAP_LOCK(pmap); 1291 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1292 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags); 1293 PMAP_UNLOCK(pmap); 1294 UNLOCK_TABLE_WR(); 1295 1296 /* 1297 * Flush the page from the instruction cache if this page is 1298 * mapped executable and cacheable. 1299 */ 1300 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1301 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1302 vm_page_aflag_set(m, PGA_EXECUTABLE); 1303 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1304 } 1305} 1306 1307static void 1308moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1309 vm_size_t sz) 1310{ 1311 1312 /* 1313 * This is much trickier than on older systems because 1314 * we can't sync the icache on physical addresses directly 1315 * without a direct map. Instead we check a couple of cases 1316 * where the memory is already mapped in and, failing that, 1317 * use the same trick we use for page zeroing to create 1318 * a temporary mapping for this physical address. 1319 */ 1320 1321 if (!pmap_bootstrapped) { 1322 /* 1323 * If PMAP is not bootstrapped, we are likely to be 1324 * in real mode. 1325 */ 1326 __syncicache((void *)pa, sz); 1327 } else if (pmap == kernel_pmap) { 1328 __syncicache((void *)va, sz); 1329 } else if (hw_direct_map) { 1330 __syncicache((void *)pa, sz); 1331 } else { 1332 /* Use the scratch page to set up a temp mapping */ 1333 1334 mtx_lock(&moea64_scratchpage_mtx); 1335 1336 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1337 __syncicache((void *)(moea64_scratchpage_va[1] + 1338 (va & ADDR_POFF)), sz); 1339 1340 mtx_unlock(&moea64_scratchpage_mtx); 1341 } 1342} 1343 1344/* 1345 * Maps a sequence of resident pages belonging to the same object. 1346 * The sequence begins with the given page m_start. This page is 1347 * mapped at the given virtual address start. Each subsequent page is 1348 * mapped at a virtual address that is offset from start by the same 1349 * amount as the page is offset from m_start within the object. The 1350 * last page in the sequence is the page with the largest offset from 1351 * m_start that can be mapped at a virtual address less than the given 1352 * virtual address end. Not every virtual page between start and end 1353 * is mapped; only those for which a resident page exists with the 1354 * corresponding offset from m_start are mapped. 1355 */ 1356void 1357moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1358 vm_page_t m_start, vm_prot_t prot) 1359{ 1360 vm_page_t m; 1361 vm_pindex_t diff, psize; 1362 1363 psize = atop(end - start); 1364 m = m_start; 1365 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1366 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1367 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1368 m = TAILQ_NEXT(m, listq); 1369 } 1370} 1371 1372void 1373moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1374 vm_prot_t prot) 1375{ 1376 1377 moea64_enter(mmu, pm, va, m, 1378 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1379} 1380 1381vm_paddr_t 1382moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1383{ 1384 struct pvo_entry *pvo; 1385 vm_paddr_t pa; 1386 1387 PMAP_LOCK(pm); 1388 pvo = moea64_pvo_find_va(pm, va); 1389 if (pvo == NULL) 1390 pa = 0; 1391 else 1392 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1393 (va - PVO_VADDR(pvo)); 1394 PMAP_UNLOCK(pm); 1395 return (pa); 1396} 1397 1398/* 1399 * Atomically extract and hold the physical page with the given 1400 * pmap and virtual address pair if that mapping permits the given 1401 * protection. 1402 */ 1403vm_page_t 1404moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1405{ 1406 struct pvo_entry *pvo; 1407 vm_page_t m; 1408 vm_paddr_t pa; 1409 1410 m = NULL; 1411 pa = 0; 1412 PMAP_LOCK(pmap); 1413retry: 1414 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1415 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1416 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1417 (prot & VM_PROT_WRITE) == 0)) { 1418 if (vm_page_pa_tryrelock(pmap, 1419 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1420 goto retry; 1421 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1422 vm_page_hold(m); 1423 } 1424 PA_UNLOCK_COND(pa); 1425 PMAP_UNLOCK(pmap); 1426 return (m); 1427} 1428 1429static mmu_t installed_mmu; 1430 1431static void * 1432moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1433{ 1434 /* 1435 * This entire routine is a horrible hack to avoid bothering kmem 1436 * for new KVA addresses. Because this can get called from inside 1437 * kmem allocation routines, calling kmem for a new address here 1438 * can lead to multiply locking non-recursive mutexes. 1439 */ 1440 vm_offset_t va; 1441 1442 vm_page_t m; 1443 int pflags, needed_lock; 1444 1445 *flags = UMA_SLAB_PRIV; 1446 needed_lock = !PMAP_LOCKED(kernel_pmap); 1447 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED; 1448 1449 for (;;) { 1450 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1451 if (m == NULL) { 1452 if (wait & M_NOWAIT) 1453 return (NULL); 1454 VM_WAIT; 1455 } else 1456 break; 1457 } 1458 1459 va = VM_PAGE_TO_PHYS(m); 1460 1461 LOCK_TABLE_WR(); 1462 if (needed_lock) 1463 PMAP_LOCK(kernel_pmap); 1464 1465 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1466 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP); 1467 1468 if (needed_lock) 1469 PMAP_UNLOCK(kernel_pmap); 1470 UNLOCK_TABLE_WR(); 1471 1472 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1473 bzero((void *)va, PAGE_SIZE); 1474 1475 return (void *)va; 1476} 1477 1478extern int elf32_nxstack; 1479 1480void 1481moea64_init(mmu_t mmu) 1482{ 1483 1484 CTR0(KTR_PMAP, "moea64_init"); 1485 1486 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1487 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1488 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1489 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1490 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1491 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1492 1493 if (!hw_direct_map) { 1494 installed_mmu = mmu; 1495 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1496 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1497 } 1498 1499#ifdef COMPAT_FREEBSD32 1500 elf32_nxstack = 1; 1501#endif 1502 1503 moea64_initialized = TRUE; 1504} 1505 1506boolean_t 1507moea64_is_referenced(mmu_t mmu, vm_page_t m) 1508{ 1509 1510 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1511 ("moea64_is_referenced: page %p is not managed", m)); 1512 return (moea64_query_bit(mmu, m, PTE_REF)); 1513} 1514 1515boolean_t 1516moea64_is_modified(mmu_t mmu, vm_page_t m) 1517{ 1518 1519 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1520 ("moea64_is_modified: page %p is not managed", m)); 1521 1522 /* 1523 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 1524 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1525 * is clear, no PTEs can have LPTE_CHG set. 1526 */ 1527 VM_OBJECT_ASSERT_WLOCKED(m->object); 1528 if ((m->oflags & VPO_BUSY) == 0 && 1529 (m->aflags & PGA_WRITEABLE) == 0) 1530 return (FALSE); 1531 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1532} 1533 1534boolean_t 1535moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1536{ 1537 struct pvo_entry *pvo; 1538 boolean_t rv; 1539 1540 PMAP_LOCK(pmap); 1541 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1542 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1543 PMAP_UNLOCK(pmap); 1544 return (rv); 1545} 1546 1547void 1548moea64_clear_reference(mmu_t mmu, vm_page_t m) 1549{ 1550 1551 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1552 ("moea64_clear_reference: page %p is not managed", m)); 1553 moea64_clear_bit(mmu, m, LPTE_REF); 1554} 1555 1556void 1557moea64_clear_modify(mmu_t mmu, vm_page_t m) 1558{ 1559 1560 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1561 ("moea64_clear_modify: page %p is not managed", m)); 1562 VM_OBJECT_ASSERT_WLOCKED(m->object); 1563 KASSERT((m->oflags & VPO_BUSY) == 0, 1564 ("moea64_clear_modify: page %p is busy", m)); 1565 1566 /* 1567 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1568 * set. If the object containing the page is locked and the page is 1569 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 1570 */ 1571 if ((m->aflags & PGA_WRITEABLE) == 0) 1572 return; 1573 moea64_clear_bit(mmu, m, LPTE_CHG); 1574} 1575 1576/* 1577 * Clear the write and modified bits in each of the given page's mappings. 1578 */ 1579void 1580moea64_remove_write(mmu_t mmu, vm_page_t m) 1581{ 1582 struct pvo_entry *pvo; 1583 uintptr_t pt; 1584 pmap_t pmap; 1585 uint64_t lo = 0; 1586 1587 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1588 ("moea64_remove_write: page %p is not managed", m)); 1589 1590 /* 1591 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 1592 * another thread while the object is locked. Thus, if PGA_WRITEABLE 1593 * is clear, no page table entries need updating. 1594 */ 1595 VM_OBJECT_ASSERT_WLOCKED(m->object); 1596 if ((m->oflags & VPO_BUSY) == 0 && 1597 (m->aflags & PGA_WRITEABLE) == 0) 1598 return; 1599 powerpc_sync(); 1600 LOCK_TABLE_RD(); 1601 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1602 pmap = pvo->pvo_pmap; 1603 PMAP_LOCK(pmap); 1604 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1605 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1606 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1607 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1608 if (pt != -1) { 1609 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1610 lo |= pvo->pvo_pte.lpte.pte_lo; 1611 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1612 MOEA64_PTE_CHANGE(mmu, pt, 1613 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1614 if (pvo->pvo_pmap == kernel_pmap) 1615 isync(); 1616 } 1617 } 1618 if ((lo & LPTE_CHG) != 0) 1619 vm_page_dirty(m); 1620 PMAP_UNLOCK(pmap); 1621 } 1622 UNLOCK_TABLE_RD(); 1623 vm_page_aflag_clear(m, PGA_WRITEABLE); 1624} 1625 1626/* 1627 * moea64_ts_referenced: 1628 * 1629 * Return a count of reference bits for a page, clearing those bits. 1630 * It is not necessary for every reference bit to be cleared, but it 1631 * is necessary that 0 only be returned when there are truly no 1632 * reference bits set. 1633 * 1634 * XXX: The exact number of bits to check and clear is a matter that 1635 * should be tested and standardized at some point in the future for 1636 * optimal aging of shared pages. 1637 */ 1638int 1639moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1640{ 1641 1642 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1643 ("moea64_ts_referenced: page %p is not managed", m)); 1644 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1645} 1646 1647/* 1648 * Modify the WIMG settings of all mappings for a page. 1649 */ 1650void 1651moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1652{ 1653 struct pvo_entry *pvo; 1654 struct pvo_head *pvo_head; 1655 uintptr_t pt; 1656 pmap_t pmap; 1657 uint64_t lo; 1658 1659 if ((m->oflags & VPO_UNMANAGED) != 0) { 1660 m->md.mdpg_cache_attrs = ma; 1661 return; 1662 } 1663 1664 pvo_head = vm_page_to_pvoh(m); 1665 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1666 LOCK_TABLE_RD(); 1667 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1668 pmap = pvo->pvo_pmap; 1669 PMAP_LOCK(pmap); 1670 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1671 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1672 pvo->pvo_pte.lpte.pte_lo |= lo; 1673 if (pt != -1) { 1674 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1675 pvo->pvo_vpn); 1676 if (pvo->pvo_pmap == kernel_pmap) 1677 isync(); 1678 } 1679 PMAP_UNLOCK(pmap); 1680 } 1681 UNLOCK_TABLE_RD(); 1682 m->md.mdpg_cache_attrs = ma; 1683} 1684 1685/* 1686 * Map a wired page into kernel virtual address space. 1687 */ 1688void 1689moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1690{ 1691 uint64_t pte_lo; 1692 int error; 1693 1694 pte_lo = moea64_calc_wimg(pa, ma); 1695 1696 LOCK_TABLE_WR(); 1697 PMAP_LOCK(kernel_pmap); 1698 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1699 NULL, va, pa, pte_lo, PVO_WIRED); 1700 PMAP_UNLOCK(kernel_pmap); 1701 UNLOCK_TABLE_WR(); 1702 1703 if (error != 0 && error != ENOENT) 1704 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1705 pa, error); 1706} 1707 1708void 1709moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1710{ 1711 1712 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1713} 1714 1715/* 1716 * Extract the physical page address associated with the given kernel virtual 1717 * address. 1718 */ 1719vm_paddr_t 1720moea64_kextract(mmu_t mmu, vm_offset_t va) 1721{ 1722 struct pvo_entry *pvo; 1723 vm_paddr_t pa; 1724 1725 /* 1726 * Shortcut the direct-mapped case when applicable. We never put 1727 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1728 */ 1729 if (va < VM_MIN_KERNEL_ADDRESS) 1730 return (va); 1731 1732 PMAP_LOCK(kernel_pmap); 1733 pvo = moea64_pvo_find_va(kernel_pmap, va); 1734 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1735 va)); 1736 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1737 PMAP_UNLOCK(kernel_pmap); 1738 return (pa); 1739} 1740 1741/* 1742 * Remove a wired page from kernel virtual address space. 1743 */ 1744void 1745moea64_kremove(mmu_t mmu, vm_offset_t va) 1746{ 1747 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1748} 1749 1750/* 1751 * Map a range of physical addresses into kernel virtual address space. 1752 * 1753 * The value passed in *virt is a suggested virtual address for the mapping. 1754 * Architectures which can support a direct-mapped physical to virtual region 1755 * can return the appropriate address within that region, leaving '*virt' 1756 * unchanged. We cannot and therefore do not; *virt is updated with the 1757 * first usable address after the mapped region. 1758 */ 1759vm_offset_t 1760moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1761 vm_paddr_t pa_end, int prot) 1762{ 1763 vm_offset_t sva, va; 1764 1765 sva = *virt; 1766 va = sva; 1767 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1768 moea64_kenter(mmu, va, pa_start); 1769 *virt = va; 1770 1771 return (sva); 1772} 1773 1774/* 1775 * Returns true if the pmap's pv is one of the first 1776 * 16 pvs linked to from this page. This count may 1777 * be changed upwards or downwards in the future; it 1778 * is only necessary that true be returned for a small 1779 * subset of pmaps for proper page aging. 1780 */ 1781boolean_t 1782moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1783{ 1784 int loops; 1785 struct pvo_entry *pvo; 1786 boolean_t rv; 1787 1788 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1789 ("moea64_page_exists_quick: page %p is not managed", m)); 1790 loops = 0; 1791 rv = FALSE; 1792 LOCK_TABLE_RD(); 1793 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1794 if (pvo->pvo_pmap == pmap) { 1795 rv = TRUE; 1796 break; 1797 } 1798 if (++loops >= 16) 1799 break; 1800 } 1801 UNLOCK_TABLE_RD(); 1802 return (rv); 1803} 1804 1805/* 1806 * Return the number of managed mappings to the given physical page 1807 * that are wired. 1808 */ 1809int 1810moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1811{ 1812 struct pvo_entry *pvo; 1813 int count; 1814 1815 count = 0; 1816 if ((m->oflags & VPO_UNMANAGED) != 0) 1817 return (count); 1818 LOCK_TABLE_RD(); 1819 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1820 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1821 count++; 1822 UNLOCK_TABLE_RD(); 1823 return (count); 1824} 1825 1826static uintptr_t moea64_vsidcontext; 1827 1828uintptr_t 1829moea64_get_unique_vsid(void) { 1830 u_int entropy; 1831 register_t hash; 1832 uint32_t mask; 1833 int i; 1834 1835 entropy = 0; 1836 __asm __volatile("mftb %0" : "=r"(entropy)); 1837 1838 mtx_lock(&moea64_slb_mutex); 1839 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1840 u_int n; 1841 1842 /* 1843 * Create a new value by mutiplying by a prime and adding in 1844 * entropy from the timebase register. This is to make the 1845 * VSID more random so that the PT hash function collides 1846 * less often. (Note that the prime casues gcc to do shifts 1847 * instead of a multiply.) 1848 */ 1849 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1850 hash = moea64_vsidcontext & (NVSIDS - 1); 1851 if (hash == 0) /* 0 is special, avoid it */ 1852 continue; 1853 n = hash >> 5; 1854 mask = 1 << (hash & (VSID_NBPW - 1)); 1855 hash = (moea64_vsidcontext & VSID_HASHMASK); 1856 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1857 /* anything free in this bucket? */ 1858 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1859 entropy = (moea64_vsidcontext >> 20); 1860 continue; 1861 } 1862 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1863 mask = 1 << i; 1864 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1865 hash |= i; 1866 } 1867 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1868 ("Allocating in-use VSID %#zx\n", hash)); 1869 moea64_vsid_bitmap[n] |= mask; 1870 mtx_unlock(&moea64_slb_mutex); 1871 return (hash); 1872 } 1873 1874 mtx_unlock(&moea64_slb_mutex); 1875 panic("%s: out of segments",__func__); 1876} 1877 1878#ifdef __powerpc64__ 1879void 1880moea64_pinit(mmu_t mmu, pmap_t pmap) 1881{ 1882 PMAP_LOCK_INIT(pmap); 1883 RB_INIT(&pmap->pmap_pvo); 1884 1885 pmap->pm_slb_tree_root = slb_alloc_tree(); 1886 pmap->pm_slb = slb_alloc_user_cache(); 1887 pmap->pm_slb_len = 0; 1888} 1889#else 1890void 1891moea64_pinit(mmu_t mmu, pmap_t pmap) 1892{ 1893 int i; 1894 uint32_t hash; 1895 1896 PMAP_LOCK_INIT(pmap); 1897 RB_INIT(&pmap->pmap_pvo); 1898 1899 if (pmap_bootstrapped) 1900 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1901 (vm_offset_t)pmap); 1902 else 1903 pmap->pmap_phys = pmap; 1904 1905 /* 1906 * Allocate some segment registers for this pmap. 1907 */ 1908 hash = moea64_get_unique_vsid(); 1909 1910 for (i = 0; i < 16; i++) 1911 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1912 1913 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1914} 1915#endif 1916 1917/* 1918 * Initialize the pmap associated with process 0. 1919 */ 1920void 1921moea64_pinit0(mmu_t mmu, pmap_t pm) 1922{ 1923 moea64_pinit(mmu, pm); 1924 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1925} 1926 1927/* 1928 * Set the physical protection on the specified range of this map as requested. 1929 */ 1930static void 1931moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 1932{ 1933 uintptr_t pt; 1934 struct vm_page *pg; 1935 uint64_t oldlo; 1936 1937 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1938 1939 /* 1940 * Grab the PTE pointer before we diddle with the cached PTE 1941 * copy. 1942 */ 1943 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1944 1945 /* 1946 * Change the protection of the page. 1947 */ 1948 oldlo = pvo->pvo_pte.lpte.pte_lo; 1949 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1950 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1951 if ((prot & VM_PROT_EXECUTE) == 0) 1952 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1953 if (prot & VM_PROT_WRITE) 1954 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW; 1955 else 1956 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1957 1958 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1959 1960 /* 1961 * If the PVO is in the page table, update that pte as well. 1962 */ 1963 if (pt != -1) 1964 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1965 pvo->pvo_vpn); 1966 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 1967 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1968 if ((pg->oflags & VPO_UNMANAGED) == 0) 1969 vm_page_aflag_set(pg, PGA_EXECUTABLE); 1970 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 1971 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE); 1972 } 1973 1974 /* 1975 * Update vm about the REF/CHG bits if the page is managed and we have 1976 * removed write access. 1977 */ 1978 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && 1979 (oldlo & LPTE_PP) != LPTE_BR && !(prot && VM_PROT_WRITE)) { 1980 if (pg != NULL) { 1981 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 1982 vm_page_dirty(pg); 1983 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 1984 vm_page_aflag_set(pg, PGA_REFERENCED); 1985 } 1986 } 1987} 1988 1989void 1990moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1991 vm_prot_t prot) 1992{ 1993 struct pvo_entry *pvo, *tpvo, key; 1994 1995 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 1996 sva, eva, prot); 1997 1998 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1999 ("moea64_protect: non current pmap")); 2000 2001 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2002 moea64_remove(mmu, pm, sva, eva); 2003 return; 2004 } 2005 2006 LOCK_TABLE_RD(); 2007 PMAP_LOCK(pm); 2008 key.pvo_vaddr = sva; 2009 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2010 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2011 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2012 moea64_pvo_protect(mmu, pm, pvo, prot); 2013 } 2014 UNLOCK_TABLE_RD(); 2015 PMAP_UNLOCK(pm); 2016} 2017 2018/* 2019 * Map a list of wired pages into kernel virtual address space. This is 2020 * intended for temporary mappings which do not need page modification or 2021 * references recorded. Existing mappings in the region are overwritten. 2022 */ 2023void 2024moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2025{ 2026 while (count-- > 0) { 2027 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2028 va += PAGE_SIZE; 2029 m++; 2030 } 2031} 2032 2033/* 2034 * Remove page mappings from kernel virtual address space. Intended for 2035 * temporary mappings entered by moea64_qenter. 2036 */ 2037void 2038moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2039{ 2040 while (count-- > 0) { 2041 moea64_kremove(mmu, va); 2042 va += PAGE_SIZE; 2043 } 2044} 2045 2046void 2047moea64_release_vsid(uint64_t vsid) 2048{ 2049 int idx, mask; 2050 2051 mtx_lock(&moea64_slb_mutex); 2052 idx = vsid & (NVSIDS-1); 2053 mask = 1 << (idx % VSID_NBPW); 2054 idx /= VSID_NBPW; 2055 KASSERT(moea64_vsid_bitmap[idx] & mask, 2056 ("Freeing unallocated VSID %#jx", vsid)); 2057 moea64_vsid_bitmap[idx] &= ~mask; 2058 mtx_unlock(&moea64_slb_mutex); 2059} 2060 2061 2062void 2063moea64_release(mmu_t mmu, pmap_t pmap) 2064{ 2065 2066 /* 2067 * Free segment registers' VSIDs 2068 */ 2069 #ifdef __powerpc64__ 2070 slb_free_tree(pmap); 2071 slb_free_user_cache(pmap->pm_slb); 2072 #else 2073 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2074 2075 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2076 #endif 2077 2078 PMAP_LOCK_DESTROY(pmap); 2079} 2080 2081/* 2082 * Remove all pages mapped by the specified pmap 2083 */ 2084void 2085moea64_remove_pages(mmu_t mmu, pmap_t pm) 2086{ 2087 struct pvo_entry *pvo, *tpvo; 2088 2089 LOCK_TABLE_WR(); 2090 PMAP_LOCK(pm); 2091 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2092 if (!(pvo->pvo_vaddr & PVO_WIRED)) 2093 moea64_pvo_remove(mmu, pvo); 2094 } 2095 UNLOCK_TABLE_WR(); 2096 PMAP_UNLOCK(pm); 2097} 2098 2099/* 2100 * Remove the given range of addresses from the specified map. 2101 */ 2102void 2103moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2104{ 2105 struct pvo_entry *pvo, *tpvo, key; 2106 2107 /* 2108 * Perform an unsynchronized read. This is, however, safe. 2109 */ 2110 if (pm->pm_stats.resident_count == 0) 2111 return; 2112 2113 LOCK_TABLE_WR(); 2114 PMAP_LOCK(pm); 2115 key.pvo_vaddr = sva; 2116 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2117 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2118 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2119 moea64_pvo_remove(mmu, pvo); 2120 } 2121 UNLOCK_TABLE_WR(); 2122 PMAP_UNLOCK(pm); 2123} 2124 2125/* 2126 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2127 * will reflect changes in pte's back to the vm_page. 2128 */ 2129void 2130moea64_remove_all(mmu_t mmu, vm_page_t m) 2131{ 2132 struct pvo_entry *pvo, *next_pvo; 2133 pmap_t pmap; 2134 2135 LOCK_TABLE_WR(); 2136 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2137 pmap = pvo->pvo_pmap; 2138 PMAP_LOCK(pmap); 2139 moea64_pvo_remove(mmu, pvo); 2140 PMAP_UNLOCK(pmap); 2141 } 2142 UNLOCK_TABLE_WR(); 2143 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m)) 2144 vm_page_dirty(m); 2145 vm_page_aflag_clear(m, PGA_WRITEABLE); 2146 vm_page_aflag_clear(m, PGA_EXECUTABLE); 2147} 2148 2149/* 2150 * Allocate a physical page of memory directly from the phys_avail map. 2151 * Can only be called from moea64_bootstrap before avail start and end are 2152 * calculated. 2153 */ 2154vm_offset_t 2155moea64_bootstrap_alloc(vm_size_t size, u_int align) 2156{ 2157 vm_offset_t s, e; 2158 int i, j; 2159 2160 size = round_page(size); 2161 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2162 if (align != 0) 2163 s = (phys_avail[i] + align - 1) & ~(align - 1); 2164 else 2165 s = phys_avail[i]; 2166 e = s + size; 2167 2168 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2169 continue; 2170 2171 if (s + size > platform_real_maxaddr()) 2172 continue; 2173 2174 if (s == phys_avail[i]) { 2175 phys_avail[i] += size; 2176 } else if (e == phys_avail[i + 1]) { 2177 phys_avail[i + 1] -= size; 2178 } else { 2179 for (j = phys_avail_count * 2; j > i; j -= 2) { 2180 phys_avail[j] = phys_avail[j - 2]; 2181 phys_avail[j + 1] = phys_avail[j - 1]; 2182 } 2183 2184 phys_avail[i + 3] = phys_avail[i + 1]; 2185 phys_avail[i + 1] = s; 2186 phys_avail[i + 2] = e; 2187 phys_avail_count++; 2188 } 2189 2190 return (s); 2191 } 2192 panic("moea64_bootstrap_alloc: could not allocate memory"); 2193} 2194 2195static int 2196moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2197 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2198 uint64_t pte_lo, int flags) 2199{ 2200 struct pvo_entry *pvo; 2201 uint64_t vsid; 2202 int first; 2203 u_int ptegidx; 2204 int i; 2205 int bootstrap; 2206 2207 /* 2208 * One nasty thing that can happen here is that the UMA calls to 2209 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2210 * which calls UMA... 2211 * 2212 * We break the loop by detecting recursion and allocating out of 2213 * the bootstrap pool. 2214 */ 2215 2216 first = 0; 2217 bootstrap = (flags & PVO_BOOTSTRAP); 2218 2219 if (!moea64_initialized) 2220 bootstrap = 1; 2221 2222 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2223 rw_assert(&moea64_table_lock, RA_WLOCKED); 2224 2225 /* 2226 * Compute the PTE Group index. 2227 */ 2228 va &= ~ADDR_POFF; 2229 vsid = va_to_vsid(pm, va); 2230 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2231 2232 /* 2233 * Remove any existing mapping for this page. Reuse the pvo entry if 2234 * there is a mapping. 2235 */ 2236 moea64_pvo_enter_calls++; 2237 2238 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2239 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2240 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2241 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2242 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2243 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2244 /* Re-insert if spilled */ 2245 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2246 &pvo->pvo_pte.lpte); 2247 if (i >= 0) 2248 PVO_PTEGIDX_SET(pvo, i); 2249 moea64_pte_overflow--; 2250 } 2251 return (0); 2252 } 2253 moea64_pvo_remove(mmu, pvo); 2254 break; 2255 } 2256 } 2257 2258 /* 2259 * If we aren't overwriting a mapping, try to allocate. 2260 */ 2261 if (bootstrap) { 2262 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2263 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2264 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2265 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2266 } 2267 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2268 moea64_bpvo_pool_index++; 2269 bootstrap = 1; 2270 } else { 2271 pvo = uma_zalloc(zone, M_NOWAIT); 2272 } 2273 2274 if (pvo == NULL) 2275 return (ENOMEM); 2276 2277 moea64_pvo_entries++; 2278 pvo->pvo_vaddr = va; 2279 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2280 | (vsid << 16); 2281 pvo->pvo_pmap = pm; 2282 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2283 pvo->pvo_vaddr &= ~ADDR_POFF; 2284 2285 if (flags & PVO_WIRED) 2286 pvo->pvo_vaddr |= PVO_WIRED; 2287 if (pvo_head != NULL) 2288 pvo->pvo_vaddr |= PVO_MANAGED; 2289 if (bootstrap) 2290 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2291 if (flags & PVO_LARGE) 2292 pvo->pvo_vaddr |= PVO_LARGE; 2293 2294 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2295 (uint64_t)(pa) | pte_lo, flags); 2296 2297 /* 2298 * Add to pmap list 2299 */ 2300 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2301 2302 /* 2303 * Remember if the list was empty and therefore will be the first 2304 * item. 2305 */ 2306 if (pvo_head != NULL) { 2307 if (LIST_FIRST(pvo_head) == NULL) 2308 first = 1; 2309 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2310 } 2311 2312 if (pvo->pvo_vaddr & PVO_WIRED) { 2313 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2314 pm->pm_stats.wired_count++; 2315 } 2316 pm->pm_stats.resident_count++; 2317 2318 /* 2319 * We hope this succeeds but it isn't required. 2320 */ 2321 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2322 if (i >= 0) { 2323 PVO_PTEGIDX_SET(pvo, i); 2324 } else { 2325 panic("moea64_pvo_enter: overflow"); 2326 moea64_pte_overflow++; 2327 } 2328 2329 if (pm == kernel_pmap) 2330 isync(); 2331 2332#ifdef __powerpc64__ 2333 /* 2334 * Make sure all our bootstrap mappings are in the SLB as soon 2335 * as virtual memory is switched on. 2336 */ 2337 if (!pmap_bootstrapped) 2338 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2339#endif 2340 2341 return (first ? ENOENT : 0); 2342} 2343 2344static void 2345moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2346{ 2347 struct vm_page *pg; 2348 uintptr_t pt; 2349 2350 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2351 rw_assert(&moea64_table_lock, RA_WLOCKED); 2352 2353 /* 2354 * If there is an active pte entry, we need to deactivate it (and 2355 * save the ref & cfg bits). 2356 */ 2357 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2358 if (pt != -1) { 2359 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2360 PVO_PTEGIDX_CLR(pvo); 2361 } else { 2362 moea64_pte_overflow--; 2363 } 2364 2365 /* 2366 * Update our statistics. 2367 */ 2368 pvo->pvo_pmap->pm_stats.resident_count--; 2369 if (pvo->pvo_vaddr & PVO_WIRED) 2370 pvo->pvo_pmap->pm_stats.wired_count--; 2371 2372 /* 2373 * Remove this PVO from the pmap list. 2374 */ 2375 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2376 2377 /* 2378 * Remove this from the overflow list and return it to the pool 2379 * if we aren't going to reuse it. 2380 */ 2381 LIST_REMOVE(pvo, pvo_olink); 2382 2383 /* 2384 * Update vm about the REF/CHG bits if the page is managed. 2385 */ 2386 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2387 2388 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) { 2389 LIST_REMOVE(pvo, pvo_vlink); 2390 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 2391 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 2392 vm_page_dirty(pg); 2393 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 2394 vm_page_aflag_set(pg, PGA_REFERENCED); 2395 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2396 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2397 } 2398 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2399 vm_page_aflag_clear(pg, PGA_EXECUTABLE); 2400 } 2401 2402 moea64_pvo_entries--; 2403 moea64_pvo_remove_calls++; 2404 2405 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2406 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2407 moea64_upvo_zone, pvo); 2408} 2409 2410static struct pvo_entry * 2411moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2412{ 2413 struct pvo_entry key; 2414 2415 key.pvo_vaddr = va & ~ADDR_POFF; 2416 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2417} 2418 2419static boolean_t 2420moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2421{ 2422 struct pvo_entry *pvo; 2423 uintptr_t pt; 2424 2425 LOCK_TABLE_RD(); 2426 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2427 /* 2428 * See if we saved the bit off. If so, return success. 2429 */ 2430 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2431 UNLOCK_TABLE_RD(); 2432 return (TRUE); 2433 } 2434 } 2435 2436 /* 2437 * No luck, now go through the hard part of looking at the PTEs 2438 * themselves. Sync so that any pending REF/CHG bits are flushed to 2439 * the PTEs. 2440 */ 2441 powerpc_sync(); 2442 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2443 2444 /* 2445 * See if this pvo has a valid PTE. if so, fetch the 2446 * REF/CHG bits from the valid PTE. If the appropriate 2447 * ptebit is set, return success. 2448 */ 2449 PMAP_LOCK(pvo->pvo_pmap); 2450 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2451 if (pt != -1) { 2452 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2453 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2454 PMAP_UNLOCK(pvo->pvo_pmap); 2455 UNLOCK_TABLE_RD(); 2456 return (TRUE); 2457 } 2458 } 2459 PMAP_UNLOCK(pvo->pvo_pmap); 2460 } 2461 2462 UNLOCK_TABLE_RD(); 2463 return (FALSE); 2464} 2465 2466static u_int 2467moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2468{ 2469 u_int count; 2470 struct pvo_entry *pvo; 2471 uintptr_t pt; 2472 2473 /* 2474 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2475 * we can reset the right ones). note that since the pvo entries and 2476 * list heads are accessed via BAT0 and are never placed in the page 2477 * table, we don't have to worry about further accesses setting the 2478 * REF/CHG bits. 2479 */ 2480 powerpc_sync(); 2481 2482 /* 2483 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2484 * valid pte clear the ptebit from the valid pte. 2485 */ 2486 count = 0; 2487 LOCK_TABLE_RD(); 2488 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2489 PMAP_LOCK(pvo->pvo_pmap); 2490 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2491 if (pt != -1) { 2492 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2493 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2494 count++; 2495 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2496 pvo->pvo_vpn, ptebit); 2497 } 2498 } 2499 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2500 PMAP_UNLOCK(pvo->pvo_pmap); 2501 } 2502 2503 UNLOCK_TABLE_RD(); 2504 return (count); 2505} 2506 2507boolean_t 2508moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2509{ 2510 struct pvo_entry *pvo, key; 2511 vm_offset_t ppa; 2512 int error = 0; 2513 2514 PMAP_LOCK(kernel_pmap); 2515 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2516 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2517 ppa < pa + size; ppa += PAGE_SIZE, 2518 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2519 if (pvo == NULL || 2520 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2521 error = EFAULT; 2522 break; 2523 } 2524 } 2525 PMAP_UNLOCK(kernel_pmap); 2526 2527 return (error); 2528} 2529 2530/* 2531 * Map a set of physical memory pages into the kernel virtual 2532 * address space. Return a pointer to where it is mapped. This 2533 * routine is intended to be used for mapping device memory, 2534 * NOT real memory. 2535 */ 2536void * 2537moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2538{ 2539 vm_offset_t va, tmpva, ppa, offset; 2540 2541 ppa = trunc_page(pa); 2542 offset = pa & PAGE_MASK; 2543 size = roundup2(offset + size, PAGE_SIZE); 2544 2545 va = kmem_alloc_nofault(kernel_map, size); 2546 2547 if (!va) 2548 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2549 2550 for (tmpva = va; size > 0;) { 2551 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2552 size -= PAGE_SIZE; 2553 tmpva += PAGE_SIZE; 2554 ppa += PAGE_SIZE; 2555 } 2556 2557 return ((void *)(va + offset)); 2558} 2559 2560void * 2561moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2562{ 2563 2564 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2565} 2566 2567void 2568moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2569{ 2570 vm_offset_t base, offset; 2571 2572 base = trunc_page(va); 2573 offset = va & PAGE_MASK; 2574 size = roundup2(offset + size, PAGE_SIZE); 2575 2576 kmem_free(kernel_map, base, size); 2577} 2578 2579void 2580moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2581{ 2582 struct pvo_entry *pvo; 2583 vm_offset_t lim; 2584 vm_paddr_t pa; 2585 vm_size_t len; 2586 2587 PMAP_LOCK(pm); 2588 while (sz > 0) { 2589 lim = round_page(va); 2590 len = MIN(lim - va, sz); 2591 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2592 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) { 2593 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 2594 (va & ADDR_POFF); 2595 moea64_syncicache(mmu, pm, va, pa, len); 2596 } 2597 va += len; 2598 sz -= len; 2599 } 2600 PMAP_UNLOCK(pm); 2601} 2602