1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#include <sys/cdefs.h> 94__FBSDID("$FreeBSD$"); 95 96/* 97 * Manages physical address maps. 98 * 99 * Since the information managed by this module is also stored by the 100 * logical address mapping module, this module may throw away valid virtual 101 * to physical mappings at almost any time. However, invalidations of 102 * mappings must be done as requested. 103 * 104 * In order to cope with hardware architectures which make virtual to 105 * physical map invalidates expensive, this module may delay invalidate 106 * reduced protection operations until such time as they are actually 107 * necessary. This module is given full information as to which processors 108 * are currently using which maps, and to when physical maps must be made 109 * correct. 110 */ 111 112#include "opt_compat.h" 113#include "opt_kstack_pages.h" 114 115#include <sys/param.h> 116#include <sys/kernel.h> 117#include <sys/queue.h> 118#include <sys/cpuset.h> 119#include <sys/ktr.h> 120#include <sys/lock.h> 121#include <sys/msgbuf.h> 122#include <sys/malloc.h> 123#include <sys/mutex.h> 124#include <sys/proc.h> 125#include <sys/rwlock.h> 126#include <sys/sched.h> 127#include <sys/sysctl.h> 128#include <sys/systm.h> 129#include <sys/vmmeter.h> 130 131#include <sys/kdb.h> 132 133#include <dev/ofw/openfirm.h> 134 135#include <vm/vm.h> 136#include <vm/vm_param.h> 137#include <vm/vm_kern.h> 138#include <vm/vm_page.h> 139#include <vm/vm_map.h> 140#include <vm/vm_object.h> 141#include <vm/vm_extern.h> 142#include <vm/vm_pageout.h> 143#include <vm/uma.h> 144 145#include <machine/_inttypes.h> 146#include <machine/cpu.h> 147#include <machine/platform.h> 148#include <machine/frame.h> 149#include <machine/md_var.h> 150#include <machine/psl.h> 151#include <machine/bat.h> 152#include <machine/hid.h> 153#include <machine/pte.h> 154#include <machine/sr.h> 155#include <machine/trap.h> 156#include <machine/mmuvar.h> 157 158#include "mmu_oea64.h" 159#include "mmu_if.h" 160#include "moea64_if.h" 161 162void moea64_release_vsid(uint64_t vsid); 163uintptr_t moea64_get_unique_vsid(void); 164 165#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 166#define ENABLE_TRANS(msr) mtmsr(msr) 167 168#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 169#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 170#define VSID_HASH_MASK 0x0000007fffffffffULL 171 172/* 173 * Locking semantics: 174 * -- Read lock: if no modifications are being made to either the PVO lists 175 * or page table or if any modifications being made result in internal 176 * changes (e.g. wiring, protection) such that the existence of the PVOs 177 * is unchanged and they remain associated with the same pmap (in which 178 * case the changes should be protected by the pmap lock) 179 * -- Write lock: required if PTEs/PVOs are being inserted or removed. 180 */ 181 182#define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock) 183#define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock) 184#define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock) 185#define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock) 186 187struct ofw_map { 188 cell_t om_va; 189 cell_t om_len; 190 cell_t om_pa_hi; 191 cell_t om_pa_lo; 192 cell_t om_mode; 193}; 194 195/* 196 * Map of physical memory regions. 197 */ 198static struct mem_region *regions; 199static struct mem_region *pregions; 200static u_int phys_avail_count; 201static int regions_sz, pregions_sz; 202 203extern void bs_remap_earlyboot(void); 204 205/* 206 * Lock for the pteg and pvo tables. 207 */ 208struct rwlock moea64_table_lock; 209struct mtx moea64_slb_mutex; 210 211/* 212 * PTEG data. 213 */ 214u_int moea64_pteg_count; 215u_int moea64_pteg_mask; 216 217/* 218 * PVO data. 219 */ 220struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 221 222uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 223uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 224 225#define BPVO_POOL_SIZE 327680 226static struct pvo_entry *moea64_bpvo_pool; 227static int moea64_bpvo_pool_index = 0; 228 229#define VSID_NBPW (sizeof(u_int32_t) * 8) 230#ifdef __powerpc64__ 231#define NVSIDS (NPMAPS * 16) 232#define VSID_HASHMASK 0xffffffffUL 233#else 234#define NVSIDS NPMAPS 235#define VSID_HASHMASK 0xfffffUL 236#endif 237static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 238 239static boolean_t moea64_initialized = FALSE; 240 241/* 242 * Statistics. 243 */ 244u_int moea64_pte_valid = 0; 245u_int moea64_pte_overflow = 0; 246u_int moea64_pvo_entries = 0; 247u_int moea64_pvo_enter_calls = 0; 248u_int moea64_pvo_remove_calls = 0; 249SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 250 &moea64_pte_valid, 0, ""); 251SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 252 &moea64_pte_overflow, 0, ""); 253SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 254 &moea64_pvo_entries, 0, ""); 255SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 256 &moea64_pvo_enter_calls, 0, ""); 257SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 258 &moea64_pvo_remove_calls, 0, ""); 259 260vm_offset_t moea64_scratchpage_va[2]; 261struct pvo_entry *moea64_scratchpage_pvo[2]; 262uintptr_t moea64_scratchpage_pte[2]; 263struct mtx moea64_scratchpage_mtx; 264 265uint64_t moea64_large_page_mask = 0; 266uint64_t moea64_large_page_size = 0; 267int moea64_large_page_shift = 0; 268 269/* 270 * PVO calls. 271 */ 272static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 273 vm_offset_t, vm_offset_t, uint64_t, int); 274static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 275static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 276 277/* 278 * Utility routines. 279 */ 280static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 281static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 282static void moea64_kremove(mmu_t, vm_offset_t); 283static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 284 vm_offset_t pa, vm_size_t sz); 285 286/* 287 * Kernel MMU interface 288 */ 289void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 290void moea64_clear_modify(mmu_t, vm_page_t); 291void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 292void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 293 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 294void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 295void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 296 vm_prot_t); 297void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 298vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 299vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 300void moea64_init(mmu_t); 301boolean_t moea64_is_modified(mmu_t, vm_page_t); 302boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 303boolean_t moea64_is_referenced(mmu_t, vm_page_t); 304int moea64_ts_referenced(mmu_t, vm_page_t); 305vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 306boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 307int moea64_page_wired_mappings(mmu_t, vm_page_t); 308void moea64_pinit(mmu_t, pmap_t); 309void moea64_pinit0(mmu_t, pmap_t); 310void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 311void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 312void moea64_qremove(mmu_t, vm_offset_t, int); 313void moea64_release(mmu_t, pmap_t); 314void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 315void moea64_remove_pages(mmu_t, pmap_t); 316void moea64_remove_all(mmu_t, vm_page_t); 317void moea64_remove_write(mmu_t, vm_page_t); 318void moea64_zero_page(mmu_t, vm_page_t); 319void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 320void moea64_zero_page_idle(mmu_t, vm_page_t); 321void moea64_activate(mmu_t, struct thread *); 322void moea64_deactivate(mmu_t, struct thread *); 323void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 324void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 325void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 326vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 327void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 328void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 329void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 330boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 331static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 332 333static mmu_method_t moea64_methods[] = { 334 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 335 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 336 MMUMETHOD(mmu_copy_page, moea64_copy_page), 337 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 338 MMUMETHOD(mmu_enter, moea64_enter), 339 MMUMETHOD(mmu_enter_object, moea64_enter_object), 340 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 341 MMUMETHOD(mmu_extract, moea64_extract), 342 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 343 MMUMETHOD(mmu_init, moea64_init), 344 MMUMETHOD(mmu_is_modified, moea64_is_modified), 345 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 346 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 347 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 348 MMUMETHOD(mmu_map, moea64_map), 349 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 350 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 351 MMUMETHOD(mmu_pinit, moea64_pinit), 352 MMUMETHOD(mmu_pinit0, moea64_pinit0), 353 MMUMETHOD(mmu_protect, moea64_protect), 354 MMUMETHOD(mmu_qenter, moea64_qenter), 355 MMUMETHOD(mmu_qremove, moea64_qremove), 356 MMUMETHOD(mmu_release, moea64_release), 357 MMUMETHOD(mmu_remove, moea64_remove), 358 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 359 MMUMETHOD(mmu_remove_all, moea64_remove_all), 360 MMUMETHOD(mmu_remove_write, moea64_remove_write), 361 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 362 MMUMETHOD(mmu_zero_page, moea64_zero_page), 363 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 364 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 365 MMUMETHOD(mmu_activate, moea64_activate), 366 MMUMETHOD(mmu_deactivate, moea64_deactivate), 367 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 368 369 /* Internal interfaces */ 370 MMUMETHOD(mmu_mapdev, moea64_mapdev), 371 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 372 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 373 MMUMETHOD(mmu_kextract, moea64_kextract), 374 MMUMETHOD(mmu_kenter, moea64_kenter), 375 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 376 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 377 378 { 0, 0 } 379}; 380 381MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 382 383static __inline u_int 384va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 385{ 386 uint64_t hash; 387 int shift; 388 389 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 390 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 391 shift); 392 return (hash & moea64_pteg_mask); 393} 394 395static __inline struct pvo_head * 396vm_page_to_pvoh(vm_page_t m) 397{ 398 399 return (&m->md.mdpg_pvoh); 400} 401 402static __inline void 403moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 404 uint64_t pte_lo, int flags) 405{ 406 407 /* 408 * Construct a PTE. Default to IMB initially. Valid bit only gets 409 * set when the real pte is set in memory. 410 * 411 * Note: Don't set the valid bit for correct operation of tlb update. 412 */ 413 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 414 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 415 416 if (flags & PVO_LARGE) 417 pt->pte_hi |= LPTE_BIG; 418 419 pt->pte_lo = pte_lo; 420} 421 422static __inline uint64_t 423moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 424{ 425 uint64_t pte_lo; 426 int i; 427 428 if (ma != VM_MEMATTR_DEFAULT) { 429 switch (ma) { 430 case VM_MEMATTR_UNCACHEABLE: 431 return (LPTE_I | LPTE_G); 432 case VM_MEMATTR_WRITE_COMBINING: 433 case VM_MEMATTR_WRITE_BACK: 434 case VM_MEMATTR_PREFETCHABLE: 435 return (LPTE_I); 436 case VM_MEMATTR_WRITE_THROUGH: 437 return (LPTE_W | LPTE_M); 438 } 439 } 440 441 /* 442 * Assume the page is cache inhibited and access is guarded unless 443 * it's in our available memory array. 444 */ 445 pte_lo = LPTE_I | LPTE_G; 446 for (i = 0; i < pregions_sz; i++) { 447 if ((pa >= pregions[i].mr_start) && 448 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 449 pte_lo &= ~(LPTE_I | LPTE_G); 450 pte_lo |= LPTE_M; 451 break; 452 } 453 } 454 455 return pte_lo; 456} 457 458/* 459 * Quick sort callout for comparing memory regions. 460 */ 461static int om_cmp(const void *a, const void *b); 462 463static int 464om_cmp(const void *a, const void *b) 465{ 466 const struct ofw_map *mapa; 467 const struct ofw_map *mapb; 468 469 mapa = a; 470 mapb = b; 471 if (mapa->om_pa_hi < mapb->om_pa_hi) 472 return (-1); 473 else if (mapa->om_pa_hi > mapb->om_pa_hi) 474 return (1); 475 else if (mapa->om_pa_lo < mapb->om_pa_lo) 476 return (-1); 477 else if (mapa->om_pa_lo > mapb->om_pa_lo) 478 return (1); 479 else 480 return (0); 481} 482 483static void 484moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 485{ 486 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 487 register_t msr; 488 vm_offset_t off; 489 vm_paddr_t pa_base; 490 int i; 491 492 bzero(translations, sz); 493 if (OF_getprop(mmu, "translations", translations, sz) == -1) 494 panic("moea64_bootstrap: can't get ofw translations"); 495 496 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 497 sz /= sizeof(*translations); 498 qsort(translations, sz, sizeof (*translations), om_cmp); 499 500 for (i = 0; i < sz; i++) { 501 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 502 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 503 translations[i].om_len); 504 505 if (translations[i].om_pa_lo % PAGE_SIZE) 506 panic("OFW translation not page-aligned!"); 507 508 pa_base = translations[i].om_pa_lo; 509 510 #ifdef __powerpc64__ 511 pa_base += (vm_offset_t)translations[i].om_pa_hi << 32; 512 #else 513 if (translations[i].om_pa_hi) 514 panic("OFW translations above 32-bit boundary!"); 515 #endif 516 517 /* Now enter the pages for this mapping */ 518 519 DISABLE_TRANS(msr); 520 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 521 if (moea64_pvo_find_va(kernel_pmap, 522 translations[i].om_va + off) != NULL) 523 continue; 524 525 moea64_kenter(mmup, translations[i].om_va + off, 526 pa_base + off); 527 } 528 ENABLE_TRANS(msr); 529 } 530} 531 532#ifdef __powerpc64__ 533static void 534moea64_probe_large_page(void) 535{ 536 uint16_t pvr = mfpvr() >> 16; 537 538 switch (pvr) { 539 case IBM970: 540 case IBM970FX: 541 case IBM970MP: 542 powerpc_sync(); isync(); 543 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 544 powerpc_sync(); isync(); 545 546 /* FALLTHROUGH */ 547 default: 548 moea64_large_page_size = 0x1000000; /* 16 MB */ 549 moea64_large_page_shift = 24; 550 } 551 552 moea64_large_page_mask = moea64_large_page_size - 1; 553} 554 555static void 556moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 557{ 558 struct slb *cache; 559 struct slb entry; 560 uint64_t esid, slbe; 561 uint64_t i; 562 563 cache = PCPU_GET(slb); 564 esid = va >> ADDR_SR_SHFT; 565 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 566 567 for (i = 0; i < 64; i++) { 568 if (cache[i].slbe == (slbe | i)) 569 return; 570 } 571 572 entry.slbe = slbe; 573 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 574 if (large) 575 entry.slbv |= SLBV_L; 576 577 slb_insert_kernel(entry.slbe, entry.slbv); 578} 579#endif 580 581static void 582moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 583 vm_offset_t kernelend) 584{ 585 register_t msr; 586 vm_paddr_t pa; 587 vm_offset_t size, off; 588 uint64_t pte_lo; 589 int i; 590 591 if (moea64_large_page_size == 0) 592 hw_direct_map = 0; 593 594 DISABLE_TRANS(msr); 595 if (hw_direct_map) { 596 LOCK_TABLE_WR(); 597 PMAP_LOCK(kernel_pmap); 598 for (i = 0; i < pregions_sz; i++) { 599 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 600 pregions[i].mr_size; pa += moea64_large_page_size) { 601 pte_lo = LPTE_M; 602 603 /* 604 * Set memory access as guarded if prefetch within 605 * the page could exit the available physmem area. 606 */ 607 if (pa & moea64_large_page_mask) { 608 pa &= moea64_large_page_mask; 609 pte_lo |= LPTE_G; 610 } 611 if (pa + moea64_large_page_size > 612 pregions[i].mr_start + pregions[i].mr_size) 613 pte_lo |= LPTE_G; 614 615 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 616 NULL, pa, pa, pte_lo, 617 PVO_WIRED | PVO_LARGE); 618 } 619 } 620 PMAP_UNLOCK(kernel_pmap); 621 UNLOCK_TABLE_WR(); 622 } else { 623 size = sizeof(struct pvo_head) * moea64_pteg_count; 624 off = (vm_offset_t)(moea64_pvo_table); 625 for (pa = off; pa < off + size; pa += PAGE_SIZE) 626 moea64_kenter(mmup, pa, pa); 627 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 628 off = (vm_offset_t)(moea64_bpvo_pool); 629 for (pa = off; pa < off + size; pa += PAGE_SIZE) 630 moea64_kenter(mmup, pa, pa); 631 632 /* 633 * Map certain important things, like ourselves. 634 * 635 * NOTE: We do not map the exception vector space. That code is 636 * used only in real mode, and leaving it unmapped allows us to 637 * catch NULL pointer deferences, instead of making NULL a valid 638 * address. 639 */ 640 641 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 642 pa += PAGE_SIZE) 643 moea64_kenter(mmup, pa, pa); 644 } 645 ENABLE_TRANS(msr); 646 647 /* 648 * Allow user to override unmapped_buf_allowed for testing. 649 * XXXKIB Only direct map implementation was tested. 650 */ 651 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 652 &unmapped_buf_allowed)) 653 unmapped_buf_allowed = hw_direct_map; 654} 655 656void 657moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 658{ 659 int i, j; 660 vm_size_t physsz, hwphyssz; 661 662#ifndef __powerpc64__ 663 /* We don't have a direct map since there is no BAT */ 664 hw_direct_map = 0; 665 666 /* Make sure battable is zero, since we have no BAT */ 667 for (i = 0; i < 16; i++) { 668 battable[i].batu = 0; 669 battable[i].batl = 0; 670 } 671#else 672 moea64_probe_large_page(); 673 674 /* Use a direct map if we have large page support */ 675 if (moea64_large_page_size > 0) 676 hw_direct_map = 1; 677 else 678 hw_direct_map = 0; 679#endif 680 681 /* Get physical memory regions from firmware */ 682 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 683 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 684 685 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 686 panic("moea64_bootstrap: phys_avail too small"); 687 688 phys_avail_count = 0; 689 physsz = 0; 690 hwphyssz = 0; 691 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 692 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 693 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 694 regions[i].mr_start + regions[i].mr_size, 695 regions[i].mr_size); 696 if (hwphyssz != 0 && 697 (physsz + regions[i].mr_size) >= hwphyssz) { 698 if (physsz < hwphyssz) { 699 phys_avail[j] = regions[i].mr_start; 700 phys_avail[j + 1] = regions[i].mr_start + 701 hwphyssz - physsz; 702 physsz = hwphyssz; 703 phys_avail_count++; 704 } 705 break; 706 } 707 phys_avail[j] = regions[i].mr_start; 708 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 709 phys_avail_count++; 710 physsz += regions[i].mr_size; 711 } 712 713 /* Check for overlap with the kernel and exception vectors */ 714 for (j = 0; j < 2*phys_avail_count; j+=2) { 715 if (phys_avail[j] < EXC_LAST) 716 phys_avail[j] += EXC_LAST; 717 718 if (kernelstart >= phys_avail[j] && 719 kernelstart < phys_avail[j+1]) { 720 if (kernelend < phys_avail[j+1]) { 721 phys_avail[2*phys_avail_count] = 722 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 723 phys_avail[2*phys_avail_count + 1] = 724 phys_avail[j+1]; 725 phys_avail_count++; 726 } 727 728 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 729 } 730 731 if (kernelend >= phys_avail[j] && 732 kernelend < phys_avail[j+1]) { 733 if (kernelstart > phys_avail[j]) { 734 phys_avail[2*phys_avail_count] = phys_avail[j]; 735 phys_avail[2*phys_avail_count + 1] = 736 kernelstart & ~PAGE_MASK; 737 phys_avail_count++; 738 } 739 740 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 741 } 742 } 743 744 physmem = btoc(physsz); 745 746#ifdef PTEGCOUNT 747 moea64_pteg_count = PTEGCOUNT; 748#else 749 moea64_pteg_count = 0x1000; 750 751 while (moea64_pteg_count < physmem) 752 moea64_pteg_count <<= 1; 753 754 moea64_pteg_count >>= 1; 755#endif /* PTEGCOUNT */ 756} 757 758void 759moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 760{ 761 vm_size_t size; 762 register_t msr; 763 int i; 764 765 /* 766 * Set PTEG mask 767 */ 768 moea64_pteg_mask = moea64_pteg_count - 1; 769 770 /* 771 * Allocate pv/overflow lists. 772 */ 773 size = sizeof(struct pvo_head) * moea64_pteg_count; 774 775 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 776 PAGE_SIZE); 777 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 778 779 DISABLE_TRANS(msr); 780 for (i = 0; i < moea64_pteg_count; i++) 781 LIST_INIT(&moea64_pvo_table[i]); 782 ENABLE_TRANS(msr); 783 784 /* 785 * Initialize the lock that synchronizes access to the pteg and pvo 786 * tables. 787 */ 788 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE); 789 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 790 791 /* 792 * Initialise the unmanaged pvo pool. 793 */ 794 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 795 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 796 moea64_bpvo_pool_index = 0; 797 798 /* 799 * Make sure kernel vsid is allocated as well as VSID 0. 800 */ 801 #ifndef __powerpc64__ 802 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 803 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 804 moea64_vsid_bitmap[0] |= 1; 805 #endif 806 807 /* 808 * Initialize the kernel pmap (which is statically allocated). 809 */ 810 #ifdef __powerpc64__ 811 for (i = 0; i < 64; i++) { 812 pcpup->pc_slb[i].slbv = 0; 813 pcpup->pc_slb[i].slbe = 0; 814 } 815 #else 816 for (i = 0; i < 16; i++) 817 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 818 #endif 819 820 kernel_pmap->pmap_phys = kernel_pmap; 821 CPU_FILL(&kernel_pmap->pm_active); 822 RB_INIT(&kernel_pmap->pmap_pvo); 823 824 PMAP_LOCK_INIT(kernel_pmap); 825 826 /* 827 * Now map in all the other buffers we allocated earlier 828 */ 829 830 moea64_setup_direct_map(mmup, kernelstart, kernelend); 831} 832 833void 834moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 835{ 836 ihandle_t mmui; 837 phandle_t chosen; 838 phandle_t mmu; 839 size_t sz; 840 int i; 841 vm_offset_t pa, va; 842 void *dpcpu; 843 844 /* 845 * Set up the Open Firmware pmap and add its mappings if not in real 846 * mode. 847 */ 848 849 chosen = OF_finddevice("/chosen"); 850 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 851 mmu = OF_instance_to_package(mmui); 852 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1) 853 sz = 0; 854 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 855 panic("moea64_bootstrap: too many ofw translations"); 856 857 if (sz > 0) 858 moea64_add_ofw_mappings(mmup, mmu, sz); 859 } 860 861 /* 862 * Calculate the last available physical address. 863 */ 864 for (i = 0; phys_avail[i + 2] != 0; i += 2) 865 ; 866 Maxmem = powerpc_btop(phys_avail[i + 1]); 867 868 /* 869 * Initialize MMU and remap early physical mappings 870 */ 871 MMU_CPU_BOOTSTRAP(mmup,0); 872 mtmsr(mfmsr() | PSL_DR | PSL_IR); 873 pmap_bootstrapped++; 874 bs_remap_earlyboot(); 875 876 /* 877 * Set the start and end of kva. 878 */ 879 virtual_avail = VM_MIN_KERNEL_ADDRESS; 880 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 881 882 /* 883 * Map the entire KVA range into the SLB. We must not fault there. 884 */ 885 #ifdef __powerpc64__ 886 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 887 moea64_bootstrap_slb_prefault(va, 0); 888 #endif 889 890 /* 891 * Figure out how far we can extend virtual_end into segment 16 892 * without running into existing mappings. Segment 16 is guaranteed 893 * to contain neither RAM nor devices (at least on Apple hardware), 894 * but will generally contain some OFW mappings we should not 895 * step on. 896 */ 897 898 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 899 PMAP_LOCK(kernel_pmap); 900 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 901 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 902 virtual_end += PAGE_SIZE; 903 PMAP_UNLOCK(kernel_pmap); 904 #endif 905 906 /* 907 * Allocate a kernel stack with a guard page for thread0 and map it 908 * into the kernel page map. 909 */ 910 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 911 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 912 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 913 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 914 thread0.td_kstack = va; 915 thread0.td_kstack_pages = KSTACK_PAGES; 916 for (i = 0; i < KSTACK_PAGES; i++) { 917 moea64_kenter(mmup, va, pa); 918 pa += PAGE_SIZE; 919 va += PAGE_SIZE; 920 } 921 922 /* 923 * Allocate virtual address space for the message buffer. 924 */ 925 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 926 msgbufp = (struct msgbuf *)virtual_avail; 927 va = virtual_avail; 928 virtual_avail += round_page(msgbufsize); 929 while (va < virtual_avail) { 930 moea64_kenter(mmup, va, pa); 931 pa += PAGE_SIZE; 932 va += PAGE_SIZE; 933 } 934 935 /* 936 * Allocate virtual address space for the dynamic percpu area. 937 */ 938 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 939 dpcpu = (void *)virtual_avail; 940 va = virtual_avail; 941 virtual_avail += DPCPU_SIZE; 942 while (va < virtual_avail) { 943 moea64_kenter(mmup, va, pa); 944 pa += PAGE_SIZE; 945 va += PAGE_SIZE; 946 } 947 dpcpu_init(dpcpu, 0); 948 949 /* 950 * Allocate some things for page zeroing. We put this directly 951 * in the page table, marked with LPTE_LOCKED, to avoid any 952 * of the PVO book-keeping or other parts of the VM system 953 * from even knowing that this hack exists. 954 */ 955 956 if (!hw_direct_map) { 957 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 958 MTX_DEF); 959 for (i = 0; i < 2; i++) { 960 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 961 virtual_end -= PAGE_SIZE; 962 963 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 964 965 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 966 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 967 LOCK_TABLE_RD(); 968 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 969 mmup, moea64_scratchpage_pvo[i]); 970 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 971 |= LPTE_LOCKED; 972 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 973 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 974 moea64_scratchpage_pvo[i]->pvo_vpn); 975 UNLOCK_TABLE_RD(); 976 } 977 } 978} 979 980/* 981 * Activate a user pmap. The pmap must be activated before its address 982 * space can be accessed in any way. 983 */ 984void 985moea64_activate(mmu_t mmu, struct thread *td) 986{ 987 pmap_t pm; 988 989 pm = &td->td_proc->p_vmspace->vm_pmap; 990 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 991 992 #ifdef __powerpc64__ 993 PCPU_SET(userslb, pm->pm_slb); 994 #else 995 PCPU_SET(curpmap, pm->pmap_phys); 996 #endif 997} 998 999void 1000moea64_deactivate(mmu_t mmu, struct thread *td) 1001{ 1002 pmap_t pm; 1003 1004 pm = &td->td_proc->p_vmspace->vm_pmap; 1005 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1006 #ifdef __powerpc64__ 1007 PCPU_SET(userslb, NULL); 1008 #else 1009 PCPU_SET(curpmap, NULL); 1010 #endif 1011} 1012 1013void 1014moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1015{ 1016 struct pvo_entry *pvo; 1017 uintptr_t pt; 1018 uint64_t vsid; 1019 int i, ptegidx; 1020 1021 LOCK_TABLE_WR(); 1022 PMAP_LOCK(pm); 1023 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 1024 1025 if (pvo != NULL) { 1026 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1027 1028 if (wired) { 1029 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1030 pm->pm_stats.wired_count++; 1031 pvo->pvo_vaddr |= PVO_WIRED; 1032 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 1033 } else { 1034 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1035 pm->pm_stats.wired_count--; 1036 pvo->pvo_vaddr &= ~PVO_WIRED; 1037 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1038 } 1039 1040 if (pt != -1) { 1041 /* Update wiring flag in page table. */ 1042 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1043 pvo->pvo_vpn); 1044 } else if (wired) { 1045 /* 1046 * If we are wiring the page, and it wasn't in the 1047 * page table before, add it. 1048 */ 1049 vsid = PVO_VSID(pvo); 1050 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 1051 pvo->pvo_vaddr & PVO_LARGE); 1052 1053 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 1054 1055 if (i >= 0) { 1056 PVO_PTEGIDX_CLR(pvo); 1057 PVO_PTEGIDX_SET(pvo, i); 1058 } 1059 } 1060 1061 } 1062 UNLOCK_TABLE_WR(); 1063 PMAP_UNLOCK(pm); 1064} 1065 1066/* 1067 * This goes through and sets the physical address of our 1068 * special scratch PTE to the PA we want to zero or copy. Because 1069 * of locking issues (this can get called in pvo_enter() by 1070 * the UMA allocator), we can't use most other utility functions here 1071 */ 1072 1073static __inline 1074void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1075 1076 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1077 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1078 1079 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1080 ~(LPTE_WIMG | LPTE_RPGN); 1081 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1082 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1083 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1084 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1085 moea64_scratchpage_pvo[which]->pvo_vpn); 1086 isync(); 1087} 1088 1089void 1090moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1091{ 1092 vm_offset_t dst; 1093 vm_offset_t src; 1094 1095 dst = VM_PAGE_TO_PHYS(mdst); 1096 src = VM_PAGE_TO_PHYS(msrc); 1097 1098 if (hw_direct_map) { 1099 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1100 } else { 1101 mtx_lock(&moea64_scratchpage_mtx); 1102 1103 moea64_set_scratchpage_pa(mmu, 0, src); 1104 moea64_set_scratchpage_pa(mmu, 1, dst); 1105 1106 bcopy((void *)moea64_scratchpage_va[0], 1107 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1108 1109 mtx_unlock(&moea64_scratchpage_mtx); 1110 } 1111} 1112 1113static inline void 1114moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1115 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1116{ 1117 void *a_cp, *b_cp; 1118 vm_offset_t a_pg_offset, b_pg_offset; 1119 int cnt; 1120 1121 while (xfersize > 0) { 1122 a_pg_offset = a_offset & PAGE_MASK; 1123 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1124 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1125 a_pg_offset; 1126 b_pg_offset = b_offset & PAGE_MASK; 1127 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1128 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1129 b_pg_offset; 1130 bcopy(a_cp, b_cp, cnt); 1131 a_offset += cnt; 1132 b_offset += cnt; 1133 xfersize -= cnt; 1134 } 1135} 1136 1137static inline void 1138moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1139 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1140{ 1141 void *a_cp, *b_cp; 1142 vm_offset_t a_pg_offset, b_pg_offset; 1143 int cnt; 1144 1145 mtx_lock(&moea64_scratchpage_mtx); 1146 while (xfersize > 0) { 1147 a_pg_offset = a_offset & PAGE_MASK; 1148 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1149 moea64_set_scratchpage_pa(mmu, 0, 1150 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1151 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1152 b_pg_offset = b_offset & PAGE_MASK; 1153 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1154 moea64_set_scratchpage_pa(mmu, 1, 1155 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1156 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1157 bcopy(a_cp, b_cp, cnt); 1158 a_offset += cnt; 1159 b_offset += cnt; 1160 xfersize -= cnt; 1161 } 1162 mtx_unlock(&moea64_scratchpage_mtx); 1163} 1164 1165void 1166moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1167 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1168{ 1169 1170 if (hw_direct_map) { 1171 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1172 xfersize); 1173 } else { 1174 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1175 xfersize); 1176 } 1177} 1178 1179void 1180moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1181{ 1182 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1183 1184 if (size + off > PAGE_SIZE) 1185 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1186 1187 if (hw_direct_map) { 1188 bzero((caddr_t)pa + off, size); 1189 } else { 1190 mtx_lock(&moea64_scratchpage_mtx); 1191 moea64_set_scratchpage_pa(mmu, 0, pa); 1192 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1193 mtx_unlock(&moea64_scratchpage_mtx); 1194 } 1195} 1196 1197/* 1198 * Zero a page of physical memory by temporarily mapping it 1199 */ 1200void 1201moea64_zero_page(mmu_t mmu, vm_page_t m) 1202{ 1203 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1204 vm_offset_t va, off; 1205 1206 if (!hw_direct_map) { 1207 mtx_lock(&moea64_scratchpage_mtx); 1208 1209 moea64_set_scratchpage_pa(mmu, 0, pa); 1210 va = moea64_scratchpage_va[0]; 1211 } else { 1212 va = pa; 1213 } 1214 1215 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1216 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1217 1218 if (!hw_direct_map) 1219 mtx_unlock(&moea64_scratchpage_mtx); 1220} 1221 1222void 1223moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1224{ 1225 1226 moea64_zero_page(mmu, m); 1227} 1228 1229/* 1230 * Map the given physical page at the specified virtual address in the 1231 * target pmap with the protection requested. If specified the page 1232 * will be wired down. 1233 */ 1234 1235void 1236moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1237 vm_prot_t prot, boolean_t wired) 1238{ 1239 struct pvo_head *pvo_head; 1240 uma_zone_t zone; 1241 vm_page_t pg; 1242 uint64_t pte_lo; 1243 u_int pvo_flags; 1244 int error; 1245 1246 if (!moea64_initialized) { 1247 pvo_head = NULL; 1248 pg = NULL; 1249 zone = moea64_upvo_zone; 1250 pvo_flags = 0; 1251 } else { 1252 pvo_head = vm_page_to_pvoh(m); 1253 pg = m; 1254 zone = moea64_mpvo_zone; 1255 pvo_flags = PVO_MANAGED; 1256 } 1257 1258 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1259 VM_OBJECT_ASSERT_LOCKED(m->object); 1260 1261 /* XXX change the pvo head for fake pages */ 1262 if ((m->oflags & VPO_UNMANAGED) != 0) { 1263 pvo_flags &= ~PVO_MANAGED; 1264 pvo_head = NULL; 1265 zone = moea64_upvo_zone; 1266 } 1267 1268 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1269 1270 if (prot & VM_PROT_WRITE) { 1271 pte_lo |= LPTE_BW; 1272 if (pmap_bootstrapped && 1273 (m->oflags & VPO_UNMANAGED) == 0) 1274 vm_page_aflag_set(m, PGA_WRITEABLE); 1275 } else 1276 pte_lo |= LPTE_BR; 1277 1278 if ((prot & VM_PROT_EXECUTE) == 0) 1279 pte_lo |= LPTE_NOEXEC; 1280 1281 if (wired) 1282 pvo_flags |= PVO_WIRED; 1283 1284 LOCK_TABLE_WR(); 1285 PMAP_LOCK(pmap); 1286 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1287 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags); 1288 PMAP_UNLOCK(pmap); 1289 UNLOCK_TABLE_WR(); 1290 1291 /* 1292 * Flush the page from the instruction cache if this page is 1293 * mapped executable and cacheable. 1294 */ 1295 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1296 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1297 vm_page_aflag_set(m, PGA_EXECUTABLE); 1298 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1299 } 1300} 1301 1302static void 1303moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1304 vm_size_t sz) 1305{ 1306 1307 /* 1308 * This is much trickier than on older systems because 1309 * we can't sync the icache on physical addresses directly 1310 * without a direct map. Instead we check a couple of cases 1311 * where the memory is already mapped in and, failing that, 1312 * use the same trick we use for page zeroing to create 1313 * a temporary mapping for this physical address. 1314 */ 1315 1316 if (!pmap_bootstrapped) { 1317 /* 1318 * If PMAP is not bootstrapped, we are likely to be 1319 * in real mode. 1320 */ 1321 __syncicache((void *)pa, sz); 1322 } else if (pmap == kernel_pmap) { 1323 __syncicache((void *)va, sz); 1324 } else if (hw_direct_map) { 1325 __syncicache((void *)pa, sz); 1326 } else { 1327 /* Use the scratch page to set up a temp mapping */ 1328 1329 mtx_lock(&moea64_scratchpage_mtx); 1330 1331 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1332 __syncicache((void *)(moea64_scratchpage_va[1] + 1333 (va & ADDR_POFF)), sz); 1334 1335 mtx_unlock(&moea64_scratchpage_mtx); 1336 } 1337} 1338 1339/* 1340 * Maps a sequence of resident pages belonging to the same object. 1341 * The sequence begins with the given page m_start. This page is 1342 * mapped at the given virtual address start. Each subsequent page is 1343 * mapped at a virtual address that is offset from start by the same 1344 * amount as the page is offset from m_start within the object. The 1345 * last page in the sequence is the page with the largest offset from 1346 * m_start that can be mapped at a virtual address less than the given 1347 * virtual address end. Not every virtual page between start and end 1348 * is mapped; only those for which a resident page exists with the 1349 * corresponding offset from m_start are mapped. 1350 */ 1351void 1352moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1353 vm_page_t m_start, vm_prot_t prot) 1354{ 1355 vm_page_t m; 1356 vm_pindex_t diff, psize; 1357 1358 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1359 1360 psize = atop(end - start); 1361 m = m_start; 1362 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1363 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1364 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1365 m = TAILQ_NEXT(m, listq); 1366 } 1367} 1368 1369void 1370moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1371 vm_prot_t prot) 1372{ 1373 1374 moea64_enter(mmu, pm, va, m, 1375 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1376} 1377 1378vm_paddr_t 1379moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1380{ 1381 struct pvo_entry *pvo; 1382 vm_paddr_t pa; 1383 1384 PMAP_LOCK(pm); 1385 pvo = moea64_pvo_find_va(pm, va); 1386 if (pvo == NULL) 1387 pa = 0; 1388 else 1389 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1390 (va - PVO_VADDR(pvo)); 1391 PMAP_UNLOCK(pm); 1392 return (pa); 1393} 1394 1395/* 1396 * Atomically extract and hold the physical page with the given 1397 * pmap and virtual address pair if that mapping permits the given 1398 * protection. 1399 */ 1400vm_page_t 1401moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1402{ 1403 struct pvo_entry *pvo; 1404 vm_page_t m; 1405 vm_paddr_t pa; 1406 1407 m = NULL; 1408 pa = 0; 1409 PMAP_LOCK(pmap); 1410retry: 1411 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1412 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1413 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1414 (prot & VM_PROT_WRITE) == 0)) { 1415 if (vm_page_pa_tryrelock(pmap, 1416 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1417 goto retry; 1418 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1419 vm_page_hold(m); 1420 } 1421 PA_UNLOCK_COND(pa); 1422 PMAP_UNLOCK(pmap); 1423 return (m); 1424} 1425 1426static mmu_t installed_mmu; 1427 1428static void * 1429moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1430{ 1431 /* 1432 * This entire routine is a horrible hack to avoid bothering kmem 1433 * for new KVA addresses. Because this can get called from inside 1434 * kmem allocation routines, calling kmem for a new address here 1435 * can lead to multiply locking non-recursive mutexes. 1436 */ 1437 vm_offset_t va; 1438 1439 vm_page_t m; 1440 int pflags, needed_lock; 1441 1442 *flags = UMA_SLAB_PRIV; 1443 needed_lock = !PMAP_LOCKED(kernel_pmap); 1444 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED; 1445 1446 for (;;) { 1447 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1448 if (m == NULL) { 1449 if (wait & M_NOWAIT) 1450 return (NULL); 1451 VM_WAIT; 1452 } else 1453 break; 1454 } 1455 1456 va = VM_PAGE_TO_PHYS(m); 1457 1458 LOCK_TABLE_WR(); 1459 if (needed_lock) 1460 PMAP_LOCK(kernel_pmap); 1461 1462 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1463 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP); 1464 1465 if (needed_lock) 1466 PMAP_UNLOCK(kernel_pmap); 1467 UNLOCK_TABLE_WR(); 1468 1469 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1470 bzero((void *)va, PAGE_SIZE); 1471 1472 return (void *)va; 1473} 1474 1475extern int elf32_nxstack; 1476 1477void 1478moea64_init(mmu_t mmu) 1479{ 1480 1481 CTR0(KTR_PMAP, "moea64_init"); 1482 1483 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1484 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1485 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1486 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1487 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1488 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1489 1490 if (!hw_direct_map) { 1491 installed_mmu = mmu; 1492 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1493 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1494 } 1495 1496#ifdef COMPAT_FREEBSD32 1497 elf32_nxstack = 1; 1498#endif 1499 1500 moea64_initialized = TRUE; 1501} 1502 1503boolean_t 1504moea64_is_referenced(mmu_t mmu, vm_page_t m) 1505{ 1506 1507 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1508 ("moea64_is_referenced: page %p is not managed", m)); 1509 return (moea64_query_bit(mmu, m, PTE_REF)); 1510} 1511 1512boolean_t 1513moea64_is_modified(mmu_t mmu, vm_page_t m) 1514{ 1515 1516 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1517 ("moea64_is_modified: page %p is not managed", m)); 1518 1519 /* 1520 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1521 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1522 * is clear, no PTEs can have LPTE_CHG set. 1523 */ 1524 VM_OBJECT_ASSERT_LOCKED(m->object); 1525 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1526 return (FALSE); 1527 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1528} 1529 1530boolean_t 1531moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1532{ 1533 struct pvo_entry *pvo; 1534 boolean_t rv; 1535 1536 PMAP_LOCK(pmap); 1537 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1538 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1539 PMAP_UNLOCK(pmap); 1540 return (rv); 1541} 1542 1543void 1544moea64_clear_modify(mmu_t mmu, vm_page_t m) 1545{ 1546 1547 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1548 ("moea64_clear_modify: page %p is not managed", m)); 1549 VM_OBJECT_ASSERT_WLOCKED(m->object); 1550 KASSERT(!vm_page_xbusied(m), 1551 ("moea64_clear_modify: page %p is exclusive busied", m)); 1552 1553 /* 1554 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1555 * set. If the object containing the page is locked and the page is 1556 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1557 */ 1558 if ((m->aflags & PGA_WRITEABLE) == 0) 1559 return; 1560 moea64_clear_bit(mmu, m, LPTE_CHG); 1561} 1562 1563/* 1564 * Clear the write and modified bits in each of the given page's mappings. 1565 */ 1566void 1567moea64_remove_write(mmu_t mmu, vm_page_t m) 1568{ 1569 struct pvo_entry *pvo; 1570 uintptr_t pt; 1571 pmap_t pmap; 1572 uint64_t lo = 0; 1573 1574 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1575 ("moea64_remove_write: page %p is not managed", m)); 1576 1577 /* 1578 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1579 * set by another thread while the object is locked. Thus, 1580 * if PGA_WRITEABLE is clear, no page table entries need updating. 1581 */ 1582 VM_OBJECT_ASSERT_WLOCKED(m->object); 1583 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1584 return; 1585 powerpc_sync(); 1586 LOCK_TABLE_RD(); 1587 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1588 pmap = pvo->pvo_pmap; 1589 PMAP_LOCK(pmap); 1590 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1591 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1592 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1593 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1594 if (pt != -1) { 1595 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1596 lo |= pvo->pvo_pte.lpte.pte_lo; 1597 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1598 MOEA64_PTE_CHANGE(mmu, pt, 1599 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1600 if (pvo->pvo_pmap == kernel_pmap) 1601 isync(); 1602 } 1603 } 1604 if ((lo & LPTE_CHG) != 0) 1605 vm_page_dirty(m); 1606 PMAP_UNLOCK(pmap); 1607 } 1608 UNLOCK_TABLE_RD(); 1609 vm_page_aflag_clear(m, PGA_WRITEABLE); 1610} 1611 1612/* 1613 * moea64_ts_referenced: 1614 * 1615 * Return a count of reference bits for a page, clearing those bits. 1616 * It is not necessary for every reference bit to be cleared, but it 1617 * is necessary that 0 only be returned when there are truly no 1618 * reference bits set. 1619 * 1620 * XXX: The exact number of bits to check and clear is a matter that 1621 * should be tested and standardized at some point in the future for 1622 * optimal aging of shared pages. 1623 */ 1624int 1625moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1626{ 1627 1628 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1629 ("moea64_ts_referenced: page %p is not managed", m)); 1630 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1631} 1632 1633/* 1634 * Modify the WIMG settings of all mappings for a page. 1635 */ 1636void 1637moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1638{ 1639 struct pvo_entry *pvo; 1640 struct pvo_head *pvo_head; 1641 uintptr_t pt; 1642 pmap_t pmap; 1643 uint64_t lo; 1644 1645 if ((m->oflags & VPO_UNMANAGED) != 0) { 1646 m->md.mdpg_cache_attrs = ma; 1647 return; 1648 } 1649 1650 pvo_head = vm_page_to_pvoh(m); 1651 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1652 LOCK_TABLE_RD(); 1653 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1654 pmap = pvo->pvo_pmap; 1655 PMAP_LOCK(pmap); 1656 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1657 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1658 pvo->pvo_pte.lpte.pte_lo |= lo; 1659 if (pt != -1) { 1660 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1661 pvo->pvo_vpn); 1662 if (pvo->pvo_pmap == kernel_pmap) 1663 isync(); 1664 } 1665 PMAP_UNLOCK(pmap); 1666 } 1667 UNLOCK_TABLE_RD(); 1668 m->md.mdpg_cache_attrs = ma; 1669} 1670 1671/* 1672 * Map a wired page into kernel virtual address space. 1673 */ 1674void 1675moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1676{ 1677 uint64_t pte_lo; 1678 int error; 1679 1680 pte_lo = moea64_calc_wimg(pa, ma); 1681 1682 LOCK_TABLE_WR(); 1683 PMAP_LOCK(kernel_pmap); 1684 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1685 NULL, va, pa, pte_lo, PVO_WIRED); 1686 PMAP_UNLOCK(kernel_pmap); 1687 UNLOCK_TABLE_WR(); 1688 1689 if (error != 0 && error != ENOENT) 1690 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1691 pa, error); 1692} 1693 1694void 1695moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1696{ 1697 1698 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1699} 1700 1701/* 1702 * Extract the physical page address associated with the given kernel virtual 1703 * address. 1704 */ 1705vm_paddr_t 1706moea64_kextract(mmu_t mmu, vm_offset_t va) 1707{ 1708 struct pvo_entry *pvo; 1709 vm_paddr_t pa; 1710 1711 /* 1712 * Shortcut the direct-mapped case when applicable. We never put 1713 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1714 */ 1715 if (va < VM_MIN_KERNEL_ADDRESS) 1716 return (va); 1717 1718 PMAP_LOCK(kernel_pmap); 1719 pvo = moea64_pvo_find_va(kernel_pmap, va); 1720 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1721 va)); 1722 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1723 PMAP_UNLOCK(kernel_pmap); 1724 return (pa); 1725} 1726 1727/* 1728 * Remove a wired page from kernel virtual address space. 1729 */ 1730void 1731moea64_kremove(mmu_t mmu, vm_offset_t va) 1732{ 1733 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1734} 1735 1736/* 1737 * Map a range of physical addresses into kernel virtual address space. 1738 * 1739 * The value passed in *virt is a suggested virtual address for the mapping. 1740 * Architectures which can support a direct-mapped physical to virtual region 1741 * can return the appropriate address within that region, leaving '*virt' 1742 * unchanged. We cannot and therefore do not; *virt is updated with the 1743 * first usable address after the mapped region. 1744 */ 1745vm_offset_t 1746moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1747 vm_paddr_t pa_end, int prot) 1748{ 1749 vm_offset_t sva, va; 1750 1751 sva = *virt; 1752 va = sva; 1753 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1754 moea64_kenter(mmu, va, pa_start); 1755 *virt = va; 1756 1757 return (sva); 1758} 1759 1760/* 1761 * Returns true if the pmap's pv is one of the first 1762 * 16 pvs linked to from this page. This count may 1763 * be changed upwards or downwards in the future; it 1764 * is only necessary that true be returned for a small 1765 * subset of pmaps for proper page aging. 1766 */ 1767boolean_t 1768moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1769{ 1770 int loops; 1771 struct pvo_entry *pvo; 1772 boolean_t rv; 1773 1774 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1775 ("moea64_page_exists_quick: page %p is not managed", m)); 1776 loops = 0; 1777 rv = FALSE; 1778 LOCK_TABLE_RD(); 1779 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1780 if (pvo->pvo_pmap == pmap) { 1781 rv = TRUE; 1782 break; 1783 } 1784 if (++loops >= 16) 1785 break; 1786 } 1787 UNLOCK_TABLE_RD(); 1788 return (rv); 1789} 1790 1791/* 1792 * Return the number of managed mappings to the given physical page 1793 * that are wired. 1794 */ 1795int 1796moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1797{ 1798 struct pvo_entry *pvo; 1799 int count; 1800 1801 count = 0; 1802 if ((m->oflags & VPO_UNMANAGED) != 0) 1803 return (count); 1804 LOCK_TABLE_RD(); 1805 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1806 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1807 count++; 1808 UNLOCK_TABLE_RD(); 1809 return (count); 1810} 1811 1812static uintptr_t moea64_vsidcontext; 1813 1814uintptr_t 1815moea64_get_unique_vsid(void) { 1816 u_int entropy; 1817 register_t hash; 1818 uint32_t mask; 1819 int i; 1820 1821 entropy = 0; 1822 __asm __volatile("mftb %0" : "=r"(entropy)); 1823 1824 mtx_lock(&moea64_slb_mutex); 1825 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1826 u_int n; 1827 1828 /* 1829 * Create a new value by mutiplying by a prime and adding in 1830 * entropy from the timebase register. This is to make the 1831 * VSID more random so that the PT hash function collides 1832 * less often. (Note that the prime casues gcc to do shifts 1833 * instead of a multiply.) 1834 */ 1835 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1836 hash = moea64_vsidcontext & (NVSIDS - 1); 1837 if (hash == 0) /* 0 is special, avoid it */ 1838 continue; 1839 n = hash >> 5; 1840 mask = 1 << (hash & (VSID_NBPW - 1)); 1841 hash = (moea64_vsidcontext & VSID_HASHMASK); 1842 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1843 /* anything free in this bucket? */ 1844 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1845 entropy = (moea64_vsidcontext >> 20); 1846 continue; 1847 } 1848 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1849 mask = 1 << i; 1850 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1851 hash |= i; 1852 } 1853 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1854 ("Allocating in-use VSID %#zx\n", hash)); 1855 moea64_vsid_bitmap[n] |= mask; 1856 mtx_unlock(&moea64_slb_mutex); 1857 return (hash); 1858 } 1859 1860 mtx_unlock(&moea64_slb_mutex); 1861 panic("%s: out of segments",__func__); 1862} 1863 1864#ifdef __powerpc64__ 1865void 1866moea64_pinit(mmu_t mmu, pmap_t pmap) 1867{ 1868 1869 RB_INIT(&pmap->pmap_pvo); 1870 1871 pmap->pm_slb_tree_root = slb_alloc_tree(); 1872 pmap->pm_slb = slb_alloc_user_cache(); 1873 pmap->pm_slb_len = 0; 1874} 1875#else 1876void 1877moea64_pinit(mmu_t mmu, pmap_t pmap) 1878{ 1879 int i; 1880 uint32_t hash; 1881 1882 RB_INIT(&pmap->pmap_pvo); 1883 1884 if (pmap_bootstrapped) 1885 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1886 (vm_offset_t)pmap); 1887 else 1888 pmap->pmap_phys = pmap; 1889 1890 /* 1891 * Allocate some segment registers for this pmap. 1892 */ 1893 hash = moea64_get_unique_vsid(); 1894 1895 for (i = 0; i < 16; i++) 1896 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1897 1898 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1899} 1900#endif 1901 1902/* 1903 * Initialize the pmap associated with process 0. 1904 */ 1905void 1906moea64_pinit0(mmu_t mmu, pmap_t pm) 1907{ 1908 1909 PMAP_LOCK_INIT(pm); 1910 moea64_pinit(mmu, pm); 1911 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1912} 1913 1914/* 1915 * Set the physical protection on the specified range of this map as requested. 1916 */ 1917static void 1918moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 1919{ 1920 uintptr_t pt; 1921 struct vm_page *pg; 1922 uint64_t oldlo; 1923 1924 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1925 1926 /* 1927 * Grab the PTE pointer before we diddle with the cached PTE 1928 * copy. 1929 */ 1930 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1931 1932 /* 1933 * Change the protection of the page. 1934 */ 1935 oldlo = pvo->pvo_pte.lpte.pte_lo; 1936 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1937 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1938 if ((prot & VM_PROT_EXECUTE) == 0) 1939 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1940 if (prot & VM_PROT_WRITE) 1941 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW; 1942 else 1943 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1944 1945 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1946 1947 /* 1948 * If the PVO is in the page table, update that pte as well. 1949 */ 1950 if (pt != -1) 1951 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1952 pvo->pvo_vpn); 1953 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 1954 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1955 if ((pg->oflags & VPO_UNMANAGED) == 0) 1956 vm_page_aflag_set(pg, PGA_EXECUTABLE); 1957 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 1958 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE); 1959 } 1960 1961 /* 1962 * Update vm about the REF/CHG bits if the page is managed and we have 1963 * removed write access. 1964 */ 1965 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && 1966 (oldlo & LPTE_PP) != LPTE_BR && !(prot & VM_PROT_WRITE)) { 1967 if (pg != NULL) { 1968 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 1969 vm_page_dirty(pg); 1970 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 1971 vm_page_aflag_set(pg, PGA_REFERENCED); 1972 } 1973 } 1974} 1975 1976void 1977moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1978 vm_prot_t prot) 1979{ 1980 struct pvo_entry *pvo, *tpvo, key; 1981 1982 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 1983 sva, eva, prot); 1984 1985 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1986 ("moea64_protect: non current pmap")); 1987 1988 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1989 moea64_remove(mmu, pm, sva, eva); 1990 return; 1991 } 1992 1993 LOCK_TABLE_RD(); 1994 PMAP_LOCK(pm); 1995 key.pvo_vaddr = sva; 1996 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1997 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1998 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1999 moea64_pvo_protect(mmu, pm, pvo, prot); 2000 } 2001 UNLOCK_TABLE_RD(); 2002 PMAP_UNLOCK(pm); 2003} 2004 2005/* 2006 * Map a list of wired pages into kernel virtual address space. This is 2007 * intended for temporary mappings which do not need page modification or 2008 * references recorded. Existing mappings in the region are overwritten. 2009 */ 2010void 2011moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2012{ 2013 while (count-- > 0) { 2014 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2015 va += PAGE_SIZE; 2016 m++; 2017 } 2018} 2019 2020/* 2021 * Remove page mappings from kernel virtual address space. Intended for 2022 * temporary mappings entered by moea64_qenter. 2023 */ 2024void 2025moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2026{ 2027 while (count-- > 0) { 2028 moea64_kremove(mmu, va); 2029 va += PAGE_SIZE; 2030 } 2031} 2032 2033void 2034moea64_release_vsid(uint64_t vsid) 2035{ 2036 int idx, mask; 2037 2038 mtx_lock(&moea64_slb_mutex); 2039 idx = vsid & (NVSIDS-1); 2040 mask = 1 << (idx % VSID_NBPW); 2041 idx /= VSID_NBPW; 2042 KASSERT(moea64_vsid_bitmap[idx] & mask, 2043 ("Freeing unallocated VSID %#jx", vsid)); 2044 moea64_vsid_bitmap[idx] &= ~mask; 2045 mtx_unlock(&moea64_slb_mutex); 2046} 2047 2048 2049void 2050moea64_release(mmu_t mmu, pmap_t pmap) 2051{ 2052 2053 /* 2054 * Free segment registers' VSIDs 2055 */ 2056 #ifdef __powerpc64__ 2057 slb_free_tree(pmap); 2058 slb_free_user_cache(pmap->pm_slb); 2059 #else 2060 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2061 2062 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2063 #endif 2064} 2065 2066/* 2067 * Remove all pages mapped by the specified pmap 2068 */ 2069void 2070moea64_remove_pages(mmu_t mmu, pmap_t pm) 2071{ 2072 struct pvo_entry *pvo, *tpvo; 2073 2074 LOCK_TABLE_WR(); 2075 PMAP_LOCK(pm); 2076 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2077 if (!(pvo->pvo_vaddr & PVO_WIRED)) 2078 moea64_pvo_remove(mmu, pvo); 2079 } 2080 UNLOCK_TABLE_WR(); 2081 PMAP_UNLOCK(pm); 2082} 2083 2084/* 2085 * Remove the given range of addresses from the specified map. 2086 */ 2087void 2088moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2089{ 2090 struct pvo_entry *pvo, *tpvo, key; 2091 2092 /* 2093 * Perform an unsynchronized read. This is, however, safe. 2094 */ 2095 if (pm->pm_stats.resident_count == 0) 2096 return; 2097 2098 LOCK_TABLE_WR(); 2099 PMAP_LOCK(pm); 2100 key.pvo_vaddr = sva; 2101 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2102 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2103 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2104 moea64_pvo_remove(mmu, pvo); 2105 } 2106 UNLOCK_TABLE_WR(); 2107 PMAP_UNLOCK(pm); 2108} 2109 2110/* 2111 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2112 * will reflect changes in pte's back to the vm_page. 2113 */ 2114void 2115moea64_remove_all(mmu_t mmu, vm_page_t m) 2116{ 2117 struct pvo_entry *pvo, *next_pvo; 2118 pmap_t pmap; 2119 2120 LOCK_TABLE_WR(); 2121 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2122 pmap = pvo->pvo_pmap; 2123 PMAP_LOCK(pmap); 2124 moea64_pvo_remove(mmu, pvo); 2125 PMAP_UNLOCK(pmap); 2126 } 2127 UNLOCK_TABLE_WR(); 2128 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m)) 2129 vm_page_dirty(m); 2130 vm_page_aflag_clear(m, PGA_WRITEABLE); 2131 vm_page_aflag_clear(m, PGA_EXECUTABLE); 2132} 2133 2134/* 2135 * Allocate a physical page of memory directly from the phys_avail map. 2136 * Can only be called from moea64_bootstrap before avail start and end are 2137 * calculated. 2138 */ 2139vm_offset_t 2140moea64_bootstrap_alloc(vm_size_t size, u_int align) 2141{ 2142 vm_offset_t s, e; 2143 int i, j; 2144 2145 size = round_page(size); 2146 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2147 if (align != 0) 2148 s = (phys_avail[i] + align - 1) & ~(align - 1); 2149 else 2150 s = phys_avail[i]; 2151 e = s + size; 2152 2153 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2154 continue; 2155 2156 if (s + size > platform_real_maxaddr()) 2157 continue; 2158 2159 if (s == phys_avail[i]) { 2160 phys_avail[i] += size; 2161 } else if (e == phys_avail[i + 1]) { 2162 phys_avail[i + 1] -= size; 2163 } else { 2164 for (j = phys_avail_count * 2; j > i; j -= 2) { 2165 phys_avail[j] = phys_avail[j - 2]; 2166 phys_avail[j + 1] = phys_avail[j - 1]; 2167 } 2168 2169 phys_avail[i + 3] = phys_avail[i + 1]; 2170 phys_avail[i + 1] = s; 2171 phys_avail[i + 2] = e; 2172 phys_avail_count++; 2173 } 2174 2175 return (s); 2176 } 2177 panic("moea64_bootstrap_alloc: could not allocate memory"); 2178} 2179 2180static int 2181moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2182 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2183 uint64_t pte_lo, int flags) 2184{ 2185 struct pvo_entry *pvo; 2186 uint64_t vsid; 2187 int first; 2188 u_int ptegidx; 2189 int i; 2190 int bootstrap; 2191 2192 /* 2193 * One nasty thing that can happen here is that the UMA calls to 2194 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2195 * which calls UMA... 2196 * 2197 * We break the loop by detecting recursion and allocating out of 2198 * the bootstrap pool. 2199 */ 2200 2201 first = 0; 2202 bootstrap = (flags & PVO_BOOTSTRAP); 2203 2204 if (!moea64_initialized) 2205 bootstrap = 1; 2206 2207 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2208 rw_assert(&moea64_table_lock, RA_WLOCKED); 2209 2210 /* 2211 * Compute the PTE Group index. 2212 */ 2213 va &= ~ADDR_POFF; 2214 vsid = va_to_vsid(pm, va); 2215 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2216 2217 /* 2218 * Remove any existing mapping for this page. Reuse the pvo entry if 2219 * there is a mapping. 2220 */ 2221 moea64_pvo_enter_calls++; 2222 2223 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2224 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2225 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2226 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2227 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2228 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2229 /* Re-insert if spilled */ 2230 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2231 &pvo->pvo_pte.lpte); 2232 if (i >= 0) 2233 PVO_PTEGIDX_SET(pvo, i); 2234 moea64_pte_overflow--; 2235 } 2236 return (0); 2237 } 2238 moea64_pvo_remove(mmu, pvo); 2239 break; 2240 } 2241 } 2242 2243 /* 2244 * If we aren't overwriting a mapping, try to allocate. 2245 */ 2246 if (bootstrap) { 2247 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2248 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2249 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2250 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2251 } 2252 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2253 moea64_bpvo_pool_index++; 2254 bootstrap = 1; 2255 } else { 2256 pvo = uma_zalloc(zone, M_NOWAIT); 2257 } 2258 2259 if (pvo == NULL) 2260 return (ENOMEM); 2261 2262 moea64_pvo_entries++; 2263 pvo->pvo_vaddr = va; 2264 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2265 | (vsid << 16); 2266 pvo->pvo_pmap = pm; 2267 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2268 pvo->pvo_vaddr &= ~ADDR_POFF; 2269 2270 if (flags & PVO_WIRED) 2271 pvo->pvo_vaddr |= PVO_WIRED; 2272 if (pvo_head != NULL) 2273 pvo->pvo_vaddr |= PVO_MANAGED; 2274 if (bootstrap) 2275 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2276 if (flags & PVO_LARGE) 2277 pvo->pvo_vaddr |= PVO_LARGE; 2278 2279 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2280 (uint64_t)(pa) | pte_lo, flags); 2281 2282 /* 2283 * Add to pmap list 2284 */ 2285 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2286 2287 /* 2288 * Remember if the list was empty and therefore will be the first 2289 * item. 2290 */ 2291 if (pvo_head != NULL) { 2292 if (LIST_FIRST(pvo_head) == NULL) 2293 first = 1; 2294 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2295 } 2296 2297 if (pvo->pvo_vaddr & PVO_WIRED) { 2298 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2299 pm->pm_stats.wired_count++; 2300 } 2301 pm->pm_stats.resident_count++; 2302 2303 /* 2304 * We hope this succeeds but it isn't required. 2305 */ 2306 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2307 if (i >= 0) { 2308 PVO_PTEGIDX_SET(pvo, i); 2309 } else { 2310 panic("moea64_pvo_enter: overflow"); 2311 moea64_pte_overflow++; 2312 } 2313 2314 if (pm == kernel_pmap) 2315 isync(); 2316 2317#ifdef __powerpc64__ 2318 /* 2319 * Make sure all our bootstrap mappings are in the SLB as soon 2320 * as virtual memory is switched on. 2321 */ 2322 if (!pmap_bootstrapped) 2323 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2324#endif 2325 2326 return (first ? ENOENT : 0); 2327} 2328 2329static void 2330moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2331{ 2332 struct vm_page *pg; 2333 uintptr_t pt; 2334 2335 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2336 rw_assert(&moea64_table_lock, RA_WLOCKED); 2337 2338 /* 2339 * If there is an active pte entry, we need to deactivate it (and 2340 * save the ref & cfg bits). 2341 */ 2342 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2343 if (pt != -1) { 2344 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2345 PVO_PTEGIDX_CLR(pvo); 2346 } else { 2347 moea64_pte_overflow--; 2348 } 2349 2350 /* 2351 * Update our statistics. 2352 */ 2353 pvo->pvo_pmap->pm_stats.resident_count--; 2354 if (pvo->pvo_vaddr & PVO_WIRED) 2355 pvo->pvo_pmap->pm_stats.wired_count--; 2356 2357 /* 2358 * Remove this PVO from the pmap list. 2359 */ 2360 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2361 2362 /* 2363 * Remove this from the overflow list and return it to the pool 2364 * if we aren't going to reuse it. 2365 */ 2366 LIST_REMOVE(pvo, pvo_olink); 2367 2368 /* 2369 * Update vm about the REF/CHG bits if the page is managed. 2370 */ 2371 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2372 2373 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) { 2374 LIST_REMOVE(pvo, pvo_vlink); 2375 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 2376 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 2377 vm_page_dirty(pg); 2378 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 2379 vm_page_aflag_set(pg, PGA_REFERENCED); 2380 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2381 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2382 } 2383 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2384 vm_page_aflag_clear(pg, PGA_EXECUTABLE); 2385 } 2386 2387 moea64_pvo_entries--; 2388 moea64_pvo_remove_calls++; 2389 2390 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2391 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2392 moea64_upvo_zone, pvo); 2393} 2394 2395static struct pvo_entry * 2396moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2397{ 2398 struct pvo_entry key; 2399 2400 key.pvo_vaddr = va & ~ADDR_POFF; 2401 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2402} 2403 2404static boolean_t 2405moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2406{ 2407 struct pvo_entry *pvo; 2408 uintptr_t pt; 2409 2410 LOCK_TABLE_RD(); 2411 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2412 /* 2413 * See if we saved the bit off. If so, return success. 2414 */ 2415 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2416 UNLOCK_TABLE_RD(); 2417 return (TRUE); 2418 } 2419 } 2420 2421 /* 2422 * No luck, now go through the hard part of looking at the PTEs 2423 * themselves. Sync so that any pending REF/CHG bits are flushed to 2424 * the PTEs. 2425 */ 2426 powerpc_sync(); 2427 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2428 2429 /* 2430 * See if this pvo has a valid PTE. if so, fetch the 2431 * REF/CHG bits from the valid PTE. If the appropriate 2432 * ptebit is set, return success. 2433 */ 2434 PMAP_LOCK(pvo->pvo_pmap); 2435 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2436 if (pt != -1) { 2437 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2438 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2439 PMAP_UNLOCK(pvo->pvo_pmap); 2440 UNLOCK_TABLE_RD(); 2441 return (TRUE); 2442 } 2443 } 2444 PMAP_UNLOCK(pvo->pvo_pmap); 2445 } 2446 2447 UNLOCK_TABLE_RD(); 2448 return (FALSE); 2449} 2450 2451static u_int 2452moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2453{ 2454 u_int count; 2455 struct pvo_entry *pvo; 2456 uintptr_t pt; 2457 2458 /* 2459 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2460 * we can reset the right ones). note that since the pvo entries and 2461 * list heads are accessed via BAT0 and are never placed in the page 2462 * table, we don't have to worry about further accesses setting the 2463 * REF/CHG bits. 2464 */ 2465 powerpc_sync(); 2466 2467 /* 2468 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2469 * valid pte clear the ptebit from the valid pte. 2470 */ 2471 count = 0; 2472 LOCK_TABLE_RD(); 2473 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2474 PMAP_LOCK(pvo->pvo_pmap); 2475 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2476 if (pt != -1) { 2477 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2478 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2479 count++; 2480 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2481 pvo->pvo_vpn, ptebit); 2482 } 2483 } 2484 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2485 PMAP_UNLOCK(pvo->pvo_pmap); 2486 } 2487 2488 UNLOCK_TABLE_RD(); 2489 return (count); 2490} 2491 2492boolean_t 2493moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2494{ 2495 struct pvo_entry *pvo, key; 2496 vm_offset_t ppa; 2497 int error = 0; 2498 2499 PMAP_LOCK(kernel_pmap); 2500 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2501 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2502 ppa < pa + size; ppa += PAGE_SIZE, 2503 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2504 if (pvo == NULL || 2505 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2506 error = EFAULT; 2507 break; 2508 } 2509 } 2510 PMAP_UNLOCK(kernel_pmap); 2511 2512 return (error); 2513} 2514 2515/* 2516 * Map a set of physical memory pages into the kernel virtual 2517 * address space. Return a pointer to where it is mapped. This 2518 * routine is intended to be used for mapping device memory, 2519 * NOT real memory. 2520 */ 2521void * 2522moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2523{ 2524 vm_offset_t va, tmpva, ppa, offset; 2525 2526 ppa = trunc_page(pa); 2527 offset = pa & PAGE_MASK; 2528 size = roundup2(offset + size, PAGE_SIZE); 2529 2530 va = kva_alloc(size); 2531 2532 if (!va) 2533 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2534 2535 for (tmpva = va; size > 0;) { 2536 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2537 size -= PAGE_SIZE; 2538 tmpva += PAGE_SIZE; 2539 ppa += PAGE_SIZE; 2540 } 2541 2542 return ((void *)(va + offset)); 2543} 2544 2545void * 2546moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2547{ 2548 2549 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2550} 2551 2552void 2553moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2554{ 2555 vm_offset_t base, offset; 2556 2557 base = trunc_page(va); 2558 offset = va & PAGE_MASK; 2559 size = roundup2(offset + size, PAGE_SIZE); 2560 2561 kva_free(base, size); 2562} 2563 2564void 2565moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2566{ 2567 struct pvo_entry *pvo; 2568 vm_offset_t lim; 2569 vm_paddr_t pa; 2570 vm_size_t len; 2571 2572 PMAP_LOCK(pm); 2573 while (sz > 0) { 2574 lim = round_page(va); 2575 len = MIN(lim - va, sz); 2576 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2577 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) { 2578 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 2579 (va & ADDR_POFF); 2580 moea64_syncicache(mmu, pm, va, pa, len); 2581 } 2582 va += len; 2583 sz -= len; 2584 } 2585 PMAP_UNLOCK(pm); 2586} 2587