mmu_oea64.c revision 236019
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#include <sys/cdefs.h> 94__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea64.c 236019 2012-05-25 18:17:26Z raj $"); 95 96/* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117#include "opt_compat.h" 118#include "opt_kstack_pages.h" 119 120#include <sys/param.h> 121#include <sys/kernel.h> 122#include <sys/queue.h> 123#include <sys/cpuset.h> 124#include <sys/ktr.h> 125#include <sys/lock.h> 126#include <sys/msgbuf.h> 127#include <sys/mutex.h> 128#include <sys/proc.h> 129#include <sys/rwlock.h> 130#include <sys/sched.h> 131#include <sys/sysctl.h> 132#include <sys/systm.h> 133#include <sys/vmmeter.h> 134 135#include <sys/kdb.h> 136 137#include <dev/ofw/openfirm.h> 138 139#include <vm/vm.h> 140#include <vm/vm_param.h> 141#include <vm/vm_kern.h> 142#include <vm/vm_page.h> 143#include <vm/vm_map.h> 144#include <vm/vm_object.h> 145#include <vm/vm_extern.h> 146#include <vm/vm_pageout.h> 147#include <vm/vm_pager.h> 148#include <vm/uma.h> 149 150#include <machine/_inttypes.h> 151#include <machine/cpu.h> 152#include <machine/platform.h> 153#include <machine/frame.h> 154#include <machine/md_var.h> 155#include <machine/psl.h> 156#include <machine/bat.h> 157#include <machine/hid.h> 158#include <machine/pte.h> 159#include <machine/sr.h> 160#include <machine/trap.h> 161#include <machine/mmuvar.h> 162 163#include "mmu_oea64.h" 164#include "mmu_if.h" 165#include "moea64_if.h" 166 167void moea64_release_vsid(uint64_t vsid); 168uintptr_t moea64_get_unique_vsid(void); 169 170#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 171#define ENABLE_TRANS(msr) mtmsr(msr) 172 173#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 174#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 175#define VSID_HASH_MASK 0x0000007fffffffffULL 176 177/* 178 * Locking semantics: 179 * -- Read lock: if no modifications are being made to either the PVO lists 180 * or page table or if any modifications being made result in internal 181 * changes (e.g. wiring, protection) such that the existence of the PVOs 182 * is unchanged and they remain associated with the same pmap (in which 183 * case the changes should be protected by the pmap lock) 184 * -- Write lock: required if PTEs/PVOs are being inserted or removed. 185 */ 186 187#define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock) 188#define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock) 189#define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock) 190#define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock) 191 192struct ofw_map { 193 cell_t om_va; 194 cell_t om_len; 195 cell_t om_pa_hi; 196 cell_t om_pa_lo; 197 cell_t om_mode; 198}; 199 200/* 201 * Map of physical memory regions. 202 */ 203static struct mem_region *regions; 204static struct mem_region *pregions; 205static u_int phys_avail_count; 206static int regions_sz, pregions_sz; 207 208extern void bs_remap_earlyboot(void); 209 210/* 211 * Lock for the pteg and pvo tables. 212 */ 213struct rwlock moea64_table_lock; 214struct mtx moea64_slb_mutex; 215 216/* 217 * PTEG data. 218 */ 219u_int moea64_pteg_count; 220u_int moea64_pteg_mask; 221 222/* 223 * PVO data. 224 */ 225struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 226 227uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 228uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 229 230#define BPVO_POOL_SIZE 327680 231static struct pvo_entry *moea64_bpvo_pool; 232static int moea64_bpvo_pool_index = 0; 233 234#define VSID_NBPW (sizeof(u_int32_t) * 8) 235#ifdef __powerpc64__ 236#define NVSIDS (NPMAPS * 16) 237#define VSID_HASHMASK 0xffffffffUL 238#else 239#define NVSIDS NPMAPS 240#define VSID_HASHMASK 0xfffffUL 241#endif 242static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 243 244static boolean_t moea64_initialized = FALSE; 245 246/* 247 * Statistics. 248 */ 249u_int moea64_pte_valid = 0; 250u_int moea64_pte_overflow = 0; 251u_int moea64_pvo_entries = 0; 252u_int moea64_pvo_enter_calls = 0; 253u_int moea64_pvo_remove_calls = 0; 254SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 255 &moea64_pte_valid, 0, ""); 256SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 257 &moea64_pte_overflow, 0, ""); 258SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 259 &moea64_pvo_entries, 0, ""); 260SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 261 &moea64_pvo_enter_calls, 0, ""); 262SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 263 &moea64_pvo_remove_calls, 0, ""); 264 265vm_offset_t moea64_scratchpage_va[2]; 266struct pvo_entry *moea64_scratchpage_pvo[2]; 267uintptr_t moea64_scratchpage_pte[2]; 268struct mtx moea64_scratchpage_mtx; 269 270uint64_t moea64_large_page_mask = 0; 271int moea64_large_page_size = 0; 272int moea64_large_page_shift = 0; 273 274/* 275 * PVO calls. 276 */ 277static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 278 vm_offset_t, vm_offset_t, uint64_t, int); 279static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 280static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 281 282/* 283 * Utility routines. 284 */ 285static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 286static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 287static void moea64_kremove(mmu_t, vm_offset_t); 288static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 289 vm_offset_t pa, vm_size_t sz); 290 291/* 292 * Kernel MMU interface 293 */ 294void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 295void moea64_clear_modify(mmu_t, vm_page_t); 296void moea64_clear_reference(mmu_t, vm_page_t); 297void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 298void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 299void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 300 vm_prot_t); 301void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 302vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 303vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 304void moea64_init(mmu_t); 305boolean_t moea64_is_modified(mmu_t, vm_page_t); 306boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 307boolean_t moea64_is_referenced(mmu_t, vm_page_t); 308boolean_t moea64_ts_referenced(mmu_t, vm_page_t); 309vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 310boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 311int moea64_page_wired_mappings(mmu_t, vm_page_t); 312void moea64_pinit(mmu_t, pmap_t); 313void moea64_pinit0(mmu_t, pmap_t); 314void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 315void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 316void moea64_qremove(mmu_t, vm_offset_t, int); 317void moea64_release(mmu_t, pmap_t); 318void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 319void moea64_remove_pages(mmu_t, pmap_t); 320void moea64_remove_all(mmu_t, vm_page_t); 321void moea64_remove_write(mmu_t, vm_page_t); 322void moea64_zero_page(mmu_t, vm_page_t); 323void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 324void moea64_zero_page_idle(mmu_t, vm_page_t); 325void moea64_activate(mmu_t, struct thread *); 326void moea64_deactivate(mmu_t, struct thread *); 327void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 328void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 329void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 330vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 331void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 332void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 333void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 334boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 335static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 336 337static mmu_method_t moea64_methods[] = { 338 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 339 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 340 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 341 MMUMETHOD(mmu_copy_page, moea64_copy_page), 342 MMUMETHOD(mmu_enter, moea64_enter), 343 MMUMETHOD(mmu_enter_object, moea64_enter_object), 344 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 345 MMUMETHOD(mmu_extract, moea64_extract), 346 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 347 MMUMETHOD(mmu_init, moea64_init), 348 MMUMETHOD(mmu_is_modified, moea64_is_modified), 349 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 350 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 351 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 352 MMUMETHOD(mmu_map, moea64_map), 353 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 354 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 355 MMUMETHOD(mmu_pinit, moea64_pinit), 356 MMUMETHOD(mmu_pinit0, moea64_pinit0), 357 MMUMETHOD(mmu_protect, moea64_protect), 358 MMUMETHOD(mmu_qenter, moea64_qenter), 359 MMUMETHOD(mmu_qremove, moea64_qremove), 360 MMUMETHOD(mmu_release, moea64_release), 361 MMUMETHOD(mmu_remove, moea64_remove), 362 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 363 MMUMETHOD(mmu_remove_all, moea64_remove_all), 364 MMUMETHOD(mmu_remove_write, moea64_remove_write), 365 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 366 MMUMETHOD(mmu_zero_page, moea64_zero_page), 367 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 368 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 369 MMUMETHOD(mmu_activate, moea64_activate), 370 MMUMETHOD(mmu_deactivate, moea64_deactivate), 371 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 372 373 /* Internal interfaces */ 374 MMUMETHOD(mmu_mapdev, moea64_mapdev), 375 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 376 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 377 MMUMETHOD(mmu_kextract, moea64_kextract), 378 MMUMETHOD(mmu_kenter, moea64_kenter), 379 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 380 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 381 382 { 0, 0 } 383}; 384 385MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 386 387static __inline u_int 388va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 389{ 390 uint64_t hash; 391 int shift; 392 393 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 394 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 395 shift); 396 return (hash & moea64_pteg_mask); 397} 398 399static __inline struct pvo_head * 400vm_page_to_pvoh(vm_page_t m) 401{ 402 403 return (&m->md.mdpg_pvoh); 404} 405 406static __inline void 407moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 408 uint64_t pte_lo, int flags) 409{ 410 411 /* 412 * Construct a PTE. Default to IMB initially. Valid bit only gets 413 * set when the real pte is set in memory. 414 * 415 * Note: Don't set the valid bit for correct operation of tlb update. 416 */ 417 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 418 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 419 420 if (flags & PVO_LARGE) 421 pt->pte_hi |= LPTE_BIG; 422 423 pt->pte_lo = pte_lo; 424} 425 426static __inline uint64_t 427moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 428{ 429 uint64_t pte_lo; 430 int i; 431 432 if (ma != VM_MEMATTR_DEFAULT) { 433 switch (ma) { 434 case VM_MEMATTR_UNCACHEABLE: 435 return (LPTE_I | LPTE_G); 436 case VM_MEMATTR_WRITE_COMBINING: 437 case VM_MEMATTR_WRITE_BACK: 438 case VM_MEMATTR_PREFETCHABLE: 439 return (LPTE_I); 440 case VM_MEMATTR_WRITE_THROUGH: 441 return (LPTE_W | LPTE_M); 442 } 443 } 444 445 /* 446 * Assume the page is cache inhibited and access is guarded unless 447 * it's in our available memory array. 448 */ 449 pte_lo = LPTE_I | LPTE_G; 450 for (i = 0; i < pregions_sz; i++) { 451 if ((pa >= pregions[i].mr_start) && 452 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 453 pte_lo &= ~(LPTE_I | LPTE_G); 454 pte_lo |= LPTE_M; 455 break; 456 } 457 } 458 459 return pte_lo; 460} 461 462/* 463 * Quick sort callout for comparing memory regions. 464 */ 465static int om_cmp(const void *a, const void *b); 466 467static int 468om_cmp(const void *a, const void *b) 469{ 470 const struct ofw_map *mapa; 471 const struct ofw_map *mapb; 472 473 mapa = a; 474 mapb = b; 475 if (mapa->om_pa_hi < mapb->om_pa_hi) 476 return (-1); 477 else if (mapa->om_pa_hi > mapb->om_pa_hi) 478 return (1); 479 else if (mapa->om_pa_lo < mapb->om_pa_lo) 480 return (-1); 481 else if (mapa->om_pa_lo > mapb->om_pa_lo) 482 return (1); 483 else 484 return (0); 485} 486 487static void 488moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 489{ 490 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 491 register_t msr; 492 vm_offset_t off; 493 vm_paddr_t pa_base; 494 int i; 495 496 bzero(translations, sz); 497 if (OF_getprop(mmu, "translations", translations, sz) == -1) 498 panic("moea64_bootstrap: can't get ofw translations"); 499 500 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 501 sz /= sizeof(*translations); 502 qsort(translations, sz, sizeof (*translations), om_cmp); 503 504 for (i = 0; i < sz; i++) { 505 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 506 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 507 translations[i].om_len); 508 509 if (translations[i].om_pa_lo % PAGE_SIZE) 510 panic("OFW translation not page-aligned!"); 511 512 pa_base = translations[i].om_pa_lo; 513 514 #ifdef __powerpc64__ 515 pa_base += (vm_offset_t)translations[i].om_pa_hi << 32; 516 #else 517 if (translations[i].om_pa_hi) 518 panic("OFW translations above 32-bit boundary!"); 519 #endif 520 521 /* Now enter the pages for this mapping */ 522 523 DISABLE_TRANS(msr); 524 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 525 if (moea64_pvo_find_va(kernel_pmap, 526 translations[i].om_va + off) != NULL) 527 continue; 528 529 moea64_kenter(mmup, translations[i].om_va + off, 530 pa_base + off); 531 } 532 ENABLE_TRANS(msr); 533 } 534} 535 536#ifdef __powerpc64__ 537static void 538moea64_probe_large_page(void) 539{ 540 uint16_t pvr = mfpvr() >> 16; 541 542 switch (pvr) { 543 case IBM970: 544 case IBM970FX: 545 case IBM970MP: 546 powerpc_sync(); isync(); 547 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 548 powerpc_sync(); isync(); 549 550 /* FALLTHROUGH */ 551 case IBMCELLBE: 552 moea64_large_page_size = 0x1000000; /* 16 MB */ 553 moea64_large_page_shift = 24; 554 break; 555 default: 556 moea64_large_page_size = 0; 557 } 558 559 moea64_large_page_mask = moea64_large_page_size - 1; 560} 561 562static void 563moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 564{ 565 struct slb *cache; 566 struct slb entry; 567 uint64_t esid, slbe; 568 uint64_t i; 569 570 cache = PCPU_GET(slb); 571 esid = va >> ADDR_SR_SHFT; 572 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 573 574 for (i = 0; i < 64; i++) { 575 if (cache[i].slbe == (slbe | i)) 576 return; 577 } 578 579 entry.slbe = slbe; 580 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 581 if (large) 582 entry.slbv |= SLBV_L; 583 584 slb_insert_kernel(entry.slbe, entry.slbv); 585} 586#endif 587 588static void 589moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 590 vm_offset_t kernelend) 591{ 592 register_t msr; 593 vm_paddr_t pa; 594 vm_offset_t size, off; 595 uint64_t pte_lo; 596 int i; 597 598 if (moea64_large_page_size == 0) 599 hw_direct_map = 0; 600 601 DISABLE_TRANS(msr); 602 if (hw_direct_map) { 603 LOCK_TABLE_WR(); 604 PMAP_LOCK(kernel_pmap); 605 for (i = 0; i < pregions_sz; i++) { 606 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 607 pregions[i].mr_size; pa += moea64_large_page_size) { 608 pte_lo = LPTE_M; 609 610 /* 611 * Set memory access as guarded if prefetch within 612 * the page could exit the available physmem area. 613 */ 614 if (pa & moea64_large_page_mask) { 615 pa &= moea64_large_page_mask; 616 pte_lo |= LPTE_G; 617 } 618 if (pa + moea64_large_page_size > 619 pregions[i].mr_start + pregions[i].mr_size) 620 pte_lo |= LPTE_G; 621 622 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 623 NULL, pa, pa, pte_lo, 624 PVO_WIRED | PVO_LARGE); 625 } 626 } 627 PMAP_UNLOCK(kernel_pmap); 628 UNLOCK_TABLE_WR(); 629 } else { 630 size = sizeof(struct pvo_head) * moea64_pteg_count; 631 off = (vm_offset_t)(moea64_pvo_table); 632 for (pa = off; pa < off + size; pa += PAGE_SIZE) 633 moea64_kenter(mmup, pa, pa); 634 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 635 off = (vm_offset_t)(moea64_bpvo_pool); 636 for (pa = off; pa < off + size; pa += PAGE_SIZE) 637 moea64_kenter(mmup, pa, pa); 638 639 /* 640 * Map certain important things, like ourselves. 641 * 642 * NOTE: We do not map the exception vector space. That code is 643 * used only in real mode, and leaving it unmapped allows us to 644 * catch NULL pointer deferences, instead of making NULL a valid 645 * address. 646 */ 647 648 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 649 pa += PAGE_SIZE) 650 moea64_kenter(mmup, pa, pa); 651 } 652 ENABLE_TRANS(msr); 653} 654 655void 656moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 657{ 658 int i, j; 659 vm_size_t physsz, hwphyssz; 660 661#ifndef __powerpc64__ 662 /* We don't have a direct map since there is no BAT */ 663 hw_direct_map = 0; 664 665 /* Make sure battable is zero, since we have no BAT */ 666 for (i = 0; i < 16; i++) { 667 battable[i].batu = 0; 668 battable[i].batl = 0; 669 } 670#else 671 moea64_probe_large_page(); 672 673 /* Use a direct map if we have large page support */ 674 if (moea64_large_page_size > 0) 675 hw_direct_map = 1; 676 else 677 hw_direct_map = 0; 678#endif 679 680 /* Get physical memory regions from firmware */ 681 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 682 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 683 684 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 685 panic("moea64_bootstrap: phys_avail too small"); 686 687 phys_avail_count = 0; 688 physsz = 0; 689 hwphyssz = 0; 690 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 691 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 692 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 693 regions[i].mr_start + regions[i].mr_size, 694 regions[i].mr_size); 695 if (hwphyssz != 0 && 696 (physsz + regions[i].mr_size) >= hwphyssz) { 697 if (physsz < hwphyssz) { 698 phys_avail[j] = regions[i].mr_start; 699 phys_avail[j + 1] = regions[i].mr_start + 700 hwphyssz - physsz; 701 physsz = hwphyssz; 702 phys_avail_count++; 703 } 704 break; 705 } 706 phys_avail[j] = regions[i].mr_start; 707 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 708 phys_avail_count++; 709 physsz += regions[i].mr_size; 710 } 711 712 /* Check for overlap with the kernel and exception vectors */ 713 for (j = 0; j < 2*phys_avail_count; j+=2) { 714 if (phys_avail[j] < EXC_LAST) 715 phys_avail[j] += EXC_LAST; 716 717 if (kernelstart >= phys_avail[j] && 718 kernelstart < phys_avail[j+1]) { 719 if (kernelend < phys_avail[j+1]) { 720 phys_avail[2*phys_avail_count] = 721 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 722 phys_avail[2*phys_avail_count + 1] = 723 phys_avail[j+1]; 724 phys_avail_count++; 725 } 726 727 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 728 } 729 730 if (kernelend >= phys_avail[j] && 731 kernelend < phys_avail[j+1]) { 732 if (kernelstart > phys_avail[j]) { 733 phys_avail[2*phys_avail_count] = phys_avail[j]; 734 phys_avail[2*phys_avail_count + 1] = 735 kernelstart & ~PAGE_MASK; 736 phys_avail_count++; 737 } 738 739 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 740 } 741 } 742 743 physmem = btoc(physsz); 744 745#ifdef PTEGCOUNT 746 moea64_pteg_count = PTEGCOUNT; 747#else 748 moea64_pteg_count = 0x1000; 749 750 while (moea64_pteg_count < physmem) 751 moea64_pteg_count <<= 1; 752 753 moea64_pteg_count >>= 1; 754#endif /* PTEGCOUNT */ 755} 756 757void 758moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 759{ 760 vm_size_t size; 761 register_t msr; 762 int i; 763 764 /* 765 * Set PTEG mask 766 */ 767 moea64_pteg_mask = moea64_pteg_count - 1; 768 769 /* 770 * Allocate pv/overflow lists. 771 */ 772 size = sizeof(struct pvo_head) * moea64_pteg_count; 773 774 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 775 PAGE_SIZE); 776 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 777 778 DISABLE_TRANS(msr); 779 for (i = 0; i < moea64_pteg_count; i++) 780 LIST_INIT(&moea64_pvo_table[i]); 781 ENABLE_TRANS(msr); 782 783 /* 784 * Initialize the lock that synchronizes access to the pteg and pvo 785 * tables. 786 */ 787 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE); 788 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 789 790 /* 791 * Initialise the unmanaged pvo pool. 792 */ 793 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 794 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 795 moea64_bpvo_pool_index = 0; 796 797 /* 798 * Make sure kernel vsid is allocated as well as VSID 0. 799 */ 800 #ifndef __powerpc64__ 801 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 802 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 803 moea64_vsid_bitmap[0] |= 1; 804 #endif 805 806 /* 807 * Initialize the kernel pmap (which is statically allocated). 808 */ 809 #ifdef __powerpc64__ 810 for (i = 0; i < 64; i++) { 811 pcpup->pc_slb[i].slbv = 0; 812 pcpup->pc_slb[i].slbe = 0; 813 } 814 #else 815 for (i = 0; i < 16; i++) 816 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 817 #endif 818 819 kernel_pmap->pmap_phys = kernel_pmap; 820 CPU_FILL(&kernel_pmap->pm_active); 821 RB_INIT(&kernel_pmap->pmap_pvo); 822 823 PMAP_LOCK_INIT(kernel_pmap); 824 825 /* 826 * Now map in all the other buffers we allocated earlier 827 */ 828 829 moea64_setup_direct_map(mmup, kernelstart, kernelend); 830} 831 832void 833moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 834{ 835 ihandle_t mmui; 836 phandle_t chosen; 837 phandle_t mmu; 838 size_t sz; 839 int i; 840 vm_offset_t pa, va; 841 void *dpcpu; 842 843 /* 844 * Set up the Open Firmware pmap and add its mappings if not in real 845 * mode. 846 */ 847 848 chosen = OF_finddevice("/chosen"); 849 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 850 mmu = OF_instance_to_package(mmui); 851 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1) 852 sz = 0; 853 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 854 panic("moea64_bootstrap: too many ofw translations"); 855 856 if (sz > 0) 857 moea64_add_ofw_mappings(mmup, mmu, sz); 858 } 859 860 /* 861 * Calculate the last available physical address. 862 */ 863 for (i = 0; phys_avail[i + 2] != 0; i += 2) 864 ; 865 Maxmem = powerpc_btop(phys_avail[i + 1]); 866 867 /* 868 * Initialize MMU and remap early physical mappings 869 */ 870 MMU_CPU_BOOTSTRAP(mmup,0); 871 mtmsr(mfmsr() | PSL_DR | PSL_IR); 872 pmap_bootstrapped++; 873 bs_remap_earlyboot(); 874 875 /* 876 * Set the start and end of kva. 877 */ 878 virtual_avail = VM_MIN_KERNEL_ADDRESS; 879 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 880 881 /* 882 * Map the entire KVA range into the SLB. We must not fault there. 883 */ 884 #ifdef __powerpc64__ 885 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 886 moea64_bootstrap_slb_prefault(va, 0); 887 #endif 888 889 /* 890 * Figure out how far we can extend virtual_end into segment 16 891 * without running into existing mappings. Segment 16 is guaranteed 892 * to contain neither RAM nor devices (at least on Apple hardware), 893 * but will generally contain some OFW mappings we should not 894 * step on. 895 */ 896 897 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 898 PMAP_LOCK(kernel_pmap); 899 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 900 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 901 virtual_end += PAGE_SIZE; 902 PMAP_UNLOCK(kernel_pmap); 903 #endif 904 905 /* 906 * Allocate a kernel stack with a guard page for thread0 and map it 907 * into the kernel page map. 908 */ 909 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 910 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 911 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 912 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 913 thread0.td_kstack = va; 914 thread0.td_kstack_pages = KSTACK_PAGES; 915 for (i = 0; i < KSTACK_PAGES; i++) { 916 moea64_kenter(mmup, va, pa); 917 pa += PAGE_SIZE; 918 va += PAGE_SIZE; 919 } 920 921 /* 922 * Allocate virtual address space for the message buffer. 923 */ 924 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 925 msgbufp = (struct msgbuf *)virtual_avail; 926 va = virtual_avail; 927 virtual_avail += round_page(msgbufsize); 928 while (va < virtual_avail) { 929 moea64_kenter(mmup, va, pa); 930 pa += PAGE_SIZE; 931 va += PAGE_SIZE; 932 } 933 934 /* 935 * Allocate virtual address space for the dynamic percpu area. 936 */ 937 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 938 dpcpu = (void *)virtual_avail; 939 va = virtual_avail; 940 virtual_avail += DPCPU_SIZE; 941 while (va < virtual_avail) { 942 moea64_kenter(mmup, va, pa); 943 pa += PAGE_SIZE; 944 va += PAGE_SIZE; 945 } 946 dpcpu_init(dpcpu, 0); 947 948 /* 949 * Allocate some things for page zeroing. We put this directly 950 * in the page table, marked with LPTE_LOCKED, to avoid any 951 * of the PVO book-keeping or other parts of the VM system 952 * from even knowing that this hack exists. 953 */ 954 955 if (!hw_direct_map) { 956 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 957 MTX_DEF); 958 for (i = 0; i < 2; i++) { 959 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 960 virtual_end -= PAGE_SIZE; 961 962 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 963 964 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 965 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 966 LOCK_TABLE_RD(); 967 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 968 mmup, moea64_scratchpage_pvo[i]); 969 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 970 |= LPTE_LOCKED; 971 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 972 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 973 moea64_scratchpage_pvo[i]->pvo_vpn); 974 UNLOCK_TABLE_RD(); 975 } 976 } 977} 978 979/* 980 * Activate a user pmap. The pmap must be activated before its address 981 * space can be accessed in any way. 982 */ 983void 984moea64_activate(mmu_t mmu, struct thread *td) 985{ 986 pmap_t pm; 987 988 pm = &td->td_proc->p_vmspace->vm_pmap; 989 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 990 991 #ifdef __powerpc64__ 992 PCPU_SET(userslb, pm->pm_slb); 993 #else 994 PCPU_SET(curpmap, pm->pmap_phys); 995 #endif 996} 997 998void 999moea64_deactivate(mmu_t mmu, struct thread *td) 1000{ 1001 pmap_t pm; 1002 1003 pm = &td->td_proc->p_vmspace->vm_pmap; 1004 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1005 #ifdef __powerpc64__ 1006 PCPU_SET(userslb, NULL); 1007 #else 1008 PCPU_SET(curpmap, NULL); 1009 #endif 1010} 1011 1012void 1013moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1014{ 1015 struct pvo_entry *pvo; 1016 uintptr_t pt; 1017 uint64_t vsid; 1018 int i, ptegidx; 1019 1020 LOCK_TABLE_WR(); 1021 PMAP_LOCK(pm); 1022 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 1023 1024 if (pvo != NULL) { 1025 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1026 1027 if (wired) { 1028 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1029 pm->pm_stats.wired_count++; 1030 pvo->pvo_vaddr |= PVO_WIRED; 1031 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 1032 } else { 1033 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1034 pm->pm_stats.wired_count--; 1035 pvo->pvo_vaddr &= ~PVO_WIRED; 1036 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1037 } 1038 1039 if (pt != -1) { 1040 /* Update wiring flag in page table. */ 1041 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1042 pvo->pvo_vpn); 1043 } else if (wired) { 1044 /* 1045 * If we are wiring the page, and it wasn't in the 1046 * page table before, add it. 1047 */ 1048 vsid = PVO_VSID(pvo); 1049 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 1050 pvo->pvo_vaddr & PVO_LARGE); 1051 1052 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 1053 1054 if (i >= 0) { 1055 PVO_PTEGIDX_CLR(pvo); 1056 PVO_PTEGIDX_SET(pvo, i); 1057 } 1058 } 1059 1060 } 1061 UNLOCK_TABLE_WR(); 1062 PMAP_UNLOCK(pm); 1063} 1064 1065/* 1066 * This goes through and sets the physical address of our 1067 * special scratch PTE to the PA we want to zero or copy. Because 1068 * of locking issues (this can get called in pvo_enter() by 1069 * the UMA allocator), we can't use most other utility functions here 1070 */ 1071 1072static __inline 1073void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1074 1075 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1076 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1077 1078 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1079 ~(LPTE_WIMG | LPTE_RPGN); 1080 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1081 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1082 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1083 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1084 moea64_scratchpage_pvo[which]->pvo_vpn); 1085 isync(); 1086} 1087 1088void 1089moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1090{ 1091 vm_offset_t dst; 1092 vm_offset_t src; 1093 1094 dst = VM_PAGE_TO_PHYS(mdst); 1095 src = VM_PAGE_TO_PHYS(msrc); 1096 1097 if (hw_direct_map) { 1098 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1099 } else { 1100 mtx_lock(&moea64_scratchpage_mtx); 1101 1102 moea64_set_scratchpage_pa(mmu, 0, src); 1103 moea64_set_scratchpage_pa(mmu, 1, dst); 1104 1105 bcopy((void *)moea64_scratchpage_va[0], 1106 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1107 1108 mtx_unlock(&moea64_scratchpage_mtx); 1109 } 1110} 1111 1112void 1113moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1114{ 1115 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1116 1117 if (size + off > PAGE_SIZE) 1118 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1119 1120 if (hw_direct_map) { 1121 bzero((caddr_t)pa + off, size); 1122 } else { 1123 mtx_lock(&moea64_scratchpage_mtx); 1124 moea64_set_scratchpage_pa(mmu, 0, pa); 1125 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1126 mtx_unlock(&moea64_scratchpage_mtx); 1127 } 1128} 1129 1130/* 1131 * Zero a page of physical memory by temporarily mapping it 1132 */ 1133void 1134moea64_zero_page(mmu_t mmu, vm_page_t m) 1135{ 1136 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1137 vm_offset_t va, off; 1138 1139 if (!hw_direct_map) { 1140 mtx_lock(&moea64_scratchpage_mtx); 1141 1142 moea64_set_scratchpage_pa(mmu, 0, pa); 1143 va = moea64_scratchpage_va[0]; 1144 } else { 1145 va = pa; 1146 } 1147 1148 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1149 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1150 1151 if (!hw_direct_map) 1152 mtx_unlock(&moea64_scratchpage_mtx); 1153} 1154 1155void 1156moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1157{ 1158 1159 moea64_zero_page(mmu, m); 1160} 1161 1162/* 1163 * Map the given physical page at the specified virtual address in the 1164 * target pmap with the protection requested. If specified the page 1165 * will be wired down. 1166 */ 1167 1168void 1169moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1170 vm_prot_t prot, boolean_t wired) 1171{ 1172 struct pvo_head *pvo_head; 1173 uma_zone_t zone; 1174 vm_page_t pg; 1175 uint64_t pte_lo; 1176 u_int pvo_flags; 1177 int error; 1178 1179 if (!moea64_initialized) { 1180 pvo_head = NULL; 1181 pg = NULL; 1182 zone = moea64_upvo_zone; 1183 pvo_flags = 0; 1184 } else { 1185 pvo_head = vm_page_to_pvoh(m); 1186 pg = m; 1187 zone = moea64_mpvo_zone; 1188 pvo_flags = PVO_MANAGED; 1189 } 1190 1191 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 1192 VM_OBJECT_LOCKED(m->object), 1193 ("moea64_enter: page %p is not busy", m)); 1194 1195 /* XXX change the pvo head for fake pages */ 1196 if ((m->oflags & VPO_UNMANAGED) != 0) { 1197 pvo_flags &= ~PVO_MANAGED; 1198 pvo_head = NULL; 1199 zone = moea64_upvo_zone; 1200 } 1201 1202 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1203 1204 if (prot & VM_PROT_WRITE) { 1205 pte_lo |= LPTE_BW; 1206 if (pmap_bootstrapped && 1207 (m->oflags & VPO_UNMANAGED) == 0) 1208 vm_page_aflag_set(m, PGA_WRITEABLE); 1209 } else 1210 pte_lo |= LPTE_BR; 1211 1212 if ((prot & VM_PROT_EXECUTE) == 0) 1213 pte_lo |= LPTE_NOEXEC; 1214 1215 if (wired) 1216 pvo_flags |= PVO_WIRED; 1217 1218 LOCK_TABLE_WR(); 1219 PMAP_LOCK(pmap); 1220 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1221 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags); 1222 PMAP_UNLOCK(pmap); 1223 UNLOCK_TABLE_WR(); 1224 1225 /* 1226 * Flush the page from the instruction cache if this page is 1227 * mapped executable and cacheable. 1228 */ 1229 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1230 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1231 vm_page_aflag_set(m, PGA_EXECUTABLE); 1232 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1233 } 1234} 1235 1236static void 1237moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1238 vm_size_t sz) 1239{ 1240 1241 /* 1242 * This is much trickier than on older systems because 1243 * we can't sync the icache on physical addresses directly 1244 * without a direct map. Instead we check a couple of cases 1245 * where the memory is already mapped in and, failing that, 1246 * use the same trick we use for page zeroing to create 1247 * a temporary mapping for this physical address. 1248 */ 1249 1250 if (!pmap_bootstrapped) { 1251 /* 1252 * If PMAP is not bootstrapped, we are likely to be 1253 * in real mode. 1254 */ 1255 __syncicache((void *)pa, sz); 1256 } else if (pmap == kernel_pmap) { 1257 __syncicache((void *)va, sz); 1258 } else if (hw_direct_map) { 1259 __syncicache((void *)pa, sz); 1260 } else { 1261 /* Use the scratch page to set up a temp mapping */ 1262 1263 mtx_lock(&moea64_scratchpage_mtx); 1264 1265 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1266 __syncicache((void *)(moea64_scratchpage_va[1] + 1267 (va & ADDR_POFF)), sz); 1268 1269 mtx_unlock(&moea64_scratchpage_mtx); 1270 } 1271} 1272 1273/* 1274 * Maps a sequence of resident pages belonging to the same object. 1275 * The sequence begins with the given page m_start. This page is 1276 * mapped at the given virtual address start. Each subsequent page is 1277 * mapped at a virtual address that is offset from start by the same 1278 * amount as the page is offset from m_start within the object. The 1279 * last page in the sequence is the page with the largest offset from 1280 * m_start that can be mapped at a virtual address less than the given 1281 * virtual address end. Not every virtual page between start and end 1282 * is mapped; only those for which a resident page exists with the 1283 * corresponding offset from m_start are mapped. 1284 */ 1285void 1286moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1287 vm_page_t m_start, vm_prot_t prot) 1288{ 1289 vm_page_t m; 1290 vm_pindex_t diff, psize; 1291 1292 psize = atop(end - start); 1293 m = m_start; 1294 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1295 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1296 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1297 m = TAILQ_NEXT(m, listq); 1298 } 1299} 1300 1301void 1302moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1303 vm_prot_t prot) 1304{ 1305 1306 moea64_enter(mmu, pm, va, m, 1307 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1308} 1309 1310vm_paddr_t 1311moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1312{ 1313 struct pvo_entry *pvo; 1314 vm_paddr_t pa; 1315 1316 PMAP_LOCK(pm); 1317 pvo = moea64_pvo_find_va(pm, va); 1318 if (pvo == NULL) 1319 pa = 0; 1320 else 1321 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1322 (va - PVO_VADDR(pvo)); 1323 PMAP_UNLOCK(pm); 1324 return (pa); 1325} 1326 1327/* 1328 * Atomically extract and hold the physical page with the given 1329 * pmap and virtual address pair if that mapping permits the given 1330 * protection. 1331 */ 1332vm_page_t 1333moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1334{ 1335 struct pvo_entry *pvo; 1336 vm_page_t m; 1337 vm_paddr_t pa; 1338 1339 m = NULL; 1340 pa = 0; 1341 PMAP_LOCK(pmap); 1342retry: 1343 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1344 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1345 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1346 (prot & VM_PROT_WRITE) == 0)) { 1347 if (vm_page_pa_tryrelock(pmap, 1348 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1349 goto retry; 1350 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1351 vm_page_hold(m); 1352 } 1353 PA_UNLOCK_COND(pa); 1354 PMAP_UNLOCK(pmap); 1355 return (m); 1356} 1357 1358static mmu_t installed_mmu; 1359 1360static void * 1361moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1362{ 1363 /* 1364 * This entire routine is a horrible hack to avoid bothering kmem 1365 * for new KVA addresses. Because this can get called from inside 1366 * kmem allocation routines, calling kmem for a new address here 1367 * can lead to multiply locking non-recursive mutexes. 1368 */ 1369 vm_offset_t va; 1370 1371 vm_page_t m; 1372 int pflags, needed_lock; 1373 1374 *flags = UMA_SLAB_PRIV; 1375 needed_lock = !PMAP_LOCKED(kernel_pmap); 1376 1377 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1378 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1379 else 1380 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1381 if (wait & M_ZERO) 1382 pflags |= VM_ALLOC_ZERO; 1383 1384 for (;;) { 1385 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1386 if (m == NULL) { 1387 if (wait & M_NOWAIT) 1388 return (NULL); 1389 VM_WAIT; 1390 } else 1391 break; 1392 } 1393 1394 va = VM_PAGE_TO_PHYS(m); 1395 1396 LOCK_TABLE_WR(); 1397 if (needed_lock) 1398 PMAP_LOCK(kernel_pmap); 1399 1400 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1401 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP); 1402 1403 if (needed_lock) 1404 PMAP_UNLOCK(kernel_pmap); 1405 UNLOCK_TABLE_WR(); 1406 1407 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1408 bzero((void *)va, PAGE_SIZE); 1409 1410 return (void *)va; 1411} 1412 1413extern int elf32_nxstack; 1414 1415void 1416moea64_init(mmu_t mmu) 1417{ 1418 1419 CTR0(KTR_PMAP, "moea64_init"); 1420 1421 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1422 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1423 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1424 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1425 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1426 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1427 1428 if (!hw_direct_map) { 1429 installed_mmu = mmu; 1430 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1431 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1432 } 1433 1434#ifdef COMPAT_FREEBSD32 1435 elf32_nxstack = 1; 1436#endif 1437 1438 moea64_initialized = TRUE; 1439} 1440 1441boolean_t 1442moea64_is_referenced(mmu_t mmu, vm_page_t m) 1443{ 1444 1445 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1446 ("moea64_is_referenced: page %p is not managed", m)); 1447 return (moea64_query_bit(mmu, m, PTE_REF)); 1448} 1449 1450boolean_t 1451moea64_is_modified(mmu_t mmu, vm_page_t m) 1452{ 1453 1454 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1455 ("moea64_is_modified: page %p is not managed", m)); 1456 1457 /* 1458 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 1459 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1460 * is clear, no PTEs can have LPTE_CHG set. 1461 */ 1462 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1463 if ((m->oflags & VPO_BUSY) == 0 && 1464 (m->aflags & PGA_WRITEABLE) == 0) 1465 return (FALSE); 1466 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1467} 1468 1469boolean_t 1470moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1471{ 1472 struct pvo_entry *pvo; 1473 boolean_t rv; 1474 1475 PMAP_LOCK(pmap); 1476 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1477 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1478 PMAP_UNLOCK(pmap); 1479 return (rv); 1480} 1481 1482void 1483moea64_clear_reference(mmu_t mmu, vm_page_t m) 1484{ 1485 1486 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1487 ("moea64_clear_reference: page %p is not managed", m)); 1488 moea64_clear_bit(mmu, m, LPTE_REF); 1489} 1490 1491void 1492moea64_clear_modify(mmu_t mmu, vm_page_t m) 1493{ 1494 1495 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1496 ("moea64_clear_modify: page %p is not managed", m)); 1497 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1498 KASSERT((m->oflags & VPO_BUSY) == 0, 1499 ("moea64_clear_modify: page %p is busy", m)); 1500 1501 /* 1502 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1503 * set. If the object containing the page is locked and the page is 1504 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 1505 */ 1506 if ((m->aflags & PGA_WRITEABLE) == 0) 1507 return; 1508 moea64_clear_bit(mmu, m, LPTE_CHG); 1509} 1510 1511/* 1512 * Clear the write and modified bits in each of the given page's mappings. 1513 */ 1514void 1515moea64_remove_write(mmu_t mmu, vm_page_t m) 1516{ 1517 struct pvo_entry *pvo; 1518 uintptr_t pt; 1519 pmap_t pmap; 1520 uint64_t lo = 0; 1521 1522 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1523 ("moea64_remove_write: page %p is not managed", m)); 1524 1525 /* 1526 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 1527 * another thread while the object is locked. Thus, if PGA_WRITEABLE 1528 * is clear, no page table entries need updating. 1529 */ 1530 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1531 if ((m->oflags & VPO_BUSY) == 0 && 1532 (m->aflags & PGA_WRITEABLE) == 0) 1533 return; 1534 powerpc_sync(); 1535 LOCK_TABLE_RD(); 1536 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1537 pmap = pvo->pvo_pmap; 1538 PMAP_LOCK(pmap); 1539 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1540 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1541 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1542 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1543 if (pt != -1) { 1544 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1545 lo |= pvo->pvo_pte.lpte.pte_lo; 1546 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1547 MOEA64_PTE_CHANGE(mmu, pt, 1548 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1549 if (pvo->pvo_pmap == kernel_pmap) 1550 isync(); 1551 } 1552 } 1553 if ((lo & LPTE_CHG) != 0) 1554 vm_page_dirty(m); 1555 PMAP_UNLOCK(pmap); 1556 } 1557 UNLOCK_TABLE_RD(); 1558 vm_page_aflag_clear(m, PGA_WRITEABLE); 1559} 1560 1561/* 1562 * moea64_ts_referenced: 1563 * 1564 * Return a count of reference bits for a page, clearing those bits. 1565 * It is not necessary for every reference bit to be cleared, but it 1566 * is necessary that 0 only be returned when there are truly no 1567 * reference bits set. 1568 * 1569 * XXX: The exact number of bits to check and clear is a matter that 1570 * should be tested and standardized at some point in the future for 1571 * optimal aging of shared pages. 1572 */ 1573boolean_t 1574moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1575{ 1576 1577 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1578 ("moea64_ts_referenced: page %p is not managed", m)); 1579 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1580} 1581 1582/* 1583 * Modify the WIMG settings of all mappings for a page. 1584 */ 1585void 1586moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1587{ 1588 struct pvo_entry *pvo; 1589 struct pvo_head *pvo_head; 1590 uintptr_t pt; 1591 pmap_t pmap; 1592 uint64_t lo; 1593 1594 if ((m->oflags & VPO_UNMANAGED) != 0) { 1595 m->md.mdpg_cache_attrs = ma; 1596 return; 1597 } 1598 1599 pvo_head = vm_page_to_pvoh(m); 1600 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1601 LOCK_TABLE_RD(); 1602 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1603 pmap = pvo->pvo_pmap; 1604 PMAP_LOCK(pmap); 1605 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1606 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1607 pvo->pvo_pte.lpte.pte_lo |= lo; 1608 if (pt != -1) { 1609 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1610 pvo->pvo_vpn); 1611 if (pvo->pvo_pmap == kernel_pmap) 1612 isync(); 1613 } 1614 PMAP_UNLOCK(pmap); 1615 } 1616 UNLOCK_TABLE_RD(); 1617 m->md.mdpg_cache_attrs = ma; 1618} 1619 1620/* 1621 * Map a wired page into kernel virtual address space. 1622 */ 1623void 1624moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1625{ 1626 uint64_t pte_lo; 1627 int error; 1628 1629 pte_lo = moea64_calc_wimg(pa, ma); 1630 1631 LOCK_TABLE_WR(); 1632 PMAP_LOCK(kernel_pmap); 1633 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1634 NULL, va, pa, pte_lo, PVO_WIRED); 1635 PMAP_UNLOCK(kernel_pmap); 1636 UNLOCK_TABLE_WR(); 1637 1638 if (error != 0 && error != ENOENT) 1639 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1640 pa, error); 1641} 1642 1643void 1644moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1645{ 1646 1647 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1648} 1649 1650/* 1651 * Extract the physical page address associated with the given kernel virtual 1652 * address. 1653 */ 1654vm_paddr_t 1655moea64_kextract(mmu_t mmu, vm_offset_t va) 1656{ 1657 struct pvo_entry *pvo; 1658 vm_paddr_t pa; 1659 1660 /* 1661 * Shortcut the direct-mapped case when applicable. We never put 1662 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1663 */ 1664 if (va < VM_MIN_KERNEL_ADDRESS) 1665 return (va); 1666 1667 PMAP_LOCK(kernel_pmap); 1668 pvo = moea64_pvo_find_va(kernel_pmap, va); 1669 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1670 va)); 1671 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1672 PMAP_UNLOCK(kernel_pmap); 1673 return (pa); 1674} 1675 1676/* 1677 * Remove a wired page from kernel virtual address space. 1678 */ 1679void 1680moea64_kremove(mmu_t mmu, vm_offset_t va) 1681{ 1682 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1683} 1684 1685/* 1686 * Map a range of physical addresses into kernel virtual address space. 1687 * 1688 * The value passed in *virt is a suggested virtual address for the mapping. 1689 * Architectures which can support a direct-mapped physical to virtual region 1690 * can return the appropriate address within that region, leaving '*virt' 1691 * unchanged. We cannot and therefore do not; *virt is updated with the 1692 * first usable address after the mapped region. 1693 */ 1694vm_offset_t 1695moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1696 vm_paddr_t pa_end, int prot) 1697{ 1698 vm_offset_t sva, va; 1699 1700 sva = *virt; 1701 va = sva; 1702 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1703 moea64_kenter(mmu, va, pa_start); 1704 *virt = va; 1705 1706 return (sva); 1707} 1708 1709/* 1710 * Returns true if the pmap's pv is one of the first 1711 * 16 pvs linked to from this page. This count may 1712 * be changed upwards or downwards in the future; it 1713 * is only necessary that true be returned for a small 1714 * subset of pmaps for proper page aging. 1715 */ 1716boolean_t 1717moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1718{ 1719 int loops; 1720 struct pvo_entry *pvo; 1721 boolean_t rv; 1722 1723 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1724 ("moea64_page_exists_quick: page %p is not managed", m)); 1725 loops = 0; 1726 rv = FALSE; 1727 LOCK_TABLE_RD(); 1728 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1729 if (pvo->pvo_pmap == pmap) { 1730 rv = TRUE; 1731 break; 1732 } 1733 if (++loops >= 16) 1734 break; 1735 } 1736 UNLOCK_TABLE_RD(); 1737 return (rv); 1738} 1739 1740/* 1741 * Return the number of managed mappings to the given physical page 1742 * that are wired. 1743 */ 1744int 1745moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1746{ 1747 struct pvo_entry *pvo; 1748 int count; 1749 1750 count = 0; 1751 if ((m->oflags & VPO_UNMANAGED) != 0) 1752 return (count); 1753 LOCK_TABLE_RD(); 1754 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1755 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1756 count++; 1757 UNLOCK_TABLE_RD(); 1758 return (count); 1759} 1760 1761static uintptr_t moea64_vsidcontext; 1762 1763uintptr_t 1764moea64_get_unique_vsid(void) { 1765 u_int entropy; 1766 register_t hash; 1767 uint32_t mask; 1768 int i; 1769 1770 entropy = 0; 1771 __asm __volatile("mftb %0" : "=r"(entropy)); 1772 1773 mtx_lock(&moea64_slb_mutex); 1774 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1775 u_int n; 1776 1777 /* 1778 * Create a new value by mutiplying by a prime and adding in 1779 * entropy from the timebase register. This is to make the 1780 * VSID more random so that the PT hash function collides 1781 * less often. (Note that the prime casues gcc to do shifts 1782 * instead of a multiply.) 1783 */ 1784 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1785 hash = moea64_vsidcontext & (NVSIDS - 1); 1786 if (hash == 0) /* 0 is special, avoid it */ 1787 continue; 1788 n = hash >> 5; 1789 mask = 1 << (hash & (VSID_NBPW - 1)); 1790 hash = (moea64_vsidcontext & VSID_HASHMASK); 1791 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1792 /* anything free in this bucket? */ 1793 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1794 entropy = (moea64_vsidcontext >> 20); 1795 continue; 1796 } 1797 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1798 mask = 1 << i; 1799 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1800 hash |= i; 1801 } 1802 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1803 ("Allocating in-use VSID %#zx\n", hash)); 1804 moea64_vsid_bitmap[n] |= mask; 1805 mtx_unlock(&moea64_slb_mutex); 1806 return (hash); 1807 } 1808 1809 mtx_unlock(&moea64_slb_mutex); 1810 panic("%s: out of segments",__func__); 1811} 1812 1813#ifdef __powerpc64__ 1814void 1815moea64_pinit(mmu_t mmu, pmap_t pmap) 1816{ 1817 PMAP_LOCK_INIT(pmap); 1818 RB_INIT(&pmap->pmap_pvo); 1819 1820 pmap->pm_slb_tree_root = slb_alloc_tree(); 1821 pmap->pm_slb = slb_alloc_user_cache(); 1822 pmap->pm_slb_len = 0; 1823} 1824#else 1825void 1826moea64_pinit(mmu_t mmu, pmap_t pmap) 1827{ 1828 int i; 1829 uint32_t hash; 1830 1831 PMAP_LOCK_INIT(pmap); 1832 RB_INIT(&pmap->pmap_pvo); 1833 1834 if (pmap_bootstrapped) 1835 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1836 (vm_offset_t)pmap); 1837 else 1838 pmap->pmap_phys = pmap; 1839 1840 /* 1841 * Allocate some segment registers for this pmap. 1842 */ 1843 hash = moea64_get_unique_vsid(); 1844 1845 for (i = 0; i < 16; i++) 1846 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1847 1848 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1849} 1850#endif 1851 1852/* 1853 * Initialize the pmap associated with process 0. 1854 */ 1855void 1856moea64_pinit0(mmu_t mmu, pmap_t pm) 1857{ 1858 moea64_pinit(mmu, pm); 1859 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1860} 1861 1862/* 1863 * Set the physical protection on the specified range of this map as requested. 1864 */ 1865static void 1866moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 1867{ 1868 uintptr_t pt; 1869 struct vm_page *pg; 1870 uint64_t oldlo; 1871 1872 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1873 1874 /* 1875 * Grab the PTE pointer before we diddle with the cached PTE 1876 * copy. 1877 */ 1878 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1879 1880 /* 1881 * Change the protection of the page. 1882 */ 1883 oldlo = pvo->pvo_pte.lpte.pte_lo; 1884 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1885 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1886 if ((prot & VM_PROT_EXECUTE) == 0) 1887 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1888 if (prot & VM_PROT_WRITE) 1889 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW; 1890 else 1891 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1892 1893 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1894 1895 /* 1896 * If the PVO is in the page table, update that pte as well. 1897 */ 1898 if (pt != -1) 1899 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1900 pvo->pvo_vpn); 1901 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 1902 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1903 if ((pg->oflags & VPO_UNMANAGED) == 0) 1904 vm_page_aflag_set(pg, PGA_EXECUTABLE); 1905 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 1906 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE); 1907 } 1908 1909 /* 1910 * Update vm about the REF/CHG bits if the page is managed and we have 1911 * removed write access. 1912 */ 1913 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && 1914 (oldlo & LPTE_PP) != LPTE_BR && !(prot && VM_PROT_WRITE)) { 1915 if (pg != NULL) { 1916 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 1917 vm_page_dirty(pg); 1918 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 1919 vm_page_aflag_set(pg, PGA_REFERENCED); 1920 } 1921 } 1922} 1923 1924void 1925moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1926 vm_prot_t prot) 1927{ 1928 struct pvo_entry *pvo, *tpvo, key; 1929 1930 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 1931 sva, eva, prot); 1932 1933 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1934 ("moea64_protect: non current pmap")); 1935 1936 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1937 moea64_remove(mmu, pm, sva, eva); 1938 return; 1939 } 1940 1941 LOCK_TABLE_RD(); 1942 PMAP_LOCK(pm); 1943 key.pvo_vaddr = sva; 1944 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1945 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1946 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1947 moea64_pvo_protect(mmu, pm, pvo, prot); 1948 } 1949 UNLOCK_TABLE_RD(); 1950 PMAP_UNLOCK(pm); 1951} 1952 1953/* 1954 * Map a list of wired pages into kernel virtual address space. This is 1955 * intended for temporary mappings which do not need page modification or 1956 * references recorded. Existing mappings in the region are overwritten. 1957 */ 1958void 1959moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 1960{ 1961 while (count-- > 0) { 1962 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1963 va += PAGE_SIZE; 1964 m++; 1965 } 1966} 1967 1968/* 1969 * Remove page mappings from kernel virtual address space. Intended for 1970 * temporary mappings entered by moea64_qenter. 1971 */ 1972void 1973moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 1974{ 1975 while (count-- > 0) { 1976 moea64_kremove(mmu, va); 1977 va += PAGE_SIZE; 1978 } 1979} 1980 1981void 1982moea64_release_vsid(uint64_t vsid) 1983{ 1984 int idx, mask; 1985 1986 mtx_lock(&moea64_slb_mutex); 1987 idx = vsid & (NVSIDS-1); 1988 mask = 1 << (idx % VSID_NBPW); 1989 idx /= VSID_NBPW; 1990 KASSERT(moea64_vsid_bitmap[idx] & mask, 1991 ("Freeing unallocated VSID %#jx", vsid)); 1992 moea64_vsid_bitmap[idx] &= ~mask; 1993 mtx_unlock(&moea64_slb_mutex); 1994} 1995 1996 1997void 1998moea64_release(mmu_t mmu, pmap_t pmap) 1999{ 2000 2001 /* 2002 * Free segment registers' VSIDs 2003 */ 2004 #ifdef __powerpc64__ 2005 slb_free_tree(pmap); 2006 slb_free_user_cache(pmap->pm_slb); 2007 #else 2008 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2009 2010 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2011 #endif 2012 2013 PMAP_LOCK_DESTROY(pmap); 2014} 2015 2016/* 2017 * Remove all pages mapped by the specified pmap 2018 */ 2019void 2020moea64_remove_pages(mmu_t mmu, pmap_t pm) 2021{ 2022 struct pvo_entry *pvo, *tpvo; 2023 2024 LOCK_TABLE_WR(); 2025 PMAP_LOCK(pm); 2026 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2027 if (!(pvo->pvo_vaddr & PVO_WIRED)) 2028 moea64_pvo_remove(mmu, pvo); 2029 } 2030 UNLOCK_TABLE_WR(); 2031 PMAP_UNLOCK(pm); 2032} 2033 2034/* 2035 * Remove the given range of addresses from the specified map. 2036 */ 2037void 2038moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2039{ 2040 struct pvo_entry *pvo, *tpvo, key; 2041 2042 /* 2043 * Perform an unsynchronized read. This is, however, safe. 2044 */ 2045 if (pm->pm_stats.resident_count == 0) 2046 return; 2047 2048 LOCK_TABLE_WR(); 2049 PMAP_LOCK(pm); 2050 key.pvo_vaddr = sva; 2051 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2052 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2053 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2054 moea64_pvo_remove(mmu, pvo); 2055 } 2056 UNLOCK_TABLE_WR(); 2057 PMAP_UNLOCK(pm); 2058} 2059 2060/* 2061 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2062 * will reflect changes in pte's back to the vm_page. 2063 */ 2064void 2065moea64_remove_all(mmu_t mmu, vm_page_t m) 2066{ 2067 struct pvo_entry *pvo, *next_pvo; 2068 pmap_t pmap; 2069 2070 LOCK_TABLE_WR(); 2071 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2072 pmap = pvo->pvo_pmap; 2073 PMAP_LOCK(pmap); 2074 moea64_pvo_remove(mmu, pvo); 2075 PMAP_UNLOCK(pmap); 2076 } 2077 UNLOCK_TABLE_WR(); 2078 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m)) 2079 vm_page_dirty(m); 2080 vm_page_aflag_clear(m, PGA_WRITEABLE); 2081 vm_page_aflag_clear(m, PGA_EXECUTABLE); 2082} 2083 2084/* 2085 * Allocate a physical page of memory directly from the phys_avail map. 2086 * Can only be called from moea64_bootstrap before avail start and end are 2087 * calculated. 2088 */ 2089vm_offset_t 2090moea64_bootstrap_alloc(vm_size_t size, u_int align) 2091{ 2092 vm_offset_t s, e; 2093 int i, j; 2094 2095 size = round_page(size); 2096 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2097 if (align != 0) 2098 s = (phys_avail[i] + align - 1) & ~(align - 1); 2099 else 2100 s = phys_avail[i]; 2101 e = s + size; 2102 2103 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2104 continue; 2105 2106 if (s + size > platform_real_maxaddr()) 2107 continue; 2108 2109 if (s == phys_avail[i]) { 2110 phys_avail[i] += size; 2111 } else if (e == phys_avail[i + 1]) { 2112 phys_avail[i + 1] -= size; 2113 } else { 2114 for (j = phys_avail_count * 2; j > i; j -= 2) { 2115 phys_avail[j] = phys_avail[j - 2]; 2116 phys_avail[j + 1] = phys_avail[j - 1]; 2117 } 2118 2119 phys_avail[i + 3] = phys_avail[i + 1]; 2120 phys_avail[i + 1] = s; 2121 phys_avail[i + 2] = e; 2122 phys_avail_count++; 2123 } 2124 2125 return (s); 2126 } 2127 panic("moea64_bootstrap_alloc: could not allocate memory"); 2128} 2129 2130static int 2131moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2132 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2133 uint64_t pte_lo, int flags) 2134{ 2135 struct pvo_entry *pvo; 2136 uint64_t vsid; 2137 int first; 2138 u_int ptegidx; 2139 int i; 2140 int bootstrap; 2141 2142 /* 2143 * One nasty thing that can happen here is that the UMA calls to 2144 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2145 * which calls UMA... 2146 * 2147 * We break the loop by detecting recursion and allocating out of 2148 * the bootstrap pool. 2149 */ 2150 2151 first = 0; 2152 bootstrap = (flags & PVO_BOOTSTRAP); 2153 2154 if (!moea64_initialized) 2155 bootstrap = 1; 2156 2157 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2158 rw_assert(&moea64_table_lock, RA_WLOCKED); 2159 2160 /* 2161 * Compute the PTE Group index. 2162 */ 2163 va &= ~ADDR_POFF; 2164 vsid = va_to_vsid(pm, va); 2165 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2166 2167 /* 2168 * Remove any existing mapping for this page. Reuse the pvo entry if 2169 * there is a mapping. 2170 */ 2171 moea64_pvo_enter_calls++; 2172 2173 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2174 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2175 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2176 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2177 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2178 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2179 /* Re-insert if spilled */ 2180 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2181 &pvo->pvo_pte.lpte); 2182 if (i >= 0) 2183 PVO_PTEGIDX_SET(pvo, i); 2184 moea64_pte_overflow--; 2185 } 2186 return (0); 2187 } 2188 moea64_pvo_remove(mmu, pvo); 2189 break; 2190 } 2191 } 2192 2193 /* 2194 * If we aren't overwriting a mapping, try to allocate. 2195 */ 2196 if (bootstrap) { 2197 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2198 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2199 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2200 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2201 } 2202 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2203 moea64_bpvo_pool_index++; 2204 bootstrap = 1; 2205 } else { 2206 pvo = uma_zalloc(zone, M_NOWAIT); 2207 } 2208 2209 if (pvo == NULL) 2210 return (ENOMEM); 2211 2212 moea64_pvo_entries++; 2213 pvo->pvo_vaddr = va; 2214 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2215 | (vsid << 16); 2216 pvo->pvo_pmap = pm; 2217 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2218 pvo->pvo_vaddr &= ~ADDR_POFF; 2219 2220 if (flags & PVO_WIRED) 2221 pvo->pvo_vaddr |= PVO_WIRED; 2222 if (pvo_head != NULL) 2223 pvo->pvo_vaddr |= PVO_MANAGED; 2224 if (bootstrap) 2225 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2226 if (flags & PVO_LARGE) 2227 pvo->pvo_vaddr |= PVO_LARGE; 2228 2229 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2230 (uint64_t)(pa) | pte_lo, flags); 2231 2232 /* 2233 * Add to pmap list 2234 */ 2235 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2236 2237 /* 2238 * Remember if the list was empty and therefore will be the first 2239 * item. 2240 */ 2241 if (pvo_head != NULL) { 2242 if (LIST_FIRST(pvo_head) == NULL) 2243 first = 1; 2244 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2245 } 2246 2247 if (pvo->pvo_vaddr & PVO_WIRED) { 2248 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2249 pm->pm_stats.wired_count++; 2250 } 2251 pm->pm_stats.resident_count++; 2252 2253 /* 2254 * We hope this succeeds but it isn't required. 2255 */ 2256 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2257 if (i >= 0) { 2258 PVO_PTEGIDX_SET(pvo, i); 2259 } else { 2260 panic("moea64_pvo_enter: overflow"); 2261 moea64_pte_overflow++; 2262 } 2263 2264 if (pm == kernel_pmap) 2265 isync(); 2266 2267#ifdef __powerpc64__ 2268 /* 2269 * Make sure all our bootstrap mappings are in the SLB as soon 2270 * as virtual memory is switched on. 2271 */ 2272 if (!pmap_bootstrapped) 2273 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2274#endif 2275 2276 return (first ? ENOENT : 0); 2277} 2278 2279static void 2280moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2281{ 2282 struct vm_page *pg; 2283 uintptr_t pt; 2284 2285 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2286 rw_assert(&moea64_table_lock, RA_WLOCKED); 2287 2288 /* 2289 * If there is an active pte entry, we need to deactivate it (and 2290 * save the ref & cfg bits). 2291 */ 2292 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2293 if (pt != -1) { 2294 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2295 PVO_PTEGIDX_CLR(pvo); 2296 } else { 2297 moea64_pte_overflow--; 2298 } 2299 2300 /* 2301 * Update our statistics. 2302 */ 2303 pvo->pvo_pmap->pm_stats.resident_count--; 2304 if (pvo->pvo_vaddr & PVO_WIRED) 2305 pvo->pvo_pmap->pm_stats.wired_count--; 2306 2307 /* 2308 * Remove this PVO from the pmap list. 2309 */ 2310 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2311 2312 /* 2313 * Remove this from the overflow list and return it to the pool 2314 * if we aren't going to reuse it. 2315 */ 2316 LIST_REMOVE(pvo, pvo_olink); 2317 2318 /* 2319 * Update vm about the REF/CHG bits if the page is managed. 2320 */ 2321 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2322 2323 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) { 2324 LIST_REMOVE(pvo, pvo_vlink); 2325 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 2326 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 2327 vm_page_dirty(pg); 2328 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 2329 vm_page_aflag_set(pg, PGA_REFERENCED); 2330 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2331 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2332 } 2333 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2334 vm_page_aflag_clear(pg, PGA_EXECUTABLE); 2335 } 2336 2337 moea64_pvo_entries--; 2338 moea64_pvo_remove_calls++; 2339 2340 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2341 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2342 moea64_upvo_zone, pvo); 2343} 2344 2345static struct pvo_entry * 2346moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2347{ 2348 struct pvo_entry key; 2349 2350 key.pvo_vaddr = va & ~ADDR_POFF; 2351 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2352} 2353 2354static boolean_t 2355moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2356{ 2357 struct pvo_entry *pvo; 2358 uintptr_t pt; 2359 2360 LOCK_TABLE_RD(); 2361 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2362 /* 2363 * See if we saved the bit off. If so, return success. 2364 */ 2365 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2366 UNLOCK_TABLE_RD(); 2367 return (TRUE); 2368 } 2369 } 2370 2371 /* 2372 * No luck, now go through the hard part of looking at the PTEs 2373 * themselves. Sync so that any pending REF/CHG bits are flushed to 2374 * the PTEs. 2375 */ 2376 powerpc_sync(); 2377 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2378 2379 /* 2380 * See if this pvo has a valid PTE. if so, fetch the 2381 * REF/CHG bits from the valid PTE. If the appropriate 2382 * ptebit is set, return success. 2383 */ 2384 PMAP_LOCK(pvo->pvo_pmap); 2385 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2386 if (pt != -1) { 2387 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2388 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2389 PMAP_UNLOCK(pvo->pvo_pmap); 2390 UNLOCK_TABLE_RD(); 2391 return (TRUE); 2392 } 2393 } 2394 PMAP_UNLOCK(pvo->pvo_pmap); 2395 } 2396 2397 UNLOCK_TABLE_RD(); 2398 return (FALSE); 2399} 2400 2401static u_int 2402moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2403{ 2404 u_int count; 2405 struct pvo_entry *pvo; 2406 uintptr_t pt; 2407 2408 /* 2409 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2410 * we can reset the right ones). note that since the pvo entries and 2411 * list heads are accessed via BAT0 and are never placed in the page 2412 * table, we don't have to worry about further accesses setting the 2413 * REF/CHG bits. 2414 */ 2415 powerpc_sync(); 2416 2417 /* 2418 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2419 * valid pte clear the ptebit from the valid pte. 2420 */ 2421 count = 0; 2422 LOCK_TABLE_RD(); 2423 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2424 PMAP_LOCK(pvo->pvo_pmap); 2425 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2426 if (pt != -1) { 2427 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2428 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2429 count++; 2430 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2431 pvo->pvo_vpn, ptebit); 2432 } 2433 } 2434 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2435 PMAP_UNLOCK(pvo->pvo_pmap); 2436 } 2437 2438 UNLOCK_TABLE_RD(); 2439 return (count); 2440} 2441 2442boolean_t 2443moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2444{ 2445 struct pvo_entry *pvo, key; 2446 vm_offset_t ppa; 2447 int error = 0; 2448 2449 PMAP_LOCK(kernel_pmap); 2450 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2451 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2452 ppa < pa + size; ppa += PAGE_SIZE, 2453 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2454 if (pvo == NULL || 2455 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2456 error = EFAULT; 2457 break; 2458 } 2459 } 2460 PMAP_UNLOCK(kernel_pmap); 2461 2462 return (error); 2463} 2464 2465/* 2466 * Map a set of physical memory pages into the kernel virtual 2467 * address space. Return a pointer to where it is mapped. This 2468 * routine is intended to be used for mapping device memory, 2469 * NOT real memory. 2470 */ 2471void * 2472moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2473{ 2474 vm_offset_t va, tmpva, ppa, offset; 2475 2476 ppa = trunc_page(pa); 2477 offset = pa & PAGE_MASK; 2478 size = roundup2(offset + size, PAGE_SIZE); 2479 2480 va = kmem_alloc_nofault(kernel_map, size); 2481 2482 if (!va) 2483 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2484 2485 for (tmpva = va; size > 0;) { 2486 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2487 size -= PAGE_SIZE; 2488 tmpva += PAGE_SIZE; 2489 ppa += PAGE_SIZE; 2490 } 2491 2492 return ((void *)(va + offset)); 2493} 2494 2495void * 2496moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2497{ 2498 2499 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2500} 2501 2502void 2503moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2504{ 2505 vm_offset_t base, offset; 2506 2507 base = trunc_page(va); 2508 offset = va & PAGE_MASK; 2509 size = roundup2(offset + size, PAGE_SIZE); 2510 2511 kmem_free(kernel_map, base, size); 2512} 2513 2514void 2515moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2516{ 2517 struct pvo_entry *pvo; 2518 vm_offset_t lim; 2519 vm_paddr_t pa; 2520 vm_size_t len; 2521 2522 PMAP_LOCK(pm); 2523 while (sz > 0) { 2524 lim = round_page(va); 2525 len = MIN(lim - va, sz); 2526 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2527 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) { 2528 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 2529 (va & ADDR_POFF); 2530 moea64_syncicache(mmu, pm, va, pa, len); 2531 } 2532 va += len; 2533 sz -= len; 2534 } 2535 PMAP_UNLOCK(pm); 2536} 2537