mmu_oea64.c revision 234155
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#include <sys/cdefs.h> 94__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea64.c 234155 2012-04-11 21:56:55Z nwhitehorn $"); 95 96/* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117#include "opt_compat.h" 118#include "opt_kstack_pages.h" 119 120#include <sys/param.h> 121#include <sys/kernel.h> 122#include <sys/queue.h> 123#include <sys/cpuset.h> 124#include <sys/ktr.h> 125#include <sys/lock.h> 126#include <sys/msgbuf.h> 127#include <sys/mutex.h> 128#include <sys/proc.h> 129#include <sys/rwlock.h> 130#include <sys/sched.h> 131#include <sys/sysctl.h> 132#include <sys/systm.h> 133#include <sys/vmmeter.h> 134 135#include <sys/kdb.h> 136 137#include <dev/ofw/openfirm.h> 138 139#include <vm/vm.h> 140#include <vm/vm_param.h> 141#include <vm/vm_kern.h> 142#include <vm/vm_page.h> 143#include <vm/vm_map.h> 144#include <vm/vm_object.h> 145#include <vm/vm_extern.h> 146#include <vm/vm_pageout.h> 147#include <vm/vm_pager.h> 148#include <vm/uma.h> 149 150#include <machine/_inttypes.h> 151#include <machine/cpu.h> 152#include <machine/platform.h> 153#include <machine/frame.h> 154#include <machine/md_var.h> 155#include <machine/psl.h> 156#include <machine/bat.h> 157#include <machine/hid.h> 158#include <machine/pte.h> 159#include <machine/sr.h> 160#include <machine/trap.h> 161#include <machine/mmuvar.h> 162 163#include "mmu_oea64.h" 164#include "mmu_if.h" 165#include "moea64_if.h" 166 167void moea64_release_vsid(uint64_t vsid); 168uintptr_t moea64_get_unique_vsid(void); 169 170#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 171#define ENABLE_TRANS(msr) mtmsr(msr) 172 173#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 174#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 175#define VSID_HASH_MASK 0x0000007fffffffffULL 176 177/* 178 * Locking semantics: 179 * -- Read lock: if no modifications are being made to either the PVO lists 180 * or page table or if any modifications being made result in internal 181 * changes (e.g. wiring, protection) such that the existence of the PVOs 182 * is unchanged and they remain associated with the same pmap (in which 183 * case the changes should be protected by the pmap lock) 184 * -- Write lock: required if PTEs/PVOs are being inserted or removed. 185 */ 186 187#define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock) 188#define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock) 189#define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock) 190#define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock) 191 192struct ofw_map { 193 cell_t om_va; 194 cell_t om_len; 195 cell_t om_pa_hi; 196 cell_t om_pa_lo; 197 cell_t om_mode; 198}; 199 200/* 201 * Map of physical memory regions. 202 */ 203static struct mem_region *regions; 204static struct mem_region *pregions; 205static u_int phys_avail_count; 206static int regions_sz, pregions_sz; 207 208extern void bs_remap_earlyboot(void); 209 210/* 211 * Lock for the pteg and pvo tables. 212 */ 213struct rwlock moea64_table_lock; 214struct mtx moea64_slb_mutex; 215 216/* 217 * PTEG data. 218 */ 219u_int moea64_pteg_count; 220u_int moea64_pteg_mask; 221 222/* 223 * PVO data. 224 */ 225struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 226struct pvo_head moea64_pvo_kunmanaged = /* list of unmanaged pages */ 227 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 228 229uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 230uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 231 232#define BPVO_POOL_SIZE 327680 233static struct pvo_entry *moea64_bpvo_pool; 234static int moea64_bpvo_pool_index = 0; 235 236#define VSID_NBPW (sizeof(u_int32_t) * 8) 237#ifdef __powerpc64__ 238#define NVSIDS (NPMAPS * 16) 239#define VSID_HASHMASK 0xffffffffUL 240#else 241#define NVSIDS NPMAPS 242#define VSID_HASHMASK 0xfffffUL 243#endif 244static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 245 246static boolean_t moea64_initialized = FALSE; 247 248/* 249 * Statistics. 250 */ 251u_int moea64_pte_valid = 0; 252u_int moea64_pte_overflow = 0; 253u_int moea64_pvo_entries = 0; 254u_int moea64_pvo_enter_calls = 0; 255u_int moea64_pvo_remove_calls = 0; 256SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 257 &moea64_pte_valid, 0, ""); 258SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 259 &moea64_pte_overflow, 0, ""); 260SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 261 &moea64_pvo_entries, 0, ""); 262SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 263 &moea64_pvo_enter_calls, 0, ""); 264SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 265 &moea64_pvo_remove_calls, 0, ""); 266 267vm_offset_t moea64_scratchpage_va[2]; 268struct pvo_entry *moea64_scratchpage_pvo[2]; 269uintptr_t moea64_scratchpage_pte[2]; 270struct mtx moea64_scratchpage_mtx; 271 272uint64_t moea64_large_page_mask = 0; 273int moea64_large_page_size = 0; 274int moea64_large_page_shift = 0; 275 276/* 277 * PVO calls. 278 */ 279static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 280 vm_offset_t, vm_offset_t, uint64_t, int); 281static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 282static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 283 284/* 285 * Utility routines. 286 */ 287static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 288static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 289static void moea64_kremove(mmu_t, vm_offset_t); 290static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 291 vm_offset_t pa, vm_size_t sz); 292 293/* 294 * Kernel MMU interface 295 */ 296void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 297void moea64_clear_modify(mmu_t, vm_page_t); 298void moea64_clear_reference(mmu_t, vm_page_t); 299void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 300void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 301void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 302 vm_prot_t); 303void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 304vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 305vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 306void moea64_init(mmu_t); 307boolean_t moea64_is_modified(mmu_t, vm_page_t); 308boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 309boolean_t moea64_is_referenced(mmu_t, vm_page_t); 310boolean_t moea64_ts_referenced(mmu_t, vm_page_t); 311vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 312boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 313int moea64_page_wired_mappings(mmu_t, vm_page_t); 314void moea64_pinit(mmu_t, pmap_t); 315void moea64_pinit0(mmu_t, pmap_t); 316void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 317void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 318void moea64_qremove(mmu_t, vm_offset_t, int); 319void moea64_release(mmu_t, pmap_t); 320void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 321void moea64_remove_pages(mmu_t, pmap_t); 322void moea64_remove_all(mmu_t, vm_page_t); 323void moea64_remove_write(mmu_t, vm_page_t); 324void moea64_zero_page(mmu_t, vm_page_t); 325void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 326void moea64_zero_page_idle(mmu_t, vm_page_t); 327void moea64_activate(mmu_t, struct thread *); 328void moea64_deactivate(mmu_t, struct thread *); 329void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 330void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 331void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 332vm_offset_t moea64_kextract(mmu_t, vm_offset_t); 333void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 334void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 335void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 336boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 337static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 338 339static mmu_method_t moea64_methods[] = { 340 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 341 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 342 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 343 MMUMETHOD(mmu_copy_page, moea64_copy_page), 344 MMUMETHOD(mmu_enter, moea64_enter), 345 MMUMETHOD(mmu_enter_object, moea64_enter_object), 346 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 347 MMUMETHOD(mmu_extract, moea64_extract), 348 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 349 MMUMETHOD(mmu_init, moea64_init), 350 MMUMETHOD(mmu_is_modified, moea64_is_modified), 351 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 352 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 353 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 354 MMUMETHOD(mmu_map, moea64_map), 355 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 356 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 357 MMUMETHOD(mmu_pinit, moea64_pinit), 358 MMUMETHOD(mmu_pinit0, moea64_pinit0), 359 MMUMETHOD(mmu_protect, moea64_protect), 360 MMUMETHOD(mmu_qenter, moea64_qenter), 361 MMUMETHOD(mmu_qremove, moea64_qremove), 362 MMUMETHOD(mmu_release, moea64_release), 363 MMUMETHOD(mmu_remove, moea64_remove), 364 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 365 MMUMETHOD(mmu_remove_all, moea64_remove_all), 366 MMUMETHOD(mmu_remove_write, moea64_remove_write), 367 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 368 MMUMETHOD(mmu_zero_page, moea64_zero_page), 369 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 370 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 371 MMUMETHOD(mmu_activate, moea64_activate), 372 MMUMETHOD(mmu_deactivate, moea64_deactivate), 373 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 374 375 /* Internal interfaces */ 376 MMUMETHOD(mmu_mapdev, moea64_mapdev), 377 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 378 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 379 MMUMETHOD(mmu_kextract, moea64_kextract), 380 MMUMETHOD(mmu_kenter, moea64_kenter), 381 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 382 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 383 384 { 0, 0 } 385}; 386 387MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 388 389static __inline u_int 390va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 391{ 392 uint64_t hash; 393 int shift; 394 395 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 396 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 397 shift); 398 return (hash & moea64_pteg_mask); 399} 400 401static __inline struct pvo_head * 402vm_page_to_pvoh(vm_page_t m) 403{ 404 405 return (&m->md.mdpg_pvoh); 406} 407 408static __inline void 409moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 410 uint64_t pte_lo, int flags) 411{ 412 413 /* 414 * Construct a PTE. Default to IMB initially. Valid bit only gets 415 * set when the real pte is set in memory. 416 * 417 * Note: Don't set the valid bit for correct operation of tlb update. 418 */ 419 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 420 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 421 422 if (flags & PVO_LARGE) 423 pt->pte_hi |= LPTE_BIG; 424 425 pt->pte_lo = pte_lo; 426} 427 428static __inline uint64_t 429moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 430{ 431 uint64_t pte_lo; 432 int i; 433 434 if (ma != VM_MEMATTR_DEFAULT) { 435 switch (ma) { 436 case VM_MEMATTR_UNCACHEABLE: 437 return (LPTE_I | LPTE_G); 438 case VM_MEMATTR_WRITE_COMBINING: 439 case VM_MEMATTR_WRITE_BACK: 440 case VM_MEMATTR_PREFETCHABLE: 441 return (LPTE_I); 442 case VM_MEMATTR_WRITE_THROUGH: 443 return (LPTE_W | LPTE_M); 444 } 445 } 446 447 /* 448 * Assume the page is cache inhibited and access is guarded unless 449 * it's in our available memory array. 450 */ 451 pte_lo = LPTE_I | LPTE_G; 452 for (i = 0; i < pregions_sz; i++) { 453 if ((pa >= pregions[i].mr_start) && 454 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 455 pte_lo &= ~(LPTE_I | LPTE_G); 456 pte_lo |= LPTE_M; 457 break; 458 } 459 } 460 461 return pte_lo; 462} 463 464/* 465 * Quick sort callout for comparing memory regions. 466 */ 467static int om_cmp(const void *a, const void *b); 468 469static int 470om_cmp(const void *a, const void *b) 471{ 472 const struct ofw_map *mapa; 473 const struct ofw_map *mapb; 474 475 mapa = a; 476 mapb = b; 477 if (mapa->om_pa_hi < mapb->om_pa_hi) 478 return (-1); 479 else if (mapa->om_pa_hi > mapb->om_pa_hi) 480 return (1); 481 else if (mapa->om_pa_lo < mapb->om_pa_lo) 482 return (-1); 483 else if (mapa->om_pa_lo > mapb->om_pa_lo) 484 return (1); 485 else 486 return (0); 487} 488 489static void 490moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 491{ 492 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 493 register_t msr; 494 vm_offset_t off; 495 vm_paddr_t pa_base; 496 int i; 497 498 bzero(translations, sz); 499 if (OF_getprop(mmu, "translations", translations, sz) == -1) 500 panic("moea64_bootstrap: can't get ofw translations"); 501 502 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 503 sz /= sizeof(*translations); 504 qsort(translations, sz, sizeof (*translations), om_cmp); 505 506 for (i = 0; i < sz; i++) { 507 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 508 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 509 translations[i].om_len); 510 511 if (translations[i].om_pa_lo % PAGE_SIZE) 512 panic("OFW translation not page-aligned!"); 513 514 pa_base = translations[i].om_pa_lo; 515 516 #ifdef __powerpc64__ 517 pa_base += (vm_offset_t)translations[i].om_pa_hi << 32; 518 #else 519 if (translations[i].om_pa_hi) 520 panic("OFW translations above 32-bit boundary!"); 521 #endif 522 523 /* Now enter the pages for this mapping */ 524 525 DISABLE_TRANS(msr); 526 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 527 if (moea64_pvo_find_va(kernel_pmap, 528 translations[i].om_va + off) != NULL) 529 continue; 530 531 moea64_kenter(mmup, translations[i].om_va + off, 532 pa_base + off); 533 } 534 ENABLE_TRANS(msr); 535 } 536} 537 538#ifdef __powerpc64__ 539static void 540moea64_probe_large_page(void) 541{ 542 uint16_t pvr = mfpvr() >> 16; 543 544 switch (pvr) { 545 case IBM970: 546 case IBM970FX: 547 case IBM970MP: 548 powerpc_sync(); isync(); 549 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 550 powerpc_sync(); isync(); 551 552 /* FALLTHROUGH */ 553 case IBMCELLBE: 554 moea64_large_page_size = 0x1000000; /* 16 MB */ 555 moea64_large_page_shift = 24; 556 break; 557 default: 558 moea64_large_page_size = 0; 559 } 560 561 moea64_large_page_mask = moea64_large_page_size - 1; 562} 563 564static void 565moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 566{ 567 struct slb *cache; 568 struct slb entry; 569 uint64_t esid, slbe; 570 uint64_t i; 571 572 cache = PCPU_GET(slb); 573 esid = va >> ADDR_SR_SHFT; 574 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 575 576 for (i = 0; i < 64; i++) { 577 if (cache[i].slbe == (slbe | i)) 578 return; 579 } 580 581 entry.slbe = slbe; 582 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 583 if (large) 584 entry.slbv |= SLBV_L; 585 586 slb_insert_kernel(entry.slbe, entry.slbv); 587} 588#endif 589 590static void 591moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 592 vm_offset_t kernelend) 593{ 594 register_t msr; 595 vm_paddr_t pa; 596 vm_offset_t size, off; 597 uint64_t pte_lo; 598 int i; 599 600 if (moea64_large_page_size == 0) 601 hw_direct_map = 0; 602 603 DISABLE_TRANS(msr); 604 if (hw_direct_map) { 605 LOCK_TABLE_WR(); 606 PMAP_LOCK(kernel_pmap); 607 for (i = 0; i < pregions_sz; i++) { 608 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 609 pregions[i].mr_size; pa += moea64_large_page_size) { 610 pte_lo = LPTE_M; 611 612 /* 613 * Set memory access as guarded if prefetch within 614 * the page could exit the available physmem area. 615 */ 616 if (pa & moea64_large_page_mask) { 617 pa &= moea64_large_page_mask; 618 pte_lo |= LPTE_G; 619 } 620 if (pa + moea64_large_page_size > 621 pregions[i].mr_start + pregions[i].mr_size) 622 pte_lo |= LPTE_G; 623 624 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 625 &moea64_pvo_kunmanaged, pa, pa, 626 pte_lo, PVO_WIRED | PVO_LARGE); 627 } 628 } 629 PMAP_UNLOCK(kernel_pmap); 630 UNLOCK_TABLE_WR(); 631 } else { 632 size = sizeof(struct pvo_head) * moea64_pteg_count; 633 off = (vm_offset_t)(moea64_pvo_table); 634 for (pa = off; pa < off + size; pa += PAGE_SIZE) 635 moea64_kenter(mmup, pa, pa); 636 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 637 off = (vm_offset_t)(moea64_bpvo_pool); 638 for (pa = off; pa < off + size; pa += PAGE_SIZE) 639 moea64_kenter(mmup, pa, pa); 640 641 /* 642 * Map certain important things, like ourselves. 643 * 644 * NOTE: We do not map the exception vector space. That code is 645 * used only in real mode, and leaving it unmapped allows us to 646 * catch NULL pointer deferences, instead of making NULL a valid 647 * address. 648 */ 649 650 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 651 pa += PAGE_SIZE) 652 moea64_kenter(mmup, pa, pa); 653 } 654 ENABLE_TRANS(msr); 655} 656 657void 658moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 659{ 660 int i, j; 661 vm_size_t physsz, hwphyssz; 662 663#ifndef __powerpc64__ 664 /* We don't have a direct map since there is no BAT */ 665 hw_direct_map = 0; 666 667 /* Make sure battable is zero, since we have no BAT */ 668 for (i = 0; i < 16; i++) { 669 battable[i].batu = 0; 670 battable[i].batl = 0; 671 } 672#else 673 moea64_probe_large_page(); 674 675 /* Use a direct map if we have large page support */ 676 if (moea64_large_page_size > 0) 677 hw_direct_map = 1; 678 else 679 hw_direct_map = 0; 680#endif 681 682 /* Get physical memory regions from firmware */ 683 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 684 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 685 686 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 687 panic("moea64_bootstrap: phys_avail too small"); 688 689 phys_avail_count = 0; 690 physsz = 0; 691 hwphyssz = 0; 692 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 693 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 694 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 695 regions[i].mr_start + regions[i].mr_size, 696 regions[i].mr_size); 697 if (hwphyssz != 0 && 698 (physsz + regions[i].mr_size) >= hwphyssz) { 699 if (physsz < hwphyssz) { 700 phys_avail[j] = regions[i].mr_start; 701 phys_avail[j + 1] = regions[i].mr_start + 702 hwphyssz - physsz; 703 physsz = hwphyssz; 704 phys_avail_count++; 705 } 706 break; 707 } 708 phys_avail[j] = regions[i].mr_start; 709 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 710 phys_avail_count++; 711 physsz += regions[i].mr_size; 712 } 713 714 /* Check for overlap with the kernel and exception vectors */ 715 for (j = 0; j < 2*phys_avail_count; j+=2) { 716 if (phys_avail[j] < EXC_LAST) 717 phys_avail[j] += EXC_LAST; 718 719 if (kernelstart >= phys_avail[j] && 720 kernelstart < phys_avail[j+1]) { 721 if (kernelend < phys_avail[j+1]) { 722 phys_avail[2*phys_avail_count] = 723 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 724 phys_avail[2*phys_avail_count + 1] = 725 phys_avail[j+1]; 726 phys_avail_count++; 727 } 728 729 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 730 } 731 732 if (kernelend >= phys_avail[j] && 733 kernelend < phys_avail[j+1]) { 734 if (kernelstart > phys_avail[j]) { 735 phys_avail[2*phys_avail_count] = phys_avail[j]; 736 phys_avail[2*phys_avail_count + 1] = 737 kernelstart & ~PAGE_MASK; 738 phys_avail_count++; 739 } 740 741 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 742 } 743 } 744 745 physmem = btoc(physsz); 746 747#ifdef PTEGCOUNT 748 moea64_pteg_count = PTEGCOUNT; 749#else 750 moea64_pteg_count = 0x1000; 751 752 while (moea64_pteg_count < physmem) 753 moea64_pteg_count <<= 1; 754 755 moea64_pteg_count >>= 1; 756#endif /* PTEGCOUNT */ 757} 758 759void 760moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 761{ 762 vm_size_t size; 763 register_t msr; 764 int i; 765 766 /* 767 * Set PTEG mask 768 */ 769 moea64_pteg_mask = moea64_pteg_count - 1; 770 771 /* 772 * Allocate pv/overflow lists. 773 */ 774 size = sizeof(struct pvo_head) * moea64_pteg_count; 775 776 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 777 PAGE_SIZE); 778 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 779 780 DISABLE_TRANS(msr); 781 for (i = 0; i < moea64_pteg_count; i++) 782 LIST_INIT(&moea64_pvo_table[i]); 783 ENABLE_TRANS(msr); 784 785 /* 786 * Initialize the lock that synchronizes access to the pteg and pvo 787 * tables. 788 */ 789 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE); 790 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 791 792 /* 793 * Initialise the unmanaged pvo pool. 794 */ 795 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 796 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 797 moea64_bpvo_pool_index = 0; 798 799 /* 800 * Make sure kernel vsid is allocated as well as VSID 0. 801 */ 802 #ifndef __powerpc64__ 803 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 804 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 805 moea64_vsid_bitmap[0] |= 1; 806 #endif 807 808 /* 809 * Initialize the kernel pmap (which is statically allocated). 810 */ 811 #ifdef __powerpc64__ 812 for (i = 0; i < 64; i++) { 813 pcpup->pc_slb[i].slbv = 0; 814 pcpup->pc_slb[i].slbe = 0; 815 } 816 #else 817 for (i = 0; i < 16; i++) 818 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 819 #endif 820 821 kernel_pmap->pmap_phys = kernel_pmap; 822 CPU_FILL(&kernel_pmap->pm_active); 823 LIST_INIT(&kernel_pmap->pmap_pvo); 824 825 PMAP_LOCK_INIT(kernel_pmap); 826 827 /* 828 * Now map in all the other buffers we allocated earlier 829 */ 830 831 moea64_setup_direct_map(mmup, kernelstart, kernelend); 832} 833 834void 835moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 836{ 837 ihandle_t mmui; 838 phandle_t chosen; 839 phandle_t mmu; 840 size_t sz; 841 int i; 842 vm_offset_t pa, va; 843 void *dpcpu; 844 845 /* 846 * Set up the Open Firmware pmap and add its mappings if not in real 847 * mode. 848 */ 849 850 chosen = OF_finddevice("/chosen"); 851 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 852 mmu = OF_instance_to_package(mmui); 853 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1) 854 sz = 0; 855 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 856 panic("moea64_bootstrap: too many ofw translations"); 857 858 if (sz > 0) 859 moea64_add_ofw_mappings(mmup, mmu, sz); 860 } 861 862 /* 863 * Calculate the last available physical address. 864 */ 865 for (i = 0; phys_avail[i + 2] != 0; i += 2) 866 ; 867 Maxmem = powerpc_btop(phys_avail[i + 1]); 868 869 /* 870 * Initialize MMU and remap early physical mappings 871 */ 872 MMU_CPU_BOOTSTRAP(mmup,0); 873 mtmsr(mfmsr() | PSL_DR | PSL_IR); 874 pmap_bootstrapped++; 875 bs_remap_earlyboot(); 876 877 /* 878 * Set the start and end of kva. 879 */ 880 virtual_avail = VM_MIN_KERNEL_ADDRESS; 881 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 882 883 /* 884 * Map the entire KVA range into the SLB. We must not fault there. 885 */ 886 #ifdef __powerpc64__ 887 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 888 moea64_bootstrap_slb_prefault(va, 0); 889 #endif 890 891 /* 892 * Figure out how far we can extend virtual_end into segment 16 893 * without running into existing mappings. Segment 16 is guaranteed 894 * to contain neither RAM nor devices (at least on Apple hardware), 895 * but will generally contain some OFW mappings we should not 896 * step on. 897 */ 898 899 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 900 PMAP_LOCK(kernel_pmap); 901 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 902 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 903 virtual_end += PAGE_SIZE; 904 PMAP_UNLOCK(kernel_pmap); 905 #endif 906 907 /* 908 * Allocate a kernel stack with a guard page for thread0 and map it 909 * into the kernel page map. 910 */ 911 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 912 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 913 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 914 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 915 thread0.td_kstack = va; 916 thread0.td_kstack_pages = KSTACK_PAGES; 917 for (i = 0; i < KSTACK_PAGES; i++) { 918 moea64_kenter(mmup, va, pa); 919 pa += PAGE_SIZE; 920 va += PAGE_SIZE; 921 } 922 923 /* 924 * Allocate virtual address space for the message buffer. 925 */ 926 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 927 msgbufp = (struct msgbuf *)virtual_avail; 928 va = virtual_avail; 929 virtual_avail += round_page(msgbufsize); 930 while (va < virtual_avail) { 931 moea64_kenter(mmup, va, pa); 932 pa += PAGE_SIZE; 933 va += PAGE_SIZE; 934 } 935 936 /* 937 * Allocate virtual address space for the dynamic percpu area. 938 */ 939 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 940 dpcpu = (void *)virtual_avail; 941 va = virtual_avail; 942 virtual_avail += DPCPU_SIZE; 943 while (va < virtual_avail) { 944 moea64_kenter(mmup, va, pa); 945 pa += PAGE_SIZE; 946 va += PAGE_SIZE; 947 } 948 dpcpu_init(dpcpu, 0); 949 950 /* 951 * Allocate some things for page zeroing. We put this directly 952 * in the page table, marked with LPTE_LOCKED, to avoid any 953 * of the PVO book-keeping or other parts of the VM system 954 * from even knowing that this hack exists. 955 */ 956 957 if (!hw_direct_map) { 958 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 959 MTX_DEF); 960 for (i = 0; i < 2; i++) { 961 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 962 virtual_end -= PAGE_SIZE; 963 964 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 965 966 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 967 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 968 LOCK_TABLE_RD(); 969 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 970 mmup, moea64_scratchpage_pvo[i]); 971 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 972 |= LPTE_LOCKED; 973 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 974 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 975 moea64_scratchpage_pvo[i]->pvo_vpn); 976 UNLOCK_TABLE_RD(); 977 } 978 } 979} 980 981/* 982 * Activate a user pmap. The pmap must be activated before its address 983 * space can be accessed in any way. 984 */ 985void 986moea64_activate(mmu_t mmu, struct thread *td) 987{ 988 pmap_t pm; 989 990 pm = &td->td_proc->p_vmspace->vm_pmap; 991 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 992 993 #ifdef __powerpc64__ 994 PCPU_SET(userslb, pm->pm_slb); 995 #else 996 PCPU_SET(curpmap, pm->pmap_phys); 997 #endif 998} 999 1000void 1001moea64_deactivate(mmu_t mmu, struct thread *td) 1002{ 1003 pmap_t pm; 1004 1005 pm = &td->td_proc->p_vmspace->vm_pmap; 1006 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1007 #ifdef __powerpc64__ 1008 PCPU_SET(userslb, NULL); 1009 #else 1010 PCPU_SET(curpmap, NULL); 1011 #endif 1012} 1013 1014void 1015moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1016{ 1017 struct pvo_entry *pvo; 1018 uintptr_t pt; 1019 uint64_t vsid; 1020 int i, ptegidx; 1021 1022 LOCK_TABLE_WR(); 1023 PMAP_LOCK(pm); 1024 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 1025 1026 if (pvo != NULL) { 1027 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1028 1029 if (wired) { 1030 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1031 pm->pm_stats.wired_count++; 1032 pvo->pvo_vaddr |= PVO_WIRED; 1033 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 1034 } else { 1035 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1036 pm->pm_stats.wired_count--; 1037 pvo->pvo_vaddr &= ~PVO_WIRED; 1038 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1039 } 1040 1041 if (pt != -1) { 1042 /* Update wiring flag in page table. */ 1043 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1044 pvo->pvo_vpn); 1045 } else if (wired) { 1046 /* 1047 * If we are wiring the page, and it wasn't in the 1048 * page table before, add it. 1049 */ 1050 vsid = PVO_VSID(pvo); 1051 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 1052 pvo->pvo_vaddr & PVO_LARGE); 1053 1054 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 1055 1056 if (i >= 0) { 1057 PVO_PTEGIDX_CLR(pvo); 1058 PVO_PTEGIDX_SET(pvo, i); 1059 } 1060 } 1061 1062 } 1063 UNLOCK_TABLE_WR(); 1064 PMAP_UNLOCK(pm); 1065} 1066 1067/* 1068 * This goes through and sets the physical address of our 1069 * special scratch PTE to the PA we want to zero or copy. Because 1070 * of locking issues (this can get called in pvo_enter() by 1071 * the UMA allocator), we can't use most other utility functions here 1072 */ 1073 1074static __inline 1075void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1076 1077 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1078 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1079 1080 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1081 ~(LPTE_WIMG | LPTE_RPGN); 1082 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1083 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1084 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1085 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1086 moea64_scratchpage_pvo[which]->pvo_vpn); 1087 isync(); 1088} 1089 1090void 1091moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1092{ 1093 vm_offset_t dst; 1094 vm_offset_t src; 1095 1096 dst = VM_PAGE_TO_PHYS(mdst); 1097 src = VM_PAGE_TO_PHYS(msrc); 1098 1099 if (hw_direct_map) { 1100 kcopy((void *)src, (void *)dst, PAGE_SIZE); 1101 } else { 1102 mtx_lock(&moea64_scratchpage_mtx); 1103 1104 moea64_set_scratchpage_pa(mmu, 0, src); 1105 moea64_set_scratchpage_pa(mmu, 1, dst); 1106 1107 kcopy((void *)moea64_scratchpage_va[0], 1108 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1109 1110 mtx_unlock(&moea64_scratchpage_mtx); 1111 } 1112} 1113 1114void 1115moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1116{ 1117 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1118 1119 if (size + off > PAGE_SIZE) 1120 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1121 1122 if (hw_direct_map) { 1123 bzero((caddr_t)pa + off, size); 1124 } else { 1125 mtx_lock(&moea64_scratchpage_mtx); 1126 moea64_set_scratchpage_pa(mmu, 0, pa); 1127 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1128 mtx_unlock(&moea64_scratchpage_mtx); 1129 } 1130} 1131 1132/* 1133 * Zero a page of physical memory by temporarily mapping it 1134 */ 1135void 1136moea64_zero_page(mmu_t mmu, vm_page_t m) 1137{ 1138 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1139 vm_offset_t va, off; 1140 1141 if (!hw_direct_map) { 1142 mtx_lock(&moea64_scratchpage_mtx); 1143 1144 moea64_set_scratchpage_pa(mmu, 0, pa); 1145 va = moea64_scratchpage_va[0]; 1146 } else { 1147 va = pa; 1148 } 1149 1150 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1151 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1152 1153 if (!hw_direct_map) 1154 mtx_unlock(&moea64_scratchpage_mtx); 1155} 1156 1157void 1158moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1159{ 1160 1161 moea64_zero_page(mmu, m); 1162} 1163 1164/* 1165 * Map the given physical page at the specified virtual address in the 1166 * target pmap with the protection requested. If specified the page 1167 * will be wired down. 1168 */ 1169 1170void 1171moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1172 vm_prot_t prot, boolean_t wired) 1173{ 1174 struct pvo_head *pvo_head; 1175 uma_zone_t zone; 1176 vm_page_t pg; 1177 uint64_t pte_lo; 1178 u_int pvo_flags; 1179 int error; 1180 1181 if (!moea64_initialized) { 1182 pvo_head = &moea64_pvo_kunmanaged; 1183 pg = NULL; 1184 zone = moea64_upvo_zone; 1185 pvo_flags = 0; 1186 } else { 1187 pvo_head = vm_page_to_pvoh(m); 1188 pg = m; 1189 zone = moea64_mpvo_zone; 1190 pvo_flags = PVO_MANAGED; 1191 } 1192 1193 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 1194 VM_OBJECT_LOCKED(m->object), 1195 ("moea64_enter: page %p is not busy", m)); 1196 1197 /* XXX change the pvo head for fake pages */ 1198 if ((m->oflags & VPO_UNMANAGED) != 0) { 1199 pvo_flags &= ~PVO_MANAGED; 1200 pvo_head = &moea64_pvo_kunmanaged; 1201 zone = moea64_upvo_zone; 1202 } 1203 1204 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1205 1206 if (prot & VM_PROT_WRITE) { 1207 pte_lo |= LPTE_BW; 1208 if (pmap_bootstrapped && 1209 (m->oflags & VPO_UNMANAGED) == 0) 1210 vm_page_aflag_set(m, PGA_WRITEABLE); 1211 } else 1212 pte_lo |= LPTE_BR; 1213 1214 if ((prot & VM_PROT_EXECUTE) == 0) 1215 pte_lo |= LPTE_NOEXEC; 1216 1217 if (wired) 1218 pvo_flags |= PVO_WIRED; 1219 1220 LOCK_TABLE_WR(); 1221 PMAP_LOCK(pmap); 1222 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1223 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags); 1224 PMAP_UNLOCK(pmap); 1225 UNLOCK_TABLE_WR(); 1226 1227 /* 1228 * Flush the page from the instruction cache if this page is 1229 * mapped executable and cacheable. 1230 */ 1231 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1232 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1233 vm_page_aflag_set(m, PGA_EXECUTABLE); 1234 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1235 } 1236} 1237 1238static void 1239moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1240 vm_size_t sz) 1241{ 1242 1243 /* 1244 * This is much trickier than on older systems because 1245 * we can't sync the icache on physical addresses directly 1246 * without a direct map. Instead we check a couple of cases 1247 * where the memory is already mapped in and, failing that, 1248 * use the same trick we use for page zeroing to create 1249 * a temporary mapping for this physical address. 1250 */ 1251 1252 if (!pmap_bootstrapped) { 1253 /* 1254 * If PMAP is not bootstrapped, we are likely to be 1255 * in real mode. 1256 */ 1257 __syncicache((void *)pa, sz); 1258 } else if (pmap == kernel_pmap) { 1259 __syncicache((void *)va, sz); 1260 } else if (hw_direct_map) { 1261 __syncicache((void *)pa, sz); 1262 } else { 1263 /* Use the scratch page to set up a temp mapping */ 1264 1265 mtx_lock(&moea64_scratchpage_mtx); 1266 1267 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1268 __syncicache((void *)(moea64_scratchpage_va[1] + 1269 (va & ADDR_POFF)), sz); 1270 1271 mtx_unlock(&moea64_scratchpage_mtx); 1272 } 1273} 1274 1275/* 1276 * Maps a sequence of resident pages belonging to the same object. 1277 * The sequence begins with the given page m_start. This page is 1278 * mapped at the given virtual address start. Each subsequent page is 1279 * mapped at a virtual address that is offset from start by the same 1280 * amount as the page is offset from m_start within the object. The 1281 * last page in the sequence is the page with the largest offset from 1282 * m_start that can be mapped at a virtual address less than the given 1283 * virtual address end. Not every virtual page between start and end 1284 * is mapped; only those for which a resident page exists with the 1285 * corresponding offset from m_start are mapped. 1286 */ 1287void 1288moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1289 vm_page_t m_start, vm_prot_t prot) 1290{ 1291 vm_page_t m; 1292 vm_pindex_t diff, psize; 1293 1294 psize = atop(end - start); 1295 m = m_start; 1296 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1297 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1298 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1299 m = TAILQ_NEXT(m, listq); 1300 } 1301} 1302 1303void 1304moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1305 vm_prot_t prot) 1306{ 1307 1308 moea64_enter(mmu, pm, va, m, 1309 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1310} 1311 1312vm_paddr_t 1313moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1314{ 1315 struct pvo_entry *pvo; 1316 vm_paddr_t pa; 1317 1318 LOCK_TABLE_RD(); 1319 PMAP_LOCK(pm); 1320 pvo = moea64_pvo_find_va(pm, va); 1321 if (pvo == NULL) 1322 pa = 0; 1323 else 1324 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1325 (va - PVO_VADDR(pvo)); 1326 UNLOCK_TABLE_RD(); 1327 PMAP_UNLOCK(pm); 1328 return (pa); 1329} 1330 1331/* 1332 * Atomically extract and hold the physical page with the given 1333 * pmap and virtual address pair if that mapping permits the given 1334 * protection. 1335 */ 1336vm_page_t 1337moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1338{ 1339 struct pvo_entry *pvo; 1340 vm_page_t m; 1341 vm_paddr_t pa; 1342 1343 m = NULL; 1344 pa = 0; 1345 LOCK_TABLE_RD(); 1346 PMAP_LOCK(pmap); 1347retry: 1348 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1349 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1350 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1351 (prot & VM_PROT_WRITE) == 0)) { 1352 if (vm_page_pa_tryrelock(pmap, 1353 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1354 goto retry; 1355 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1356 vm_page_hold(m); 1357 } 1358 PA_UNLOCK_COND(pa); 1359 UNLOCK_TABLE_RD(); 1360 PMAP_UNLOCK(pmap); 1361 return (m); 1362} 1363 1364static mmu_t installed_mmu; 1365 1366static void * 1367moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1368{ 1369 /* 1370 * This entire routine is a horrible hack to avoid bothering kmem 1371 * for new KVA addresses. Because this can get called from inside 1372 * kmem allocation routines, calling kmem for a new address here 1373 * can lead to multiply locking non-recursive mutexes. 1374 */ 1375 vm_offset_t va; 1376 1377 vm_page_t m; 1378 int pflags, needed_lock; 1379 1380 *flags = UMA_SLAB_PRIV; 1381 needed_lock = !PMAP_LOCKED(kernel_pmap); 1382 1383 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1384 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1385 else 1386 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1387 if (wait & M_ZERO) 1388 pflags |= VM_ALLOC_ZERO; 1389 1390 for (;;) { 1391 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1392 if (m == NULL) { 1393 if (wait & M_NOWAIT) 1394 return (NULL); 1395 VM_WAIT; 1396 } else 1397 break; 1398 } 1399 1400 va = VM_PAGE_TO_PHYS(m); 1401 1402 LOCK_TABLE_WR(); 1403 if (needed_lock) 1404 PMAP_LOCK(kernel_pmap); 1405 1406 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1407 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1408 PVO_WIRED | PVO_BOOTSTRAP); 1409 1410 if (needed_lock) 1411 PMAP_UNLOCK(kernel_pmap); 1412 UNLOCK_TABLE_WR(); 1413 1414 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1415 bzero((void *)va, PAGE_SIZE); 1416 1417 return (void *)va; 1418} 1419 1420extern int elf32_nxstack; 1421 1422void 1423moea64_init(mmu_t mmu) 1424{ 1425 1426 CTR0(KTR_PMAP, "moea64_init"); 1427 1428 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1429 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1430 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1431 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1432 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1433 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1434 1435 if (!hw_direct_map) { 1436 installed_mmu = mmu; 1437 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1438 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1439 } 1440 1441#ifdef COMPAT_FREEBSD32 1442 elf32_nxstack = 1; 1443#endif 1444 1445 moea64_initialized = TRUE; 1446} 1447 1448boolean_t 1449moea64_is_referenced(mmu_t mmu, vm_page_t m) 1450{ 1451 1452 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1453 ("moea64_is_referenced: page %p is not managed", m)); 1454 return (moea64_query_bit(mmu, m, PTE_REF)); 1455} 1456 1457boolean_t 1458moea64_is_modified(mmu_t mmu, vm_page_t m) 1459{ 1460 1461 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1462 ("moea64_is_modified: page %p is not managed", m)); 1463 1464 /* 1465 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 1466 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1467 * is clear, no PTEs can have LPTE_CHG set. 1468 */ 1469 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1470 if ((m->oflags & VPO_BUSY) == 0 && 1471 (m->aflags & PGA_WRITEABLE) == 0) 1472 return (FALSE); 1473 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1474} 1475 1476boolean_t 1477moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1478{ 1479 struct pvo_entry *pvo; 1480 boolean_t rv; 1481 1482 LOCK_TABLE_RD(); 1483 PMAP_LOCK(pmap); 1484 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1485 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1486 PMAP_UNLOCK(pmap); 1487 UNLOCK_TABLE_RD(); 1488 return (rv); 1489} 1490 1491void 1492moea64_clear_reference(mmu_t mmu, vm_page_t m) 1493{ 1494 1495 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1496 ("moea64_clear_reference: page %p is not managed", m)); 1497 moea64_clear_bit(mmu, m, LPTE_REF); 1498} 1499 1500void 1501moea64_clear_modify(mmu_t mmu, vm_page_t m) 1502{ 1503 1504 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1505 ("moea64_clear_modify: page %p is not managed", m)); 1506 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1507 KASSERT((m->oflags & VPO_BUSY) == 0, 1508 ("moea64_clear_modify: page %p is busy", m)); 1509 1510 /* 1511 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1512 * set. If the object containing the page is locked and the page is 1513 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 1514 */ 1515 if ((m->aflags & PGA_WRITEABLE) == 0) 1516 return; 1517 moea64_clear_bit(mmu, m, LPTE_CHG); 1518} 1519 1520/* 1521 * Clear the write and modified bits in each of the given page's mappings. 1522 */ 1523void 1524moea64_remove_write(mmu_t mmu, vm_page_t m) 1525{ 1526 struct pvo_entry *pvo; 1527 uintptr_t pt; 1528 pmap_t pmap; 1529 uint64_t lo = 0; 1530 1531 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1532 ("moea64_remove_write: page %p is not managed", m)); 1533 1534 /* 1535 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 1536 * another thread while the object is locked. Thus, if PGA_WRITEABLE 1537 * is clear, no page table entries need updating. 1538 */ 1539 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1540 if ((m->oflags & VPO_BUSY) == 0 && 1541 (m->aflags & PGA_WRITEABLE) == 0) 1542 return; 1543 powerpc_sync(); 1544 LOCK_TABLE_RD(); 1545 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1546 pmap = pvo->pvo_pmap; 1547 PMAP_LOCK(pmap); 1548 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1549 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1550 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1551 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1552 if (pt != -1) { 1553 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1554 lo |= pvo->pvo_pte.lpte.pte_lo; 1555 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1556 MOEA64_PTE_CHANGE(mmu, pt, 1557 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1558 if (pvo->pvo_pmap == kernel_pmap) 1559 isync(); 1560 } 1561 } 1562 if ((lo & LPTE_CHG) != 0) 1563 vm_page_dirty(m); 1564 PMAP_UNLOCK(pmap); 1565 } 1566 UNLOCK_TABLE_RD(); 1567 vm_page_aflag_clear(m, PGA_WRITEABLE); 1568} 1569 1570/* 1571 * moea64_ts_referenced: 1572 * 1573 * Return a count of reference bits for a page, clearing those bits. 1574 * It is not necessary for every reference bit to be cleared, but it 1575 * is necessary that 0 only be returned when there are truly no 1576 * reference bits set. 1577 * 1578 * XXX: The exact number of bits to check and clear is a matter that 1579 * should be tested and standardized at some point in the future for 1580 * optimal aging of shared pages. 1581 */ 1582boolean_t 1583moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1584{ 1585 1586 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1587 ("moea64_ts_referenced: page %p is not managed", m)); 1588 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1589} 1590 1591/* 1592 * Modify the WIMG settings of all mappings for a page. 1593 */ 1594void 1595moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1596{ 1597 struct pvo_entry *pvo; 1598 struct pvo_head *pvo_head; 1599 uintptr_t pt; 1600 pmap_t pmap; 1601 uint64_t lo; 1602 1603 if ((m->oflags & VPO_UNMANAGED) != 0) { 1604 m->md.mdpg_cache_attrs = ma; 1605 return; 1606 } 1607 1608 pvo_head = vm_page_to_pvoh(m); 1609 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1610 LOCK_TABLE_RD(); 1611 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1612 pmap = pvo->pvo_pmap; 1613 PMAP_LOCK(pmap); 1614 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1615 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1616 pvo->pvo_pte.lpte.pte_lo |= lo; 1617 if (pt != -1) { 1618 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1619 pvo->pvo_vpn); 1620 if (pvo->pvo_pmap == kernel_pmap) 1621 isync(); 1622 } 1623 PMAP_UNLOCK(pmap); 1624 } 1625 UNLOCK_TABLE_RD(); 1626 m->md.mdpg_cache_attrs = ma; 1627} 1628 1629/* 1630 * Map a wired page into kernel virtual address space. 1631 */ 1632void 1633moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1634{ 1635 uint64_t pte_lo; 1636 int error; 1637 1638 pte_lo = moea64_calc_wimg(pa, ma); 1639 1640 LOCK_TABLE_WR(); 1641 PMAP_LOCK(kernel_pmap); 1642 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1643 &moea64_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1644 PMAP_UNLOCK(kernel_pmap); 1645 UNLOCK_TABLE_WR(); 1646 1647 if (error != 0 && error != ENOENT) 1648 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1649 pa, error); 1650} 1651 1652void 1653moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1654{ 1655 1656 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1657} 1658 1659/* 1660 * Extract the physical page address associated with the given kernel virtual 1661 * address. 1662 */ 1663vm_offset_t 1664moea64_kextract(mmu_t mmu, vm_offset_t va) 1665{ 1666 struct pvo_entry *pvo; 1667 vm_paddr_t pa; 1668 1669 /* 1670 * Shortcut the direct-mapped case when applicable. We never put 1671 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1672 */ 1673 if (va < VM_MIN_KERNEL_ADDRESS) 1674 return (va); 1675 1676 LOCK_TABLE_RD(); 1677 PMAP_LOCK(kernel_pmap); 1678 pvo = moea64_pvo_find_va(kernel_pmap, va); 1679 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1680 va)); 1681 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1682 UNLOCK_TABLE_RD(); 1683 PMAP_UNLOCK(kernel_pmap); 1684 return (pa); 1685} 1686 1687/* 1688 * Remove a wired page from kernel virtual address space. 1689 */ 1690void 1691moea64_kremove(mmu_t mmu, vm_offset_t va) 1692{ 1693 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1694} 1695 1696/* 1697 * Map a range of physical addresses into kernel virtual address space. 1698 * 1699 * The value passed in *virt is a suggested virtual address for the mapping. 1700 * Architectures which can support a direct-mapped physical to virtual region 1701 * can return the appropriate address within that region, leaving '*virt' 1702 * unchanged. We cannot and therefore do not; *virt is updated with the 1703 * first usable address after the mapped region. 1704 */ 1705vm_offset_t 1706moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1707 vm_offset_t pa_end, int prot) 1708{ 1709 vm_offset_t sva, va; 1710 1711 sva = *virt; 1712 va = sva; 1713 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1714 moea64_kenter(mmu, va, pa_start); 1715 *virt = va; 1716 1717 return (sva); 1718} 1719 1720/* 1721 * Returns true if the pmap's pv is one of the first 1722 * 16 pvs linked to from this page. This count may 1723 * be changed upwards or downwards in the future; it 1724 * is only necessary that true be returned for a small 1725 * subset of pmaps for proper page aging. 1726 */ 1727boolean_t 1728moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1729{ 1730 int loops; 1731 struct pvo_entry *pvo; 1732 boolean_t rv; 1733 1734 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1735 ("moea64_page_exists_quick: page %p is not managed", m)); 1736 loops = 0; 1737 rv = FALSE; 1738 LOCK_TABLE_RD(); 1739 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1740 if (pvo->pvo_pmap == pmap) { 1741 rv = TRUE; 1742 break; 1743 } 1744 if (++loops >= 16) 1745 break; 1746 } 1747 UNLOCK_TABLE_RD(); 1748 return (rv); 1749} 1750 1751/* 1752 * Return the number of managed mappings to the given physical page 1753 * that are wired. 1754 */ 1755int 1756moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1757{ 1758 struct pvo_entry *pvo; 1759 int count; 1760 1761 count = 0; 1762 if ((m->oflags & VPO_UNMANAGED) != 0) 1763 return (count); 1764 LOCK_TABLE_RD(); 1765 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1766 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1767 count++; 1768 UNLOCK_TABLE_RD(); 1769 return (count); 1770} 1771 1772static uintptr_t moea64_vsidcontext; 1773 1774uintptr_t 1775moea64_get_unique_vsid(void) { 1776 u_int entropy; 1777 register_t hash; 1778 uint32_t mask; 1779 int i; 1780 1781 entropy = 0; 1782 __asm __volatile("mftb %0" : "=r"(entropy)); 1783 1784 mtx_lock(&moea64_slb_mutex); 1785 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1786 u_int n; 1787 1788 /* 1789 * Create a new value by mutiplying by a prime and adding in 1790 * entropy from the timebase register. This is to make the 1791 * VSID more random so that the PT hash function collides 1792 * less often. (Note that the prime casues gcc to do shifts 1793 * instead of a multiply.) 1794 */ 1795 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1796 hash = moea64_vsidcontext & (NVSIDS - 1); 1797 if (hash == 0) /* 0 is special, avoid it */ 1798 continue; 1799 n = hash >> 5; 1800 mask = 1 << (hash & (VSID_NBPW - 1)); 1801 hash = (moea64_vsidcontext & VSID_HASHMASK); 1802 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1803 /* anything free in this bucket? */ 1804 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1805 entropy = (moea64_vsidcontext >> 20); 1806 continue; 1807 } 1808 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1809 mask = 1 << i; 1810 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1811 hash |= i; 1812 } 1813 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1814 ("Allocating in-use VSID %#zx\n", hash)); 1815 moea64_vsid_bitmap[n] |= mask; 1816 mtx_unlock(&moea64_slb_mutex); 1817 return (hash); 1818 } 1819 1820 mtx_unlock(&moea64_slb_mutex); 1821 panic("%s: out of segments",__func__); 1822} 1823 1824#ifdef __powerpc64__ 1825void 1826moea64_pinit(mmu_t mmu, pmap_t pmap) 1827{ 1828 PMAP_LOCK_INIT(pmap); 1829 LIST_INIT(&pmap->pmap_pvo); 1830 1831 pmap->pm_slb_tree_root = slb_alloc_tree(); 1832 pmap->pm_slb = slb_alloc_user_cache(); 1833 pmap->pm_slb_len = 0; 1834} 1835#else 1836void 1837moea64_pinit(mmu_t mmu, pmap_t pmap) 1838{ 1839 int i; 1840 uint32_t hash; 1841 1842 PMAP_LOCK_INIT(pmap); 1843 LIST_INIT(&pmap->pmap_pvo); 1844 1845 if (pmap_bootstrapped) 1846 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1847 (vm_offset_t)pmap); 1848 else 1849 pmap->pmap_phys = pmap; 1850 1851 /* 1852 * Allocate some segment registers for this pmap. 1853 */ 1854 hash = moea64_get_unique_vsid(); 1855 1856 for (i = 0; i < 16; i++) 1857 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1858 1859 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1860} 1861#endif 1862 1863/* 1864 * Initialize the pmap associated with process 0. 1865 */ 1866void 1867moea64_pinit0(mmu_t mmu, pmap_t pm) 1868{ 1869 moea64_pinit(mmu, pm); 1870 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1871} 1872 1873/* 1874 * Set the physical protection on the specified range of this map as requested. 1875 */ 1876static void 1877moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 1878{ 1879 uintptr_t pt; 1880 struct vm_page *pg; 1881 uint64_t oldlo; 1882 1883 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1884 1885 /* 1886 * Grab the PTE pointer before we diddle with the cached PTE 1887 * copy. 1888 */ 1889 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1890 1891 /* 1892 * Change the protection of the page. 1893 */ 1894 oldlo = pvo->pvo_pte.lpte.pte_lo; 1895 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1896 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1897 if ((prot & VM_PROT_EXECUTE) == 0) 1898 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1899 if (prot & VM_PROT_WRITE) 1900 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW; 1901 else 1902 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1903 1904 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1905 1906 /* 1907 * If the PVO is in the page table, update that pte as well. 1908 */ 1909 if (pt != -1) 1910 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1911 pvo->pvo_vpn); 1912 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 1913 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1914 if ((pg->oflags & VPO_UNMANAGED) == 0) 1915 vm_page_aflag_set(pg, PGA_EXECUTABLE); 1916 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 1917 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE); 1918 } 1919 1920 /* 1921 * Update vm about the REF/CHG bits if the page is managed and we have 1922 * removed write access. 1923 */ 1924 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && 1925 (oldlo & LPTE_PP) != LPTE_BR && !(prot && VM_PROT_WRITE)) { 1926 if (pg != NULL) { 1927 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 1928 vm_page_dirty(pg); 1929 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 1930 vm_page_aflag_set(pg, PGA_REFERENCED); 1931 } 1932 } 1933} 1934 1935void 1936moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1937 vm_prot_t prot) 1938{ 1939 struct pvo_entry *pvo, *tpvo; 1940 1941 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 1942 sva, eva, prot); 1943 1944 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1945 ("moea64_protect: non current pmap")); 1946 1947 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1948 moea64_remove(mmu, pm, sva, eva); 1949 return; 1950 } 1951 1952 LOCK_TABLE_RD(); 1953 PMAP_LOCK(pm); 1954 if ((eva - sva)/PAGE_SIZE < pm->pm_stats.resident_count) { 1955 while (sva < eva) { 1956 #ifdef __powerpc64__ 1957 if (pm != kernel_pmap && 1958 user_va_to_slb_entry(pm, sva) == NULL) { 1959 sva = roundup2(sva + 1, SEGMENT_LENGTH); 1960 continue; 1961 } 1962 #endif 1963 pvo = moea64_pvo_find_va(pm, sva); 1964 if (pvo != NULL) 1965 moea64_pvo_protect(mmu, pm, pvo, prot); 1966 sva += PAGE_SIZE; 1967 } 1968 } else { 1969 LIST_FOREACH_SAFE(pvo, &pm->pmap_pvo, pvo_plink, tpvo) { 1970 if (PVO_VADDR(pvo) < sva || PVO_VADDR(pvo) >= eva) 1971 continue; 1972 moea64_pvo_protect(mmu, pm, pvo, prot); 1973 } 1974 } 1975 UNLOCK_TABLE_RD(); 1976 PMAP_UNLOCK(pm); 1977} 1978 1979/* 1980 * Map a list of wired pages into kernel virtual address space. This is 1981 * intended for temporary mappings which do not need page modification or 1982 * references recorded. Existing mappings in the region are overwritten. 1983 */ 1984void 1985moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 1986{ 1987 while (count-- > 0) { 1988 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1989 va += PAGE_SIZE; 1990 m++; 1991 } 1992} 1993 1994/* 1995 * Remove page mappings from kernel virtual address space. Intended for 1996 * temporary mappings entered by moea64_qenter. 1997 */ 1998void 1999moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2000{ 2001 while (count-- > 0) { 2002 moea64_kremove(mmu, va); 2003 va += PAGE_SIZE; 2004 } 2005} 2006 2007void 2008moea64_release_vsid(uint64_t vsid) 2009{ 2010 int idx, mask; 2011 2012 mtx_lock(&moea64_slb_mutex); 2013 idx = vsid & (NVSIDS-1); 2014 mask = 1 << (idx % VSID_NBPW); 2015 idx /= VSID_NBPW; 2016 KASSERT(moea64_vsid_bitmap[idx] & mask, 2017 ("Freeing unallocated VSID %#jx", vsid)); 2018 moea64_vsid_bitmap[idx] &= ~mask; 2019 mtx_unlock(&moea64_slb_mutex); 2020} 2021 2022 2023void 2024moea64_release(mmu_t mmu, pmap_t pmap) 2025{ 2026 2027 /* 2028 * Free segment registers' VSIDs 2029 */ 2030 #ifdef __powerpc64__ 2031 slb_free_tree(pmap); 2032 slb_free_user_cache(pmap->pm_slb); 2033 #else 2034 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2035 2036 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2037 #endif 2038 2039 PMAP_LOCK_DESTROY(pmap); 2040} 2041 2042/* 2043 * Remove all pages mapped by the specified pmap 2044 */ 2045void 2046moea64_remove_pages(mmu_t mmu, pmap_t pm) 2047{ 2048 struct pvo_entry *pvo, *tpvo; 2049 2050 LOCK_TABLE_WR(); 2051 PMAP_LOCK(pm); 2052 LIST_FOREACH_SAFE(pvo, &pm->pmap_pvo, pvo_plink, tpvo) { 2053 if (!(pvo->pvo_vaddr & PVO_WIRED)) 2054 moea64_pvo_remove(mmu, pvo); 2055 } 2056 UNLOCK_TABLE_WR(); 2057 PMAP_UNLOCK(pm); 2058} 2059 2060/* 2061 * Remove the given range of addresses from the specified map. 2062 */ 2063void 2064moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2065{ 2066 struct pvo_entry *pvo, *tpvo; 2067 2068 /* 2069 * Perform an unsynchronized read. This is, however, safe. 2070 */ 2071 if (pm->pm_stats.resident_count == 0) 2072 return; 2073 2074 LOCK_TABLE_WR(); 2075 PMAP_LOCK(pm); 2076 if ((eva - sva)/PAGE_SIZE < pm->pm_stats.resident_count) { 2077 while (sva < eva) { 2078 #ifdef __powerpc64__ 2079 if (pm != kernel_pmap && 2080 user_va_to_slb_entry(pm, sva) == NULL) { 2081 sva = roundup2(sva + 1, SEGMENT_LENGTH); 2082 continue; 2083 } 2084 #endif 2085 pvo = moea64_pvo_find_va(pm, sva); 2086 if (pvo != NULL) 2087 moea64_pvo_remove(mmu, pvo); 2088 sva += PAGE_SIZE; 2089 } 2090 } else { 2091 LIST_FOREACH_SAFE(pvo, &pm->pmap_pvo, pvo_plink, tpvo) { 2092 if (PVO_VADDR(pvo) < sva || PVO_VADDR(pvo) >= eva) 2093 continue; 2094 moea64_pvo_remove(mmu, pvo); 2095 } 2096 } 2097 UNLOCK_TABLE_WR(); 2098 PMAP_UNLOCK(pm); 2099} 2100 2101/* 2102 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2103 * will reflect changes in pte's back to the vm_page. 2104 */ 2105void 2106moea64_remove_all(mmu_t mmu, vm_page_t m) 2107{ 2108 struct pvo_entry *pvo, *next_pvo; 2109 pmap_t pmap; 2110 2111 LOCK_TABLE_WR(); 2112 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2113 pmap = pvo->pvo_pmap; 2114 PMAP_LOCK(pmap); 2115 moea64_pvo_remove(mmu, pvo); 2116 PMAP_UNLOCK(pmap); 2117 } 2118 UNLOCK_TABLE_WR(); 2119 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m)) 2120 vm_page_dirty(m); 2121 vm_page_aflag_clear(m, PGA_WRITEABLE); 2122 vm_page_aflag_clear(m, PGA_EXECUTABLE); 2123} 2124 2125/* 2126 * Allocate a physical page of memory directly from the phys_avail map. 2127 * Can only be called from moea64_bootstrap before avail start and end are 2128 * calculated. 2129 */ 2130vm_offset_t 2131moea64_bootstrap_alloc(vm_size_t size, u_int align) 2132{ 2133 vm_offset_t s, e; 2134 int i, j; 2135 2136 size = round_page(size); 2137 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2138 if (align != 0) 2139 s = (phys_avail[i] + align - 1) & ~(align - 1); 2140 else 2141 s = phys_avail[i]; 2142 e = s + size; 2143 2144 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2145 continue; 2146 2147 if (s + size > platform_real_maxaddr()) 2148 continue; 2149 2150 if (s == phys_avail[i]) { 2151 phys_avail[i] += size; 2152 } else if (e == phys_avail[i + 1]) { 2153 phys_avail[i + 1] -= size; 2154 } else { 2155 for (j = phys_avail_count * 2; j > i; j -= 2) { 2156 phys_avail[j] = phys_avail[j - 2]; 2157 phys_avail[j + 1] = phys_avail[j - 1]; 2158 } 2159 2160 phys_avail[i + 3] = phys_avail[i + 1]; 2161 phys_avail[i + 1] = s; 2162 phys_avail[i + 2] = e; 2163 phys_avail_count++; 2164 } 2165 2166 return (s); 2167 } 2168 panic("moea64_bootstrap_alloc: could not allocate memory"); 2169} 2170 2171static int 2172moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2173 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2174 uint64_t pte_lo, int flags) 2175{ 2176 struct pvo_entry *pvo; 2177 uint64_t vsid; 2178 int first; 2179 u_int ptegidx; 2180 int i; 2181 int bootstrap; 2182 2183 /* 2184 * One nasty thing that can happen here is that the UMA calls to 2185 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2186 * which calls UMA... 2187 * 2188 * We break the loop by detecting recursion and allocating out of 2189 * the bootstrap pool. 2190 */ 2191 2192 first = 0; 2193 bootstrap = (flags & PVO_BOOTSTRAP); 2194 2195 if (!moea64_initialized) 2196 bootstrap = 1; 2197 2198 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2199 rw_assert(&moea64_table_lock, RA_WLOCKED); 2200 2201 /* 2202 * Compute the PTE Group index. 2203 */ 2204 va &= ~ADDR_POFF; 2205 vsid = va_to_vsid(pm, va); 2206 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2207 2208 /* 2209 * Remove any existing mapping for this page. Reuse the pvo entry if 2210 * there is a mapping. 2211 */ 2212 moea64_pvo_enter_calls++; 2213 2214 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2215 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2216 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2217 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2218 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2219 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2220 /* Re-insert if spilled */ 2221 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2222 &pvo->pvo_pte.lpte); 2223 if (i >= 0) 2224 PVO_PTEGIDX_SET(pvo, i); 2225 moea64_pte_overflow--; 2226 } 2227 return (0); 2228 } 2229 moea64_pvo_remove(mmu, pvo); 2230 break; 2231 } 2232 } 2233 2234 /* 2235 * If we aren't overwriting a mapping, try to allocate. 2236 */ 2237 if (bootstrap) { 2238 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2239 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2240 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2241 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2242 } 2243 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2244 moea64_bpvo_pool_index++; 2245 bootstrap = 1; 2246 } else { 2247 /* 2248 * Note: drop the table lock around the UMA allocation in 2249 * case the UMA allocator needs to manipulate the page 2250 * table. The mapping we are working with is already 2251 * protected by the PMAP lock. 2252 */ 2253 pvo = uma_zalloc(zone, M_NOWAIT); 2254 } 2255 2256 if (pvo == NULL) 2257 return (ENOMEM); 2258 2259 moea64_pvo_entries++; 2260 pvo->pvo_vaddr = va; 2261 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2262 | (vsid << 16); 2263 pvo->pvo_pmap = pm; 2264 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2265 pvo->pvo_vaddr &= ~ADDR_POFF; 2266 2267 if (flags & PVO_WIRED) 2268 pvo->pvo_vaddr |= PVO_WIRED; 2269 if (pvo_head != &moea64_pvo_kunmanaged) 2270 pvo->pvo_vaddr |= PVO_MANAGED; 2271 if (bootstrap) 2272 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2273 if (flags & PVO_LARGE) 2274 pvo->pvo_vaddr |= PVO_LARGE; 2275 2276 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2277 (uint64_t)(pa) | pte_lo, flags); 2278 2279 /* 2280 * Add to pmap list 2281 */ 2282 LIST_INSERT_HEAD(&pm->pmap_pvo, pvo, pvo_plink); 2283 2284 /* 2285 * Remember if the list was empty and therefore will be the first 2286 * item. 2287 */ 2288 if (LIST_FIRST(pvo_head) == NULL) 2289 first = 1; 2290 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2291 2292 if (pvo->pvo_vaddr & PVO_WIRED) { 2293 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2294 pm->pm_stats.wired_count++; 2295 } 2296 pm->pm_stats.resident_count++; 2297 2298 /* 2299 * We hope this succeeds but it isn't required. 2300 */ 2301 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2302 if (i >= 0) { 2303 PVO_PTEGIDX_SET(pvo, i); 2304 } else { 2305 panic("moea64_pvo_enter: overflow"); 2306 moea64_pte_overflow++; 2307 } 2308 2309 if (pm == kernel_pmap) 2310 isync(); 2311 2312#ifdef __powerpc64__ 2313 /* 2314 * Make sure all our bootstrap mappings are in the SLB as soon 2315 * as virtual memory is switched on. 2316 */ 2317 if (!pmap_bootstrapped) 2318 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2319#endif 2320 2321 return (first ? ENOENT : 0); 2322} 2323 2324static void 2325moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2326{ 2327 struct vm_page *pg; 2328 uintptr_t pt; 2329 2330 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2331 rw_assert(&moea64_table_lock, RA_WLOCKED); 2332 2333 /* 2334 * If there is an active pte entry, we need to deactivate it (and 2335 * save the ref & cfg bits). 2336 */ 2337 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2338 if (pt != -1) { 2339 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2340 PVO_PTEGIDX_CLR(pvo); 2341 } else { 2342 moea64_pte_overflow--; 2343 } 2344 2345 /* 2346 * Update our statistics. 2347 */ 2348 pvo->pvo_pmap->pm_stats.resident_count--; 2349 if (pvo->pvo_vaddr & PVO_WIRED) 2350 pvo->pvo_pmap->pm_stats.wired_count--; 2351 2352 /* 2353 * Remove this PVO from the PV and pmap lists. 2354 */ 2355 LIST_REMOVE(pvo, pvo_vlink); 2356 LIST_REMOVE(pvo, pvo_plink); 2357 2358 /* 2359 * Remove this from the overflow list and return it to the pool 2360 * if we aren't going to reuse it. 2361 */ 2362 LIST_REMOVE(pvo, pvo_olink); 2363 2364 /* 2365 * Update vm about the REF/CHG bits if the page is managed. 2366 */ 2367 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2368 2369 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) { 2370 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 2371 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 2372 vm_page_dirty(pg); 2373 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 2374 vm_page_aflag_set(pg, PGA_REFERENCED); 2375 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2376 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2377 } 2378 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2379 vm_page_aflag_clear(pg, PGA_EXECUTABLE); 2380 } 2381 2382 moea64_pvo_entries--; 2383 moea64_pvo_remove_calls++; 2384 2385 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2386 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2387 moea64_upvo_zone, pvo); 2388} 2389 2390static struct pvo_entry * 2391moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2392{ 2393 struct pvo_entry *pvo; 2394 int ptegidx; 2395 uint64_t vsid; 2396 #ifdef __powerpc64__ 2397 uint64_t slbv; 2398 2399 if (pm == kernel_pmap) { 2400 slbv = kernel_va_to_slbv(va); 2401 } else { 2402 struct slb *slb; 2403 slb = user_va_to_slb_entry(pm, va); 2404 /* The page is not mapped if the segment isn't */ 2405 if (slb == NULL) 2406 return NULL; 2407 slbv = slb->slbv; 2408 } 2409 2410 vsid = (slbv & SLBV_VSID_MASK) >> SLBV_VSID_SHIFT; 2411 if (slbv & SLBV_L) 2412 va &= ~moea64_large_page_mask; 2413 else 2414 va &= ~ADDR_POFF; 2415 ptegidx = va_to_pteg(vsid, va, slbv & SLBV_L); 2416 #else 2417 va &= ~ADDR_POFF; 2418 vsid = va_to_vsid(pm, va); 2419 ptegidx = va_to_pteg(vsid, va, 0); 2420 #endif 2421 2422 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2423 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) 2424 break; 2425 } 2426 2427 return (pvo); 2428} 2429 2430static boolean_t 2431moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2432{ 2433 struct pvo_entry *pvo; 2434 uintptr_t pt; 2435 2436 LOCK_TABLE_RD(); 2437 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2438 /* 2439 * See if we saved the bit off. If so, return success. 2440 */ 2441 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2442 UNLOCK_TABLE_RD(); 2443 return (TRUE); 2444 } 2445 } 2446 2447 /* 2448 * No luck, now go through the hard part of looking at the PTEs 2449 * themselves. Sync so that any pending REF/CHG bits are flushed to 2450 * the PTEs. 2451 */ 2452 powerpc_sync(); 2453 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2454 2455 /* 2456 * See if this pvo has a valid PTE. if so, fetch the 2457 * REF/CHG bits from the valid PTE. If the appropriate 2458 * ptebit is set, return success. 2459 */ 2460 PMAP_LOCK(pvo->pvo_pmap); 2461 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2462 if (pt != -1) { 2463 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2464 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2465 PMAP_UNLOCK(pvo->pvo_pmap); 2466 UNLOCK_TABLE_RD(); 2467 return (TRUE); 2468 } 2469 } 2470 PMAP_UNLOCK(pvo->pvo_pmap); 2471 } 2472 2473 UNLOCK_TABLE_RD(); 2474 return (FALSE); 2475} 2476 2477static u_int 2478moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2479{ 2480 u_int count; 2481 struct pvo_entry *pvo; 2482 uintptr_t pt; 2483 2484 /* 2485 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2486 * we can reset the right ones). note that since the pvo entries and 2487 * list heads are accessed via BAT0 and are never placed in the page 2488 * table, we don't have to worry about further accesses setting the 2489 * REF/CHG bits. 2490 */ 2491 powerpc_sync(); 2492 2493 /* 2494 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2495 * valid pte clear the ptebit from the valid pte. 2496 */ 2497 count = 0; 2498 LOCK_TABLE_RD(); 2499 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2500 PMAP_LOCK(pvo->pvo_pmap); 2501 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2502 if (pt != -1) { 2503 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2504 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2505 count++; 2506 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2507 pvo->pvo_vpn, ptebit); 2508 } 2509 } 2510 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2511 PMAP_UNLOCK(pvo->pvo_pmap); 2512 } 2513 2514 UNLOCK_TABLE_RD(); 2515 return (count); 2516} 2517 2518boolean_t 2519moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2520{ 2521 struct pvo_entry *pvo; 2522 vm_offset_t ppa; 2523 int error = 0; 2524 2525 LOCK_TABLE_RD(); 2526 PMAP_LOCK(kernel_pmap); 2527 for (ppa = pa & ~ADDR_POFF; ppa < pa + size; ppa += PAGE_SIZE) { 2528 pvo = moea64_pvo_find_va(kernel_pmap, ppa); 2529 if (pvo == NULL || 2530 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2531 error = EFAULT; 2532 break; 2533 } 2534 } 2535 UNLOCK_TABLE_RD(); 2536 PMAP_UNLOCK(kernel_pmap); 2537 2538 return (error); 2539} 2540 2541/* 2542 * Map a set of physical memory pages into the kernel virtual 2543 * address space. Return a pointer to where it is mapped. This 2544 * routine is intended to be used for mapping device memory, 2545 * NOT real memory. 2546 */ 2547void * 2548moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2549{ 2550 vm_offset_t va, tmpva, ppa, offset; 2551 2552 ppa = trunc_page(pa); 2553 offset = pa & PAGE_MASK; 2554 size = roundup2(offset + size, PAGE_SIZE); 2555 2556 va = kmem_alloc_nofault(kernel_map, size); 2557 2558 if (!va) 2559 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2560 2561 for (tmpva = va; size > 0;) { 2562 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2563 size -= PAGE_SIZE; 2564 tmpva += PAGE_SIZE; 2565 ppa += PAGE_SIZE; 2566 } 2567 2568 return ((void *)(va + offset)); 2569} 2570 2571void * 2572moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2573{ 2574 2575 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2576} 2577 2578void 2579moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2580{ 2581 vm_offset_t base, offset; 2582 2583 base = trunc_page(va); 2584 offset = va & PAGE_MASK; 2585 size = roundup2(offset + size, PAGE_SIZE); 2586 2587 kmem_free(kernel_map, base, size); 2588} 2589 2590void 2591moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2592{ 2593 struct pvo_entry *pvo; 2594 vm_offset_t lim; 2595 vm_paddr_t pa; 2596 vm_size_t len; 2597 2598 LOCK_TABLE_RD(); 2599 PMAP_LOCK(pm); 2600 while (sz > 0) { 2601 lim = round_page(va); 2602 len = MIN(lim - va, sz); 2603 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2604 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) { 2605 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 2606 (va & ADDR_POFF); 2607 moea64_syncicache(mmu, pm, va, pa, len); 2608 } 2609 va += len; 2610 sz -= len; 2611 } 2612 UNLOCK_TABLE_RD(); 2613 PMAP_UNLOCK(pm); 2614} 2615