mmu_oea64.c revision 213335
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#include <sys/cdefs.h> 94__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea64.c 213335 2010-10-01 18:59:30Z nwhitehorn $"); 95 96/* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117#include "opt_kstack_pages.h" 118 119#include <sys/param.h> 120#include <sys/kernel.h> 121#include <sys/ktr.h> 122#include <sys/lock.h> 123#include <sys/msgbuf.h> 124#include <sys/mutex.h> 125#include <sys/proc.h> 126#include <sys/sysctl.h> 127#include <sys/systm.h> 128#include <sys/vmmeter.h> 129 130#include <sys/kdb.h> 131 132#include <dev/ofw/openfirm.h> 133 134#include <vm/vm.h> 135#include <vm/vm_param.h> 136#include <vm/vm_kern.h> 137#include <vm/vm_page.h> 138#include <vm/vm_map.h> 139#include <vm/vm_object.h> 140#include <vm/vm_extern.h> 141#include <vm/vm_pageout.h> 142#include <vm/vm_pager.h> 143#include <vm/uma.h> 144 145#include <machine/_inttypes.h> 146#include <machine/cpu.h> 147#include <machine/platform.h> 148#include <machine/frame.h> 149#include <machine/md_var.h> 150#include <machine/psl.h> 151#include <machine/bat.h> 152#include <machine/hid.h> 153#include <machine/pte.h> 154#include <machine/sr.h> 155#include <machine/trap.h> 156#include <machine/mmuvar.h> 157 158#include "mmu_if.h" 159 160#define MOEA_DEBUG 161 162#define TODO panic("%s: not implemented", __func__); 163void moea64_release_vsid(uint64_t vsid); 164uintptr_t moea64_get_unique_vsid(void); 165 166static __inline register_t 167cntlzd(volatile register_t a) { 168 register_t b; 169 __asm ("cntlzd %0, %1" : "=r"(b) : "r"(a)); 170 return b; 171} 172 173#define PTESYNC() __asm __volatile("ptesync"); 174#define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 175#define SYNC() __asm __volatile("sync"); 176#define EIEIO() __asm __volatile("eieio"); 177 178/* 179 * The tlbie instruction must be executed in 64-bit mode 180 * so we have to twiddle MSR[SF] around every invocation. 181 * Just to add to the fun, exceptions must be off as well 182 * so that we can't trap in 64-bit mode. What a pain. 183 */ 184struct mtx tlbie_mutex; 185 186static __inline void 187TLBIE(uint64_t vpn) { 188#ifndef __powerpc64__ 189 register_t vpn_hi, vpn_lo; 190 register_t msr; 191 register_t scratch; 192#endif 193 194 vpn <<= ADDR_PIDX_SHFT; 195 vpn &= ~(0xffffULL << 48); 196 197 mtx_lock_spin(&tlbie_mutex); 198#ifdef __powerpc64__ 199 __asm __volatile("\ 200 ptesync; \ 201 tlbie %0; \ 202 eieio; \ 203 tlbsync; \ 204 ptesync;" 205 :: "r"(vpn) : "memory"); 206#else 207 vpn_hi = (uint32_t)(vpn >> 32); 208 vpn_lo = (uint32_t)vpn; 209 210 __asm __volatile("\ 211 mfmsr %0; \ 212 mr %1, %0; \ 213 insrdi %1,%5,1,0; \ 214 mtmsrd %1; \ 215 ptesync; \ 216 \ 217 sld %1,%2,%4; \ 218 or %1,%1,%3; \ 219 tlbie %1; \ 220 \ 221 mtmsrd %0; \ 222 eieio; \ 223 tlbsync; \ 224 ptesync;" 225 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) 226 : "memory"); 227#endif 228 mtx_unlock_spin(&tlbie_mutex); 229} 230 231#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync() 232#define ENABLE_TRANS(msr) mtmsr(msr); isync() 233 234#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 235#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 236#define VSID_HASH_MASK 0x0000007fffffffffULL 237 238#define PVO_PTEGIDX_MASK 0x007UL /* which PTEG slot */ 239#define PVO_PTEGIDX_VALID 0x008UL /* slot is valid */ 240#define PVO_WIRED 0x010UL /* PVO entry is wired */ 241#define PVO_MANAGED 0x020UL /* PVO entry is managed */ 242#define PVO_BOOTSTRAP 0x080UL /* PVO entry allocated during 243 bootstrap */ 244#define PVO_FAKE 0x100UL /* fictitious phys page */ 245#define PVO_LARGE 0x200UL /* large page */ 246#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 247#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 248#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 249#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 250#define PVO_PTEGIDX_CLR(pvo) \ 251 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 252#define PVO_PTEGIDX_SET(pvo, i) \ 253 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 254#define PVO_VSID(pvo) ((pvo)->pvo_vpn >> 16) 255 256#define MOEA_PVO_CHECK(pvo) 257 258#define LOCK_TABLE() mtx_lock(&moea64_table_mutex) 259#define UNLOCK_TABLE() mtx_unlock(&moea64_table_mutex); 260#define ASSERT_TABLE_LOCK() mtx_assert(&moea64_table_mutex, MA_OWNED) 261 262struct ofw_map { 263 cell_t om_va; 264 cell_t om_len; 265 cell_t om_pa_hi; 266 cell_t om_pa_lo; 267 cell_t om_mode; 268}; 269 270/* 271 * Map of physical memory regions. 272 */ 273static struct mem_region *regions; 274static struct mem_region *pregions; 275static u_int phys_avail_count; 276static int regions_sz, pregions_sz; 277extern int ofw_real_mode; 278 279extern struct pmap ofw_pmap; 280 281extern void bs_remap_earlyboot(void); 282 283 284/* 285 * Lock for the pteg and pvo tables. 286 */ 287struct mtx moea64_table_mutex; 288struct mtx moea64_slb_mutex; 289 290/* 291 * PTEG data. 292 */ 293static struct lpteg *moea64_pteg_table; 294u_int moea64_pteg_count; 295u_int moea64_pteg_mask; 296 297/* 298 * PVO data. 299 */ 300struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 301struct pvo_head moea64_pvo_kunmanaged = /* list of unmanaged pages */ 302 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 303 304uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 305uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 306 307#define BPVO_POOL_SIZE 327680 308static struct pvo_entry *moea64_bpvo_pool; 309static int moea64_bpvo_pool_index = 0; 310 311#define VSID_NBPW (sizeof(u_int32_t) * 8) 312#ifdef __powerpc64__ 313#define NVSIDS (NPMAPS * 16) 314#define VSID_HASHMASK 0xffffffffUL 315#else 316#define NVSIDS NPMAPS 317#define VSID_HASHMASK 0xfffffUL 318#endif 319static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 320 321static boolean_t moea64_initialized = FALSE; 322 323/* 324 * Statistics. 325 */ 326u_int moea64_pte_valid = 0; 327u_int moea64_pte_overflow = 0; 328u_int moea64_pvo_entries = 0; 329u_int moea64_pvo_enter_calls = 0; 330u_int moea64_pvo_remove_calls = 0; 331SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 332 &moea64_pte_valid, 0, ""); 333SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 334 &moea64_pte_overflow, 0, ""); 335SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 336 &moea64_pvo_entries, 0, ""); 337SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 338 &moea64_pvo_enter_calls, 0, ""); 339SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 340 &moea64_pvo_remove_calls, 0, ""); 341 342vm_offset_t moea64_scratchpage_va[2]; 343uint64_t moea64_scratchpage_vpn[2]; 344struct lpte *moea64_scratchpage_pte[2]; 345struct mtx moea64_scratchpage_mtx; 346 347uint64_t moea64_large_page_mask = 0; 348int moea64_large_page_size = 0; 349int moea64_large_page_shift = 0; 350 351/* 352 * Allocate physical memory for use in moea64_bootstrap. 353 */ 354static vm_offset_t moea64_bootstrap_alloc(vm_size_t, u_int); 355 356/* 357 * PTE calls. 358 */ 359static int moea64_pte_insert(u_int, struct lpte *); 360 361/* 362 * PVO calls. 363 */ 364static int moea64_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 365 vm_offset_t, vm_offset_t, uint64_t, int); 366static void moea64_pvo_remove(struct pvo_entry *); 367static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 368static struct lpte *moea64_pvo_to_pte(const struct pvo_entry *); 369 370/* 371 * Utility routines. 372 */ 373static void moea64_bootstrap(mmu_t mmup, 374 vm_offset_t kernelstart, vm_offset_t kernelend); 375static void moea64_cpu_bootstrap(mmu_t, int ap); 376static void moea64_enter_locked(pmap_t, vm_offset_t, vm_page_t, 377 vm_prot_t, boolean_t); 378static boolean_t moea64_query_bit(vm_page_t, u_int64_t); 379static u_int moea64_clear_bit(vm_page_t, u_int64_t); 380static void moea64_kremove(mmu_t, vm_offset_t); 381static void moea64_syncicache(pmap_t pmap, vm_offset_t va, 382 vm_offset_t pa, vm_size_t sz); 383static void tlbia(void); 384#ifdef __powerpc64__ 385static void slbia(void); 386#endif 387 388/* 389 * Kernel MMU interface 390 */ 391void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 392void moea64_clear_modify(mmu_t, vm_page_t); 393void moea64_clear_reference(mmu_t, vm_page_t); 394void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 395void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 396void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 397 vm_prot_t); 398void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 399vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 400vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 401void moea64_init(mmu_t); 402boolean_t moea64_is_modified(mmu_t, vm_page_t); 403boolean_t moea64_is_referenced(mmu_t, vm_page_t); 404boolean_t moea64_ts_referenced(mmu_t, vm_page_t); 405vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 406boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 407int moea64_page_wired_mappings(mmu_t, vm_page_t); 408void moea64_pinit(mmu_t, pmap_t); 409void moea64_pinit0(mmu_t, pmap_t); 410void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 411void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 412void moea64_qremove(mmu_t, vm_offset_t, int); 413void moea64_release(mmu_t, pmap_t); 414void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 415void moea64_remove_all(mmu_t, vm_page_t); 416void moea64_remove_write(mmu_t, vm_page_t); 417void moea64_zero_page(mmu_t, vm_page_t); 418void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 419void moea64_zero_page_idle(mmu_t, vm_page_t); 420void moea64_activate(mmu_t, struct thread *); 421void moea64_deactivate(mmu_t, struct thread *); 422void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 423void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 424void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 425vm_offset_t moea64_kextract(mmu_t, vm_offset_t); 426void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 427void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 428void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 429boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 430static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 431 432static mmu_method_t moea64_methods[] = { 433 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 434 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 435 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 436 MMUMETHOD(mmu_copy_page, moea64_copy_page), 437 MMUMETHOD(mmu_enter, moea64_enter), 438 MMUMETHOD(mmu_enter_object, moea64_enter_object), 439 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 440 MMUMETHOD(mmu_extract, moea64_extract), 441 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 442 MMUMETHOD(mmu_init, moea64_init), 443 MMUMETHOD(mmu_is_modified, moea64_is_modified), 444 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 445 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 446 MMUMETHOD(mmu_map, moea64_map), 447 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 448 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 449 MMUMETHOD(mmu_pinit, moea64_pinit), 450 MMUMETHOD(mmu_pinit0, moea64_pinit0), 451 MMUMETHOD(mmu_protect, moea64_protect), 452 MMUMETHOD(mmu_qenter, moea64_qenter), 453 MMUMETHOD(mmu_qremove, moea64_qremove), 454 MMUMETHOD(mmu_release, moea64_release), 455 MMUMETHOD(mmu_remove, moea64_remove), 456 MMUMETHOD(mmu_remove_all, moea64_remove_all), 457 MMUMETHOD(mmu_remove_write, moea64_remove_write), 458 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 459 MMUMETHOD(mmu_zero_page, moea64_zero_page), 460 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 461 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 462 MMUMETHOD(mmu_activate, moea64_activate), 463 MMUMETHOD(mmu_deactivate, moea64_deactivate), 464 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 465 466 /* Internal interfaces */ 467 MMUMETHOD(mmu_bootstrap, moea64_bootstrap), 468 MMUMETHOD(mmu_cpu_bootstrap, moea64_cpu_bootstrap), 469 MMUMETHOD(mmu_mapdev, moea64_mapdev), 470 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 471 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 472 MMUMETHOD(mmu_kextract, moea64_kextract), 473 MMUMETHOD(mmu_kenter, moea64_kenter), 474 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 475 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 476 477 { 0, 0 } 478}; 479 480MMU_DEF(oea64_mmu, MMU_TYPE_G5, moea64_methods, 0); 481 482static __inline u_int 483va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 484{ 485 uint64_t hash; 486 int shift; 487 488 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 489 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 490 shift); 491 return (hash & moea64_pteg_mask); 492} 493 494static __inline struct pvo_head * 495vm_page_to_pvoh(vm_page_t m) 496{ 497 498 return (&m->md.mdpg_pvoh); 499} 500 501static __inline void 502moea64_attr_clear(vm_page_t m, u_int64_t ptebit) 503{ 504 505 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 506 m->md.mdpg_attrs &= ~ptebit; 507} 508 509static __inline u_int64_t 510moea64_attr_fetch(vm_page_t m) 511{ 512 513 return (m->md.mdpg_attrs); 514} 515 516static __inline void 517moea64_attr_save(vm_page_t m, u_int64_t ptebit) 518{ 519 520 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 521 m->md.mdpg_attrs |= ptebit; 522} 523 524static __inline void 525moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 526 uint64_t pte_lo, int flags) 527{ 528 529 ASSERT_TABLE_LOCK(); 530 531 /* 532 * Construct a PTE. Default to IMB initially. Valid bit only gets 533 * set when the real pte is set in memory. 534 * 535 * Note: Don't set the valid bit for correct operation of tlb update. 536 */ 537 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 538 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 539 540 if (flags & PVO_LARGE) 541 pt->pte_hi |= LPTE_BIG; 542 543 pt->pte_lo = pte_lo; 544} 545 546static __inline void 547moea64_pte_synch(struct lpte *pt, struct lpte *pvo_pt) 548{ 549 550 ASSERT_TABLE_LOCK(); 551 552 pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG); 553} 554 555static __inline void 556moea64_pte_clear(struct lpte *pt, uint64_t vpn, u_int64_t ptebit) 557{ 558 ASSERT_TABLE_LOCK(); 559 560 /* 561 * As shown in Section 7.6.3.2.3 562 */ 563 pt->pte_lo &= ~ptebit; 564 TLBIE(vpn); 565} 566 567static __inline void 568moea64_pte_set(struct lpte *pt, struct lpte *pvo_pt) 569{ 570 571 ASSERT_TABLE_LOCK(); 572 pvo_pt->pte_hi |= LPTE_VALID; 573 574 /* 575 * Update the PTE as defined in section 7.6.3.1. 576 * Note that the REF/CHG bits are from pvo_pt and thus should have 577 * been saved so this routine can restore them (if desired). 578 */ 579 pt->pte_lo = pvo_pt->pte_lo; 580 EIEIO(); 581 pt->pte_hi = pvo_pt->pte_hi; 582 PTESYNC(); 583 moea64_pte_valid++; 584} 585 586static __inline void 587moea64_pte_unset(struct lpte *pt, struct lpte *pvo_pt, uint64_t vpn) 588{ 589 ASSERT_TABLE_LOCK(); 590 pvo_pt->pte_hi &= ~LPTE_VALID; 591 592 /* 593 * Force the reg & chg bits back into the PTEs. 594 */ 595 SYNC(); 596 597 /* 598 * Invalidate the pte. 599 */ 600 pt->pte_hi &= ~LPTE_VALID; 601 TLBIE(vpn); 602 603 /* 604 * Save the reg & chg bits. 605 */ 606 moea64_pte_synch(pt, pvo_pt); 607 moea64_pte_valid--; 608} 609 610static __inline void 611moea64_pte_change(struct lpte *pt, struct lpte *pvo_pt, uint64_t vpn) 612{ 613 614 /* 615 * Invalidate the PTE 616 */ 617 moea64_pte_unset(pt, pvo_pt, vpn); 618 moea64_pte_set(pt, pvo_pt); 619} 620 621static __inline uint64_t 622moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 623{ 624 uint64_t pte_lo; 625 int i; 626 627 if (ma != VM_MEMATTR_DEFAULT) { 628 switch (ma) { 629 case VM_MEMATTR_UNCACHEABLE: 630 return (LPTE_I | LPTE_G); 631 case VM_MEMATTR_WRITE_COMBINING: 632 case VM_MEMATTR_WRITE_BACK: 633 case VM_MEMATTR_PREFETCHABLE: 634 return (LPTE_I); 635 case VM_MEMATTR_WRITE_THROUGH: 636 return (LPTE_W | LPTE_M); 637 } 638 } 639 640 /* 641 * Assume the page is cache inhibited and access is guarded unless 642 * it's in our available memory array. 643 */ 644 pte_lo = LPTE_I | LPTE_G; 645 for (i = 0; i < pregions_sz; i++) { 646 if ((pa >= pregions[i].mr_start) && 647 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 648 pte_lo &= ~(LPTE_I | LPTE_G); 649 pte_lo |= LPTE_M; 650 break; 651 } 652 } 653 654 return pte_lo; 655} 656 657/* 658 * Quick sort callout for comparing memory regions. 659 */ 660static int mr_cmp(const void *a, const void *b); 661static int om_cmp(const void *a, const void *b); 662 663static int 664mr_cmp(const void *a, const void *b) 665{ 666 const struct mem_region *regiona; 667 const struct mem_region *regionb; 668 669 regiona = a; 670 regionb = b; 671 if (regiona->mr_start < regionb->mr_start) 672 return (-1); 673 else if (regiona->mr_start > regionb->mr_start) 674 return (1); 675 else 676 return (0); 677} 678 679static int 680om_cmp(const void *a, const void *b) 681{ 682 const struct ofw_map *mapa; 683 const struct ofw_map *mapb; 684 685 mapa = a; 686 mapb = b; 687 if (mapa->om_pa_hi < mapb->om_pa_hi) 688 return (-1); 689 else if (mapa->om_pa_hi > mapb->om_pa_hi) 690 return (1); 691 else if (mapa->om_pa_lo < mapb->om_pa_lo) 692 return (-1); 693 else if (mapa->om_pa_lo > mapb->om_pa_lo) 694 return (1); 695 else 696 return (0); 697} 698 699static void 700moea64_cpu_bootstrap(mmu_t mmup, int ap) 701{ 702 int i = 0; 703 #ifdef __powerpc64__ 704 struct slb *slb = PCPU_GET(slb); 705 #endif 706 707 /* 708 * Initialize segment registers and MMU 709 */ 710 711 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); isync(); 712 713 /* 714 * Install kernel SLB entries 715 */ 716 717 #ifdef __powerpc64__ 718 slbia(); 719 720 for (i = 0; i < 64; i++) { 721 if (!(slb[i].slbe & SLBE_VALID)) 722 continue; 723 724 __asm __volatile ("slbmte %0, %1" :: 725 "r"(slb[i].slbv), "r"(slb[i].slbe)); 726 } 727 #else 728 for (i = 0; i < 16; i++) 729 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 730 #endif 731 732 /* 733 * Install page table 734 */ 735 736 __asm __volatile ("ptesync; mtsdr1 %0; isync" 737 :: "r"((uintptr_t)moea64_pteg_table 738 | (64 - cntlzd(moea64_pteg_mask >> 11)))); 739 tlbia(); 740} 741 742static void 743moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 744{ 745 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 746 register_t msr; 747 vm_offset_t off; 748 vm_paddr_t pa_base; 749 int i, ofw_mappings; 750 751 bzero(translations, sz); 752 if (OF_getprop(mmu, "translations", translations, sz) == -1) 753 panic("moea64_bootstrap: can't get ofw translations"); 754 755 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 756 sz /= sizeof(*translations); 757 qsort(translations, sz, sizeof (*translations), om_cmp); 758 759 for (i = 0, ofw_mappings = 0; i < sz; i++) { 760 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 761 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 762 translations[i].om_len); 763 764 if (translations[i].om_pa_lo % PAGE_SIZE) 765 panic("OFW translation not page-aligned!"); 766 767 pa_base = translations[i].om_pa_lo; 768 769 #ifdef __powerpc64__ 770 pa_base += (vm_offset_t)translations[i].om_pa_hi << 32; 771 #else 772 if (translations[i].om_pa_hi) 773 panic("OFW translations above 32-bit boundary!"); 774 #endif 775 776 /* Now enter the pages for this mapping */ 777 778 DISABLE_TRANS(msr); 779 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 780 if (moea64_pvo_find_va(kernel_pmap, 781 translations[i].om_va + off) != NULL) 782 continue; 783 784 moea64_kenter(mmup, translations[i].om_va + off, 785 pa_base + off); 786 787 ofw_mappings++; 788 } 789 ENABLE_TRANS(msr); 790 } 791} 792 793#ifdef __powerpc64__ 794static void 795moea64_probe_large_page(void) 796{ 797 uint16_t pvr = mfpvr() >> 16; 798 799 switch (pvr) { 800 case IBM970: 801 case IBM970FX: 802 case IBM970MP: 803 powerpc_sync(); isync(); 804 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 805 powerpc_sync(); isync(); 806 807 /* FALLTHROUGH */ 808 case IBMCELLBE: 809 moea64_large_page_size = 0x1000000; /* 16 MB */ 810 moea64_large_page_shift = 24; 811 break; 812 default: 813 moea64_large_page_size = 0; 814 } 815 816 moea64_large_page_mask = moea64_large_page_size - 1; 817} 818 819static void 820moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 821{ 822 struct slb *cache; 823 struct slb entry; 824 uint64_t esid, slbe; 825 uint64_t i; 826 827 cache = PCPU_GET(slb); 828 esid = va >> ADDR_SR_SHFT; 829 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 830 831 for (i = 0; i < 64; i++) { 832 if (cache[i].slbe == (slbe | i)) 833 return; 834 } 835 836 entry.slbe = slbe; 837 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 838 if (large) 839 entry.slbv |= SLBV_L; 840 841 slb_insert_kernel(entry.slbe, entry.slbv); 842} 843#endif 844 845static void 846moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 847 vm_offset_t kernelend) 848{ 849 register_t msr; 850 vm_paddr_t pa; 851 vm_offset_t size, off; 852 uint64_t pte_lo; 853 int i; 854 855 if (moea64_large_page_size == 0) 856 hw_direct_map = 0; 857 858 DISABLE_TRANS(msr); 859 if (hw_direct_map) { 860 PMAP_LOCK(kernel_pmap); 861 for (i = 0; i < pregions_sz; i++) { 862 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 863 pregions[i].mr_size; pa += moea64_large_page_size) { 864 pte_lo = LPTE_M; 865 866 /* 867 * Set memory access as guarded if prefetch within 868 * the page could exit the available physmem area. 869 */ 870 if (pa & moea64_large_page_mask) { 871 pa &= moea64_large_page_mask; 872 pte_lo |= LPTE_G; 873 } 874 if (pa + moea64_large_page_size > 875 pregions[i].mr_start + pregions[i].mr_size) 876 pte_lo |= LPTE_G; 877 878 moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 879 &moea64_pvo_kunmanaged, pa, pa, 880 pte_lo, PVO_WIRED | PVO_LARGE | 881 VM_PROT_EXECUTE); 882 } 883 } 884 PMAP_UNLOCK(kernel_pmap); 885 } else { 886 size = moea64_pteg_count * sizeof(struct lpteg); 887 off = (vm_offset_t)(moea64_pteg_table); 888 for (pa = off; pa < off + size; pa += PAGE_SIZE) 889 moea64_kenter(mmup, pa, pa); 890 size = sizeof(struct pvo_head) * moea64_pteg_count; 891 off = (vm_offset_t)(moea64_pvo_table); 892 for (pa = off; pa < off + size; pa += PAGE_SIZE) 893 moea64_kenter(mmup, pa, pa); 894 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 895 off = (vm_offset_t)(moea64_bpvo_pool); 896 for (pa = off; pa < off + size; pa += PAGE_SIZE) 897 moea64_kenter(mmup, pa, pa); 898 899 /* 900 * Map certain important things, like ourselves. 901 * 902 * NOTE: We do not map the exception vector space. That code is 903 * used only in real mode, and leaving it unmapped allows us to 904 * catch NULL pointer deferences, instead of making NULL a valid 905 * address. 906 */ 907 908 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 909 pa += PAGE_SIZE) 910 moea64_kenter(mmup, pa, pa); 911 } 912 ENABLE_TRANS(msr); 913} 914 915static void 916moea64_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 917{ 918 ihandle_t mmui; 919 phandle_t chosen; 920 phandle_t mmu; 921 size_t sz; 922 int i, j; 923 vm_size_t size, physsz, hwphyssz; 924 vm_offset_t pa, va; 925 register_t msr; 926 void *dpcpu; 927 928#ifndef __powerpc64__ 929 /* We don't have a direct map since there is no BAT */ 930 hw_direct_map = 0; 931 932 /* Make sure battable is zero, since we have no BAT */ 933 for (i = 0; i < 16; i++) { 934 battable[i].batu = 0; 935 battable[i].batl = 0; 936 } 937#else 938 moea64_probe_large_page(); 939 940 /* Use a direct map if we have large page support */ 941 if (moea64_large_page_size > 0) 942 hw_direct_map = 1; 943 else 944 hw_direct_map = 0; 945#endif 946 947 /* Get physical memory regions from firmware */ 948 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 949 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 950 951 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 952 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 953 panic("moea64_bootstrap: phys_avail too small"); 954 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 955 phys_avail_count = 0; 956 physsz = 0; 957 hwphyssz = 0; 958 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 959 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 960 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 961 regions[i].mr_start + regions[i].mr_size, 962 regions[i].mr_size); 963 if (hwphyssz != 0 && 964 (physsz + regions[i].mr_size) >= hwphyssz) { 965 if (physsz < hwphyssz) { 966 phys_avail[j] = regions[i].mr_start; 967 phys_avail[j + 1] = regions[i].mr_start + 968 hwphyssz - physsz; 969 physsz = hwphyssz; 970 phys_avail_count++; 971 } 972 break; 973 } 974 phys_avail[j] = regions[i].mr_start; 975 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 976 phys_avail_count++; 977 physsz += regions[i].mr_size; 978 } 979 980 /* Check for overlap with the kernel and exception vectors */ 981 for (j = 0; j < 2*phys_avail_count; j+=2) { 982 if (phys_avail[j] < EXC_LAST) 983 phys_avail[j] += EXC_LAST; 984 985 if (kernelstart >= phys_avail[j] && 986 kernelstart < phys_avail[j+1]) { 987 if (kernelend < phys_avail[j+1]) { 988 phys_avail[2*phys_avail_count] = 989 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 990 phys_avail[2*phys_avail_count + 1] = 991 phys_avail[j+1]; 992 phys_avail_count++; 993 } 994 995 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 996 } 997 998 if (kernelend >= phys_avail[j] && 999 kernelend < phys_avail[j+1]) { 1000 if (kernelstart > phys_avail[j]) { 1001 phys_avail[2*phys_avail_count] = phys_avail[j]; 1002 phys_avail[2*phys_avail_count + 1] = 1003 kernelstart & ~PAGE_MASK; 1004 phys_avail_count++; 1005 } 1006 1007 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 1008 } 1009 } 1010 1011 physmem = btoc(physsz); 1012 1013 /* 1014 * Allocate PTEG table. 1015 */ 1016#ifdef PTEGCOUNT 1017 moea64_pteg_count = PTEGCOUNT; 1018#else 1019 moea64_pteg_count = 0x1000; 1020 1021 while (moea64_pteg_count < physmem) 1022 moea64_pteg_count <<= 1; 1023 1024 moea64_pteg_count >>= 1; 1025#endif /* PTEGCOUNT */ 1026 1027 size = moea64_pteg_count * sizeof(struct lpteg); 1028 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes", 1029 moea64_pteg_count, size); 1030 1031 /* 1032 * We now need to allocate memory. This memory, to be allocated, 1033 * has to reside in a page table. The page table we are about to 1034 * allocate. We don't have BAT. So drop to data real mode for a minute 1035 * as a measure of last resort. We do this a couple times. 1036 */ 1037 1038 moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size); 1039 DISABLE_TRANS(msr); 1040 bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg)); 1041 ENABLE_TRANS(msr); 1042 1043 moea64_pteg_mask = moea64_pteg_count - 1; 1044 1045 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 1046 1047 /* 1048 * Allocate pv/overflow lists. 1049 */ 1050 size = sizeof(struct pvo_head) * moea64_pteg_count; 1051 1052 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 1053 PAGE_SIZE); 1054 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 1055 1056 DISABLE_TRANS(msr); 1057 for (i = 0; i < moea64_pteg_count; i++) 1058 LIST_INIT(&moea64_pvo_table[i]); 1059 ENABLE_TRANS(msr); 1060 1061 /* 1062 * Initialize the lock that synchronizes access to the pteg and pvo 1063 * tables. 1064 */ 1065 mtx_init(&moea64_table_mutex, "pmap table", NULL, MTX_DEF | 1066 MTX_RECURSE); 1067 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 1068 1069 /* 1070 * Initialize the TLBIE lock. TLBIE can only be executed by one CPU. 1071 */ 1072 mtx_init(&tlbie_mutex, "tlbie mutex", NULL, MTX_SPIN); 1073 1074 /* 1075 * Initialise the unmanaged pvo pool. 1076 */ 1077 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 1078 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 1079 moea64_bpvo_pool_index = 0; 1080 1081 /* 1082 * Make sure kernel vsid is allocated as well as VSID 0. 1083 */ 1084 #ifndef __powerpc64__ 1085 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 1086 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 1087 moea64_vsid_bitmap[0] |= 1; 1088 #endif 1089 1090 /* 1091 * Initialize the kernel pmap (which is statically allocated). 1092 */ 1093 #ifdef __powerpc64__ 1094 for (i = 0; i < 64; i++) { 1095 pcpup->pc_slb[i].slbv = 0; 1096 pcpup->pc_slb[i].slbe = 0; 1097 } 1098 #else 1099 for (i = 0; i < 16; i++) 1100 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 1101 #endif 1102 1103 kernel_pmap->pmap_phys = kernel_pmap; 1104 kernel_pmap->pm_active = ~0; 1105 1106 PMAP_LOCK_INIT(kernel_pmap); 1107 1108 /* 1109 * Now map in all the other buffers we allocated earlier 1110 */ 1111 1112 moea64_setup_direct_map(mmup, kernelstart, kernelend); 1113 1114 /* 1115 * Set up the Open Firmware pmap and add its mappings if not in real 1116 * mode. 1117 */ 1118 1119 if (!ofw_real_mode) { 1120 #ifndef __powerpc64__ 1121 moea64_pinit(mmup, &ofw_pmap); 1122 1123 for (i = 0; i < 16; i++) 1124 ofw_pmap.pm_sr[i] = kernel_pmap->pm_sr[i]; 1125 #endif 1126 1127 if ((chosen = OF_finddevice("/chosen")) == -1) 1128 panic("moea64_bootstrap: can't find /chosen"); 1129 OF_getprop(chosen, "mmu", &mmui, 4); 1130 1131 if ((mmu = OF_instance_to_package(mmui)) == -1) 1132 panic("moea64_bootstrap: can't get mmu package"); 1133 if ((sz = OF_getproplen(mmu, "translations")) == -1) 1134 panic("moea64_bootstrap: can't get ofw translation count"); 1135 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 1136 panic("moea64_bootstrap: too many ofw translations"); 1137 1138 moea64_add_ofw_mappings(mmup, mmu, sz); 1139 } 1140 1141#ifdef SMP 1142 TLBSYNC(); 1143#endif 1144 1145 /* 1146 * Calculate the last available physical address. 1147 */ 1148 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1149 ; 1150 Maxmem = powerpc_btop(phys_avail[i + 1]); 1151 1152 /* 1153 * Initialize MMU and remap early physical mappings 1154 */ 1155 moea64_cpu_bootstrap(mmup,0); 1156 mtmsr(mfmsr() | PSL_DR | PSL_IR); isync(); 1157 pmap_bootstrapped++; 1158 bs_remap_earlyboot(); 1159 1160 /* 1161 * Set the start and end of kva. 1162 */ 1163 virtual_avail = VM_MIN_KERNEL_ADDRESS; 1164 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 1165 1166 /* 1167 * Map the entire KVA range into the SLB. We must not fault there. 1168 */ 1169 #ifdef __powerpc64__ 1170 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 1171 moea64_bootstrap_slb_prefault(va, 0); 1172 #endif 1173 1174 /* 1175 * Figure out how far we can extend virtual_end into segment 16 1176 * without running into existing mappings. Segment 16 is guaranteed 1177 * to contain neither RAM nor devices (at least on Apple hardware), 1178 * but will generally contain some OFW mappings we should not 1179 * step on. 1180 */ 1181 1182 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1183 PMAP_LOCK(kernel_pmap); 1184 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1185 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1186 virtual_end += PAGE_SIZE; 1187 PMAP_UNLOCK(kernel_pmap); 1188 #endif 1189 1190 /* 1191 * Allocate some things for page zeroing. We put this directly 1192 * in the page table, marked with LPTE_LOCKED, to avoid any 1193 * of the PVO book-keeping or other parts of the VM system 1194 * from even knowing that this hack exists. 1195 */ 1196 1197 if (!hw_direct_map) { 1198 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1199 MTX_DEF); 1200 for (i = 0; i < 2; i++) { 1201 struct lpte pt; 1202 uint64_t vsid; 1203 int pteidx, ptegidx; 1204 1205 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1206 virtual_end -= PAGE_SIZE; 1207 1208 LOCK_TABLE(); 1209 1210 vsid = va_to_vsid(kernel_pmap, 1211 moea64_scratchpage_va[i]); 1212 moea64_pte_create(&pt, vsid, moea64_scratchpage_va[i], 1213 LPTE_NOEXEC, 0); 1214 pt.pte_hi |= LPTE_LOCKED; 1215 1216 moea64_scratchpage_vpn[i] = (vsid << 16) | 1217 ((moea64_scratchpage_va[i] & ADDR_PIDX) >> 1218 ADDR_PIDX_SHFT); 1219 ptegidx = va_to_pteg(vsid, moea64_scratchpage_va[i], 0); 1220 pteidx = moea64_pte_insert(ptegidx, &pt); 1221 if (pt.pte_hi & LPTE_HID) 1222 ptegidx ^= moea64_pteg_mask; 1223 1224 moea64_scratchpage_pte[i] = 1225 &moea64_pteg_table[ptegidx].pt[pteidx]; 1226 1227 UNLOCK_TABLE(); 1228 } 1229 } 1230 1231 /* 1232 * Allocate a kernel stack with a guard page for thread0 and map it 1233 * into the kernel page map. 1234 */ 1235 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 1236 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1237 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 1238 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 1239 thread0.td_kstack = va; 1240 thread0.td_kstack_pages = KSTACK_PAGES; 1241 for (i = 0; i < KSTACK_PAGES; i++) { 1242 moea64_kenter(mmup, va, pa); 1243 pa += PAGE_SIZE; 1244 va += PAGE_SIZE; 1245 } 1246 1247 /* 1248 * Allocate virtual address space for the message buffer. 1249 */ 1250 pa = msgbuf_phys = moea64_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 1251 msgbufp = (struct msgbuf *)virtual_avail; 1252 va = virtual_avail; 1253 virtual_avail += round_page(MSGBUF_SIZE); 1254 while (va < virtual_avail) { 1255 moea64_kenter(mmup, va, pa); 1256 pa += PAGE_SIZE; 1257 va += PAGE_SIZE; 1258 } 1259 1260 /* 1261 * Allocate virtual address space for the dynamic percpu area. 1262 */ 1263 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1264 dpcpu = (void *)virtual_avail; 1265 va = virtual_avail; 1266 virtual_avail += DPCPU_SIZE; 1267 while (va < virtual_avail) { 1268 moea64_kenter(mmup, va, pa); 1269 pa += PAGE_SIZE; 1270 va += PAGE_SIZE; 1271 } 1272 dpcpu_init(dpcpu, 0); 1273} 1274 1275/* 1276 * Activate a user pmap. The pmap must be activated before its address 1277 * space can be accessed in any way. 1278 */ 1279void 1280moea64_activate(mmu_t mmu, struct thread *td) 1281{ 1282 pmap_t pm; 1283 1284 pm = &td->td_proc->p_vmspace->vm_pmap; 1285 pm->pm_active |= PCPU_GET(cpumask); 1286 1287 #ifdef __powerpc64__ 1288 PCPU_SET(userslb, pm->pm_slb); 1289 #else 1290 PCPU_SET(curpmap, pm->pmap_phys); 1291 #endif 1292} 1293 1294void 1295moea64_deactivate(mmu_t mmu, struct thread *td) 1296{ 1297 pmap_t pm; 1298 1299 pm = &td->td_proc->p_vmspace->vm_pmap; 1300 pm->pm_active &= ~(PCPU_GET(cpumask)); 1301 #ifdef __powerpc64__ 1302 PCPU_SET(userslb, NULL); 1303 #else 1304 PCPU_SET(curpmap, NULL); 1305 #endif 1306} 1307 1308void 1309moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1310{ 1311 struct pvo_entry *pvo; 1312 struct lpte *pt; 1313 uint64_t vsid; 1314 int i, ptegidx; 1315 1316 PMAP_LOCK(pm); 1317 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 1318 1319 if (pvo != NULL) { 1320 LOCK_TABLE(); 1321 pt = moea64_pvo_to_pte(pvo); 1322 1323 if (wired) { 1324 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1325 pm->pm_stats.wired_count++; 1326 pvo->pvo_vaddr |= PVO_WIRED; 1327 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 1328 } else { 1329 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1330 pm->pm_stats.wired_count--; 1331 pvo->pvo_vaddr &= ~PVO_WIRED; 1332 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1333 } 1334 1335 if (pt != NULL) { 1336 /* Update wiring flag in page table. */ 1337 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1338 pvo->pvo_vpn); 1339 } else if (wired) { 1340 /* 1341 * If we are wiring the page, and it wasn't in the 1342 * page table before, add it. 1343 */ 1344 vsid = PVO_VSID(pvo); 1345 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 1346 pvo->pvo_vaddr & PVO_LARGE); 1347 1348 i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte); 1349 if (i >= 0) { 1350 PVO_PTEGIDX_CLR(pvo); 1351 PVO_PTEGIDX_SET(pvo, i); 1352 } 1353 } 1354 1355 UNLOCK_TABLE(); 1356 } 1357 PMAP_UNLOCK(pm); 1358} 1359 1360/* 1361 * This goes through and sets the physical address of our 1362 * special scratch PTE to the PA we want to zero or copy. Because 1363 * of locking issues (this can get called in pvo_enter() by 1364 * the UMA allocator), we can't use most other utility functions here 1365 */ 1366 1367static __inline 1368void moea64_set_scratchpage_pa(int which, vm_offset_t pa) { 1369 1370 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1371 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1372 1373 moea64_scratchpage_pte[which]->pte_hi &= ~LPTE_VALID; 1374 TLBIE(moea64_scratchpage_vpn[which]); 1375 1376 moea64_scratchpage_pte[which]->pte_lo &= 1377 ~(LPTE_WIMG | LPTE_RPGN); 1378 moea64_scratchpage_pte[which]->pte_lo |= 1379 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1380 EIEIO(); 1381 1382 moea64_scratchpage_pte[which]->pte_hi |= LPTE_VALID; 1383 PTESYNC(); isync(); 1384} 1385 1386void 1387moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1388{ 1389 vm_offset_t dst; 1390 vm_offset_t src; 1391 1392 dst = VM_PAGE_TO_PHYS(mdst); 1393 src = VM_PAGE_TO_PHYS(msrc); 1394 1395 if (hw_direct_map) { 1396 kcopy((void *)src, (void *)dst, PAGE_SIZE); 1397 } else { 1398 mtx_lock(&moea64_scratchpage_mtx); 1399 1400 moea64_set_scratchpage_pa(0,src); 1401 moea64_set_scratchpage_pa(1,dst); 1402 1403 kcopy((void *)moea64_scratchpage_va[0], 1404 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1405 1406 mtx_unlock(&moea64_scratchpage_mtx); 1407 } 1408} 1409 1410void 1411moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1412{ 1413 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1414 1415 if (!moea64_initialized) 1416 panic("moea64_zero_page: can't zero pa %#" PRIxPTR, pa); 1417 if (size + off > PAGE_SIZE) 1418 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1419 1420 if (hw_direct_map) { 1421 bzero((caddr_t)pa + off, size); 1422 } else { 1423 mtx_lock(&moea64_scratchpage_mtx); 1424 moea64_set_scratchpage_pa(0,pa); 1425 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1426 mtx_unlock(&moea64_scratchpage_mtx); 1427 } 1428} 1429 1430/* 1431 * Zero a page of physical memory by temporarily mapping it 1432 */ 1433void 1434moea64_zero_page(mmu_t mmu, vm_page_t m) 1435{ 1436 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1437 vm_offset_t va, off; 1438 1439 if (!moea64_initialized) 1440 panic("moea64_zero_page: can't zero pa %#zx", pa); 1441 1442 if (!hw_direct_map) { 1443 mtx_lock(&moea64_scratchpage_mtx); 1444 1445 moea64_set_scratchpage_pa(0,pa); 1446 va = moea64_scratchpage_va[0]; 1447 } else { 1448 va = pa; 1449 } 1450 1451 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1452 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1453 1454 if (!hw_direct_map) 1455 mtx_unlock(&moea64_scratchpage_mtx); 1456} 1457 1458void 1459moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1460{ 1461 1462 moea64_zero_page(mmu, m); 1463} 1464 1465/* 1466 * Map the given physical page at the specified virtual address in the 1467 * target pmap with the protection requested. If specified the page 1468 * will be wired down. 1469 */ 1470void 1471moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1472 vm_prot_t prot, boolean_t wired) 1473{ 1474 1475 vm_page_lock_queues(); 1476 PMAP_LOCK(pmap); 1477 moea64_enter_locked(pmap, va, m, prot, wired); 1478 vm_page_unlock_queues(); 1479 PMAP_UNLOCK(pmap); 1480} 1481 1482/* 1483 * Map the given physical page at the specified virtual address in the 1484 * target pmap with the protection requested. If specified the page 1485 * will be wired down. 1486 * 1487 * The page queues and pmap must be locked. 1488 */ 1489 1490static void 1491moea64_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1492 boolean_t wired) 1493{ 1494 struct pvo_head *pvo_head; 1495 uma_zone_t zone; 1496 vm_page_t pg; 1497 uint64_t pte_lo; 1498 u_int pvo_flags; 1499 int error; 1500 1501 if (!moea64_initialized) { 1502 pvo_head = &moea64_pvo_kunmanaged; 1503 pg = NULL; 1504 zone = moea64_upvo_zone; 1505 pvo_flags = 0; 1506 } else { 1507 pvo_head = vm_page_to_pvoh(m); 1508 pg = m; 1509 zone = moea64_mpvo_zone; 1510 pvo_flags = PVO_MANAGED; 1511 } 1512 1513 if (pmap_bootstrapped) 1514 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1515 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1516 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1517 (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1518 ("moea64_enter_locked: page %p is not busy", m)); 1519 1520 /* XXX change the pvo head for fake pages */ 1521 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1522 pvo_flags &= ~PVO_MANAGED; 1523 pvo_head = &moea64_pvo_kunmanaged; 1524 zone = moea64_upvo_zone; 1525 } 1526 1527 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1528 1529 if (prot & VM_PROT_WRITE) { 1530 pte_lo |= LPTE_BW; 1531 if (pmap_bootstrapped && 1532 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1533 vm_page_flag_set(m, PG_WRITEABLE); 1534 } else 1535 pte_lo |= LPTE_BR; 1536 1537 if (prot & VM_PROT_EXECUTE) 1538 pvo_flags |= VM_PROT_EXECUTE; 1539 1540 if (wired) 1541 pvo_flags |= PVO_WIRED; 1542 1543 if ((m->flags & PG_FICTITIOUS) != 0) 1544 pvo_flags |= PVO_FAKE; 1545 1546 error = moea64_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1547 pte_lo, pvo_flags); 1548 1549 /* 1550 * Flush the page from the instruction cache if this page is 1551 * mapped executable and cacheable. 1552 */ 1553 if ((pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1554 moea64_syncicache(pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1555 } 1556} 1557 1558static void 1559moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_size_t sz) 1560{ 1561 1562 /* 1563 * This is much trickier than on older systems because 1564 * we can't sync the icache on physical addresses directly 1565 * without a direct map. Instead we check a couple of cases 1566 * where the memory is already mapped in and, failing that, 1567 * use the same trick we use for page zeroing to create 1568 * a temporary mapping for this physical address. 1569 */ 1570 1571 if (!pmap_bootstrapped) { 1572 /* 1573 * If PMAP is not bootstrapped, we are likely to be 1574 * in real mode. 1575 */ 1576 __syncicache((void *)pa, sz); 1577 } else if (pmap == kernel_pmap) { 1578 __syncicache((void *)va, sz); 1579 } else if (hw_direct_map) { 1580 __syncicache((void *)pa, sz); 1581 } else { 1582 /* Use the scratch page to set up a temp mapping */ 1583 1584 mtx_lock(&moea64_scratchpage_mtx); 1585 1586 moea64_set_scratchpage_pa(1,pa & ~ADDR_POFF); 1587 __syncicache((void *)(moea64_scratchpage_va[1] + 1588 (va & ADDR_POFF)), sz); 1589 1590 mtx_unlock(&moea64_scratchpage_mtx); 1591 } 1592} 1593 1594/* 1595 * Maps a sequence of resident pages belonging to the same object. 1596 * The sequence begins with the given page m_start. This page is 1597 * mapped at the given virtual address start. Each subsequent page is 1598 * mapped at a virtual address that is offset from start by the same 1599 * amount as the page is offset from m_start within the object. The 1600 * last page in the sequence is the page with the largest offset from 1601 * m_start that can be mapped at a virtual address less than the given 1602 * virtual address end. Not every virtual page between start and end 1603 * is mapped; only those for which a resident page exists with the 1604 * corresponding offset from m_start are mapped. 1605 */ 1606void 1607moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1608 vm_page_t m_start, vm_prot_t prot) 1609{ 1610 vm_page_t m; 1611 vm_pindex_t diff, psize; 1612 1613 psize = atop(end - start); 1614 m = m_start; 1615 vm_page_lock_queues(); 1616 PMAP_LOCK(pm); 1617 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1618 moea64_enter_locked(pm, start + ptoa(diff), m, prot & 1619 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1620 m = TAILQ_NEXT(m, listq); 1621 } 1622 vm_page_unlock_queues(); 1623 PMAP_UNLOCK(pm); 1624} 1625 1626void 1627moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1628 vm_prot_t prot) 1629{ 1630 1631 vm_page_lock_queues(); 1632 PMAP_LOCK(pm); 1633 moea64_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1634 FALSE); 1635 vm_page_unlock_queues(); 1636 PMAP_UNLOCK(pm); 1637} 1638 1639vm_paddr_t 1640moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1641{ 1642 struct pvo_entry *pvo; 1643 vm_paddr_t pa; 1644 1645 PMAP_LOCK(pm); 1646 pvo = moea64_pvo_find_va(pm, va); 1647 if (pvo == NULL) 1648 pa = 0; 1649 else 1650 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1651 (va - PVO_VADDR(pvo)); 1652 PMAP_UNLOCK(pm); 1653 return (pa); 1654} 1655 1656/* 1657 * Atomically extract and hold the physical page with the given 1658 * pmap and virtual address pair if that mapping permits the given 1659 * protection. 1660 */ 1661vm_page_t 1662moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1663{ 1664 struct pvo_entry *pvo; 1665 vm_page_t m; 1666 vm_paddr_t pa; 1667 1668 m = NULL; 1669 pa = 0; 1670 PMAP_LOCK(pmap); 1671retry: 1672 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1673 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1674 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1675 (prot & VM_PROT_WRITE) == 0)) { 1676 if (vm_page_pa_tryrelock(pmap, 1677 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1678 goto retry; 1679 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1680 vm_page_hold(m); 1681 } 1682 PA_UNLOCK_COND(pa); 1683 PMAP_UNLOCK(pmap); 1684 return (m); 1685} 1686 1687static void * 1688moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1689{ 1690 /* 1691 * This entire routine is a horrible hack to avoid bothering kmem 1692 * for new KVA addresses. Because this can get called from inside 1693 * kmem allocation routines, calling kmem for a new address here 1694 * can lead to multiply locking non-recursive mutexes. 1695 */ 1696 static vm_pindex_t color; 1697 vm_offset_t va; 1698 1699 vm_page_t m; 1700 int pflags, needed_lock; 1701 1702 *flags = UMA_SLAB_PRIV; 1703 needed_lock = !PMAP_LOCKED(kernel_pmap); 1704 1705 if (needed_lock) 1706 PMAP_LOCK(kernel_pmap); 1707 1708 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1709 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1710 else 1711 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1712 if (wait & M_ZERO) 1713 pflags |= VM_ALLOC_ZERO; 1714 1715 for (;;) { 1716 m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ); 1717 if (m == NULL) { 1718 if (wait & M_NOWAIT) 1719 return (NULL); 1720 VM_WAIT; 1721 } else 1722 break; 1723 } 1724 1725 va = VM_PAGE_TO_PHYS(m); 1726 1727 moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1728 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1729 PVO_WIRED | PVO_BOOTSTRAP); 1730 1731 if (needed_lock) 1732 PMAP_UNLOCK(kernel_pmap); 1733 1734 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1735 bzero((void *)va, PAGE_SIZE); 1736 1737 return (void *)va; 1738} 1739 1740void 1741moea64_init(mmu_t mmu) 1742{ 1743 1744 CTR0(KTR_PMAP, "moea64_init"); 1745 1746 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1747 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1748 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1749 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1750 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1751 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1752 1753 if (!hw_direct_map) { 1754 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1755 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1756 } 1757 1758 moea64_initialized = TRUE; 1759} 1760 1761boolean_t 1762moea64_is_referenced(mmu_t mmu, vm_page_t m) 1763{ 1764 1765 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1766 ("moea64_is_referenced: page %p is not managed", m)); 1767 return (moea64_query_bit(m, PTE_REF)); 1768} 1769 1770boolean_t 1771moea64_is_modified(mmu_t mmu, vm_page_t m) 1772{ 1773 1774 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1775 ("moea64_is_modified: page %p is not managed", m)); 1776 1777 /* 1778 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1779 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1780 * is clear, no PTEs can have LPTE_CHG set. 1781 */ 1782 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1783 if ((m->oflags & VPO_BUSY) == 0 && 1784 (m->flags & PG_WRITEABLE) == 0) 1785 return (FALSE); 1786 return (moea64_query_bit(m, LPTE_CHG)); 1787} 1788 1789void 1790moea64_clear_reference(mmu_t mmu, vm_page_t m) 1791{ 1792 1793 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1794 ("moea64_clear_reference: page %p is not managed", m)); 1795 moea64_clear_bit(m, LPTE_REF); 1796} 1797 1798void 1799moea64_clear_modify(mmu_t mmu, vm_page_t m) 1800{ 1801 1802 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1803 ("moea64_clear_modify: page %p is not managed", m)); 1804 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1805 KASSERT((m->oflags & VPO_BUSY) == 0, 1806 ("moea64_clear_modify: page %p is busy", m)); 1807 1808 /* 1809 * If the page is not PG_WRITEABLE, then no PTEs can have LPTE_CHG 1810 * set. If the object containing the page is locked and the page is 1811 * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1812 */ 1813 if ((m->flags & PG_WRITEABLE) == 0) 1814 return; 1815 moea64_clear_bit(m, LPTE_CHG); 1816} 1817 1818/* 1819 * Clear the write and modified bits in each of the given page's mappings. 1820 */ 1821void 1822moea64_remove_write(mmu_t mmu, vm_page_t m) 1823{ 1824 struct pvo_entry *pvo; 1825 struct lpte *pt; 1826 pmap_t pmap; 1827 uint64_t lo; 1828 1829 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1830 ("moea64_remove_write: page %p is not managed", m)); 1831 1832 /* 1833 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1834 * another thread while the object is locked. Thus, if PG_WRITEABLE 1835 * is clear, no page table entries need updating. 1836 */ 1837 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1838 if ((m->oflags & VPO_BUSY) == 0 && 1839 (m->flags & PG_WRITEABLE) == 0) 1840 return; 1841 vm_page_lock_queues(); 1842 lo = moea64_attr_fetch(m); 1843 SYNC(); 1844 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1845 pmap = pvo->pvo_pmap; 1846 PMAP_LOCK(pmap); 1847 LOCK_TABLE(); 1848 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1849 pt = moea64_pvo_to_pte(pvo); 1850 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1851 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1852 if (pt != NULL) { 1853 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 1854 lo |= pvo->pvo_pte.lpte.pte_lo; 1855 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1856 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1857 pvo->pvo_vpn); 1858 if (pvo->pvo_pmap == kernel_pmap) 1859 isync(); 1860 } 1861 } 1862 UNLOCK_TABLE(); 1863 PMAP_UNLOCK(pmap); 1864 } 1865 if ((lo & LPTE_CHG) != 0) { 1866 moea64_attr_clear(m, LPTE_CHG); 1867 vm_page_dirty(m); 1868 } 1869 vm_page_flag_clear(m, PG_WRITEABLE); 1870 vm_page_unlock_queues(); 1871} 1872 1873/* 1874 * moea64_ts_referenced: 1875 * 1876 * Return a count of reference bits for a page, clearing those bits. 1877 * It is not necessary for every reference bit to be cleared, but it 1878 * is necessary that 0 only be returned when there are truly no 1879 * reference bits set. 1880 * 1881 * XXX: The exact number of bits to check and clear is a matter that 1882 * should be tested and standardized at some point in the future for 1883 * optimal aging of shared pages. 1884 */ 1885boolean_t 1886moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1887{ 1888 1889 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1890 ("moea64_ts_referenced: page %p is not managed", m)); 1891 return (moea64_clear_bit(m, LPTE_REF)); 1892} 1893 1894/* 1895 * Modify the WIMG settings of all mappings for a page. 1896 */ 1897void 1898moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1899{ 1900 struct pvo_entry *pvo; 1901 struct pvo_head *pvo_head; 1902 struct lpte *pt; 1903 pmap_t pmap; 1904 uint64_t lo; 1905 1906 if (m->flags & PG_FICTITIOUS) { 1907 m->md.mdpg_cache_attrs = ma; 1908 return; 1909 } 1910 1911 vm_page_lock_queues(); 1912 pvo_head = vm_page_to_pvoh(m); 1913 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1914 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1915 pmap = pvo->pvo_pmap; 1916 PMAP_LOCK(pmap); 1917 LOCK_TABLE(); 1918 pt = moea64_pvo_to_pte(pvo); 1919 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1920 pvo->pvo_pte.lpte.pte_lo |= lo; 1921 if (pt != NULL) { 1922 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1923 pvo->pvo_vpn); 1924 if (pvo->pvo_pmap == kernel_pmap) 1925 isync(); 1926 } 1927 UNLOCK_TABLE(); 1928 PMAP_UNLOCK(pmap); 1929 } 1930 m->md.mdpg_cache_attrs = ma; 1931 vm_page_unlock_queues(); 1932} 1933 1934/* 1935 * Map a wired page into kernel virtual address space. 1936 */ 1937void 1938moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1939{ 1940 uint64_t pte_lo; 1941 int error; 1942 1943 pte_lo = moea64_calc_wimg(pa, ma); 1944 1945 PMAP_LOCK(kernel_pmap); 1946 error = moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1947 &moea64_pvo_kunmanaged, va, pa, pte_lo, 1948 PVO_WIRED | VM_PROT_EXECUTE); 1949 1950 if (error != 0 && error != ENOENT) 1951 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1952 pa, error); 1953 1954 /* 1955 * Flush the memory from the instruction cache. 1956 */ 1957 if ((pte_lo & (LPTE_I | LPTE_G)) == 0) { 1958 __syncicache((void *)va, PAGE_SIZE); 1959 } 1960 PMAP_UNLOCK(kernel_pmap); 1961} 1962 1963void 1964moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1965{ 1966 1967 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1968} 1969 1970/* 1971 * Extract the physical page address associated with the given kernel virtual 1972 * address. 1973 */ 1974vm_offset_t 1975moea64_kextract(mmu_t mmu, vm_offset_t va) 1976{ 1977 struct pvo_entry *pvo; 1978 vm_paddr_t pa; 1979 1980 /* 1981 * Shortcut the direct-mapped case when applicable. We never put 1982 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1983 */ 1984 if (va < VM_MIN_KERNEL_ADDRESS) 1985 return (va); 1986 1987 PMAP_LOCK(kernel_pmap); 1988 pvo = moea64_pvo_find_va(kernel_pmap, va); 1989 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1990 va)); 1991 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) + (va - PVO_VADDR(pvo)); 1992 PMAP_UNLOCK(kernel_pmap); 1993 return (pa); 1994} 1995 1996/* 1997 * Remove a wired page from kernel virtual address space. 1998 */ 1999void 2000moea64_kremove(mmu_t mmu, vm_offset_t va) 2001{ 2002 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 2003} 2004 2005/* 2006 * Map a range of physical addresses into kernel virtual address space. 2007 * 2008 * The value passed in *virt is a suggested virtual address for the mapping. 2009 * Architectures which can support a direct-mapped physical to virtual region 2010 * can return the appropriate address within that region, leaving '*virt' 2011 * unchanged. We cannot and therefore do not; *virt is updated with the 2012 * first usable address after the mapped region. 2013 */ 2014vm_offset_t 2015moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 2016 vm_offset_t pa_end, int prot) 2017{ 2018 vm_offset_t sva, va; 2019 2020 sva = *virt; 2021 va = sva; 2022 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2023 moea64_kenter(mmu, va, pa_start); 2024 *virt = va; 2025 2026 return (sva); 2027} 2028 2029/* 2030 * Returns true if the pmap's pv is one of the first 2031 * 16 pvs linked to from this page. This count may 2032 * be changed upwards or downwards in the future; it 2033 * is only necessary that true be returned for a small 2034 * subset of pmaps for proper page aging. 2035 */ 2036boolean_t 2037moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2038{ 2039 int loops; 2040 struct pvo_entry *pvo; 2041 boolean_t rv; 2042 2043 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2044 ("moea64_page_exists_quick: page %p is not managed", m)); 2045 loops = 0; 2046 rv = FALSE; 2047 vm_page_lock_queues(); 2048 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2049 if (pvo->pvo_pmap == pmap) { 2050 rv = TRUE; 2051 break; 2052 } 2053 if (++loops >= 16) 2054 break; 2055 } 2056 vm_page_unlock_queues(); 2057 return (rv); 2058} 2059 2060/* 2061 * Return the number of managed mappings to the given physical page 2062 * that are wired. 2063 */ 2064int 2065moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2066{ 2067 struct pvo_entry *pvo; 2068 int count; 2069 2070 count = 0; 2071 if ((m->flags & PG_FICTITIOUS) != 0) 2072 return (count); 2073 vm_page_lock_queues(); 2074 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2075 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 2076 count++; 2077 vm_page_unlock_queues(); 2078 return (count); 2079} 2080 2081static uintptr_t moea64_vsidcontext; 2082 2083uintptr_t 2084moea64_get_unique_vsid(void) { 2085 u_int entropy; 2086 register_t hash; 2087 uint32_t mask; 2088 int i; 2089 2090 entropy = 0; 2091 __asm __volatile("mftb %0" : "=r"(entropy)); 2092 2093 mtx_lock(&moea64_slb_mutex); 2094 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2095 u_int n; 2096 2097 /* 2098 * Create a new value by mutiplying by a prime and adding in 2099 * entropy from the timebase register. This is to make the 2100 * VSID more random so that the PT hash function collides 2101 * less often. (Note that the prime casues gcc to do shifts 2102 * instead of a multiply.) 2103 */ 2104 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2105 hash = moea64_vsidcontext & (NVSIDS - 1); 2106 if (hash == 0) /* 0 is special, avoid it */ 2107 continue; 2108 n = hash >> 5; 2109 mask = 1 << (hash & (VSID_NBPW - 1)); 2110 hash = (moea64_vsidcontext & VSID_HASHMASK); 2111 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2112 /* anything free in this bucket? */ 2113 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2114 entropy = (moea64_vsidcontext >> 20); 2115 continue; 2116 } 2117 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2118 mask = 1 << i; 2119 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 2120 hash |= i; 2121 } 2122 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2123 ("Allocating in-use VSID %#zx\n", hash)); 2124 moea64_vsid_bitmap[n] |= mask; 2125 mtx_unlock(&moea64_slb_mutex); 2126 return (hash); 2127 } 2128 2129 mtx_unlock(&moea64_slb_mutex); 2130 panic("%s: out of segments",__func__); 2131} 2132 2133#ifdef __powerpc64__ 2134void 2135moea64_pinit(mmu_t mmu, pmap_t pmap) 2136{ 2137 PMAP_LOCK_INIT(pmap); 2138 2139 pmap->pm_slb_tree_root = slb_alloc_tree(); 2140 pmap->pm_slb = slb_alloc_user_cache(); 2141 pmap->pm_slb_len = 0; 2142} 2143#else 2144void 2145moea64_pinit(mmu_t mmu, pmap_t pmap) 2146{ 2147 int i; 2148 uint32_t hash; 2149 2150 PMAP_LOCK_INIT(pmap); 2151 2152 if (pmap_bootstrapped) 2153 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2154 (vm_offset_t)pmap); 2155 else 2156 pmap->pmap_phys = pmap; 2157 2158 /* 2159 * Allocate some segment registers for this pmap. 2160 */ 2161 hash = moea64_get_unique_vsid(); 2162 2163 for (i = 0; i < 16; i++) 2164 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2165 2166 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2167} 2168#endif 2169 2170/* 2171 * Initialize the pmap associated with process 0. 2172 */ 2173void 2174moea64_pinit0(mmu_t mmu, pmap_t pm) 2175{ 2176 moea64_pinit(mmu, pm); 2177 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2178} 2179 2180/* 2181 * Set the physical protection on the specified range of this map as requested. 2182 */ 2183void 2184moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2185 vm_prot_t prot) 2186{ 2187 struct pvo_entry *pvo; 2188 struct lpte *pt; 2189 2190 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 2191 eva, prot); 2192 2193 2194 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2195 ("moea64_protect: non current pmap")); 2196 2197 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2198 moea64_remove(mmu, pm, sva, eva); 2199 return; 2200 } 2201 2202 vm_page_lock_queues(); 2203 PMAP_LOCK(pm); 2204 for (; sva < eva; sva += PAGE_SIZE) { 2205 pvo = moea64_pvo_find_va(pm, sva); 2206 if (pvo == NULL) 2207 continue; 2208 2209 /* 2210 * Grab the PTE pointer before we diddle with the cached PTE 2211 * copy. 2212 */ 2213 LOCK_TABLE(); 2214 pt = moea64_pvo_to_pte(pvo); 2215 2216 /* 2217 * Change the protection of the page. 2218 */ 2219 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 2220 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 2221 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 2222 if ((prot & VM_PROT_EXECUTE) == 0) 2223 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 2224 2225 /* 2226 * If the PVO is in the page table, update that pte as well. 2227 */ 2228 if (pt != NULL) { 2229 moea64_pte_change(pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2230 if ((pvo->pvo_pte.lpte.pte_lo & 2231 (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2232 moea64_syncicache(pm, sva, 2233 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, 2234 PAGE_SIZE); 2235 } 2236 } 2237 UNLOCK_TABLE(); 2238 } 2239 vm_page_unlock_queues(); 2240 PMAP_UNLOCK(pm); 2241} 2242 2243/* 2244 * Map a list of wired pages into kernel virtual address space. This is 2245 * intended for temporary mappings which do not need page modification or 2246 * references recorded. Existing mappings in the region are overwritten. 2247 */ 2248void 2249moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2250{ 2251 while (count-- > 0) { 2252 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2253 va += PAGE_SIZE; 2254 m++; 2255 } 2256} 2257 2258/* 2259 * Remove page mappings from kernel virtual address space. Intended for 2260 * temporary mappings entered by moea64_qenter. 2261 */ 2262void 2263moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2264{ 2265 while (count-- > 0) { 2266 moea64_kremove(mmu, va); 2267 va += PAGE_SIZE; 2268 } 2269} 2270 2271void 2272moea64_release_vsid(uint64_t vsid) 2273{ 2274 int idx, mask; 2275 2276 mtx_lock(&moea64_slb_mutex); 2277 idx = vsid & (NVSIDS-1); 2278 mask = 1 << (idx % VSID_NBPW); 2279 idx /= VSID_NBPW; 2280 KASSERT(moea64_vsid_bitmap[idx] & mask, 2281 ("Freeing unallocated VSID %#jx", vsid)); 2282 moea64_vsid_bitmap[idx] &= ~mask; 2283 mtx_unlock(&moea64_slb_mutex); 2284} 2285 2286 2287void 2288moea64_release(mmu_t mmu, pmap_t pmap) 2289{ 2290 2291 /* 2292 * Free segment registers' VSIDs 2293 */ 2294 #ifdef __powerpc64__ 2295 slb_free_tree(pmap); 2296 slb_free_user_cache(pmap->pm_slb); 2297 #else 2298 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2299 2300 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2301 #endif 2302 2303 PMAP_LOCK_DESTROY(pmap); 2304} 2305 2306/* 2307 * Remove the given range of addresses from the specified map. 2308 */ 2309void 2310moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2311{ 2312 struct pvo_entry *pvo; 2313 2314 vm_page_lock_queues(); 2315 PMAP_LOCK(pm); 2316 for (; sva < eva; sva += PAGE_SIZE) { 2317 pvo = moea64_pvo_find_va(pm, sva); 2318 if (pvo != NULL) 2319 moea64_pvo_remove(pvo); 2320 } 2321 vm_page_unlock_queues(); 2322 PMAP_UNLOCK(pm); 2323} 2324 2325/* 2326 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2327 * will reflect changes in pte's back to the vm_page. 2328 */ 2329void 2330moea64_remove_all(mmu_t mmu, vm_page_t m) 2331{ 2332 struct pvo_head *pvo_head; 2333 struct pvo_entry *pvo, *next_pvo; 2334 pmap_t pmap; 2335 2336 vm_page_lock_queues(); 2337 pvo_head = vm_page_to_pvoh(m); 2338 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 2339 next_pvo = LIST_NEXT(pvo, pvo_vlink); 2340 2341 MOEA_PVO_CHECK(pvo); /* sanity check */ 2342 pmap = pvo->pvo_pmap; 2343 PMAP_LOCK(pmap); 2344 moea64_pvo_remove(pvo); 2345 PMAP_UNLOCK(pmap); 2346 } 2347 if ((m->flags & PG_WRITEABLE) && moea64_is_modified(mmu, m)) { 2348 moea64_attr_clear(m, LPTE_CHG); 2349 vm_page_dirty(m); 2350 } 2351 vm_page_flag_clear(m, PG_WRITEABLE); 2352 vm_page_unlock_queues(); 2353} 2354 2355/* 2356 * Allocate a physical page of memory directly from the phys_avail map. 2357 * Can only be called from moea64_bootstrap before avail start and end are 2358 * calculated. 2359 */ 2360static vm_offset_t 2361moea64_bootstrap_alloc(vm_size_t size, u_int align) 2362{ 2363 vm_offset_t s, e; 2364 int i, j; 2365 2366 size = round_page(size); 2367 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2368 if (align != 0) 2369 s = (phys_avail[i] + align - 1) & ~(align - 1); 2370 else 2371 s = phys_avail[i]; 2372 e = s + size; 2373 2374 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2375 continue; 2376 2377 if (s == phys_avail[i]) { 2378 phys_avail[i] += size; 2379 } else if (e == phys_avail[i + 1]) { 2380 phys_avail[i + 1] -= size; 2381 } else { 2382 for (j = phys_avail_count * 2; j > i; j -= 2) { 2383 phys_avail[j] = phys_avail[j - 2]; 2384 phys_avail[j + 1] = phys_avail[j - 1]; 2385 } 2386 2387 phys_avail[i + 3] = phys_avail[i + 1]; 2388 phys_avail[i + 1] = s; 2389 phys_avail[i + 2] = e; 2390 phys_avail_count++; 2391 } 2392 2393 return (s); 2394 } 2395 panic("moea64_bootstrap_alloc: could not allocate memory"); 2396} 2397 2398static void 2399tlbia(void) 2400{ 2401 vm_offset_t i; 2402 #ifndef __powerpc64__ 2403 register_t msr, scratch; 2404 #endif 2405 2406 TLBSYNC(); 2407 2408 for (i = 0; i < 0xFF000; i += 0x00001000) { 2409 #ifdef __powerpc64__ 2410 __asm __volatile("tlbiel %0" :: "r"(i)); 2411 #else 2412 __asm __volatile("\ 2413 mfmsr %0; \ 2414 mr %1, %0; \ 2415 insrdi %1,%3,1,0; \ 2416 mtmsrd %1; \ 2417 isync; \ 2418 \ 2419 tlbiel %2; \ 2420 \ 2421 mtmsrd %0; \ 2422 isync;" 2423 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 2424 #endif 2425 } 2426 2427 EIEIO(); 2428 TLBSYNC(); 2429} 2430 2431#ifdef __powerpc64__ 2432static void 2433slbia(void) 2434{ 2435 register_t seg0; 2436 2437 __asm __volatile ("slbia"); 2438 __asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) : "r"(0)); 2439} 2440#endif 2441 2442static int 2443moea64_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 2444 vm_offset_t va, vm_offset_t pa, uint64_t pte_lo, int flags) 2445{ 2446 struct pvo_entry *pvo; 2447 uint64_t vsid; 2448 int first; 2449 u_int ptegidx; 2450 int i; 2451 int bootstrap; 2452 2453 /* 2454 * One nasty thing that can happen here is that the UMA calls to 2455 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2456 * which calls UMA... 2457 * 2458 * We break the loop by detecting recursion and allocating out of 2459 * the bootstrap pool. 2460 */ 2461 2462 first = 0; 2463 bootstrap = (flags & PVO_BOOTSTRAP); 2464 2465 if (!moea64_initialized) 2466 bootstrap = 1; 2467 2468 /* 2469 * Compute the PTE Group index. 2470 */ 2471 va &= ~ADDR_POFF; 2472 vsid = va_to_vsid(pm, va); 2473 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2474 2475 /* 2476 * Remove any existing mapping for this page. Reuse the pvo entry if 2477 * there is a mapping. 2478 */ 2479 LOCK_TABLE(); 2480 2481 moea64_pvo_enter_calls++; 2482 2483 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2484 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2485 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2486 (pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == 2487 (pte_lo & LPTE_PP)) { 2488 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2489 /* Re-insert if spilled */ 2490 i = moea64_pte_insert(ptegidx, 2491 &pvo->pvo_pte.lpte); 2492 if (i >= 0) 2493 PVO_PTEGIDX_SET(pvo, i); 2494 moea64_pte_overflow--; 2495 } 2496 UNLOCK_TABLE(); 2497 return (0); 2498 } 2499 moea64_pvo_remove(pvo); 2500 break; 2501 } 2502 } 2503 2504 /* 2505 * If we aren't overwriting a mapping, try to allocate. 2506 */ 2507 if (bootstrap) { 2508 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2509 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2510 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2511 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2512 } 2513 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2514 moea64_bpvo_pool_index++; 2515 bootstrap = 1; 2516 } else { 2517 /* 2518 * Note: drop the table lock around the UMA allocation in 2519 * case the UMA allocator needs to manipulate the page 2520 * table. The mapping we are working with is already 2521 * protected by the PMAP lock. 2522 */ 2523 UNLOCK_TABLE(); 2524 pvo = uma_zalloc(zone, M_NOWAIT); 2525 LOCK_TABLE(); 2526 } 2527 2528 if (pvo == NULL) { 2529 UNLOCK_TABLE(); 2530 return (ENOMEM); 2531 } 2532 2533 moea64_pvo_entries++; 2534 pvo->pvo_vaddr = va; 2535 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2536 | (vsid << 16); 2537 pvo->pvo_pmap = pm; 2538 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2539 pvo->pvo_vaddr &= ~ADDR_POFF; 2540 2541 if (!(flags & VM_PROT_EXECUTE)) 2542 pte_lo |= LPTE_NOEXEC; 2543 if (flags & PVO_WIRED) 2544 pvo->pvo_vaddr |= PVO_WIRED; 2545 if (pvo_head != &moea64_pvo_kunmanaged) 2546 pvo->pvo_vaddr |= PVO_MANAGED; 2547 if (bootstrap) 2548 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2549 if (flags & PVO_FAKE) 2550 pvo->pvo_vaddr |= PVO_FAKE; 2551 if (flags & PVO_LARGE) 2552 pvo->pvo_vaddr |= PVO_LARGE; 2553 2554 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2555 (uint64_t)(pa) | pte_lo, flags); 2556 2557 /* 2558 * Remember if the list was empty and therefore will be the first 2559 * item. 2560 */ 2561 if (LIST_FIRST(pvo_head) == NULL) 2562 first = 1; 2563 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2564 2565 if (pvo->pvo_vaddr & PVO_WIRED) { 2566 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2567 pm->pm_stats.wired_count++; 2568 } 2569 pm->pm_stats.resident_count++; 2570 2571 /* 2572 * We hope this succeeds but it isn't required. 2573 */ 2574 i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte); 2575 if (i >= 0) { 2576 PVO_PTEGIDX_SET(pvo, i); 2577 } else { 2578 panic("moea64_pvo_enter: overflow"); 2579 moea64_pte_overflow++; 2580 } 2581 2582 if (pm == kernel_pmap) 2583 isync(); 2584 2585 UNLOCK_TABLE(); 2586 2587#ifdef __powerpc64__ 2588 /* 2589 * Make sure all our bootstrap mappings are in the SLB as soon 2590 * as virtual memory is switched on. 2591 */ 2592 if (!pmap_bootstrapped) 2593 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2594#endif 2595 2596 return (first ? ENOENT : 0); 2597} 2598 2599static void 2600moea64_pvo_remove(struct pvo_entry *pvo) 2601{ 2602 struct lpte *pt; 2603 2604 /* 2605 * If there is an active pte entry, we need to deactivate it (and 2606 * save the ref & cfg bits). 2607 */ 2608 LOCK_TABLE(); 2609 pt = moea64_pvo_to_pte(pvo); 2610 if (pt != NULL) { 2611 moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2612 PVO_PTEGIDX_CLR(pvo); 2613 } else { 2614 moea64_pte_overflow--; 2615 } 2616 2617 /* 2618 * Update our statistics. 2619 */ 2620 pvo->pvo_pmap->pm_stats.resident_count--; 2621 if (pvo->pvo_vaddr & PVO_WIRED) 2622 pvo->pvo_pmap->pm_stats.wired_count--; 2623 2624 /* 2625 * Save the REF/CHG bits into their cache if the page is managed. 2626 */ 2627 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2628 struct vm_page *pg; 2629 2630 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2631 if (pg != NULL) { 2632 moea64_attr_save(pg, pvo->pvo_pte.lpte.pte_lo & 2633 (LPTE_REF | LPTE_CHG)); 2634 } 2635 } 2636 2637 /* 2638 * Remove this PVO from the PV list. 2639 */ 2640 LIST_REMOVE(pvo, pvo_vlink); 2641 2642 /* 2643 * Remove this from the overflow list and return it to the pool 2644 * if we aren't going to reuse it. 2645 */ 2646 LIST_REMOVE(pvo, pvo_olink); 2647 2648 moea64_pvo_entries--; 2649 moea64_pvo_remove_calls++; 2650 2651 UNLOCK_TABLE(); 2652 2653 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2654 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2655 moea64_upvo_zone, pvo); 2656} 2657 2658static struct pvo_entry * 2659moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2660{ 2661 struct pvo_entry *pvo; 2662 int ptegidx; 2663 uint64_t vsid; 2664 #ifdef __powerpc64__ 2665 uint64_t slbv; 2666 2667 if (pm == kernel_pmap) { 2668 slbv = kernel_va_to_slbv(va); 2669 } else { 2670 struct slb *slb; 2671 slb = user_va_to_slb_entry(pm, va); 2672 /* The page is not mapped if the segment isn't */ 2673 if (slb == NULL) 2674 return NULL; 2675 slbv = slb->slbv; 2676 } 2677 2678 vsid = (slbv & SLBV_VSID_MASK) >> SLBV_VSID_SHIFT; 2679 if (slbv & SLBV_L) 2680 va &= ~moea64_large_page_mask; 2681 else 2682 va &= ~ADDR_POFF; 2683 ptegidx = va_to_pteg(vsid, va, slbv & SLBV_L); 2684 #else 2685 va &= ~ADDR_POFF; 2686 vsid = va_to_vsid(pm, va); 2687 ptegidx = va_to_pteg(vsid, va, 0); 2688 #endif 2689 2690 LOCK_TABLE(); 2691 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2692 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) 2693 break; 2694 } 2695 UNLOCK_TABLE(); 2696 2697 return (pvo); 2698} 2699 2700static struct lpte * 2701moea64_pvo_to_pte(const struct pvo_entry *pvo) 2702{ 2703 struct lpte *pt; 2704 int pteidx, ptegidx; 2705 uint64_t vsid; 2706 2707 ASSERT_TABLE_LOCK(); 2708 2709 /* If the PTEG index is not set, then there is no page table entry */ 2710 if (!PVO_PTEGIDX_ISSET(pvo)) 2711 return (NULL); 2712 2713 /* 2714 * Calculate the ptegidx 2715 */ 2716 vsid = PVO_VSID(pvo); 2717 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 2718 pvo->pvo_vaddr & PVO_LARGE); 2719 2720 /* 2721 * We can find the actual pte entry without searching by grabbing 2722 * the PTEG index from 3 unused bits in pvo_vaddr and by 2723 * noticing the HID bit. 2724 */ 2725 if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID) 2726 ptegidx ^= moea64_pteg_mask; 2727 2728 pteidx = (ptegidx << 3) | PVO_PTEGIDX_GET(pvo); 2729 2730 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 2731 !PVO_PTEGIDX_ISSET(pvo)) { 2732 panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no " 2733 "valid pte index", pvo); 2734 } 2735 2736 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 && 2737 PVO_PTEGIDX_ISSET(pvo)) { 2738 panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo " 2739 "pvo but no valid pte", pvo); 2740 } 2741 2742 pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2743 if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) == 2744 LPTE_VALID) { 2745 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) { 2746 panic("moea64_pvo_to_pte: pvo %p has valid pte in " 2747 "moea64_pteg_table %p but invalid in pvo", pvo, pt); 2748 } 2749 2750 if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & 2751 ~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) { 2752 panic("moea64_pvo_to_pte: pvo %p pte does not match " 2753 "pte %p in moea64_pteg_table difference is %#x", 2754 pvo, pt, 2755 (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo)); 2756 } 2757 2758 return (pt); 2759 } 2760 2761 if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) { 2762 panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in " 2763 "moea64_pteg_table but valid in pvo", pvo, pt); 2764 } 2765 2766 return (NULL); 2767} 2768 2769static __inline int 2770moea64_pte_spillable_ident(u_int ptegidx) 2771{ 2772 struct lpte *pt; 2773 int i, j, k; 2774 2775 /* Start at a random slot */ 2776 i = mftb() % 8; 2777 k = -1; 2778 for (j = 0; j < 8; j++) { 2779 pt = &moea64_pteg_table[ptegidx].pt[(i + j) % 8]; 2780 if (pt->pte_hi & (LPTE_LOCKED | LPTE_WIRED)) 2781 continue; 2782 2783 /* This is a candidate, so remember it */ 2784 k = (i + j) % 8; 2785 2786 /* Try to get a page that has not been used lately */ 2787 if (!(pt->pte_lo & LPTE_REF)) 2788 return (k); 2789 } 2790 2791 return (k); 2792} 2793 2794static int 2795moea64_pte_insert(u_int ptegidx, struct lpte *pvo_pt) 2796{ 2797 struct lpte *pt; 2798 struct pvo_entry *pvo; 2799 u_int pteg_bktidx; 2800 int i; 2801 2802 ASSERT_TABLE_LOCK(); 2803 2804 /* 2805 * First try primary hash. 2806 */ 2807 pteg_bktidx = ptegidx; 2808 for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) { 2809 if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) { 2810 pvo_pt->pte_hi &= ~LPTE_HID; 2811 moea64_pte_set(pt, pvo_pt); 2812 return (i); 2813 } 2814 } 2815 2816 /* 2817 * Now try secondary hash. 2818 */ 2819 pteg_bktidx ^= moea64_pteg_mask; 2820 for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) { 2821 if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) { 2822 pvo_pt->pte_hi |= LPTE_HID; 2823 moea64_pte_set(pt, pvo_pt); 2824 return (i); 2825 } 2826 } 2827 2828 /* 2829 * Out of luck. Find a PTE to sacrifice. 2830 */ 2831 pteg_bktidx = ptegidx; 2832 i = moea64_pte_spillable_ident(pteg_bktidx); 2833 if (i < 0) { 2834 pteg_bktidx ^= moea64_pteg_mask; 2835 i = moea64_pte_spillable_ident(pteg_bktidx); 2836 } 2837 2838 if (i < 0) { 2839 /* No freeable slots in either PTEG? We're hosed. */ 2840 panic("moea64_pte_insert: overflow"); 2841 return (-1); 2842 } 2843 2844 if (pteg_bktidx == ptegidx) 2845 pvo_pt->pte_hi &= ~LPTE_HID; 2846 else 2847 pvo_pt->pte_hi |= LPTE_HID; 2848 2849 /* 2850 * Synchronize the sacrifice PTE with its PVO, then mark both 2851 * invalid. The PVO will be reused when/if the VM system comes 2852 * here after a fault. 2853 */ 2854 pt = &moea64_pteg_table[pteg_bktidx].pt[i]; 2855 2856 if (pt->pte_hi & LPTE_HID) 2857 pteg_bktidx ^= moea64_pteg_mask; /* PTEs indexed by primary */ 2858 2859 LIST_FOREACH(pvo, &moea64_pvo_table[pteg_bktidx], pvo_olink) { 2860 if (pvo->pvo_pte.lpte.pte_hi == pt->pte_hi) { 2861 KASSERT(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID, 2862 ("Invalid PVO for valid PTE!")); 2863 moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2864 PVO_PTEGIDX_CLR(pvo); 2865 moea64_pte_overflow++; 2866 break; 2867 } 2868 } 2869 2870 KASSERT(pvo->pvo_pte.lpte.pte_hi == pt->pte_hi, 2871 ("Unable to find PVO for spilled PTE")); 2872 2873 /* 2874 * Set the new PTE. 2875 */ 2876 moea64_pte_set(pt, pvo_pt); 2877 2878 return (i); 2879} 2880 2881static boolean_t 2882moea64_query_bit(vm_page_t m, u_int64_t ptebit) 2883{ 2884 struct pvo_entry *pvo; 2885 struct lpte *pt; 2886 2887 if (moea64_attr_fetch(m) & ptebit) 2888 return (TRUE); 2889 2890 vm_page_lock_queues(); 2891 2892 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2893 MOEA_PVO_CHECK(pvo); /* sanity check */ 2894 2895 /* 2896 * See if we saved the bit off. If so, cache it and return 2897 * success. 2898 */ 2899 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2900 moea64_attr_save(m, ptebit); 2901 MOEA_PVO_CHECK(pvo); /* sanity check */ 2902 vm_page_unlock_queues(); 2903 return (TRUE); 2904 } 2905 } 2906 2907 /* 2908 * No luck, now go through the hard part of looking at the PTEs 2909 * themselves. Sync so that any pending REF/CHG bits are flushed to 2910 * the PTEs. 2911 */ 2912 SYNC(); 2913 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2914 MOEA_PVO_CHECK(pvo); /* sanity check */ 2915 2916 /* 2917 * See if this pvo has a valid PTE. if so, fetch the 2918 * REF/CHG bits from the valid PTE. If the appropriate 2919 * ptebit is set, cache it and return success. 2920 */ 2921 LOCK_TABLE(); 2922 pt = moea64_pvo_to_pte(pvo); 2923 if (pt != NULL) { 2924 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2925 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2926 UNLOCK_TABLE(); 2927 2928 moea64_attr_save(m, ptebit); 2929 MOEA_PVO_CHECK(pvo); /* sanity check */ 2930 vm_page_unlock_queues(); 2931 return (TRUE); 2932 } 2933 } 2934 UNLOCK_TABLE(); 2935 } 2936 2937 vm_page_unlock_queues(); 2938 return (FALSE); 2939} 2940 2941static u_int 2942moea64_clear_bit(vm_page_t m, u_int64_t ptebit) 2943{ 2944 u_int count; 2945 struct pvo_entry *pvo; 2946 struct lpte *pt; 2947 2948 vm_page_lock_queues(); 2949 2950 /* 2951 * Clear the cached value. 2952 */ 2953 moea64_attr_clear(m, ptebit); 2954 2955 /* 2956 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2957 * we can reset the right ones). note that since the pvo entries and 2958 * list heads are accessed via BAT0 and are never placed in the page 2959 * table, we don't have to worry about further accesses setting the 2960 * REF/CHG bits. 2961 */ 2962 SYNC(); 2963 2964 /* 2965 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2966 * valid pte clear the ptebit from the valid pte. 2967 */ 2968 count = 0; 2969 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2970 MOEA_PVO_CHECK(pvo); /* sanity check */ 2971 2972 LOCK_TABLE(); 2973 pt = moea64_pvo_to_pte(pvo); 2974 if (pt != NULL) { 2975 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2976 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2977 count++; 2978 moea64_pte_clear(pt, pvo->pvo_vpn, ptebit); 2979 } 2980 } 2981 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2982 MOEA_PVO_CHECK(pvo); /* sanity check */ 2983 UNLOCK_TABLE(); 2984 } 2985 2986 vm_page_unlock_queues(); 2987 return (count); 2988} 2989 2990boolean_t 2991moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2992{ 2993 struct pvo_entry *pvo; 2994 vm_offset_t ppa; 2995 int error = 0; 2996 2997 PMAP_LOCK(kernel_pmap); 2998 for (ppa = pa & ~ADDR_POFF; ppa < pa + size; ppa += PAGE_SIZE) { 2999 pvo = moea64_pvo_find_va(kernel_pmap, ppa); 3000 if (pvo == NULL || 3001 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 3002 error = EFAULT; 3003 break; 3004 } 3005 } 3006 PMAP_UNLOCK(kernel_pmap); 3007 3008 return (error); 3009} 3010 3011/* 3012 * Map a set of physical memory pages into the kernel virtual 3013 * address space. Return a pointer to where it is mapped. This 3014 * routine is intended to be used for mapping device memory, 3015 * NOT real memory. 3016 */ 3017void * 3018moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 3019{ 3020 vm_offset_t va, tmpva, ppa, offset; 3021 3022 ppa = trunc_page(pa); 3023 offset = pa & PAGE_MASK; 3024 size = roundup(offset + size, PAGE_SIZE); 3025 3026 va = kmem_alloc_nofault(kernel_map, size); 3027 3028 if (!va) 3029 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 3030 3031 for (tmpva = va; size > 0;) { 3032 moea64_kenter_attr(mmu, tmpva, ppa, ma); 3033 size -= PAGE_SIZE; 3034 tmpva += PAGE_SIZE; 3035 ppa += PAGE_SIZE; 3036 } 3037 3038 return ((void *)(va + offset)); 3039} 3040 3041void * 3042moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 3043{ 3044 3045 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 3046} 3047 3048void 3049moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 3050{ 3051 vm_offset_t base, offset; 3052 3053 base = trunc_page(va); 3054 offset = va & PAGE_MASK; 3055 size = roundup(offset + size, PAGE_SIZE); 3056 3057 kmem_free(kernel_map, base, size); 3058} 3059 3060static void 3061moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 3062{ 3063 struct pvo_entry *pvo; 3064 vm_offset_t lim; 3065 vm_paddr_t pa; 3066 vm_size_t len; 3067 3068 PMAP_LOCK(pm); 3069 while (sz > 0) { 3070 lim = round_page(va); 3071 len = MIN(lim - va, sz); 3072 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 3073 if (pvo != NULL) { 3074 pa = (pvo->pvo_pte.pte.pte_lo & LPTE_RPGN) | 3075 (va & ADDR_POFF); 3076 moea64_syncicache(pm, va, pa, len); 3077 } 3078 va += len; 3079 sz -= len; 3080 } 3081 PMAP_UNLOCK(pm); 3082} 3083