mmu_oea64.c revision 208504
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#include <sys/cdefs.h> 94__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea64.c 208504 2010-05-24 14:26:57Z alc $"); 95 96/* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117#include "opt_kstack_pages.h" 118 119#include <sys/param.h> 120#include <sys/kernel.h> 121#include <sys/ktr.h> 122#include <sys/lock.h> 123#include <sys/msgbuf.h> 124#include <sys/mutex.h> 125#include <sys/proc.h> 126#include <sys/sysctl.h> 127#include <sys/systm.h> 128#include <sys/vmmeter.h> 129 130#include <sys/kdb.h> 131 132#include <dev/ofw/openfirm.h> 133 134#include <vm/vm.h> 135#include <vm/vm_param.h> 136#include <vm/vm_kern.h> 137#include <vm/vm_page.h> 138#include <vm/vm_map.h> 139#include <vm/vm_object.h> 140#include <vm/vm_extern.h> 141#include <vm/vm_pageout.h> 142#include <vm/vm_pager.h> 143#include <vm/uma.h> 144 145#include <machine/cpu.h> 146#include <machine/platform.h> 147#include <machine/frame.h> 148#include <machine/md_var.h> 149#include <machine/psl.h> 150#include <machine/bat.h> 151#include <machine/pte.h> 152#include <machine/sr.h> 153#include <machine/trap.h> 154#include <machine/mmuvar.h> 155 156#include "mmu_if.h" 157 158#define MOEA_DEBUG 159 160#define TODO panic("%s: not implemented", __func__); 161 162static __inline u_int32_t 163cntlzw(volatile u_int32_t a) { 164 u_int32_t b; 165 __asm ("cntlzw %0, %1" : "=r"(b) : "r"(a)); 166 return b; 167} 168 169static __inline uint64_t 170va_to_vsid(pmap_t pm, vm_offset_t va) 171{ 172 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK); 173} 174 175#define PTESYNC() __asm __volatile("ptesync"); 176#define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 177#define SYNC() __asm __volatile("sync"); 178#define EIEIO() __asm __volatile("eieio"); 179 180/* 181 * The tlbie instruction must be executed in 64-bit mode 182 * so we have to twiddle MSR[SF] around every invocation. 183 * Just to add to the fun, exceptions must be off as well 184 * so that we can't trap in 64-bit mode. What a pain. 185 */ 186struct mtx tlbie_mutex; 187 188static __inline void 189TLBIE(pmap_t pmap, vm_offset_t va) { 190 uint64_t vpn; 191 register_t vpn_hi, vpn_lo; 192 register_t msr; 193 register_t scratch; 194 195 vpn = (uint64_t)(va & ADDR_PIDX); 196 if (pmap != NULL) 197 vpn |= (va_to_vsid(pmap,va) << 28); 198 vpn &= ~(0xffffULL << 48); 199 200 vpn_hi = (uint32_t)(vpn >> 32); 201 vpn_lo = (uint32_t)vpn; 202 203 mtx_lock_spin(&tlbie_mutex); 204 __asm __volatile("\ 205 mfmsr %0; \ 206 mr %1, %0; \ 207 insrdi %1,%5,1,0; \ 208 mtmsrd %1; \ 209 ptesync; \ 210 \ 211 sld %1,%2,%4; \ 212 or %1,%1,%3; \ 213 tlbie %1; \ 214 \ 215 mtmsrd %0; \ 216 eieio; \ 217 tlbsync; \ 218 ptesync;" 219 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) 220 : "memory"); 221 mtx_unlock_spin(&tlbie_mutex); 222} 223 224#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync() 225#define ENABLE_TRANS(msr) mtmsr(msr); isync() 226 227#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 228#define VSID_TO_SR(vsid) ((vsid) & 0xf) 229#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 230#define VSID_HASH_MASK 0x0000007fffffffffULL 231 232#define PVO_PTEGIDX_MASK 0x007UL /* which PTEG slot */ 233#define PVO_PTEGIDX_VALID 0x008UL /* slot is valid */ 234#define PVO_WIRED 0x010UL /* PVO entry is wired */ 235#define PVO_MANAGED 0x020UL /* PVO entry is managed */ 236#define PVO_BOOTSTRAP 0x080UL /* PVO entry allocated during 237 bootstrap */ 238#define PVO_FAKE 0x100UL /* fictitious phys page */ 239#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 240#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 241#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 242#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 243#define PVO_PTEGIDX_CLR(pvo) \ 244 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 245#define PVO_PTEGIDX_SET(pvo, i) \ 246 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 247 248#define MOEA_PVO_CHECK(pvo) 249 250#define LOCK_TABLE() mtx_lock(&moea64_table_mutex) 251#define UNLOCK_TABLE() mtx_unlock(&moea64_table_mutex); 252#define ASSERT_TABLE_LOCK() mtx_assert(&moea64_table_mutex, MA_OWNED) 253 254struct ofw_map { 255 vm_offset_t om_va; 256 vm_size_t om_len; 257 vm_offset_t om_pa_hi; 258 vm_offset_t om_pa_lo; 259 u_int om_mode; 260}; 261 262/* 263 * Map of physical memory regions. 264 */ 265static struct mem_region *regions; 266static struct mem_region *pregions; 267extern u_int phys_avail_count; 268extern int regions_sz, pregions_sz; 269extern int ofw_real_mode; 270 271extern struct pmap ofw_pmap; 272 273extern void bs_remap_earlyboot(void); 274 275 276/* 277 * Lock for the pteg and pvo tables. 278 */ 279struct mtx moea64_table_mutex; 280 281/* 282 * PTEG data. 283 */ 284static struct lpteg *moea64_pteg_table; 285u_int moea64_pteg_count; 286u_int moea64_pteg_mask; 287 288/* 289 * PVO data. 290 */ 291struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 292/* lists of unmanaged pages */ 293struct pvo_head moea64_pvo_kunmanaged = 294 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 295struct pvo_head moea64_pvo_unmanaged = 296 LIST_HEAD_INITIALIZER(moea64_pvo_unmanaged); 297 298uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 299uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 300 301#define BPVO_POOL_SIZE 327680 302static struct pvo_entry *moea64_bpvo_pool; 303static int moea64_bpvo_pool_index = 0; 304 305#define VSID_NBPW (sizeof(u_int32_t) * 8) 306static u_int moea64_vsid_bitmap[NPMAPS / VSID_NBPW]; 307 308static boolean_t moea64_initialized = FALSE; 309 310/* 311 * Statistics. 312 */ 313u_int moea64_pte_valid = 0; 314u_int moea64_pte_overflow = 0; 315u_int moea64_pvo_entries = 0; 316u_int moea64_pvo_enter_calls = 0; 317u_int moea64_pvo_remove_calls = 0; 318SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 319 &moea64_pte_valid, 0, ""); 320SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 321 &moea64_pte_overflow, 0, ""); 322SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 323 &moea64_pvo_entries, 0, ""); 324SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 325 &moea64_pvo_enter_calls, 0, ""); 326SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 327 &moea64_pvo_remove_calls, 0, ""); 328 329vm_offset_t moea64_scratchpage_va[2]; 330struct lpte *moea64_scratchpage_pte[2]; 331struct mtx moea64_scratchpage_mtx; 332 333/* 334 * Allocate physical memory for use in moea64_bootstrap. 335 */ 336static vm_offset_t moea64_bootstrap_alloc(vm_size_t, u_int); 337 338/* 339 * PTE calls. 340 */ 341static int moea64_pte_insert(u_int, struct lpte *); 342 343/* 344 * PVO calls. 345 */ 346static int moea64_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 347 vm_offset_t, vm_offset_t, uint64_t, int); 348static void moea64_pvo_remove(struct pvo_entry *, int); 349static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t, int *); 350static struct lpte *moea64_pvo_to_pte(const struct pvo_entry *, int); 351 352/* 353 * Utility routines. 354 */ 355static void moea64_bridge_bootstrap(mmu_t mmup, 356 vm_offset_t kernelstart, vm_offset_t kernelend); 357static void moea64_bridge_cpu_bootstrap(mmu_t, int ap); 358static void moea64_enter_locked(pmap_t, vm_offset_t, vm_page_t, 359 vm_prot_t, boolean_t); 360static boolean_t moea64_query_bit(vm_page_t, u_int64_t); 361static u_int moea64_clear_bit(vm_page_t, u_int64_t, u_int64_t *); 362static void moea64_kremove(mmu_t, vm_offset_t); 363static void moea64_syncicache(pmap_t pmap, vm_offset_t va, 364 vm_offset_t pa, vm_size_t sz); 365static void tlbia(void); 366 367/* 368 * Kernel MMU interface 369 */ 370void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 371void moea64_clear_modify(mmu_t, vm_page_t); 372void moea64_clear_reference(mmu_t, vm_page_t); 373void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 374void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 375void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 376 vm_prot_t); 377void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 378vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 379vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 380void moea64_init(mmu_t); 381boolean_t moea64_is_modified(mmu_t, vm_page_t); 382boolean_t moea64_is_referenced(mmu_t, vm_page_t); 383boolean_t moea64_ts_referenced(mmu_t, vm_page_t); 384vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 385boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 386int moea64_page_wired_mappings(mmu_t, vm_page_t); 387void moea64_pinit(mmu_t, pmap_t); 388void moea64_pinit0(mmu_t, pmap_t); 389void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 390void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 391void moea64_qremove(mmu_t, vm_offset_t, int); 392void moea64_release(mmu_t, pmap_t); 393void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 394void moea64_remove_all(mmu_t, vm_page_t); 395void moea64_remove_write(mmu_t, vm_page_t); 396void moea64_zero_page(mmu_t, vm_page_t); 397void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 398void moea64_zero_page_idle(mmu_t, vm_page_t); 399void moea64_activate(mmu_t, struct thread *); 400void moea64_deactivate(mmu_t, struct thread *); 401void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 402void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 403vm_offset_t moea64_kextract(mmu_t, vm_offset_t); 404void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 405boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 406static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 407 408static mmu_method_t moea64_bridge_methods[] = { 409 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 410 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 411 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 412 MMUMETHOD(mmu_copy_page, moea64_copy_page), 413 MMUMETHOD(mmu_enter, moea64_enter), 414 MMUMETHOD(mmu_enter_object, moea64_enter_object), 415 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 416 MMUMETHOD(mmu_extract, moea64_extract), 417 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 418 MMUMETHOD(mmu_init, moea64_init), 419 MMUMETHOD(mmu_is_modified, moea64_is_modified), 420 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 421 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 422 MMUMETHOD(mmu_map, moea64_map), 423 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 424 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 425 MMUMETHOD(mmu_pinit, moea64_pinit), 426 MMUMETHOD(mmu_pinit0, moea64_pinit0), 427 MMUMETHOD(mmu_protect, moea64_protect), 428 MMUMETHOD(mmu_qenter, moea64_qenter), 429 MMUMETHOD(mmu_qremove, moea64_qremove), 430 MMUMETHOD(mmu_release, moea64_release), 431 MMUMETHOD(mmu_remove, moea64_remove), 432 MMUMETHOD(mmu_remove_all, moea64_remove_all), 433 MMUMETHOD(mmu_remove_write, moea64_remove_write), 434 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 435 MMUMETHOD(mmu_zero_page, moea64_zero_page), 436 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 437 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 438 MMUMETHOD(mmu_activate, moea64_activate), 439 MMUMETHOD(mmu_deactivate, moea64_deactivate), 440 441 /* Internal interfaces */ 442 MMUMETHOD(mmu_bootstrap, moea64_bridge_bootstrap), 443 MMUMETHOD(mmu_cpu_bootstrap, moea64_bridge_cpu_bootstrap), 444 MMUMETHOD(mmu_mapdev, moea64_mapdev), 445 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 446 MMUMETHOD(mmu_kextract, moea64_kextract), 447 MMUMETHOD(mmu_kenter, moea64_kenter), 448 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 449 450 { 0, 0 } 451}; 452 453static mmu_def_t oea64_bridge_mmu = { 454 MMU_TYPE_G5, 455 moea64_bridge_methods, 456 0 457}; 458MMU_DEF(oea64_bridge_mmu); 459 460static __inline u_int 461va_to_pteg(uint64_t vsid, vm_offset_t addr) 462{ 463 uint64_t hash; 464 465 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 466 ADDR_PIDX_SHFT); 467 return (hash & moea64_pteg_mask); 468} 469 470static __inline struct pvo_head * 471pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 472{ 473 struct vm_page *pg; 474 475 pg = PHYS_TO_VM_PAGE(pa); 476 477 if (pg_p != NULL) 478 *pg_p = pg; 479 480 if (pg == NULL) 481 return (&moea64_pvo_unmanaged); 482 483 return (&pg->md.mdpg_pvoh); 484} 485 486static __inline struct pvo_head * 487vm_page_to_pvoh(vm_page_t m) 488{ 489 490 return (&m->md.mdpg_pvoh); 491} 492 493static __inline void 494moea64_attr_clear(vm_page_t m, u_int64_t ptebit) 495{ 496 497 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 498 m->md.mdpg_attrs &= ~ptebit; 499} 500 501static __inline u_int64_t 502moea64_attr_fetch(vm_page_t m) 503{ 504 505 return (m->md.mdpg_attrs); 506} 507 508static __inline void 509moea64_attr_save(vm_page_t m, u_int64_t ptebit) 510{ 511 512 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 513 m->md.mdpg_attrs |= ptebit; 514} 515 516static __inline void 517moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 518 uint64_t pte_lo) 519{ 520 ASSERT_TABLE_LOCK(); 521 522 /* 523 * Construct a PTE. Default to IMB initially. Valid bit only gets 524 * set when the real pte is set in memory. 525 * 526 * Note: Don't set the valid bit for correct operation of tlb update. 527 */ 528 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 529 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 530 531 pt->pte_lo = pte_lo; 532} 533 534static __inline void 535moea64_pte_synch(struct lpte *pt, struct lpte *pvo_pt) 536{ 537 538 ASSERT_TABLE_LOCK(); 539 540 pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG); 541} 542 543static __inline void 544moea64_pte_clear(struct lpte *pt, pmap_t pmap, vm_offset_t va, u_int64_t ptebit) 545{ 546 ASSERT_TABLE_LOCK(); 547 548 /* 549 * As shown in Section 7.6.3.2.3 550 */ 551 pt->pte_lo &= ~ptebit; 552 TLBIE(pmap,va); 553} 554 555static __inline void 556moea64_pte_set(struct lpte *pt, struct lpte *pvo_pt) 557{ 558 559 ASSERT_TABLE_LOCK(); 560 pvo_pt->pte_hi |= LPTE_VALID; 561 562 /* 563 * Update the PTE as defined in section 7.6.3.1. 564 * Note that the REF/CHG bits are from pvo_pt and thus should have 565 * been saved so this routine can restore them (if desired). 566 */ 567 pt->pte_lo = pvo_pt->pte_lo; 568 EIEIO(); 569 pt->pte_hi = pvo_pt->pte_hi; 570 PTESYNC(); 571 moea64_pte_valid++; 572} 573 574static __inline void 575moea64_pte_unset(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 576{ 577 ASSERT_TABLE_LOCK(); 578 pvo_pt->pte_hi &= ~LPTE_VALID; 579 580 /* 581 * Force the reg & chg bits back into the PTEs. 582 */ 583 SYNC(); 584 585 /* 586 * Invalidate the pte. 587 */ 588 pt->pte_hi &= ~LPTE_VALID; 589 TLBIE(pmap,va); 590 591 /* 592 * Save the reg & chg bits. 593 */ 594 moea64_pte_synch(pt, pvo_pt); 595 moea64_pte_valid--; 596} 597 598static __inline void 599moea64_pte_change(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 600{ 601 602 /* 603 * Invalidate the PTE 604 */ 605 moea64_pte_unset(pt, pvo_pt, pmap, va); 606 moea64_pte_set(pt, pvo_pt); 607 if (pmap == kernel_pmap) 608 isync(); 609} 610 611static __inline uint64_t 612moea64_calc_wimg(vm_offset_t pa) 613{ 614 uint64_t pte_lo; 615 int i; 616 617 /* 618 * Assume the page is cache inhibited and access is guarded unless 619 * it's in our available memory array. 620 */ 621 pte_lo = LPTE_I | LPTE_G; 622 for (i = 0; i < pregions_sz; i++) { 623 if ((pa >= pregions[i].mr_start) && 624 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 625 pte_lo &= ~(LPTE_I | LPTE_G); 626 pte_lo |= LPTE_M; 627 break; 628 } 629 } 630 631 return pte_lo; 632} 633 634/* 635 * Quick sort callout for comparing memory regions. 636 */ 637static int mr_cmp(const void *a, const void *b); 638static int om_cmp(const void *a, const void *b); 639 640static int 641mr_cmp(const void *a, const void *b) 642{ 643 const struct mem_region *regiona; 644 const struct mem_region *regionb; 645 646 regiona = a; 647 regionb = b; 648 if (regiona->mr_start < regionb->mr_start) 649 return (-1); 650 else if (regiona->mr_start > regionb->mr_start) 651 return (1); 652 else 653 return (0); 654} 655 656static int 657om_cmp(const void *a, const void *b) 658{ 659 const struct ofw_map *mapa; 660 const struct ofw_map *mapb; 661 662 mapa = a; 663 mapb = b; 664 if (mapa->om_pa_hi < mapb->om_pa_hi) 665 return (-1); 666 else if (mapa->om_pa_hi > mapb->om_pa_hi) 667 return (1); 668 else if (mapa->om_pa_lo < mapb->om_pa_lo) 669 return (-1); 670 else if (mapa->om_pa_lo > mapb->om_pa_lo) 671 return (1); 672 else 673 return (0); 674} 675 676static void 677moea64_bridge_cpu_bootstrap(mmu_t mmup, int ap) 678{ 679 int i = 0; 680 681 /* 682 * Initialize segment registers and MMU 683 */ 684 685 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); isync(); 686 for (i = 0; i < 16; i++) { 687 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 688 } 689 __asm __volatile ("ptesync; mtsdr1 %0; isync" 690 :: "r"((u_int)moea64_pteg_table 691 | (32 - cntlzw(moea64_pteg_mask >> 11)))); 692 tlbia(); 693} 694 695static void 696moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 697{ 698 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 699 register_t msr; 700 vm_offset_t off; 701 vm_paddr_t pa_base; 702 int i, ofw_mappings; 703 704 bzero(translations, sz); 705 if (OF_getprop(mmu, "translations", translations, sz) == -1) 706 panic("moea64_bootstrap: can't get ofw translations"); 707 708 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 709 sz /= sizeof(*translations); 710 qsort(translations, sz, sizeof (*translations), om_cmp); 711 712 for (i = 0, ofw_mappings = 0; i < sz; i++) { 713 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 714 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 715 translations[i].om_len); 716 717 if (translations[i].om_pa_lo % PAGE_SIZE) 718 panic("OFW translation not page-aligned!"); 719 720 if (translations[i].om_pa_hi) 721 panic("OFW translations above 32-bit boundary!"); 722 723 pa_base = translations[i].om_pa_lo; 724 725 /* Now enter the pages for this mapping */ 726 727 DISABLE_TRANS(msr); 728 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 729 moea64_kenter(mmup, translations[i].om_va + off, 730 pa_base + off); 731 732 ofw_mappings++; 733 } 734 ENABLE_TRANS(msr); 735 } 736} 737 738static void 739moea64_bridge_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 740{ 741 ihandle_t mmui; 742 phandle_t chosen; 743 phandle_t mmu; 744 size_t sz; 745 int i, j; 746 vm_size_t size, physsz, hwphyssz; 747 vm_offset_t pa, va, off; 748 register_t msr; 749 void *dpcpu; 750 751 /* We don't have a direct map since there is no BAT */ 752 hw_direct_map = 0; 753 754 /* Make sure battable is zero, since we have no BAT */ 755 for (i = 0; i < 16; i++) { 756 battable[i].batu = 0; 757 battable[i].batl = 0; 758 } 759 760 /* Get physical memory regions from firmware */ 761 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 762 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 763 764 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 765 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 766 panic("moea64_bootstrap: phys_avail too small"); 767 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 768 phys_avail_count = 0; 769 physsz = 0; 770 hwphyssz = 0; 771 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 772 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 773 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 774 regions[i].mr_start + regions[i].mr_size, 775 regions[i].mr_size); 776 if (hwphyssz != 0 && 777 (physsz + regions[i].mr_size) >= hwphyssz) { 778 if (physsz < hwphyssz) { 779 phys_avail[j] = regions[i].mr_start; 780 phys_avail[j + 1] = regions[i].mr_start + 781 hwphyssz - physsz; 782 physsz = hwphyssz; 783 phys_avail_count++; 784 } 785 break; 786 } 787 phys_avail[j] = regions[i].mr_start; 788 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 789 phys_avail_count++; 790 physsz += regions[i].mr_size; 791 } 792 physmem = btoc(physsz); 793 794 /* 795 * Allocate PTEG table. 796 */ 797#ifdef PTEGCOUNT 798 moea64_pteg_count = PTEGCOUNT; 799#else 800 moea64_pteg_count = 0x1000; 801 802 while (moea64_pteg_count < physmem) 803 moea64_pteg_count <<= 1; 804#endif /* PTEGCOUNT */ 805 806 size = moea64_pteg_count * sizeof(struct lpteg); 807 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes", 808 moea64_pteg_count, size); 809 810 /* 811 * We now need to allocate memory. This memory, to be allocated, 812 * has to reside in a page table. The page table we are about to 813 * allocate. We don't have BAT. So drop to data real mode for a minute 814 * as a measure of last resort. We do this a couple times. 815 */ 816 817 moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size); 818 DISABLE_TRANS(msr); 819 bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg)); 820 ENABLE_TRANS(msr); 821 822 moea64_pteg_mask = moea64_pteg_count - 1; 823 824 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 825 826 /* 827 * Allocate pv/overflow lists. 828 */ 829 size = sizeof(struct pvo_head) * moea64_pteg_count; 830 831 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 832 PAGE_SIZE); 833 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 834 835 DISABLE_TRANS(msr); 836 for (i = 0; i < moea64_pteg_count; i++) 837 LIST_INIT(&moea64_pvo_table[i]); 838 ENABLE_TRANS(msr); 839 840 /* 841 * Initialize the lock that synchronizes access to the pteg and pvo 842 * tables. 843 */ 844 mtx_init(&moea64_table_mutex, "pmap table", NULL, MTX_DEF | 845 MTX_RECURSE); 846 847 /* 848 * Initialize the TLBIE lock. TLBIE can only be executed by one CPU. 849 */ 850 mtx_init(&tlbie_mutex, "tlbie mutex", NULL, MTX_SPIN); 851 852 /* 853 * Initialise the unmanaged pvo pool. 854 */ 855 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 856 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 857 moea64_bpvo_pool_index = 0; 858 859 /* 860 * Make sure kernel vsid is allocated as well as VSID 0. 861 */ 862 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 863 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 864 moea64_vsid_bitmap[0] |= 1; 865 866 /* 867 * Initialize the kernel pmap (which is statically allocated). 868 */ 869 for (i = 0; i < 16; i++) 870 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 871 872 kernel_pmap->pmap_phys = kernel_pmap; 873 kernel_pmap->pm_active = ~0; 874 875 PMAP_LOCK_INIT(kernel_pmap); 876 877 /* 878 * Now map in all the other buffers we allocated earlier 879 */ 880 881 DISABLE_TRANS(msr); 882 size = moea64_pteg_count * sizeof(struct lpteg); 883 off = (vm_offset_t)(moea64_pteg_table); 884 for (pa = off; pa < off + size; pa += PAGE_SIZE) 885 moea64_kenter(mmup, pa, pa); 886 size = sizeof(struct pvo_head) * moea64_pteg_count; 887 off = (vm_offset_t)(moea64_pvo_table); 888 for (pa = off; pa < off + size; pa += PAGE_SIZE) 889 moea64_kenter(mmup, pa, pa); 890 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 891 off = (vm_offset_t)(moea64_bpvo_pool); 892 for (pa = off; pa < off + size; pa += PAGE_SIZE) 893 moea64_kenter(mmup, pa, pa); 894 895 /* 896 * Map certain important things, like ourselves. 897 * 898 * NOTE: We do not map the exception vector space. That code is 899 * used only in real mode, and leaving it unmapped allows us to 900 * catch NULL pointer deferences, instead of making NULL a valid 901 * address. 902 */ 903 904 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; pa += PAGE_SIZE) 905 moea64_kenter(mmup, pa, pa); 906 ENABLE_TRANS(msr); 907 908 if (!ofw_real_mode) { 909 /* 910 * Set up the Open Firmware pmap and add its mappings. 911 */ 912 913 moea64_pinit(mmup, &ofw_pmap); 914 for (i = 0; i < 16; i++) 915 ofw_pmap.pm_sr[i] = kernel_pmap->pm_sr[i]; 916 917 if ((chosen = OF_finddevice("/chosen")) == -1) 918 panic("moea64_bootstrap: can't find /chosen"); 919 OF_getprop(chosen, "mmu", &mmui, 4); 920 if ((mmu = OF_instance_to_package(mmui)) == -1) 921 panic("moea64_bootstrap: can't get mmu package"); 922 if ((sz = OF_getproplen(mmu, "translations")) == -1) 923 panic("moea64_bootstrap: can't get ofw translation count"); 924 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 925 panic("moea64_bootstrap: too many ofw translations"); 926 927 moea64_add_ofw_mappings(mmup, mmu, sz); 928 } 929 930#ifdef SMP 931 TLBSYNC(); 932#endif 933 934 /* 935 * Calculate the last available physical address. 936 */ 937 for (i = 0; phys_avail[i + 2] != 0; i += 2) 938 ; 939 Maxmem = powerpc_btop(phys_avail[i + 1]); 940 941 /* 942 * Initialize MMU and remap early physical mappings 943 */ 944 moea64_bridge_cpu_bootstrap(mmup,0); 945 mtmsr(mfmsr() | PSL_DR | PSL_IR); isync(); 946 pmap_bootstrapped++; 947 bs_remap_earlyboot(); 948 949 /* 950 * Set the start and end of kva. 951 */ 952 virtual_avail = VM_MIN_KERNEL_ADDRESS; 953 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 954 955 /* 956 * Figure out how far we can extend virtual_end into segment 16 957 * without running into existing mappings. Segment 16 is guaranteed 958 * to contain neither RAM nor devices (at least on Apple hardware), 959 * but will generally contain some OFW mappings we should not 960 * step on. 961 */ 962 963 PMAP_LOCK(kernel_pmap); 964 while (moea64_pvo_find_va(kernel_pmap, virtual_end+1, NULL) == NULL) 965 virtual_end += PAGE_SIZE; 966 PMAP_UNLOCK(kernel_pmap); 967 968 /* 969 * Allocate some things for page zeroing. We put this directly 970 * in the page table, marked with LPTE_LOCKED, to avoid any 971 * of the PVO book-keeping or other parts of the VM system 972 * from even knowing that this hack exists. 973 */ 974 975 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, MTX_DEF); 976 for (i = 0; i < 2; i++) { 977 struct lpte pt; 978 uint64_t vsid; 979 int pteidx, ptegidx; 980 981 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 982 virtual_end -= PAGE_SIZE; 983 984 LOCK_TABLE(); 985 986 vsid = va_to_vsid(kernel_pmap, moea64_scratchpage_va[i]); 987 moea64_pte_create(&pt, vsid, moea64_scratchpage_va[i], 988 LPTE_NOEXEC); 989 pt.pte_hi |= LPTE_LOCKED; 990 991 ptegidx = va_to_pteg(vsid, moea64_scratchpage_va[i]); 992 pteidx = moea64_pte_insert(ptegidx, &pt); 993 if (pt.pte_hi & LPTE_HID) 994 ptegidx ^= moea64_pteg_mask; 995 996 moea64_scratchpage_pte[i] = 997 &moea64_pteg_table[ptegidx].pt[pteidx]; 998 999 UNLOCK_TABLE(); 1000 } 1001 1002 /* 1003 * Allocate a kernel stack with a guard page for thread0 and map it 1004 * into the kernel page map. 1005 */ 1006 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 1007 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1008 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 1009 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 1010 thread0.td_kstack = va; 1011 thread0.td_kstack_pages = KSTACK_PAGES; 1012 for (i = 0; i < KSTACK_PAGES; i++) { 1013 moea64_kenter(mmup, va, pa); 1014 pa += PAGE_SIZE; 1015 va += PAGE_SIZE; 1016 } 1017 1018 /* 1019 * Allocate virtual address space for the message buffer. 1020 */ 1021 pa = msgbuf_phys = moea64_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 1022 msgbufp = (struct msgbuf *)virtual_avail; 1023 va = virtual_avail; 1024 virtual_avail += round_page(MSGBUF_SIZE); 1025 while (va < virtual_avail) { 1026 moea64_kenter(mmup, va, pa); 1027 pa += PAGE_SIZE; 1028 va += PAGE_SIZE; 1029 } 1030 1031 /* 1032 * Allocate virtual address space for the dynamic percpu area. 1033 */ 1034 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1035 dpcpu = (void *)virtual_avail; 1036 virtual_avail += DPCPU_SIZE; 1037 while (va < virtual_avail) { 1038 moea64_kenter(mmup, va, pa); 1039 pa += PAGE_SIZE; 1040 va += PAGE_SIZE; 1041 } 1042 dpcpu_init(dpcpu, 0); 1043} 1044 1045/* 1046 * Activate a user pmap. The pmap must be activated before it's address 1047 * space can be accessed in any way. 1048 */ 1049void 1050moea64_activate(mmu_t mmu, struct thread *td) 1051{ 1052 pmap_t pm, pmr; 1053 1054 /* 1055 * Load all the data we need up front to encourage the compiler to 1056 * not issue any loads while we have interrupts disabled below. 1057 */ 1058 pm = &td->td_proc->p_vmspace->vm_pmap; 1059 pmr = pm->pmap_phys; 1060 1061 pm->pm_active |= PCPU_GET(cpumask); 1062 PCPU_SET(curpmap, pmr); 1063} 1064 1065void 1066moea64_deactivate(mmu_t mmu, struct thread *td) 1067{ 1068 pmap_t pm; 1069 1070 pm = &td->td_proc->p_vmspace->vm_pmap; 1071 pm->pm_active &= ~(PCPU_GET(cpumask)); 1072 PCPU_SET(curpmap, NULL); 1073} 1074 1075void 1076moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1077{ 1078 struct pvo_entry *pvo; 1079 1080 PMAP_LOCK(pm); 1081 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1082 1083 if (pvo != NULL) { 1084 if (wired) { 1085 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1086 pm->pm_stats.wired_count++; 1087 pvo->pvo_vaddr |= PVO_WIRED; 1088 } else { 1089 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1090 pm->pm_stats.wired_count--; 1091 pvo->pvo_vaddr &= ~PVO_WIRED; 1092 } 1093 } 1094 PMAP_UNLOCK(pm); 1095} 1096 1097/* 1098 * This goes through and sets the physical address of our 1099 * special scratch PTE to the PA we want to zero or copy. Because 1100 * of locking issues (this can get called in pvo_enter() by 1101 * the UMA allocator), we can't use most other utility functions here 1102 */ 1103 1104static __inline 1105void moea64_set_scratchpage_pa(int which, vm_offset_t pa) { 1106 1107 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1108 1109 moea64_scratchpage_pte[which]->pte_hi &= ~LPTE_VALID; 1110 TLBIE(kernel_pmap, moea64_scratchpage_va[which]); 1111 1112 moea64_scratchpage_pte[which]->pte_lo &= 1113 ~(LPTE_WIMG | LPTE_RPGN); 1114 moea64_scratchpage_pte[which]->pte_lo |= 1115 moea64_calc_wimg(pa) | (uint64_t)pa; 1116 EIEIO(); 1117 1118 moea64_scratchpage_pte[which]->pte_hi |= LPTE_VALID; 1119 PTESYNC(); isync(); 1120} 1121 1122void 1123moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1124{ 1125 vm_offset_t dst; 1126 vm_offset_t src; 1127 1128 dst = VM_PAGE_TO_PHYS(mdst); 1129 src = VM_PAGE_TO_PHYS(msrc); 1130 1131 mtx_lock(&moea64_scratchpage_mtx); 1132 1133 moea64_set_scratchpage_pa(0,src); 1134 moea64_set_scratchpage_pa(1,dst); 1135 1136 kcopy((void *)moea64_scratchpage_va[0], 1137 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1138 1139 mtx_unlock(&moea64_scratchpage_mtx); 1140} 1141 1142void 1143moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1144{ 1145 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1146 1147 if (!moea64_initialized) 1148 panic("moea64_zero_page: can't zero pa %#x", pa); 1149 if (size + off > PAGE_SIZE) 1150 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1151 1152 mtx_lock(&moea64_scratchpage_mtx); 1153 1154 moea64_set_scratchpage_pa(0,pa); 1155 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1156 mtx_unlock(&moea64_scratchpage_mtx); 1157} 1158 1159/* 1160 * Zero a page of physical memory by temporarily mapping it 1161 */ 1162void 1163moea64_zero_page(mmu_t mmu, vm_page_t m) 1164{ 1165 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1166 vm_offset_t off; 1167 1168 if (!moea64_initialized) 1169 panic("moea64_zero_page: can't zero pa %#x", pa); 1170 1171 mtx_lock(&moea64_scratchpage_mtx); 1172 1173 moea64_set_scratchpage_pa(0,pa); 1174 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1175 __asm __volatile("dcbz 0,%0" :: 1176 "r"(moea64_scratchpage_va[0] + off)); 1177 mtx_unlock(&moea64_scratchpage_mtx); 1178} 1179 1180void 1181moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1182{ 1183 1184 moea64_zero_page(mmu, m); 1185} 1186 1187/* 1188 * Map the given physical page at the specified virtual address in the 1189 * target pmap with the protection requested. If specified the page 1190 * will be wired down. 1191 */ 1192void 1193moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1194 vm_prot_t prot, boolean_t wired) 1195{ 1196 1197 vm_page_lock_queues(); 1198 PMAP_LOCK(pmap); 1199 moea64_enter_locked(pmap, va, m, prot, wired); 1200 vm_page_unlock_queues(); 1201 PMAP_UNLOCK(pmap); 1202} 1203 1204/* 1205 * Map the given physical page at the specified virtual address in the 1206 * target pmap with the protection requested. If specified the page 1207 * will be wired down. 1208 * 1209 * The page queues and pmap must be locked. 1210 */ 1211 1212static void 1213moea64_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1214 boolean_t wired) 1215{ 1216 struct pvo_head *pvo_head; 1217 uma_zone_t zone; 1218 vm_page_t pg; 1219 uint64_t pte_lo; 1220 u_int pvo_flags; 1221 int error; 1222 1223 if (!moea64_initialized) { 1224 pvo_head = &moea64_pvo_kunmanaged; 1225 pg = NULL; 1226 zone = moea64_upvo_zone; 1227 pvo_flags = 0; 1228 } else { 1229 pvo_head = vm_page_to_pvoh(m); 1230 pg = m; 1231 zone = moea64_mpvo_zone; 1232 pvo_flags = PVO_MANAGED; 1233 } 1234 1235 if (pmap_bootstrapped) 1236 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1237 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1238 KASSERT((m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1239 ("moea64_enter_locked: page %p is not busy", m)); 1240 1241 /* XXX change the pvo head for fake pages */ 1242 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1243 pvo_flags &= ~PVO_MANAGED; 1244 pvo_head = &moea64_pvo_kunmanaged; 1245 zone = moea64_upvo_zone; 1246 } 1247 1248 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m)); 1249 1250 if (prot & VM_PROT_WRITE) { 1251 pte_lo |= LPTE_BW; 1252 if (pmap_bootstrapped) 1253 vm_page_flag_set(m, PG_WRITEABLE); 1254 } else 1255 pte_lo |= LPTE_BR; 1256 1257 if (prot & VM_PROT_EXECUTE) 1258 pvo_flags |= VM_PROT_EXECUTE; 1259 1260 if (wired) 1261 pvo_flags |= PVO_WIRED; 1262 1263 if ((m->flags & PG_FICTITIOUS) != 0) 1264 pvo_flags |= PVO_FAKE; 1265 1266 error = moea64_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1267 pte_lo, pvo_flags); 1268 1269 /* 1270 * Flush the page from the instruction cache if this page is 1271 * mapped executable and cacheable. 1272 */ 1273 if ((pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1274 moea64_syncicache(pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1275 } 1276} 1277 1278static void 1279moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_size_t sz) 1280{ 1281 1282 /* 1283 * This is much trickier than on older systems because 1284 * we can't sync the icache on physical addresses directly 1285 * without a direct map. Instead we check a couple of cases 1286 * where the memory is already mapped in and, failing that, 1287 * use the same trick we use for page zeroing to create 1288 * a temporary mapping for this physical address. 1289 */ 1290 1291 if (!pmap_bootstrapped) { 1292 /* 1293 * If PMAP is not bootstrapped, we are likely to be 1294 * in real mode. 1295 */ 1296 __syncicache((void *)pa, sz); 1297 } else if (pmap == kernel_pmap) { 1298 __syncicache((void *)va, sz); 1299 } else { 1300 /* Use the scratch page to set up a temp mapping */ 1301 1302 mtx_lock(&moea64_scratchpage_mtx); 1303 1304 moea64_set_scratchpage_pa(1,pa & ~ADDR_POFF); 1305 __syncicache((void *)(moea64_scratchpage_va[1] + 1306 (va & ADDR_POFF)), sz); 1307 1308 mtx_unlock(&moea64_scratchpage_mtx); 1309 } 1310} 1311 1312/* 1313 * Maps a sequence of resident pages belonging to the same object. 1314 * The sequence begins with the given page m_start. This page is 1315 * mapped at the given virtual address start. Each subsequent page is 1316 * mapped at a virtual address that is offset from start by the same 1317 * amount as the page is offset from m_start within the object. The 1318 * last page in the sequence is the page with the largest offset from 1319 * m_start that can be mapped at a virtual address less than the given 1320 * virtual address end. Not every virtual page between start and end 1321 * is mapped; only those for which a resident page exists with the 1322 * corresponding offset from m_start are mapped. 1323 */ 1324void 1325moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1326 vm_page_t m_start, vm_prot_t prot) 1327{ 1328 vm_page_t m; 1329 vm_pindex_t diff, psize; 1330 1331 psize = atop(end - start); 1332 m = m_start; 1333 PMAP_LOCK(pm); 1334 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1335 moea64_enter_locked(pm, start + ptoa(diff), m, prot & 1336 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1337 m = TAILQ_NEXT(m, listq); 1338 } 1339 PMAP_UNLOCK(pm); 1340} 1341 1342void 1343moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1344 vm_prot_t prot) 1345{ 1346 1347 vm_page_lock_queues(); 1348 PMAP_LOCK(pm); 1349 moea64_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1350 FALSE); 1351 vm_page_unlock_queues(); 1352 PMAP_UNLOCK(pm); 1353} 1354 1355vm_paddr_t 1356moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1357{ 1358 struct pvo_entry *pvo; 1359 vm_paddr_t pa; 1360 1361 PMAP_LOCK(pm); 1362 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1363 if (pvo == NULL) 1364 pa = 0; 1365 else 1366 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1367 PMAP_UNLOCK(pm); 1368 return (pa); 1369} 1370 1371/* 1372 * Atomically extract and hold the physical page with the given 1373 * pmap and virtual address pair if that mapping permits the given 1374 * protection. 1375 */ 1376vm_page_t 1377moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1378{ 1379 struct pvo_entry *pvo; 1380 vm_page_t m; 1381 vm_paddr_t pa; 1382 1383 m = NULL; 1384 pa = 0; 1385 PMAP_LOCK(pmap); 1386retry: 1387 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1388 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1389 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1390 (prot & VM_PROT_WRITE) == 0)) { 1391 if (vm_page_pa_tryrelock(pmap, 1392 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1393 goto retry; 1394 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1395 vm_page_hold(m); 1396 } 1397 PA_UNLOCK_COND(pa); 1398 PMAP_UNLOCK(pmap); 1399 return (m); 1400} 1401 1402static void * 1403moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1404{ 1405 /* 1406 * This entire routine is a horrible hack to avoid bothering kmem 1407 * for new KVA addresses. Because this can get called from inside 1408 * kmem allocation routines, calling kmem for a new address here 1409 * can lead to multiply locking non-recursive mutexes. 1410 */ 1411 static vm_pindex_t color; 1412 vm_offset_t va; 1413 1414 vm_page_t m; 1415 int pflags, needed_lock; 1416 1417 *flags = UMA_SLAB_PRIV; 1418 needed_lock = !PMAP_LOCKED(kernel_pmap); 1419 1420 if (needed_lock) 1421 PMAP_LOCK(kernel_pmap); 1422 1423 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1424 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1425 else 1426 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1427 if (wait & M_ZERO) 1428 pflags |= VM_ALLOC_ZERO; 1429 1430 for (;;) { 1431 m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ); 1432 if (m == NULL) { 1433 if (wait & M_NOWAIT) 1434 return (NULL); 1435 VM_WAIT; 1436 } else 1437 break; 1438 } 1439 1440 va = VM_PAGE_TO_PHYS(m); 1441 1442 moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1443 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1444 PVO_WIRED | PVO_BOOTSTRAP); 1445 1446 if (needed_lock) 1447 PMAP_UNLOCK(kernel_pmap); 1448 1449 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1450 bzero((void *)va, PAGE_SIZE); 1451 1452 return (void *)va; 1453} 1454 1455void 1456moea64_init(mmu_t mmu) 1457{ 1458 1459 CTR0(KTR_PMAP, "moea64_init"); 1460 1461 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1462 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1463 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1464 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1465 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1466 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1467 1468 if (!hw_direct_map) { 1469 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1470 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1471 } 1472 1473 moea64_initialized = TRUE; 1474} 1475 1476boolean_t 1477moea64_is_referenced(mmu_t mmu, vm_page_t m) 1478{ 1479 1480 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1481 return (FALSE); 1482 return (moea64_query_bit(m, PTE_REF)); 1483} 1484 1485boolean_t 1486moea64_is_modified(mmu_t mmu, vm_page_t m) 1487{ 1488 boolean_t rv; 1489 1490 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1491 ("moea64_is_modified: page %p is not managed", m)); 1492 1493 /* 1494 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1495 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1496 * is clear, no PTEs can have LPTE_CHG set. 1497 */ 1498 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1499 if ((m->oflags & VPO_BUSY) == 0 && 1500 (m->flags & PG_WRITEABLE) == 0) 1501 return (FALSE); 1502 vm_page_lock_queues(); 1503 rv = moea64_query_bit(m, LPTE_CHG); 1504 vm_page_unlock_queues(); 1505 return (rv); 1506} 1507 1508void 1509moea64_clear_reference(mmu_t mmu, vm_page_t m) 1510{ 1511 1512 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1513 ("moea64_clear_reference: page %p is not managed", m)); 1514 vm_page_lock_queues(); 1515 moea64_clear_bit(m, LPTE_REF, NULL); 1516 vm_page_unlock_queues(); 1517} 1518 1519void 1520moea64_clear_modify(mmu_t mmu, vm_page_t m) 1521{ 1522 1523 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1524 ("moea64_clear_modify: page %p is not managed", m)); 1525 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1526 KASSERT((m->oflags & VPO_BUSY) == 0, 1527 ("moea64_clear_modify: page %p is busy", m)); 1528 1529 /* 1530 * If the page is not PG_WRITEABLE, then no PTEs can have LPTE_CHG 1531 * set. If the object containing the page is locked and the page is 1532 * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1533 */ 1534 if ((m->flags & PG_WRITEABLE) == 0) 1535 return; 1536 vm_page_lock_queues(); 1537 moea64_clear_bit(m, LPTE_CHG, NULL); 1538 vm_page_unlock_queues(); 1539} 1540 1541/* 1542 * Clear the write and modified bits in each of the given page's mappings. 1543 */ 1544void 1545moea64_remove_write(mmu_t mmu, vm_page_t m) 1546{ 1547 struct pvo_entry *pvo; 1548 struct lpte *pt; 1549 pmap_t pmap; 1550 uint64_t lo; 1551 1552 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1553 ("moea64_remove_write: page %p is not managed", m)); 1554 1555 /* 1556 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1557 * another thread while the object is locked. Thus, if PG_WRITEABLE 1558 * is clear, no page table entries need updating. 1559 */ 1560 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1561 if ((m->oflags & VPO_BUSY) == 0 && 1562 (m->flags & PG_WRITEABLE) == 0) 1563 return; 1564 vm_page_lock_queues(); 1565 lo = moea64_attr_fetch(m); 1566 SYNC(); 1567 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1568 pmap = pvo->pvo_pmap; 1569 PMAP_LOCK(pmap); 1570 LOCK_TABLE(); 1571 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1572 pt = moea64_pvo_to_pte(pvo, -1); 1573 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1574 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1575 if (pt != NULL) { 1576 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 1577 lo |= pvo->pvo_pte.lpte.pte_lo; 1578 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1579 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1580 pvo->pvo_pmap, PVO_VADDR(pvo)); 1581 } 1582 } 1583 UNLOCK_TABLE(); 1584 PMAP_UNLOCK(pmap); 1585 } 1586 if ((lo & LPTE_CHG) != 0) { 1587 moea64_attr_clear(m, LPTE_CHG); 1588 vm_page_dirty(m); 1589 } 1590 vm_page_flag_clear(m, PG_WRITEABLE); 1591 vm_page_unlock_queues(); 1592} 1593 1594/* 1595 * moea64_ts_referenced: 1596 * 1597 * Return a count of reference bits for a page, clearing those bits. 1598 * It is not necessary for every reference bit to be cleared, but it 1599 * is necessary that 0 only be returned when there are truly no 1600 * reference bits set. 1601 * 1602 * XXX: The exact number of bits to check and clear is a matter that 1603 * should be tested and standardized at some point in the future for 1604 * optimal aging of shared pages. 1605 */ 1606boolean_t 1607moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1608{ 1609 int count; 1610 1611 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1612 return (0); 1613 1614 count = moea64_clear_bit(m, LPTE_REF, NULL); 1615 1616 return (count); 1617} 1618 1619/* 1620 * Map a wired page into kernel virtual address space. 1621 */ 1622void 1623moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1624{ 1625 uint64_t pte_lo; 1626 int error; 1627 1628#if 0 1629 if (!pmap_bootstrapped) { 1630 if (va >= VM_MIN_KERNEL_ADDRESS && va < virtual_end) 1631 panic("Trying to enter an address in KVA -- %#x!\n",pa); 1632 } 1633#endif 1634 1635 pte_lo = moea64_calc_wimg(pa); 1636 1637 PMAP_LOCK(kernel_pmap); 1638 error = moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1639 &moea64_pvo_kunmanaged, va, pa, pte_lo, 1640 PVO_WIRED | VM_PROT_EXECUTE); 1641 1642 if (error != 0 && error != ENOENT) 1643 panic("moea64_kenter: failed to enter va %#x pa %#x: %d", va, 1644 pa, error); 1645 1646 /* 1647 * Flush the memory from the instruction cache. 1648 */ 1649 if ((pte_lo & (LPTE_I | LPTE_G)) == 0) { 1650 __syncicache((void *)va, PAGE_SIZE); 1651 } 1652 PMAP_UNLOCK(kernel_pmap); 1653} 1654 1655/* 1656 * Extract the physical page address associated with the given kernel virtual 1657 * address. 1658 */ 1659vm_offset_t 1660moea64_kextract(mmu_t mmu, vm_offset_t va) 1661{ 1662 struct pvo_entry *pvo; 1663 vm_paddr_t pa; 1664 1665 /* 1666 * Shortcut the direct-mapped case when applicable. We never put 1667 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1668 */ 1669 if (va < VM_MIN_KERNEL_ADDRESS) 1670 return (va); 1671 1672 PMAP_LOCK(kernel_pmap); 1673 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1674 KASSERT(pvo != NULL, ("moea64_kextract: no addr found")); 1675 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1676 PMAP_UNLOCK(kernel_pmap); 1677 return (pa); 1678} 1679 1680/* 1681 * Remove a wired page from kernel virtual address space. 1682 */ 1683void 1684moea64_kremove(mmu_t mmu, vm_offset_t va) 1685{ 1686 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1687} 1688 1689/* 1690 * Map a range of physical addresses into kernel virtual address space. 1691 * 1692 * The value passed in *virt is a suggested virtual address for the mapping. 1693 * Architectures which can support a direct-mapped physical to virtual region 1694 * can return the appropriate address within that region, leaving '*virt' 1695 * unchanged. We cannot and therefore do not; *virt is updated with the 1696 * first usable address after the mapped region. 1697 */ 1698vm_offset_t 1699moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1700 vm_offset_t pa_end, int prot) 1701{ 1702 vm_offset_t sva, va; 1703 1704 sva = *virt; 1705 va = sva; 1706 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1707 moea64_kenter(mmu, va, pa_start); 1708 *virt = va; 1709 1710 return (sva); 1711} 1712 1713/* 1714 * Returns true if the pmap's pv is one of the first 1715 * 16 pvs linked to from this page. This count may 1716 * be changed upwards or downwards in the future; it 1717 * is only necessary that true be returned for a small 1718 * subset of pmaps for proper page aging. 1719 */ 1720boolean_t 1721moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1722{ 1723 int loops; 1724 struct pvo_entry *pvo; 1725 1726 if (!moea64_initialized || (m->flags & PG_FICTITIOUS)) 1727 return FALSE; 1728 1729 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1730 1731 loops = 0; 1732 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1733 if (pvo->pvo_pmap == pmap) 1734 return (TRUE); 1735 if (++loops >= 16) 1736 break; 1737 } 1738 1739 return (FALSE); 1740} 1741 1742/* 1743 * Return the number of managed mappings to the given physical page 1744 * that are wired. 1745 */ 1746int 1747moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1748{ 1749 struct pvo_entry *pvo; 1750 int count; 1751 1752 count = 0; 1753 if (!moea64_initialized || (m->flags & PG_FICTITIOUS) != 0) 1754 return (count); 1755 vm_page_lock_queues(); 1756 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1757 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1758 count++; 1759 vm_page_unlock_queues(); 1760 return (count); 1761} 1762 1763static u_int moea64_vsidcontext; 1764 1765void 1766moea64_pinit(mmu_t mmu, pmap_t pmap) 1767{ 1768 int i, mask; 1769 u_int entropy; 1770 1771 PMAP_LOCK_INIT(pmap); 1772 1773 entropy = 0; 1774 __asm __volatile("mftb %0" : "=r"(entropy)); 1775 1776 if (pmap_bootstrapped) 1777 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, (vm_offset_t)pmap); 1778 else 1779 pmap->pmap_phys = pmap; 1780 1781 /* 1782 * Allocate some segment registers for this pmap. 1783 */ 1784 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1785 u_int hash, n; 1786 1787 /* 1788 * Create a new value by mutiplying by a prime and adding in 1789 * entropy from the timebase register. This is to make the 1790 * VSID more random so that the PT hash function collides 1791 * less often. (Note that the prime casues gcc to do shifts 1792 * instead of a multiply.) 1793 */ 1794 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1795 hash = moea64_vsidcontext & (NPMAPS - 1); 1796 if (hash == 0) /* 0 is special, avoid it */ 1797 continue; 1798 n = hash >> 5; 1799 mask = 1 << (hash & (VSID_NBPW - 1)); 1800 hash = (moea64_vsidcontext & 0xfffff); 1801 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1802 /* anything free in this bucket? */ 1803 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1804 entropy = (moea64_vsidcontext >> 20); 1805 continue; 1806 } 1807 i = ffs(~moea64_vsid_bitmap[i]) - 1; 1808 mask = 1 << i; 1809 hash &= 0xfffff & ~(VSID_NBPW - 1); 1810 hash |= i; 1811 } 1812 moea64_vsid_bitmap[n] |= mask; 1813 for (i = 0; i < 16; i++) { 1814 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1815 } 1816 return; 1817 } 1818 1819 panic("moea64_pinit: out of segments"); 1820} 1821 1822/* 1823 * Initialize the pmap associated with process 0. 1824 */ 1825void 1826moea64_pinit0(mmu_t mmu, pmap_t pm) 1827{ 1828 moea64_pinit(mmu, pm); 1829 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1830} 1831 1832/* 1833 * Set the physical protection on the specified range of this map as requested. 1834 */ 1835void 1836moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1837 vm_prot_t prot) 1838{ 1839 struct pvo_entry *pvo; 1840 struct lpte *pt; 1841 int pteidx; 1842 1843 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1844 eva, prot); 1845 1846 1847 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1848 ("moea64_protect: non current pmap")); 1849 1850 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1851 moea64_remove(mmu, pm, sva, eva); 1852 return; 1853 } 1854 1855 vm_page_lock_queues(); 1856 PMAP_LOCK(pm); 1857 for (; sva < eva; sva += PAGE_SIZE) { 1858 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1859 if (pvo == NULL) 1860 continue; 1861 1862 /* 1863 * Grab the PTE pointer before we diddle with the cached PTE 1864 * copy. 1865 */ 1866 LOCK_TABLE(); 1867 pt = moea64_pvo_to_pte(pvo, pteidx); 1868 1869 /* 1870 * Change the protection of the page. 1871 */ 1872 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1873 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1874 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1875 if ((prot & VM_PROT_EXECUTE) == 0) 1876 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1877 1878 /* 1879 * If the PVO is in the page table, update that pte as well. 1880 */ 1881 if (pt != NULL) { 1882 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1883 pvo->pvo_pmap, PVO_VADDR(pvo)); 1884 if ((pvo->pvo_pte.lpte.pte_lo & 1885 (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1886 moea64_syncicache(pm, sva, 1887 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, 1888 PAGE_SIZE); 1889 } 1890 } 1891 UNLOCK_TABLE(); 1892 } 1893 vm_page_unlock_queues(); 1894 PMAP_UNLOCK(pm); 1895} 1896 1897/* 1898 * Map a list of wired pages into kernel virtual address space. This is 1899 * intended for temporary mappings which do not need page modification or 1900 * references recorded. Existing mappings in the region are overwritten. 1901 */ 1902void 1903moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 1904{ 1905 while (count-- > 0) { 1906 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1907 va += PAGE_SIZE; 1908 m++; 1909 } 1910} 1911 1912/* 1913 * Remove page mappings from kernel virtual address space. Intended for 1914 * temporary mappings entered by moea64_qenter. 1915 */ 1916void 1917moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 1918{ 1919 while (count-- > 0) { 1920 moea64_kremove(mmu, va); 1921 va += PAGE_SIZE; 1922 } 1923} 1924 1925void 1926moea64_release(mmu_t mmu, pmap_t pmap) 1927{ 1928 int idx, mask; 1929 1930 /* 1931 * Free segment register's VSID 1932 */ 1933 if (pmap->pm_sr[0] == 0) 1934 panic("moea64_release"); 1935 1936 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1937 mask = 1 << (idx % VSID_NBPW); 1938 idx /= VSID_NBPW; 1939 moea64_vsid_bitmap[idx] &= ~mask; 1940 PMAP_LOCK_DESTROY(pmap); 1941} 1942 1943/* 1944 * Remove the given range of addresses from the specified map. 1945 */ 1946void 1947moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1948{ 1949 struct pvo_entry *pvo; 1950 int pteidx; 1951 1952 vm_page_lock_queues(); 1953 PMAP_LOCK(pm); 1954 for (; sva < eva; sva += PAGE_SIZE) { 1955 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1956 if (pvo != NULL) { 1957 moea64_pvo_remove(pvo, pteidx); 1958 } 1959 } 1960 vm_page_unlock_queues(); 1961 PMAP_UNLOCK(pm); 1962} 1963 1964/* 1965 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 1966 * will reflect changes in pte's back to the vm_page. 1967 */ 1968void 1969moea64_remove_all(mmu_t mmu, vm_page_t m) 1970{ 1971 struct pvo_head *pvo_head; 1972 struct pvo_entry *pvo, *next_pvo; 1973 pmap_t pmap; 1974 1975 vm_page_lock_queues(); 1976 pvo_head = vm_page_to_pvoh(m); 1977 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1978 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1979 1980 MOEA_PVO_CHECK(pvo); /* sanity check */ 1981 pmap = pvo->pvo_pmap; 1982 PMAP_LOCK(pmap); 1983 moea64_pvo_remove(pvo, -1); 1984 PMAP_UNLOCK(pmap); 1985 } 1986 if ((m->flags & PG_WRITEABLE) && moea64_is_modified(mmu, m)) { 1987 moea64_attr_clear(m, LPTE_CHG); 1988 vm_page_dirty(m); 1989 } 1990 vm_page_flag_clear(m, PG_WRITEABLE); 1991 vm_page_unlock_queues(); 1992} 1993 1994/* 1995 * Allocate a physical page of memory directly from the phys_avail map. 1996 * Can only be called from moea64_bootstrap before avail start and end are 1997 * calculated. 1998 */ 1999static vm_offset_t 2000moea64_bootstrap_alloc(vm_size_t size, u_int align) 2001{ 2002 vm_offset_t s, e; 2003 int i, j; 2004 2005 size = round_page(size); 2006 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2007 if (align != 0) 2008 s = (phys_avail[i] + align - 1) & ~(align - 1); 2009 else 2010 s = phys_avail[i]; 2011 e = s + size; 2012 2013 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2014 continue; 2015 2016 if (s == phys_avail[i]) { 2017 phys_avail[i] += size; 2018 } else if (e == phys_avail[i + 1]) { 2019 phys_avail[i + 1] -= size; 2020 } else { 2021 for (j = phys_avail_count * 2; j > i; j -= 2) { 2022 phys_avail[j] = phys_avail[j - 2]; 2023 phys_avail[j + 1] = phys_avail[j - 1]; 2024 } 2025 2026 phys_avail[i + 3] = phys_avail[i + 1]; 2027 phys_avail[i + 1] = s; 2028 phys_avail[i + 2] = e; 2029 phys_avail_count++; 2030 } 2031 2032 return (s); 2033 } 2034 panic("moea64_bootstrap_alloc: could not allocate memory"); 2035} 2036 2037static void 2038tlbia(void) 2039{ 2040 vm_offset_t i; 2041 register_t msr, scratch; 2042 2043 for (i = 0; i < 0xFF000; i += 0x00001000) { 2044 __asm __volatile("\ 2045 mfmsr %0; \ 2046 mr %1, %0; \ 2047 insrdi %1,%3,1,0; \ 2048 mtmsrd %1; \ 2049 ptesync; \ 2050 \ 2051 tlbiel %2; \ 2052 \ 2053 mtmsrd %0; \ 2054 eieio; \ 2055 tlbsync; \ 2056 ptesync;" 2057 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 2058 } 2059} 2060 2061static int 2062moea64_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 2063 vm_offset_t va, vm_offset_t pa, uint64_t pte_lo, int flags) 2064{ 2065 struct pvo_entry *pvo; 2066 uint64_t vsid; 2067 int first; 2068 u_int ptegidx; 2069 int i; 2070 int bootstrap; 2071 2072 /* 2073 * One nasty thing that can happen here is that the UMA calls to 2074 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2075 * which calls UMA... 2076 * 2077 * We break the loop by detecting recursion and allocating out of 2078 * the bootstrap pool. 2079 */ 2080 2081 moea64_pvo_enter_calls++; 2082 first = 0; 2083 bootstrap = (flags & PVO_BOOTSTRAP); 2084 2085 if (!moea64_initialized) 2086 bootstrap = 1; 2087 2088 /* 2089 * Compute the PTE Group index. 2090 */ 2091 va &= ~ADDR_POFF; 2092 vsid = va_to_vsid(pm, va); 2093 ptegidx = va_to_pteg(vsid, va); 2094 2095 /* 2096 * Remove any existing mapping for this page. Reuse the pvo entry if 2097 * there is a mapping. 2098 */ 2099 LOCK_TABLE(); 2100 2101 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2102 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2103 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2104 (pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == 2105 (pte_lo & LPTE_PP)) { 2106 UNLOCK_TABLE(); 2107 return (0); 2108 } 2109 moea64_pvo_remove(pvo, -1); 2110 break; 2111 } 2112 } 2113 2114 /* 2115 * If we aren't overwriting a mapping, try to allocate. 2116 */ 2117 if (bootstrap) { 2118 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2119 panic("moea64_enter: bpvo pool exhausted, %d, %d, %d", 2120 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2121 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2122 } 2123 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2124 moea64_bpvo_pool_index++; 2125 bootstrap = 1; 2126 } else { 2127 /* 2128 * Note: drop the table lock around the UMA allocation in 2129 * case the UMA allocator needs to manipulate the page 2130 * table. The mapping we are working with is already 2131 * protected by the PMAP lock. 2132 */ 2133 UNLOCK_TABLE(); 2134 pvo = uma_zalloc(zone, M_NOWAIT); 2135 LOCK_TABLE(); 2136 } 2137 2138 if (pvo == NULL) { 2139 UNLOCK_TABLE(); 2140 return (ENOMEM); 2141 } 2142 2143 moea64_pvo_entries++; 2144 pvo->pvo_vaddr = va; 2145 pvo->pvo_pmap = pm; 2146 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2147 pvo->pvo_vaddr &= ~ADDR_POFF; 2148 2149 if (!(flags & VM_PROT_EXECUTE)) 2150 pte_lo |= LPTE_NOEXEC; 2151 if (flags & PVO_WIRED) 2152 pvo->pvo_vaddr |= PVO_WIRED; 2153 if (pvo_head != &moea64_pvo_kunmanaged) 2154 pvo->pvo_vaddr |= PVO_MANAGED; 2155 if (bootstrap) 2156 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2157 if (flags & PVO_FAKE) 2158 pvo->pvo_vaddr |= PVO_FAKE; 2159 2160 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2161 (uint64_t)(pa) | pte_lo); 2162 2163 /* 2164 * Remember if the list was empty and therefore will be the first 2165 * item. 2166 */ 2167 if (LIST_FIRST(pvo_head) == NULL) 2168 first = 1; 2169 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2170 2171 if (pvo->pvo_vaddr & PVO_WIRED) 2172 pm->pm_stats.wired_count++; 2173 pm->pm_stats.resident_count++; 2174 2175 /* 2176 * We hope this succeeds but it isn't required. 2177 */ 2178 i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte); 2179 if (i >= 0) { 2180 PVO_PTEGIDX_SET(pvo, i); 2181 } else { 2182 panic("moea64_pvo_enter: overflow"); 2183 moea64_pte_overflow++; 2184 } 2185 2186 if (pm == kernel_pmap) 2187 isync(); 2188 2189 UNLOCK_TABLE(); 2190 2191 return (first ? ENOENT : 0); 2192} 2193 2194static void 2195moea64_pvo_remove(struct pvo_entry *pvo, int pteidx) 2196{ 2197 struct lpte *pt; 2198 2199 /* 2200 * If there is an active pte entry, we need to deactivate it (and 2201 * save the ref & cfg bits). 2202 */ 2203 LOCK_TABLE(); 2204 pt = moea64_pvo_to_pte(pvo, pteidx); 2205 if (pt != NULL) { 2206 moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_pmap, 2207 PVO_VADDR(pvo)); 2208 PVO_PTEGIDX_CLR(pvo); 2209 } else { 2210 moea64_pte_overflow--; 2211 } 2212 2213 /* 2214 * Update our statistics. 2215 */ 2216 pvo->pvo_pmap->pm_stats.resident_count--; 2217 if (pvo->pvo_vaddr & PVO_WIRED) 2218 pvo->pvo_pmap->pm_stats.wired_count--; 2219 2220 /* 2221 * Save the REF/CHG bits into their cache if the page is managed. 2222 */ 2223 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2224 struct vm_page *pg; 2225 2226 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2227 if (pg != NULL) { 2228 moea64_attr_save(pg, pvo->pvo_pte.lpte.pte_lo & 2229 (LPTE_REF | LPTE_CHG)); 2230 } 2231 } 2232 2233 /* 2234 * Remove this PVO from the PV list. 2235 */ 2236 LIST_REMOVE(pvo, pvo_vlink); 2237 2238 /* 2239 * Remove this from the overflow list and return it to the pool 2240 * if we aren't going to reuse it. 2241 */ 2242 LIST_REMOVE(pvo, pvo_olink); 2243 UNLOCK_TABLE(); 2244 2245 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2246 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2247 moea64_upvo_zone, pvo); 2248 2249 moea64_pvo_entries--; 2250 moea64_pvo_remove_calls++; 2251} 2252 2253static __inline int 2254moea64_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2255{ 2256 2257 /* 2258 * We can find the actual pte entry without searching by grabbing 2259 * the PTEG index from 3 unused bits in pvo_vaddr and by 2260 * noticing the HID bit. 2261 */ 2262 if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID) 2263 ptegidx ^= moea64_pteg_mask; 2264 2265 return ((ptegidx << 3) | PVO_PTEGIDX_GET(pvo)); 2266} 2267 2268static struct pvo_entry * 2269moea64_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2270{ 2271 struct pvo_entry *pvo; 2272 int ptegidx; 2273 uint64_t vsid; 2274 2275 va &= ~ADDR_POFF; 2276 vsid = va_to_vsid(pm, va); 2277 ptegidx = va_to_pteg(vsid, va); 2278 2279 LOCK_TABLE(); 2280 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2281 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2282 if (pteidx_p) 2283 *pteidx_p = moea64_pvo_pte_index(pvo, ptegidx); 2284 break; 2285 } 2286 } 2287 UNLOCK_TABLE(); 2288 2289 return (pvo); 2290} 2291 2292static struct lpte * 2293moea64_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2294{ 2295 struct lpte *pt; 2296 2297 /* 2298 * If we haven't been supplied the ptegidx, calculate it. 2299 */ 2300 if (pteidx == -1) { 2301 int ptegidx; 2302 uint64_t vsid; 2303 2304 vsid = va_to_vsid(pvo->pvo_pmap, PVO_VADDR(pvo)); 2305 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo)); 2306 pteidx = moea64_pvo_pte_index(pvo, ptegidx); 2307 } 2308 2309 pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2310 2311 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 2312 !PVO_PTEGIDX_ISSET(pvo)) { 2313 panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no " 2314 "valid pte index", pvo); 2315 } 2316 2317 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 && 2318 PVO_PTEGIDX_ISSET(pvo)) { 2319 panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo " 2320 "pvo but no valid pte", pvo); 2321 } 2322 2323 if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) == 2324 LPTE_VALID) { 2325 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) { 2326 panic("moea64_pvo_to_pte: pvo %p has valid pte in " 2327 "moea64_pteg_table %p but invalid in pvo", pvo, pt); 2328 } 2329 2330 if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & 2331 ~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) { 2332 panic("moea64_pvo_to_pte: pvo %p pte does not match " 2333 "pte %p in moea64_pteg_table difference is %#x", 2334 pvo, pt, 2335 (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo)); 2336 } 2337 2338 ASSERT_TABLE_LOCK(); 2339 return (pt); 2340 } 2341 2342 if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) { 2343 panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in " 2344 "moea64_pteg_table but valid in pvo", pvo, pt); 2345 } 2346 2347 return (NULL); 2348} 2349 2350static int 2351moea64_pte_insert(u_int ptegidx, struct lpte *pvo_pt) 2352{ 2353 struct lpte *pt; 2354 int i; 2355 2356 ASSERT_TABLE_LOCK(); 2357 2358 /* 2359 * First try primary hash. 2360 */ 2361 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2362 if ((pt->pte_hi & LPTE_VALID) == 0 && 2363 (pt->pte_hi & LPTE_LOCKED) == 0) { 2364 pvo_pt->pte_hi &= ~LPTE_HID; 2365 moea64_pte_set(pt, pvo_pt); 2366 return (i); 2367 } 2368 } 2369 2370 /* 2371 * Now try secondary hash. 2372 */ 2373 ptegidx ^= moea64_pteg_mask; 2374 2375 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2376 if ((pt->pte_hi & LPTE_VALID) == 0 && 2377 (pt->pte_hi & LPTE_LOCKED) == 0) { 2378 pvo_pt->pte_hi |= LPTE_HID; 2379 moea64_pte_set(pt, pvo_pt); 2380 return (i); 2381 } 2382 } 2383 2384 panic("moea64_pte_insert: overflow"); 2385 return (-1); 2386} 2387 2388static boolean_t 2389moea64_query_bit(vm_page_t m, u_int64_t ptebit) 2390{ 2391 struct pvo_entry *pvo; 2392 struct lpte *pt; 2393 2394 if (moea64_attr_fetch(m) & ptebit) 2395 return (TRUE); 2396 2397 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2398 2399 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2400 MOEA_PVO_CHECK(pvo); /* sanity check */ 2401 2402 /* 2403 * See if we saved the bit off. If so, cache it and return 2404 * success. 2405 */ 2406 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2407 moea64_attr_save(m, ptebit); 2408 MOEA_PVO_CHECK(pvo); /* sanity check */ 2409 return (TRUE); 2410 } 2411 } 2412 2413 /* 2414 * No luck, now go through the hard part of looking at the PTEs 2415 * themselves. Sync so that any pending REF/CHG bits are flushed to 2416 * the PTEs. 2417 */ 2418 SYNC(); 2419 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2420 MOEA_PVO_CHECK(pvo); /* sanity check */ 2421 2422 /* 2423 * See if this pvo has a valid PTE. if so, fetch the 2424 * REF/CHG bits from the valid PTE. If the appropriate 2425 * ptebit is set, cache it and return success. 2426 */ 2427 LOCK_TABLE(); 2428 pt = moea64_pvo_to_pte(pvo, -1); 2429 if (pt != NULL) { 2430 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2431 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2432 UNLOCK_TABLE(); 2433 2434 moea64_attr_save(m, ptebit); 2435 MOEA_PVO_CHECK(pvo); /* sanity check */ 2436 return (TRUE); 2437 } 2438 } 2439 UNLOCK_TABLE(); 2440 } 2441 2442 return (FALSE); 2443} 2444 2445static u_int 2446moea64_clear_bit(vm_page_t m, u_int64_t ptebit, u_int64_t *origbit) 2447{ 2448 u_int count; 2449 struct pvo_entry *pvo; 2450 struct lpte *pt; 2451 uint64_t rv; 2452 2453 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2454 2455 /* 2456 * Clear the cached value. 2457 */ 2458 rv = moea64_attr_fetch(m); 2459 moea64_attr_clear(m, ptebit); 2460 2461 /* 2462 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2463 * we can reset the right ones). note that since the pvo entries and 2464 * list heads are accessed via BAT0 and are never placed in the page 2465 * table, we don't have to worry about further accesses setting the 2466 * REF/CHG bits. 2467 */ 2468 SYNC(); 2469 2470 /* 2471 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2472 * valid pte clear the ptebit from the valid pte. 2473 */ 2474 count = 0; 2475 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2476 MOEA_PVO_CHECK(pvo); /* sanity check */ 2477 2478 LOCK_TABLE(); 2479 pt = moea64_pvo_to_pte(pvo, -1); 2480 if (pt != NULL) { 2481 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2482 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2483 count++; 2484 moea64_pte_clear(pt, pvo->pvo_pmap, PVO_VADDR(pvo), ptebit); 2485 } 2486 } 2487 rv |= pvo->pvo_pte.lpte.pte_lo; 2488 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2489 MOEA_PVO_CHECK(pvo); /* sanity check */ 2490 UNLOCK_TABLE(); 2491 } 2492 2493 if (origbit != NULL) { 2494 *origbit = rv; 2495 } 2496 2497 return (count); 2498} 2499 2500boolean_t 2501moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2502{ 2503 struct pvo_entry *pvo; 2504 vm_offset_t ppa; 2505 int error = 0; 2506 2507 PMAP_LOCK(kernel_pmap); 2508 for (ppa = pa & ~ADDR_POFF; ppa < pa + size; ppa += PAGE_SIZE) { 2509 pvo = moea64_pvo_find_va(kernel_pmap, ppa, NULL); 2510 if (pvo == NULL || 2511 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2512 error = EFAULT; 2513 break; 2514 } 2515 } 2516 PMAP_UNLOCK(kernel_pmap); 2517 2518 return (error); 2519} 2520 2521/* 2522 * Map a set of physical memory pages into the kernel virtual 2523 * address space. Return a pointer to where it is mapped. This 2524 * routine is intended to be used for mapping device memory, 2525 * NOT real memory. 2526 */ 2527void * 2528moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2529{ 2530 vm_offset_t va, tmpva, ppa, offset; 2531 2532 ppa = trunc_page(pa); 2533 offset = pa & PAGE_MASK; 2534 size = roundup(offset + size, PAGE_SIZE); 2535 2536 va = kmem_alloc_nofault(kernel_map, size); 2537 2538 if (!va) 2539 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2540 2541 for (tmpva = va; size > 0;) { 2542 moea64_kenter(mmu, tmpva, ppa); 2543 size -= PAGE_SIZE; 2544 tmpva += PAGE_SIZE; 2545 ppa += PAGE_SIZE; 2546 } 2547 2548 return ((void *)(va + offset)); 2549} 2550 2551void 2552moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2553{ 2554 vm_offset_t base, offset; 2555 2556 base = trunc_page(va); 2557 offset = va & PAGE_MASK; 2558 size = roundup(offset + size, PAGE_SIZE); 2559 2560 kmem_free(kernel_map, base, size); 2561} 2562 2563static void 2564moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2565{ 2566 struct pvo_entry *pvo; 2567 vm_offset_t lim; 2568 vm_paddr_t pa; 2569 vm_size_t len; 2570 2571 PMAP_LOCK(pm); 2572 while (sz > 0) { 2573 lim = round_page(va); 2574 len = MIN(lim - va, sz); 2575 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2576 if (pvo != NULL) { 2577 pa = (pvo->pvo_pte.pte.pte_lo & LPTE_RPGN) | 2578 (va & ADDR_POFF); 2579 moea64_syncicache(pm, va, pa, len); 2580 } 2581 va += len; 2582 sz -= len; 2583 } 2584 PMAP_UNLOCK(pm); 2585} 2586