1/*- 2 * Copyright (c) 2003-2012 Broadcom Corporation 3 * All Rights Reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD$"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/types.h> 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/malloc.h> 38#include <sys/bus.h> 39#include <sys/endian.h> 40#include <sys/rman.h> 41#include <sys/pciio.h> 42 43#include <vm/vm.h> 44#include <vm/vm_param.h> 45#include <vm/pmap.h> 46 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include <dev/pci/pci_private.h> 50 51#include <dev/uart/uart.h> 52#include <dev/uart/uart_bus.h> 53#include <dev/uart/uart_cpu.h> 54 55#include <machine/bus.h> 56#include <machine/md_var.h> 57#include <machine/intr_machdep.h> 58#include <machine/cpuregs.h> 59 60#include <mips/nlm/hal/haldefs.h> 61#include <mips/nlm/interrupt.h> 62#include <mips/nlm/hal/iomap.h> 63#include <mips/nlm/hal/mips-extns.h> 64#include <mips/nlm/hal/pic.h> 65#include <mips/nlm/hal/bridge.h> 66#include <mips/nlm/hal/gbu.h> 67#include <mips/nlm/hal/pcibus.h> 68#include <mips/nlm/hal/uart.h> 69#include <mips/nlm/xlp.h> 70 71#include "pcib_if.h" 72#include "pci_if.h" 73 74#define EMUL_MEM_START 0x16000000UL 75#define EMUL_MEM_END 0x18ffffffUL 76 77/* SoC device qurik handling */ 78static int irt_irq_map[4 * 256]; 79static int irq_irt_map[64]; 80 81static void 82xlp_add_irq(int node, int irt, int irq) 83{ 84 int nodeirt = node * 256 + irt; 85 86 irt_irq_map[nodeirt] = irq; 87 irq_irt_map[irq] = nodeirt; 88} 89 90int 91xlp_irq_to_irt(int irq) 92{ 93 return irq_irt_map[irq]; 94} 95 96int 97xlp_irt_to_irq(int nodeirt) 98{ 99 return irt_irq_map[nodeirt]; 100} 101 102/* Override PCI a bit for SoC devices */ 103 104enum { 105 INTERNAL_DEV = 0x1, /* internal device, skip on enumeration */ 106 MEM_RES_EMUL = 0x2, /* no MEM or IO bar, custom res alloc */ 107 SHARED_IRQ = 0x4, 108 DEV_MMIO32 = 0x8, /* byte access not allowed to mmio */ 109}; 110 111struct soc_dev_desc { 112 u_int devid; /* device ID */ 113 int irqbase; /* start IRQ */ 114 u_int flags; /* flags */ 115 int ndevs; /* to keep track of number of devices */ 116}; 117 118struct soc_dev_desc xlp_dev_desc[] = { 119 { PCI_DEVICE_ID_NLM_ICI, 0, INTERNAL_DEV }, 120 { PCI_DEVICE_ID_NLM_PIC, 0, INTERNAL_DEV }, 121 { PCI_DEVICE_ID_NLM_FMN, 0, INTERNAL_DEV }, 122 { PCI_DEVICE_ID_NLM_UART, PIC_UART_0_IRQ, MEM_RES_EMUL | DEV_MMIO32}, 123 { PCI_DEVICE_ID_NLM_I2C, 0, MEM_RES_EMUL | DEV_MMIO32 }, 124 { PCI_DEVICE_ID_NLM_NOR, 0, MEM_RES_EMUL }, 125 { PCI_DEVICE_ID_NLM_MMC, PIC_MMC_IRQ, MEM_RES_EMUL }, 126 { PCI_DEVICE_ID_NLM_EHCI, PIC_EHCI_0_IRQ, 0 } 127}; 128 129struct xlp_devinfo { 130 struct pci_devinfo pcidev; 131 int irq; 132 int flags; 133 u_long mem_res_start; 134}; 135 136static __inline struct soc_dev_desc * 137xlp_find_soc_desc(int devid) 138{ 139 struct soc_dev_desc *p; 140 int i, n; 141 142 n = sizeof(xlp_dev_desc) / sizeof(xlp_dev_desc[0]); 143 for (i = 0, p = xlp_dev_desc; i < n; i++, p++) 144 if (p->devid == devid) 145 return (p); 146 return (NULL); 147} 148 149static struct resource * 150xlp_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 151 u_long start, u_long end, u_long count, u_int flags) 152{ 153 struct resource *r; 154 struct xlp_devinfo *xlp_devinfo; 155 int busno; 156 157 /* 158 * Do custom allocation for MEMORY resource for SoC device if 159 * MEM_RES_EMUL flag is set 160 */ 161 busno = pci_get_bus(child); 162 if ((type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) && busno == 0) { 163 xlp_devinfo = (struct xlp_devinfo *)device_get_ivars(child); 164 if ((xlp_devinfo->flags & MEM_RES_EMUL) != 0) { 165 /* no emulation for IO ports */ 166 if (type == SYS_RES_IOPORT) 167 return (NULL); 168 169 start = xlp_devinfo->mem_res_start; 170 count = XLP_PCIE_CFG_SIZE - XLP_IO_PCI_HDRSZ; 171 172 /* MMC needs to 2 slots with rids 16 and 20 and a 173 * fixup for size */ 174 if (pci_get_device(child) == PCI_DEVICE_ID_NLM_MMC) { 175 count = 0x100; 176 if (*rid == 16) 177 ; /* first slot already setup */ 178 else if (*rid == 20) 179 start += 0x100; /* second slot */ 180 else 181 return (NULL); 182 } 183 184 end = start + count - 1; 185 r = BUS_ALLOC_RESOURCE(device_get_parent(bus), child, 186 type, rid, start, end, count, flags); 187 if (r == NULL) 188 return (NULL); 189 if ((xlp_devinfo->flags & DEV_MMIO32) != 0) 190 rman_set_bustag(r, rmi_uart_bus_space); 191 return (r); 192 } 193 } 194 195 /* Not custom alloc, use PCI code */ 196 return (pci_alloc_resource(bus, child, type, rid, start, end, count, 197 flags)); 198} 199 200static int 201xlp_pci_release_resource(device_t bus, device_t child, int type, int rid, 202 struct resource *r) 203{ 204 u_long start; 205 206 /* If custom alloc, handle that */ 207 start = rman_get_start(r); 208 if (type == SYS_RES_MEMORY && pci_get_bus(child) == 0 && 209 start >= EMUL_MEM_START && start <= EMUL_MEM_END) 210 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 211 type, rid, r)); 212 213 /* use default PCI function */ 214 return (bus_generic_rl_release_resource(bus, child, type, rid, r)); 215} 216 217static void 218xlp_add_soc_child(device_t pcib, device_t dev, int b, int s, int f) 219{ 220 struct pci_devinfo *dinfo; 221 struct xlp_devinfo *xlp_dinfo; 222 struct soc_dev_desc *si; 223 uint64_t pcibase; 224 int domain, node, irt, irq, flags, devoffset, num; 225 uint16_t devid; 226 227 domain = pcib_get_domain(dev); 228 node = s / 8; 229 devoffset = XLP_HDR_OFFSET(node, 0, s % 8, f); 230 if (!nlm_dev_exists(devoffset)) 231 return; 232 233 /* Find if there is a desc for the SoC device */ 234 devid = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVICE, 2); 235 si = xlp_find_soc_desc(devid); 236 237 /* update flags and irq from desc if available */ 238 irq = 0; 239 flags = 0; 240 if (si != NULL) { 241 if (si->irqbase != 0) 242 irq = si->irqbase + si->ndevs; 243 flags = si->flags; 244 si->ndevs++; 245 } 246 247 /* skip internal devices */ 248 if ((flags & INTERNAL_DEV) != 0) 249 return; 250 251 /* PCIe interfaces are special, bug in Ax */ 252 if (devid == PCI_DEVICE_ID_NLM_PCIE) { 253 xlp_add_irq(node, xlp_pcie_link_irt(f), PIC_PCIE_0_IRQ + f); 254 } else { 255 /* Stash intline and pin in shadow reg for devices */ 256 pcibase = nlm_pcicfg_base(devoffset); 257 irt = nlm_irtstart(pcibase); 258 num = nlm_irtnum(pcibase); 259 if (irq != 0 && num > 0) { 260 xlp_add_irq(node, irt, irq); 261 nlm_write_reg(pcibase, XLP_PCI_DEVSCRATCH_REG0, 262 (1 << 8) | irq); 263 } 264 } 265 dinfo = pci_read_device(pcib, domain, b, s, f, sizeof(*xlp_dinfo)); 266 if (dinfo == NULL) 267 return; 268 xlp_dinfo = (struct xlp_devinfo *)dinfo; 269 xlp_dinfo->irq = irq; 270 xlp_dinfo->flags = flags; 271 272 /* memory resource from ecfg space, if MEM_RES_EMUL is set */ 273 if ((flags & MEM_RES_EMUL) != 0) 274 xlp_dinfo->mem_res_start = XLP_DEFAULT_IO_BASE + devoffset + 275 XLP_IO_PCI_HDRSZ; 276 pci_add_child(dev, dinfo); 277} 278 279static int 280xlp_pci_attach(device_t dev) 281{ 282 device_t pcib = device_get_parent(dev); 283 int maxslots, s, f, pcifunchigh; 284 int busno; 285 uint8_t hdrtype; 286 287 /* 288 * The on-chip devices are on a bus that is almost, but not 289 * quite, completely like PCI. Add those things by hand. 290 */ 291 busno = pcib_get_bus(dev); 292 maxslots = PCIB_MAXSLOTS(pcib); 293 for (s = 0; s <= maxslots; s++) { 294 pcifunchigh = 0; 295 f = 0; 296 hdrtype = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_HDRTYPE, 1); 297 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 298 continue; 299 if (hdrtype & PCIM_MFDEV) 300 pcifunchigh = PCI_FUNCMAX; 301 for (f = 0; f <= pcifunchigh; f++) 302 xlp_add_soc_child(pcib, dev, busno, s, f); 303 } 304 return (bus_generic_attach(dev)); 305} 306 307static int 308xlp_pci_probe(device_t dev) 309{ 310 device_t pcib; 311 312 pcib = device_get_parent(dev); 313 /* 314 * Only the top level bus has SoC devices, leave the rest to 315 * Generic PCI code 316 */ 317 if (strcmp(device_get_nameunit(pcib), "pcib0") != 0) 318 return (ENXIO); 319 device_set_desc(dev, "XLP SoCbus"); 320 return (BUS_PROBE_DEFAULT); 321} 322 323static devclass_t pci_devclass; 324static device_method_t xlp_pci_methods[] = { 325 /* Device interface */ 326 DEVMETHOD(device_probe, xlp_pci_probe), 327 DEVMETHOD(device_attach, xlp_pci_attach), 328 DEVMETHOD(bus_alloc_resource, xlp_pci_alloc_resource), 329 DEVMETHOD(bus_release_resource, xlp_pci_release_resource), 330 331 DEVMETHOD_END 332}; 333 334DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, sizeof(struct pci_softc), 335 pci_driver); 336DRIVER_MODULE(xlp_pci, pcib, xlp_pci_driver, pci_devclass, 0, 0); 337 338static devclass_t pcib_devclass; 339static struct rman irq_rman, port_rman, mem_rman, emul_rman; 340 341static void 342xlp_pcib_init_resources(void) 343{ 344 irq_rman.rm_start = 0; 345 irq_rman.rm_end = 255; 346 irq_rman.rm_type = RMAN_ARRAY; 347 irq_rman.rm_descr = "PCI Mapped Interrupts"; 348 if (rman_init(&irq_rman) 349 || rman_manage_region(&irq_rman, 0, 255)) 350 panic("pci_init_resources irq_rman"); 351 352 port_rman.rm_start = 0; 353 port_rman.rm_end = ~0ul; 354 port_rman.rm_type = RMAN_ARRAY; 355 port_rman.rm_descr = "I/O ports"; 356 if (rman_init(&port_rman) 357 || rman_manage_region(&port_rman, PCIE_IO_BASE, PCIE_IO_LIMIT)) 358 panic("pci_init_resources port_rman"); 359 360 mem_rman.rm_start = 0; 361 mem_rman.rm_end = ~0ul; 362 mem_rman.rm_type = RMAN_ARRAY; 363 mem_rman.rm_descr = "I/O memory"; 364 if (rman_init(&mem_rman) 365 || rman_manage_region(&mem_rman, PCIE_MEM_BASE, PCIE_MEM_LIMIT)) 366 panic("pci_init_resources mem_rman"); 367 368 /* 369 * This includes the GBU (nor flash) memory range and the PCIe 370 * memory area. 371 */ 372 emul_rman.rm_start = 0; 373 emul_rman.rm_end = ~0ul; 374 emul_rman.rm_type = RMAN_ARRAY; 375 emul_rman.rm_descr = "Emulated MEMIO"; 376 if (rman_init(&emul_rman) 377 || rman_manage_region(&emul_rman, EMUL_MEM_START, EMUL_MEM_END)) 378 panic("pci_init_resources emul_rman"); 379} 380 381static int 382xlp_pcib_probe(device_t dev) 383{ 384 385 device_set_desc(dev, "XLP PCI bus"); 386 xlp_pcib_init_resources(); 387 return (0); 388} 389 390static int 391xlp_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 392{ 393 394 switch (which) { 395 case PCIB_IVAR_DOMAIN: 396 *result = 0; 397 return (0); 398 case PCIB_IVAR_BUS: 399 *result = 0; 400 return (0); 401 } 402 return (ENOENT); 403} 404 405static int 406xlp_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 407{ 408 switch (which) { 409 case PCIB_IVAR_DOMAIN: 410 return (EINVAL); 411 case PCIB_IVAR_BUS: 412 return (EINVAL); 413 } 414 return (ENOENT); 415} 416 417static int 418xlp_pcib_maxslots(device_t dev) 419{ 420 421 return (PCI_SLOTMAX); 422} 423 424static u_int32_t 425xlp_pcib_read_config(device_t dev, u_int b, u_int s, u_int f, 426 u_int reg, int width) 427{ 428 uint32_t data = 0; 429 uint64_t cfgaddr; 430 int regindex = reg/sizeof(uint32_t); 431 432 cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); 433 if ((width == 2) && (reg & 1)) 434 return 0xFFFFFFFF; 435 else if ((width == 4) && (reg & 3)) 436 return 0xFFFFFFFF; 437 438 /* 439 * The intline and int pin of SoC devices are DOA, except 440 * for bridges (slot %8 == 1). 441 * use the values we stashed in a writable PCI scratch reg. 442 */ 443 if (b == 0 && regindex == 0xf && s % 8 > 1) 444 regindex = XLP_PCI_DEVSCRATCH_REG0; 445 446 data = nlm_read_pci_reg(cfgaddr, regindex); 447 if (width == 1) 448 return ((data >> ((reg & 3) << 3)) & 0xff); 449 else if (width == 2) 450 return ((data >> ((reg & 3) << 3)) & 0xffff); 451 else 452 return (data); 453} 454 455static void 456xlp_pcib_write_config(device_t dev, u_int b, u_int s, u_int f, 457 u_int reg, u_int32_t val, int width) 458{ 459 uint64_t cfgaddr; 460 uint32_t data = 0; 461 int regindex = reg / sizeof(uint32_t); 462 463 cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); 464 if ((width == 2) && (reg & 1)) 465 return; 466 else if ((width == 4) && (reg & 3)) 467 return; 468 469 if (width == 1) { 470 data = nlm_read_pci_reg(cfgaddr, regindex); 471 data = (data & ~(0xff << ((reg & 3) << 3))) | 472 (val << ((reg & 3) << 3)); 473 } else if (width == 2) { 474 data = nlm_read_pci_reg(cfgaddr, regindex); 475 data = (data & ~(0xffff << ((reg & 3) << 3))) | 476 (val << ((reg & 3) << 3)); 477 } else { 478 data = val; 479 } 480 481 /* 482 * use shadow reg for intpin/intline which are dead 483 */ 484 if (b == 0 && regindex == 0xf && s % 8 > 1) 485 regindex = XLP_PCI_DEVSCRATCH_REG0; 486 nlm_write_pci_reg(cfgaddr, regindex, data); 487} 488 489/* 490 * Enable byte swap in hardware when compiled big-endian. 491 * Programs a link's PCIe SWAP regions from the link's IO and MEM address 492 * ranges. 493 */ 494static void 495xlp_pcib_hardware_swap_enable(int node, int link) 496{ 497#if BYTE_ORDER == BIG_ENDIAN 498 uint64_t bbase, linkpcibase; 499 uint32_t bar; 500 int pcieoffset; 501 502 pcieoffset = XLP_IO_PCIE_OFFSET(node, link); 503 if (!nlm_dev_exists(pcieoffset)) 504 return; 505 506 bbase = nlm_get_bridge_regbase(node); 507 linkpcibase = nlm_pcicfg_base(pcieoffset); 508 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_BASE0 + link); 509 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar); 510 511 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link); 512 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar | 0xFFF); 513 514 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link); 515 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar); 516 517 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link); 518 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF); 519#endif 520} 521 522static int 523xlp_pcib_attach(device_t dev) 524{ 525 int node, link; 526 527 /* enable hardware swap on all nodes/links */ 528 for (node = 0; node < XLP_MAX_NODES; node++) 529 for (link = 0; link < 4; link++) 530 xlp_pcib_hardware_swap_enable(node, link); 531 532 device_add_child(dev, "pci", 0); 533 bus_generic_attach(dev); 534 return (0); 535} 536 537static void 538xlp_pcib_identify(driver_t * driver, device_t parent) 539{ 540 541 BUS_ADD_CHILD(parent, 0, "pcib", 0); 542} 543 544/* 545 * XLS PCIe can have upto 4 links, and each link has its on IRQ 546 * Find the link on which the device is on 547 */ 548static int 549xlp_pcie_link(device_t pcib, device_t dev) 550{ 551 device_t parent, tmp; 552 553 /* find the lane on which the slot is connected to */ 554 tmp = dev; 555 while (1) { 556 parent = device_get_parent(tmp); 557 if (parent == NULL || parent == pcib) { 558 device_printf(dev, "Cannot find parent bus\n"); 559 return (-1); 560 } 561 if (strcmp(device_get_nameunit(parent), "pci0") == 0) 562 break; 563 tmp = parent; 564 } 565 return (pci_get_function(tmp)); 566} 567 568static int 569xlp_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 570{ 571 int i, link; 572 573 /* 574 * Each link has 32 MSIs that can be allocated, but for now 575 * we only support one device per link. 576 * msi_alloc() equivalent is needed when we start supporting 577 * bridges on the PCIe link. 578 */ 579 link = xlp_pcie_link(pcib, dev); 580 if (link == -1) 581 return (ENXIO); 582 583 /* 584 * encode the irq so that we know it is a MSI interrupt when we 585 * setup interrupts 586 */ 587 for (i = 0; i < count; i++) 588 irqs[i] = 64 + link * 32 + i; 589 590 return (0); 591} 592 593static int 594xlp_release_msi(device_t pcib, device_t dev, int count, int *irqs) 595{ 596 return (0); 597} 598 599static int 600xlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 601 uint32_t *data) 602{ 603 int msi, irt; 604 605 if (irq >= 64) { 606 msi = irq - 64; 607 *addr = MIPS_MSI_ADDR(0); 608 609 irt = xlp_pcie_link_irt(msi/32); 610 if (irt != -1) 611 *data = MIPS_MSI_DATA(xlp_irt_to_irq(irt)); 612 return (0); 613 } else { 614 device_printf(dev, "%s: map_msi for irq %d - ignored", 615 device_get_nameunit(pcib), irq); 616 return (ENXIO); 617 } 618} 619 620static void 621bridge_pcie_ack(int irq) 622{ 623 uint32_t node,reg; 624 uint64_t base; 625 626 node = nlm_nodeid(); 627 reg = PCIE_MSI_STATUS; 628 629 switch (irq) { 630 case PIC_PCIE_0_IRQ: 631 base = nlm_pcicfg_base(XLP_IO_PCIE0_OFFSET(node)); 632 break; 633 case PIC_PCIE_1_IRQ: 634 base = nlm_pcicfg_base(XLP_IO_PCIE1_OFFSET(node)); 635 break; 636 case PIC_PCIE_2_IRQ: 637 base = nlm_pcicfg_base(XLP_IO_PCIE2_OFFSET(node)); 638 break; 639 case PIC_PCIE_3_IRQ: 640 base = nlm_pcicfg_base(XLP_IO_PCIE3_OFFSET(node)); 641 break; 642 default: 643 return; 644 } 645 646 nlm_write_pci_reg(base, reg, 0xFFFFFFFF); 647 return; 648} 649 650static int 651mips_platform_pcib_setup_intr(device_t dev, device_t child, 652 struct resource *irq, int flags, driver_filter_t *filt, 653 driver_intr_t *intr, void *arg, void **cookiep) 654{ 655 int error = 0; 656 int xlpirq; 657 void *extra_ack; 658 659 error = rman_activate_resource(irq); 660 if (error) 661 return error; 662 if (rman_get_start(irq) != rman_get_end(irq)) { 663 device_printf(dev, "Interrupt allocation %lu != %lu\n", 664 rman_get_start(irq), rman_get_end(irq)); 665 return (EINVAL); 666 } 667 xlpirq = rman_get_start(irq); 668 if (xlpirq == 0) 669 return (0); 670 671 if (strcmp(device_get_name(dev), "pcib") != 0) 672 return (0); 673 674 /* 675 * temporary hack for MSI, we support just one device per 676 * link, and assign the link interrupt to the device interrupt 677 */ 678 if (xlpirq >= 64) { 679 int node, val, link; 680 uint64_t base; 681 682 xlpirq -= 64; 683 if (xlpirq % 32 != 0) 684 return (0); 685 686 node = nlm_nodeid(); 687 link = xlpirq / 32; 688 base = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node,link)); 689 690 /* MSI Interrupt Vector enable at bridge's configuration */ 691 nlm_write_pci_reg(base, PCIE_MSI_EN, PCIE_MSI_VECTOR_INT_EN); 692 693 val = nlm_read_pci_reg(base, PCIE_INT_EN0); 694 /* MSI Interrupt enable at bridge's configuration */ 695 nlm_write_pci_reg(base, PCIE_INT_EN0, 696 (val | PCIE_MSI_INT_EN)); 697 698 /* legacy interrupt disable at bridge */ 699 val = nlm_read_pci_reg(base, PCIE_BRIDGE_CMD); 700 nlm_write_pci_reg(base, PCIE_BRIDGE_CMD, 701 (val | PCIM_CMD_INTxDIS)); 702 703 /* MSI address update at bridge */ 704 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRL, 705 MSI_MIPS_ADDR_BASE); 706 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRH, 0); 707 708 val = nlm_read_pci_reg(base, PCIE_BRIDGE_MSI_CAP); 709 /* MSI capability enable at bridge */ 710 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP, 711 (val | (PCIM_MSICTRL_MSI_ENABLE << 16) | 712 (PCIM_MSICTRL_MMC_32 << 16))); 713 714 xlpirq = xlp_pcie_link_irt(xlpirq / 32); 715 if (xlpirq == -1) 716 return (EINVAL); 717 xlpirq = xlp_irt_to_irq(xlpirq); 718 } 719 /* Set all irqs to CPU 0 for now */ 720 nlm_pic_write_irt_direct(xlp_pic_base, xlp_irq_to_irt(xlpirq), 1, 0, 721 PIC_LOCAL_SCHEDULING, xlpirq, 0); 722 extra_ack = NULL; 723 if (xlpirq >= PIC_PCIE_0_IRQ && xlpirq <= PIC_PCIE_3_IRQ) 724 extra_ack = bridge_pcie_ack; 725 xlp_establish_intr(device_get_name(child), filt, 726 intr, arg, xlpirq, flags, cookiep, extra_ack); 727 728 return (0); 729} 730 731static int 732mips_platform_pcib_teardown_intr(device_t dev, device_t child, 733 struct resource *irq, void *cookie) 734{ 735 if (strcmp(device_get_name(child), "pci") == 0) { 736 /* if needed reprogram the pic to clear pcix related entry */ 737 device_printf(dev, "teardown intr\n"); 738 } 739 return (bus_generic_teardown_intr(dev, child, irq, cookie)); 740} 741 742static struct resource * 743xlp_pcib_alloc_resource(device_t bus, device_t child, int type, int *rid, 744 u_long start, u_long end, u_long count, u_int flags) 745{ 746 struct rman *rm = NULL; 747 struct resource *rv; 748 void *va; 749 int needactivate = flags & RF_ACTIVE; 750 751 switch (type) { 752 case SYS_RES_IRQ: 753 rm = &irq_rman; 754 break; 755 756 case SYS_RES_IOPORT: 757 rm = &port_rman; 758 break; 759 760 case SYS_RES_MEMORY: 761 if (start >= EMUL_MEM_START && start <= EMUL_MEM_END) 762 rm = &emul_rman; 763 else 764 rm = &mem_rman; 765 break; 766 767 default: 768 return (0); 769 } 770 771 rv = rman_reserve_resource(rm, start, end, count, flags, child); 772 if (rv == NULL) 773 return (NULL); 774 775 rman_set_rid(rv, *rid); 776 777 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { 778 va = pmap_mapdev(start, count); 779 rman_set_bushandle(rv, (bus_space_handle_t)va); 780 rman_set_bustag(rv, rmi_bus_space); 781 } 782 if (needactivate) { 783 if (bus_activate_resource(child, type, *rid, rv)) { 784 rman_release_resource(rv); 785 return (NULL); 786 } 787 } 788 return (rv); 789} 790 791static int 792xlp_pcib_release_resource(device_t bus, device_t child, int type, int rid, 793 struct resource *r) 794{ 795 796 return (rman_release_resource(r)); 797} 798 799static int 800xlp_pcib_activate_resource(device_t bus, device_t child, int type, int rid, 801 struct resource *r) 802{ 803 804 return (rman_activate_resource(r)); 805} 806 807static int 808xlp_pcib_deactivate_resource(device_t bus, device_t child, int type, int rid, 809 struct resource *r) 810{ 811 812 return (rman_deactivate_resource(r)); 813} 814 815static int 816mips_pcib_route_interrupt(device_t bus, device_t dev, int pin) 817{ 818 int irt, link; 819 820 /* 821 * Validate requested pin number. 822 */ 823 if ((pin < 1) || (pin > 4)) 824 return (255); 825 826 if (pci_get_bus(dev) == 0 && 827 pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC) { 828 /* SoC devices */ 829 uint64_t pcibase; 830 int f, n, d, num; 831 832 f = pci_get_function(dev); 833 n = pci_get_slot(dev) / 8; 834 d = pci_get_slot(dev) % 8; 835 836 /* 837 * For PCIe links, return link IRT, for other SoC devices 838 * get the IRT from its PCIe header 839 */ 840 if (d == 1) { 841 irt = xlp_pcie_link_irt(f); 842 } else { 843 pcibase = nlm_pcicfg_base(XLP_HDR_OFFSET(n, 0, d, f)); 844 irt = nlm_irtstart(pcibase); 845 num = nlm_irtnum(pcibase); 846 if (num != 1) 847 device_printf(bus, "[%d:%d:%d] Error %d IRQs\n", 848 n, d, f, num); 849 } 850 } else { 851 /* Regular PCI devices */ 852 link = xlp_pcie_link(bus, dev); 853 irt = xlp_pcie_link_irt(link); 854 } 855 856 if (irt != -1) 857 return (xlp_irt_to_irq(irt)); 858 859 return (255); 860} 861 862static device_method_t xlp_pcib_methods[] = { 863 /* Device interface */ 864 DEVMETHOD(device_identify, xlp_pcib_identify), 865 DEVMETHOD(device_probe, xlp_pcib_probe), 866 DEVMETHOD(device_attach, xlp_pcib_attach), 867 868 /* Bus interface */ 869 DEVMETHOD(bus_read_ivar, xlp_pcib_read_ivar), 870 DEVMETHOD(bus_write_ivar, xlp_pcib_write_ivar), 871 DEVMETHOD(bus_alloc_resource, xlp_pcib_alloc_resource), 872 DEVMETHOD(bus_release_resource, xlp_pcib_release_resource), 873 DEVMETHOD(bus_activate_resource, xlp_pcib_activate_resource), 874 DEVMETHOD(bus_deactivate_resource, xlp_pcib_deactivate_resource), 875 DEVMETHOD(bus_setup_intr, mips_platform_pcib_setup_intr), 876 DEVMETHOD(bus_teardown_intr, mips_platform_pcib_teardown_intr), 877 878 /* pcib interface */ 879 DEVMETHOD(pcib_maxslots, xlp_pcib_maxslots), 880 DEVMETHOD(pcib_read_config, xlp_pcib_read_config), 881 DEVMETHOD(pcib_write_config, xlp_pcib_write_config), 882 DEVMETHOD(pcib_route_interrupt, mips_pcib_route_interrupt), 883 884 DEVMETHOD(pcib_alloc_msi, xlp_alloc_msi), 885 DEVMETHOD(pcib_release_msi, xlp_release_msi), 886 DEVMETHOD(pcib_map_msi, xlp_map_msi), 887 888 DEVMETHOD_END 889}; 890 891static driver_t xlp_pcib_driver = { 892 "pcib", 893 xlp_pcib_methods, 894 1, /* no softc */ 895}; 896 897DRIVER_MODULE(pcib, nexus, xlp_pcib_driver, pcib_devclass, 0, 0); 898