1/*- 2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ 17 * $FreeBSD$ 18 */ 19 20#define URTWN_CONFIG_INDEX 0 21#define URTWN_IFACE_INDEX 0 22 23#define URTWN_NOISE_FLOOR -95 24 25#define R92C_MAX_CHAINS 2 26 27/* Maximum number of output pipes is 3. */ 28#define R92C_MAX_EPOUT 3 29 30#define R92C_MAX_TX_PWR 0x3f 31 32#define R92C_PUBQ_NPAGES 231 33#define R92C_TXPKTBUF_COUNT 256 34#define R92C_TX_PAGE_COUNT 248 35#define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 36 37#define R92C_H2C_NBOX 4 38 39/* USB Requests. */ 40#define R92C_REQ_REGS 0x05 41 42/* 43 * MAC registers. 44 */ 45/* System Configuration. */ 46#define R92C_SYS_ISO_CTRL 0x000 47#define R92C_SYS_FUNC_EN 0x002 48#define R92C_APS_FSMCO 0x004 49#define R92C_SYS_CLKR 0x008 50#define R92C_AFE_MISC 0x010 51#define R92C_SPS0_CTRL 0x011 52#define R92C_SPS_OCP_CFG 0x018 53#define R92C_RSV_CTRL 0x01c 54#define R92C_RF_CTRL 0x01f 55#define R92C_LDOA15_CTRL 0x020 56#define R92C_LDOV12D_CTRL 0x021 57#define R92C_LDOHCI12_CTRL 0x022 58#define R92C_LPLDO_CTRL 0x023 59#define R92C_AFE_XTAL_CTRL 0x024 60#define R92C_AFE_PLL_CTRL 0x028 61#define R92C_EFUSE_CTRL 0x030 62#define R92C_EFUSE_TEST 0x034 63#define R92C_PWR_DATA 0x038 64#define R92C_CAL_TIMER 0x03c 65#define R92C_ACLK_MON 0x03e 66#define R92C_GPIO_MUXCFG 0x040 67#define R92C_GPIO_IO_SEL 0x042 68#define R92C_MAC_PINMUX_CFG 0x043 69#define R92C_GPIO_PIN_CTRL 0x044 70#define R92C_GPIO_INTM 0x048 71#define R92C_LEDCFG0 0x04c 72#define R92C_LEDCFG1 0x04d 73#define R92C_LEDCFG2 0x04e 74#define R92C_LEDCFG3 0x04f 75#define R92C_FSIMR 0x050 76#define R92C_FSISR 0x054 77#define R92C_HSIMR 0x058 78#define R92C_HSISR 0x05c 79#define R92C_MCUFWDL 0x080 80#define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 81#define R92C_BIST_SCAN 0x0d0 82#define R92C_BIST_RPT 0x0d4 83#define R92C_BIST_ROM_RPT 0x0d8 84#define R92C_USB_SIE_INTF 0x0e0 85#define R92C_PCIE_MIO_INTF 0x0e4 86#define R92C_PCIE_MIO_INTD 0x0e8 87#define R92C_HPON_FSM 0x0ec 88#define R92C_SYS_CFG 0x0f0 89/* MAC General Configuration. */ 90#define R92C_CR 0x100 91#define R92C_PBP 0x104 92#define R92C_TRXDMA_CTRL 0x10c 93#define R92C_TRXFF_BNDY 0x114 94#define R92C_TRXFF_STATUS 0x118 95#define R92C_RXFF_PTR 0x11c 96#define R92C_HIMR 0x120 97#define R92C_HISR 0x124 98#define R92C_HIMRE 0x128 99#define R92C_HISRE 0x12c 100#define R92C_CPWM 0x12f 101#define R92C_FWIMR 0x130 102#define R92C_FWISR 0x134 103#define R92C_PKTBUF_DBG_CTRL 0x140 104#define R92C_PKTBUF_DBG_DATA_L 0x144 105#define R92C_PKTBUF_DBG_DATA_H 0x148 106#define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 107#define R92C_TCUNIT_BASE 0x164 108#define R92C_MBIST_START 0x174 109#define R92C_MBIST_DONE 0x178 110#define R92C_MBIST_FAIL 0x17c 111#define R92C_C2HEVT_MSG_NORMAL 0x1a0 112#define R92C_C2HEVT_MSG_TEST 0x1b8 113#define R92C_C2HEVT_CLEAR 0x1bf 114#define R92C_MCUTST_1 0x1c0 115#define R92C_FMETHR 0x1c8 116#define R92C_HMETFR 0x1cc 117#define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 118#define R92C_LLT_INIT 0x1e0 119#define R92C_BB_ACCESS_CTRL 0x1e8 120#define R92C_BB_ACCESS_DATA 0x1ec 121/* Tx DMA Configuration. */ 122#define R92C_RQPN 0x200 123#define R92C_FIFOPAGE 0x204 124#define R92C_TDECTRL 0x208 125#define R92C_TXDMA_OFFSET_CHK 0x20c 126#define R92C_TXDMA_STATUS 0x210 127#define R92C_RQPN_NPQ 0x214 128/* Rx DMA Configuration. */ 129#define R92C_RXDMA_AGG_PG_TH 0x280 130#define R92C_RXPKT_NUM 0x284 131#define R92C_RXDMA_STATUS 0x288 132/* Protocol Configuration. */ 133#define R92C_FWHW_TXQ_CTRL 0x420 134#define R92C_HWSEQ_CTRL 0x423 135#define R92C_TXPKTBUF_BCNQ_BDNY 0x424 136#define R92C_TXPKTBUF_MGQ_BDNY 0x425 137#define R92C_SPEC_SIFS 0x428 138#define R92C_RL 0x42a 139#define R92C_DARFRC 0x430 140#define R92C_RARFRC 0x438 141#define R92C_RRSR 0x440 142#define R92C_ARFR(i) (0x444 + (i) * 4) 143#define R92C_AGGLEN_LMT 0x458 144#define R92C_AMPDU_MIN_SPACE 0x45c 145#define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 146#define R92C_FAST_EDCA_CTRL 0x460 147#define R92C_RD_RESP_PKT_TH 0x463 148#define R92C_INIRTS_RATE_SEL 0x480 149#define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 150/* EDCA Configuration. */ 151#define R92C_EDCA_VO_PARAM 0x500 152#define R92C_EDCA_VI_PARAM 0x504 153#define R92C_EDCA_BE_PARAM 0x508 154#define R92C_EDCA_BK_PARAM 0x50c 155#define R92C_BCNTCFG 0x510 156#define R92C_PIFS 0x512 157#define R92C_RDG_PIFS 0x513 158#define R92C_SIFS_CCK 0x514 159#define R92C_SIFS_OFDM 0x516 160#define R92C_AGGR_BREAK_TIME 0x51a 161#define R92C_SLOT 0x51b 162#define R92C_TX_PTCL_CTRL 0x520 163#define R92C_TXPAUSE 0x522 164#define R92C_DIS_TXREQ_CLR 0x523 165#define R92C_RD_CTRL 0x524 166#define R92C_TBTT_PROHIBIT 0x540 167#define R92C_RD_NAV_NXT 0x544 168#define R92C_NAV_PROT_LEN 0x546 169#define R92C_BCN_CTRL 0x550 170#define R92C_USTIME_TSF 0x551 171#define R92C_MBID_NUM 0x552 172#define R92C_DUAL_TSF_RST 0x553 173#define R92C_BCN_INTERVAL 0x554 174#define R92C_DRVERLYINT 0x558 175#define R92C_BCNDMATIM 0x559 176#define R92C_ATIMWND 0x55a 177#define R92C_BCN_MAX_ERR 0x55d 178#define R92C_RXTSF_OFFSET_CCK 0x55e 179#define R92C_RXTSF_OFFSET_OFDM 0x55f 180#define R92C_TSFTR 0x560 181#define R92C_INIT_TSFTR 0x564 182#define R92C_PSTIMER 0x580 183#define R92C_TIMER0 0x584 184#define R92C_TIMER1 0x588 185#define R92C_ACMHWCTRL 0x5c0 186#define R92C_ACMRSTCTRL 0x5c1 187#define R92C_ACMAVG 0x5c2 188#define R92C_VO_ADMTIME 0x5c4 189#define R92C_VI_ADMTIME 0x5c6 190#define R92C_BE_ADMTIME 0x5c8 191#define R92C_EDCA_RANDOM_GEN 0x5cc 192#define R92C_SCH_TXCMD 0x5d0 193/* WMAC Configuration. */ 194#define R92C_APSD_CTRL 0x600 195#define R92C_BWOPMODE 0x603 196#define R92C_RCR 0x608 197#define R92C_RX_DRVINFO_SZ 0x60f 198#define R92C_MACID 0x610 199#define R92C_BSSID 0x618 200#define R92C_MAR 0x620 201#define R92C_MAC_SPEC_SIFS 0x63a 202#define R92C_R2T_SIFS 0x63c 203#define R92C_T2T_SIFS 0x63e 204#define R92C_ACKTO 0x640 205#define R92C_CAMCMD 0x670 206#define R92C_CAMWRITE 0x674 207#define R92C_CAMREAD 0x678 208#define R92C_CAMDBG 0x67c 209#define R92C_SECCFG 0x680 210#define R92C_RXFLTMAP0 0x6a0 211#define R92C_RXFLTMAP1 0x6a2 212#define R92C_RXFLTMAP2 0x6a4 213 214/* Bits for R92C_SYS_ISO_CTRL. */ 215#define R92C_SYS_ISO_CTRL_MD2PP 0x0001 216#define R92C_SYS_ISO_CTRL_UA2USB 0x0002 217#define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 218#define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 219#define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 220#define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 221#define R92C_SYS_ISO_CTRL_DIOP 0x0040 222#define R92C_SYS_ISO_CTRL_DIOE 0x0080 223#define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 224#define R92C_SYS_ISO_CTRL_DIOR 0x0200 225#define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 226#define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 227 228/* Bits for R92C_SYS_FUNC_EN. */ 229#define R92C_SYS_FUNC_EN_BBRSTB 0x0001 230#define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 231#define R92C_SYS_FUNC_EN_USBA 0x0004 232#define R92C_SYS_FUNC_EN_UPLL 0x0008 233#define R92C_SYS_FUNC_EN_USBD 0x0010 234#define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 235#define R92C_SYS_FUNC_EN_PCIEA 0x0040 236#define R92C_SYS_FUNC_EN_PPLL 0x0080 237#define R92C_SYS_FUNC_EN_PCIED 0x0100 238#define R92C_SYS_FUNC_EN_DIOE 0x0200 239#define R92C_SYS_FUNC_EN_CPUEN 0x0400 240#define R92C_SYS_FUNC_EN_DCORE 0x0800 241#define R92C_SYS_FUNC_EN_ELDR 0x1000 242#define R92C_SYS_FUNC_EN_DIO_RF 0x2000 243#define R92C_SYS_FUNC_EN_HWPDN 0x4000 244#define R92C_SYS_FUNC_EN_MREGEN 0x8000 245 246/* Bits for R92C_APS_FSMCO. */ 247#define R92C_APS_FSMCO_PFM_LDALL 0x00000001 248#define R92C_APS_FSMCO_PFM_ALDN 0x00000002 249#define R92C_APS_FSMCO_PFM_LDKP 0x00000004 250#define R92C_APS_FSMCO_PFM_WOWL 0x00000008 251#define R92C_APS_FSMCO_PDN_EN 0x00000010 252#define R92C_APS_FSMCO_PDN_PL 0x00000020 253#define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 254#define R92C_APS_FSMCO_APFM_OFF 0x00000200 255#define R92C_APS_FSMCO_APFM_RSM 0x00000400 256#define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 257#define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 258#define R92C_APS_FSMCO_APDM_MAC 0x00002000 259#define R92C_APS_FSMCO_APDM_HOST 0x00004000 260#define R92C_APS_FSMCO_APDM_HPDN 0x00008000 261#define R92C_APS_FSMCO_RDY_MACON 0x00010000 262#define R92C_APS_FSMCO_SUS_HOST 0x00020000 263#define R92C_APS_FSMCO_ROP_ALD 0x00100000 264#define R92C_APS_FSMCO_ROP_PWR 0x00200000 265#define R92C_APS_FSMCO_ROP_SPS 0x00400000 266#define R92C_APS_FSMCO_SOP_MRST 0x02000000 267#define R92C_APS_FSMCO_SOP_FUSE 0x04000000 268#define R92C_APS_FSMCO_SOP_ABG 0x08000000 269#define R92C_APS_FSMCO_SOP_AMB 0x10000000 270#define R92C_APS_FSMCO_SOP_RCK 0x20000000 271#define R92C_APS_FSMCO_SOP_A8M 0x40000000 272#define R92C_APS_FSMCO_XOP_BTCK 0x80000000 273 274/* Bits for R92C_SYS_CLKR. */ 275#define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 276#define R92C_SYS_CLKR_ANA8M 0x00000002 277#define R92C_SYS_CLKR_MACSLP 0x00000010 278#define R92C_SYS_CLKR_LOADER_EN 0x00000020 279#define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 280#define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 281#define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 282#define R92C_SYS_CLKR_SEC_EN 0x00000400 283#define R92C_SYS_CLKR_MAC_EN 0x00000800 284#define R92C_SYS_CLKR_SYS_EN 0x00001000 285#define R92C_SYS_CLKR_RING_EN 0x00002000 286 287/* Bits for R92C_RF_CTRL. */ 288#define R92C_RF_CTRL_EN 0x01 289#define R92C_RF_CTRL_RSTB 0x02 290#define R92C_RF_CTRL_SDMRSTB 0x04 291 292/* Bits for R92C_LDOV12D_CTRL. */ 293#define R92C_LDOV12D_CTRL_LDV12_EN 0x01 294 295/* Bits for R92C_EFUSE_CTRL. */ 296#define R92C_EFUSE_CTRL_DATA_M 0x000000ff 297#define R92C_EFUSE_CTRL_DATA_S 0 298#define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 299#define R92C_EFUSE_CTRL_ADDR_S 8 300#define R92C_EFUSE_CTRL_VALID 0x80000000 301 302/* Bits for R92C_GPIO_MUXCFG. */ 303#define R92C_GPIO_MUXCFG_ENBT 0x0020 304 305/* Bits for R92C_LEDCFG0. */ 306#define R92C_LEDCFG0_DIS 0x08 307 308/* Bits for R92C_MCUFWDL. */ 309#define R92C_MCUFWDL_EN 0x00000001 310#define R92C_MCUFWDL_RDY 0x00000002 311#define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 312#define R92C_MCUFWDL_MACINI_RDY 0x00000008 313#define R92C_MCUFWDL_BBINI_RDY 0x00000010 314#define R92C_MCUFWDL_RFINI_RDY 0x00000020 315#define R92C_MCUFWDL_WINTINI_RDY 0x00000040 316#define R92C_MCUFWDL_PAGE_M 0x00070000 317#define R92C_MCUFWDL_PAGE_S 16 318#define R92C_MCUFWDL_CPRST 0x00800000 319 320/* Bits for R92C_HPON_FSM. */ 321#define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 322#define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 323#define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 324 325/* Bits for R92C_SYS_CFG. */ 326#define R92C_SYS_CFG_XCLK_VLD 0x00000001 327#define R92C_SYS_CFG_ACLK_VLD 0x00000002 328#define R92C_SYS_CFG_UCLK_VLD 0x00000004 329#define R92C_SYS_CFG_PCLK_VLD 0x00000008 330#define R92C_SYS_CFG_PCIRSTB 0x00000010 331#define R92C_SYS_CFG_V15_VLD 0x00000020 332#define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 333#define R92C_SYS_CFG_SIC_IDLE 0x00000100 334#define R92C_SYS_CFG_BD_MAC2 0x00000200 335#define R92C_SYS_CFG_BD_MAC1 0x00000400 336#define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 337#define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 338#define R92C_SYS_CFG_CHIP_VER_RTL_S 12 339#define R92C_SYS_CFG_BT_FUNC 0x00010000 340#define R92C_SYS_CFG_VENDOR_UMC 0x00080000 341#define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 342#define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 343#define R92C_SYS_CFG_TRP_BT_EN 0x01000000 344#define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 345#define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 346#define R92C_SYS_CFG_TYPE_92C 0x08000000 347 348/* Bits for R92C_CR. */ 349#define R92C_CR_HCI_TXDMA_EN 0x00000001 350#define R92C_CR_HCI_RXDMA_EN 0x00000002 351#define R92C_CR_TXDMA_EN 0x00000004 352#define R92C_CR_RXDMA_EN 0x00000008 353#define R92C_CR_PROTOCOL_EN 0x00000010 354#define R92C_CR_SCHEDULE_EN 0x00000020 355#define R92C_CR_MACTXEN 0x00000040 356#define R92C_CR_MACRXEN 0x00000080 357#define R92C_CR_ENSEC 0x00000200 358#define R92C_CR_NETTYPE_S 16 359#define R92C_CR_NETTYPE_M 0x00030000 360#define R92C_CR_NETTYPE_NOLINK 0 361#define R92C_CR_NETTYPE_ADHOC 1 362#define R92C_CR_NETTYPE_INFRA 2 363#define R92C_CR_NETTYPE_AP 3 364 365/* Bits for R92C_PBP. */ 366#define R92C_PBP_PSRX_M 0x0f 367#define R92C_PBP_PSRX_S 0 368#define R92C_PBP_PSTX_M 0xf0 369#define R92C_PBP_PSTX_S 4 370#define R92C_PBP_64 0 371#define R92C_PBP_128 1 372#define R92C_PBP_256 2 373#define R92C_PBP_512 3 374#define R92C_PBP_1024 4 375 376/* Bits for R92C_TRXDMA_CTRL. */ 377#define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 378#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 379#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 380#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 381#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 382#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 383#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 384#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 385#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 386#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 387#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 388#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 389#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 390#define R92C_TRXDMA_CTRL_QUEUE_LOW 1 391#define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 392#define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 393#define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 394/* Shortcuts. */ 395#define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 396#define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 397#define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 398#define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 399#define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 400#define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 401 402/* Bits for R92C_LLT_INIT. */ 403#define R92C_LLT_INIT_DATA_M 0x000000ff 404#define R92C_LLT_INIT_DATA_S 0 405#define R92C_LLT_INIT_ADDR_M 0x0000ff00 406#define R92C_LLT_INIT_ADDR_S 8 407#define R92C_LLT_INIT_OP_M 0xc0000000 408#define R92C_LLT_INIT_OP_S 30 409#define R92C_LLT_INIT_OP_NO_ACTIVE 0 410#define R92C_LLT_INIT_OP_WRITE 1 411 412/* Bits for R92C_RQPN. */ 413#define R92C_RQPN_HPQ_M 0x000000ff 414#define R92C_RQPN_HPQ_S 0 415#define R92C_RQPN_LPQ_M 0x0000ff00 416#define R92C_RQPN_LPQ_S 8 417#define R92C_RQPN_PUBQ_M 0x00ff0000 418#define R92C_RQPN_PUBQ_S 16 419#define R92C_RQPN_LD 0x80000000 420 421/* Bits for R92C_TDECTRL. */ 422#define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f 423#define R92C_TDECTRL_BLK_DESC_NUM_S 4 424 425/* Bits for R92C_FWHW_TXQ_CTRL. */ 426#define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 427 428/* Bits for R92C_SPEC_SIFS. */ 429#define R92C_SPEC_SIFS_CCK_M 0x00ff 430#define R92C_SPEC_SIFS_CCK_S 0 431#define R92C_SPEC_SIFS_OFDM_M 0xff00 432#define R92C_SPEC_SIFS_OFDM_S 8 433 434/* Bits for R92C_RL. */ 435#define R92C_RL_LRL_M 0x003f 436#define R92C_RL_LRL_S 0 437#define R92C_RL_SRL_M 0x3f00 438#define R92C_RL_SRL_S 8 439 440/* Bits for R92C_RRSR. */ 441#define R92C_RRSR_RATE_BITMAP_M 0x000fffff 442#define R92C_RRSR_RATE_BITMAP_S 0 443#define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 444#define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 445#define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 446#define R92C_RRSR_SHORT 0x00800000 447 448/* Bits for R92C_EDCA_XX_PARAM. */ 449#define R92C_EDCA_PARAM_AIFS_M 0x000000ff 450#define R92C_EDCA_PARAM_AIFS_S 0 451#define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 452#define R92C_EDCA_PARAM_ECWMIN_S 8 453#define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 454#define R92C_EDCA_PARAM_ECWMAX_S 12 455#define R92C_EDCA_PARAM_TXOP_M 0xffff0000 456#define R92C_EDCA_PARAM_TXOP_S 16 457 458/* Bits for R92C_BCN_CTRL. */ 459#define R92C_BCN_CTRL_EN_MBSSID 0x02 460#define R92C_BCN_CTRL_TXBCN_RPT 0x04 461#define R92C_BCN_CTRL_EN_BCN 0x08 462#define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 463 464/* Bits for R92C_APSD_CTRL. */ 465#define R92C_APSD_CTRL_OFF 0x40 466#define R92C_APSD_CTRL_OFF_STATUS 0x80 467 468/* Bits for R92C_BWOPMODE. */ 469#define R92C_BWOPMODE_11J 0x01 470#define R92C_BWOPMODE_5G 0x02 471#define R92C_BWOPMODE_20MHZ 0x04 472 473/* Bits for R92C_RCR. */ 474#define R92C_RCR_AAP 0x00000001 475#define R92C_RCR_APM 0x00000002 476#define R92C_RCR_AM 0x00000004 477#define R92C_RCR_AB 0x00000008 478#define R92C_RCR_ADD3 0x00000010 479#define R92C_RCR_APWRMGT 0x00000020 480#define R92C_RCR_CBSSID_DATA 0x00000040 481#define R92C_RCR_CBSSID_BCN 0x00000080 482#define R92C_RCR_ACRC32 0x00000100 483#define R92C_RCR_AICV 0x00000200 484#define R92C_RCR_ADF 0x00000800 485#define R92C_RCR_ACF 0x00001000 486#define R92C_RCR_AMF 0x00002000 487#define R92C_RCR_HTC_LOC_CTRL 0x00004000 488#define R92C_RCR_MFBEN 0x00400000 489#define R92C_RCR_LSIGEN 0x00800000 490#define R92C_RCR_ENMBID 0x01000000 491#define R92C_RCR_APP_BA_SSN 0x08000000 492#define R92C_RCR_APP_PHYSTS 0x10000000 493#define R92C_RCR_APP_ICV 0x20000000 494#define R92C_RCR_APP_MIC 0x40000000 495#define R92C_RCR_APPFCS 0x80000000 496 497/* Bits for R92C_CAMCMD. */ 498#define R92C_CAMCMD_ADDR_M 0x0000ffff 499#define R92C_CAMCMD_ADDR_S 0 500#define R92C_CAMCMD_WRITE 0x00010000 501#define R92C_CAMCMD_CLR 0x40000000 502#define R92C_CAMCMD_POLLING 0x80000000 503 504 505/* 506 * Baseband registers. 507 */ 508#define R92C_FPGA0_RFMOD 0x800 509#define R92C_FPGA0_TXINFO 0x804 510#define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 511#define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 512#define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 513#define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 514#define R92C_TXAGC_A_CCK1_MCS32 0xe08 515#define R92C_TXAGC_B_CCK1_55_MCS32 0x838 516#define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 517#define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 518#define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 519#define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 520#define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 521#define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 522#define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 523#define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 524#define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 525#define R92C_FPGA0_ANAPARAM2 0x884 526#define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 527#define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 528#define R92C_FPGA1_RFMOD 0x900 529#define R92C_FPGA1_TXINFO 0x90c 530#define R92C_CCK0_SYSTEM 0xa00 531#define R92C_CCK0_AFESETTING 0xa04 532#define R92C_OFDM0_TRXPATHENA 0xc04 533#define R92C_OFDM0_TRMUXPAR 0xc08 534#define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 535#define R92C_OFDM0_AGCPARAM1 0xc70 536#define R92C_OFDM0_AGCRSSITABLE 0xc78 537#define R92C_OFDM1_LSTF 0xd00 538 539/* Bits for R92C_FPGA[01]_RFMOD. */ 540#define R92C_RFMOD_40MHZ 0x00000001 541#define R92C_RFMOD_JAPAN 0x00000002 542#define R92C_RFMOD_CCK_TXSC 0x00000030 543#define R92C_RFMOD_CCK_EN 0x01000000 544#define R92C_RFMOD_OFDM_EN 0x02000000 545 546/* Bits for R92C_HSSI_PARAM1(i). */ 547#define R92C_HSSI_PARAM1_PI 0x00000100 548 549/* Bits for R92C_HSSI_PARAM2(i). */ 550#define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 551#define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 552#define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 553#define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 554#define R92C_HSSI_PARAM2_READ_ADDR_S 23 555#define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 556 557/* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 558#define R92C_TXAGC_A_CCK1_M 0x0000ff00 559#define R92C_TXAGC_A_CCK1_S 8 560 561/* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 562#define R92C_TXAGC_B_CCK11_M 0x000000ff 563#define R92C_TXAGC_B_CCK11_S 0 564#define R92C_TXAGC_A_CCK2_M 0x0000ff00 565#define R92C_TXAGC_A_CCK2_S 8 566#define R92C_TXAGC_A_CCK55_M 0x00ff0000 567#define R92C_TXAGC_A_CCK55_S 16 568#define R92C_TXAGC_A_CCK11_M 0xff000000 569#define R92C_TXAGC_A_CCK11_S 24 570 571/* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 572#define R92C_TXAGC_B_CCK1_M 0x0000ff00 573#define R92C_TXAGC_B_CCK1_S 8 574#define R92C_TXAGC_B_CCK2_M 0x00ff0000 575#define R92C_TXAGC_B_CCK2_S 16 576#define R92C_TXAGC_B_CCK55_M 0xff000000 577#define R92C_TXAGC_B_CCK55_S 24 578 579/* Bits for R92C_TXAGC_RATE18_06(x). */ 580#define R92C_TXAGC_RATE06_M 0x000000ff 581#define R92C_TXAGC_RATE06_S 0 582#define R92C_TXAGC_RATE09_M 0x0000ff00 583#define R92C_TXAGC_RATE09_S 8 584#define R92C_TXAGC_RATE12_M 0x00ff0000 585#define R92C_TXAGC_RATE12_S 16 586#define R92C_TXAGC_RATE18_M 0xff000000 587#define R92C_TXAGC_RATE18_S 24 588 589/* Bits for R92C_TXAGC_RATE54_24(x). */ 590#define R92C_TXAGC_RATE24_M 0x000000ff 591#define R92C_TXAGC_RATE24_S 0 592#define R92C_TXAGC_RATE36_M 0x0000ff00 593#define R92C_TXAGC_RATE36_S 8 594#define R92C_TXAGC_RATE48_M 0x00ff0000 595#define R92C_TXAGC_RATE48_S 16 596#define R92C_TXAGC_RATE54_M 0xff000000 597#define R92C_TXAGC_RATE54_S 24 598 599/* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 600#define R92C_TXAGC_MCS00_M 0x000000ff 601#define R92C_TXAGC_MCS00_S 0 602#define R92C_TXAGC_MCS01_M 0x0000ff00 603#define R92C_TXAGC_MCS01_S 8 604#define R92C_TXAGC_MCS02_M 0x00ff0000 605#define R92C_TXAGC_MCS02_S 16 606#define R92C_TXAGC_MCS03_M 0xff000000 607#define R92C_TXAGC_MCS03_S 24 608 609/* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 610#define R92C_TXAGC_MCS04_M 0x000000ff 611#define R92C_TXAGC_MCS04_S 0 612#define R92C_TXAGC_MCS05_M 0x0000ff00 613#define R92C_TXAGC_MCS05_S 8 614#define R92C_TXAGC_MCS06_M 0x00ff0000 615#define R92C_TXAGC_MCS06_S 16 616#define R92C_TXAGC_MCS07_M 0xff000000 617#define R92C_TXAGC_MCS07_S 24 618 619/* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 620#define R92C_TXAGC_MCS08_M 0x000000ff 621#define R92C_TXAGC_MCS08_S 0 622#define R92C_TXAGC_MCS09_M 0x0000ff00 623#define R92C_TXAGC_MCS09_S 8 624#define R92C_TXAGC_MCS10_M 0x00ff0000 625#define R92C_TXAGC_MCS10_S 16 626#define R92C_TXAGC_MCS11_M 0xff000000 627#define R92C_TXAGC_MCS11_S 24 628 629/* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 630#define R92C_TXAGC_MCS12_M 0x000000ff 631#define R92C_TXAGC_MCS12_S 0 632#define R92C_TXAGC_MCS13_M 0x0000ff00 633#define R92C_TXAGC_MCS13_S 8 634#define R92C_TXAGC_MCS14_M 0x00ff0000 635#define R92C_TXAGC_MCS14_S 16 636#define R92C_TXAGC_MCS15_M 0xff000000 637#define R92C_TXAGC_MCS15_S 24 638 639/* Bits for R92C_LSSI_PARAM(i). */ 640#define R92C_LSSI_PARAM_DATA_M 0x000fffff 641#define R92C_LSSI_PARAM_DATA_S 0 642#define R92C_LSSI_PARAM_ADDR_M 0x03f00000 643#define R92C_LSSI_PARAM_ADDR_S 20 644 645/* Bits for R92C_FPGA0_ANAPARAM2. */ 646#define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 647 648/* Bits for R92C_LSSI_READBACK(i). */ 649#define R92C_LSSI_READBACK_DATA_M 0x000fffff 650#define R92C_LSSI_READBACK_DATA_S 0 651 652/* Bits for R92C_OFDM0_AGCCORE1(i). */ 653#define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 654#define R92C_OFDM0_AGCCORE1_GAIN_S 0 655 656 657/* 658 * USB registers. 659 */ 660#define R92C_USB_INFO 0xfe17 661#define R92C_USB_SPECIAL_OPTION 0xfe55 662#define R92C_USB_HCPWM 0xfe57 663#define R92C_USB_HRPWM 0xfe58 664#define R92C_USB_DMA_AGG_TO 0xfe5b 665#define R92C_USB_AGG_TO 0xfe5c 666#define R92C_USB_AGG_TH 0xfe5d 667#define R92C_USB_VID 0xfe60 668#define R92C_USB_PID 0xfe62 669#define R92C_USB_OPTIONAL 0xfe64 670#define R92C_USB_EP 0xfe65 671#define R92C_USB_PHY 0xfe68 672#define R92C_USB_MAC_ADDR 0xfe70 673#define R92C_USB_STRING 0xfe80 674 675/* Bits for R92C_USB_SPECIAL_OPTION. */ 676#define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 677 678/* Bits for R92C_USB_EP. */ 679#define R92C_USB_EP_HQ_M 0x000f 680#define R92C_USB_EP_HQ_S 0 681#define R92C_USB_EP_NQ_M 0x00f0 682#define R92C_USB_EP_NQ_S 4 683#define R92C_USB_EP_LQ_M 0x0f00 684#define R92C_USB_EP_LQ_S 8 685 686 687/* 688 * Firmware base address. 689 */ 690#define R92C_FW_START_ADDR 0x1000 691#define R92C_FW_PAGE_SIZE 4096 692 693 694/* 695 * RF (6052) registers. 696 */ 697#define R92C_RF_AC 0x00 698#define R92C_RF_IQADJ_G(i) (0x01 + (i)) 699#define R92C_RF_POW_TRSW 0x05 700#define R92C_RF_GAIN_RX 0x06 701#define R92C_RF_GAIN_TX 0x07 702#define R92C_RF_TXM_IDAC 0x08 703#define R92C_RF_BS_IQGEN 0x0f 704#define R92C_RF_MODE1 0x10 705#define R92C_RF_MODE2 0x11 706#define R92C_RF_RX_AGC_HP 0x12 707#define R92C_RF_TX_AGC 0x13 708#define R92C_RF_BIAS 0x14 709#define R92C_RF_IPA 0x15 710#define R92C_RF_POW_ABILITY 0x17 711#define R92C_RF_CHNLBW 0x18 712#define R92C_RF_RX_G1 0x1a 713#define R92C_RF_RX_G2 0x1b 714#define R92C_RF_RX_BB2 0x1c 715#define R92C_RF_RX_BB1 0x1d 716#define R92C_RF_RCK1 0x1e 717#define R92C_RF_RCK2 0x1f 718#define R92C_RF_TX_G(i) (0x20 + (i)) 719#define R92C_RF_TX_BB1 0x23 720#define R92C_RF_T_METER 0x24 721#define R92C_RF_SYN_G(i) (0x25 + (i)) 722#define R92C_RF_RCK_OS 0x30 723#define R92C_RF_TXPA_G(i) (0x31 + (i)) 724 725/* Bits for R92C_RF_AC. */ 726#define R92C_RF_AC_MODE_M 0x70000 727#define R92C_RF_AC_MODE_S 16 728#define R92C_RF_AC_MODE_STANDBY 1 729 730/* Bits for R92C_RF_CHNLBW. */ 731#define R92C_RF_CHNLBW_CHNL_M 0x003ff 732#define R92C_RF_CHNLBW_CHNL_S 0 733#define R92C_RF_CHNLBW_BW20 0x00400 734#define R92C_RF_CHNLBW_LCSTART 0x08000 735 736 737/* 738 * CAM entries. 739 */ 740#define R92C_CAM_ENTRY_COUNT 32 741 742#define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 743#define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 744#define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 745 746/* Bits for R92C_CAM_CTL0(i). */ 747#define R92C_CAM_KEYID_M 0x00000003 748#define R92C_CAM_KEYID_S 0 749#define R92C_CAM_ALGO_M 0x0000001c 750#define R92C_CAM_ALGO_S 2 751#define R92C_CAM_ALGO_NONE 0 752#define R92C_CAM_ALGO_WEP40 1 753#define R92C_CAM_ALGO_TKIP 2 754#define R92C_CAM_ALGO_AES 4 755#define R92C_CAM_ALGO_WEP104 5 756#define R92C_CAM_VALID 0x00008000 757#define R92C_CAM_MACLO_M 0xffff0000 758#define R92C_CAM_MACLO_S 16 759 760/* Rate adaptation modes. */ 761#define R92C_RAID_11GN 1 762#define R92C_RAID_11N 3 763#define R92C_RAID_11BG 4 764#define R92C_RAID_11G 5 /* "pure" 11g */ 765#define R92C_RAID_11B 6 766 767 768/* Macros to access unaligned little-endian memory. */ 769#define LE_READ_2(x) ((x)[0] | (x)[1] << 8) 770#define LE_READ_4(x) ((x)[0] | (x)[1] << 8 | (x)[2] << 16 | (x)[3] << 24) 771 772/* 773 * Macros to access subfields in registers. 774 */ 775/* Mask and Shift (getter). */ 776#define MS(val, field) \ 777 (((val) & field##_M) >> field##_S) 778 779/* Shift and Mask (setter). */ 780#define SM(field, val) \ 781 (((val) << field##_S) & field##_M) 782 783/* Rewrite. */ 784#define RW(var, field, val) \ 785 (((var) & ~field##_M) | SM(field, val)) 786 787/* 788 * Firmware image header. 789 */ 790struct r92c_fw_hdr { 791 /* QWORD0 */ 792 uint16_t signature; 793 uint8_t category; 794 uint8_t function; 795 uint16_t version; 796 uint16_t subversion; 797 /* QWORD1 */ 798 uint8_t month; 799 uint8_t date; 800 uint8_t hour; 801 uint8_t minute; 802 uint16_t ramcodesize; 803 uint16_t reserved2; 804 /* QWORD2 */ 805 uint32_t svnidx; 806 uint32_t reserved3; 807 /* QWORD3 */ 808 uint32_t reserved4; 809 uint32_t reserved5; 810} __packed; 811 812/* 813 * Host to firmware commands. 814 */ 815struct r92c_fw_cmd { 816 uint8_t id; 817#define R92C_CMD_AP_OFFLOAD 0 818#define R92C_CMD_SET_PWRMODE 1 819#define R92C_CMD_JOINBSS_RPT 2 820#define R92C_CMD_RSVD_PAGE 3 821#define R92C_CMD_RSSI 4 822#define R92C_CMD_RSSI_SETTING 5 823#define R92C_CMD_MACID_CONFIG 6 824#define R92C_CMD_MACID_PS_MODE 7 825#define R92C_CMD_P2P_PS_OFFLOAD 8 826#define R92C_CMD_SELECTIVE_SUSPEND 9 827#define R92C_CMD_FLAG_EXT 0x80 828 829 uint8_t msg[5]; 830} __packed; 831 832/* Structure for R92C_CMD_RSSI_SETTING. */ 833struct r92c_fw_cmd_rssi { 834 uint8_t macid; 835 uint8_t reserved; 836 uint8_t pwdb; 837} __packed; 838 839/* Structure for R92C_CMD_MACID_CONFIG. */ 840struct r92c_fw_cmd_macid_cfg { 841 uint32_t mask; 842 uint8_t macid; 843#define URTWN_MACID_BSS 0 844#define URTWN_MACID_BC 4 /* Broadcast. */ 845#define URTWN_MACID_VALID 0x80 846} __packed; 847 848/* 849 * RTL8192CU ROM image. 850 */ 851struct r92c_rom { 852 uint16_t id; /* 0x8192 */ 853 uint8_t reserved1[5]; 854 uint8_t dbg_sel; 855 uint16_t reserved2; 856 uint16_t vid; 857 uint16_t pid; 858 uint8_t usb_opt; 859 uint8_t ep_setting; 860 uint16_t reserved3; 861 uint8_t usb_phy; 862 uint8_t reserved4[3]; 863 uint8_t macaddr[6]; 864 uint8_t string[61]; /* "Realtek" */ 865 uint8_t subcustomer_id; 866 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 867 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 868 uint8_t ht40_2s_tx_pwr_diff[3]; 869 uint8_t ht20_tx_pwr_diff[3]; 870 uint8_t ofdm_tx_pwr_diff[3]; 871 uint8_t ht40_max_pwr[3]; 872 uint8_t ht20_max_pwr[3]; 873 uint8_t xtal_calib; 874 uint8_t tssi[R92C_MAX_CHAINS]; 875 uint8_t thermal_meter; 876 uint8_t rf_opt1; 877#define R92C_ROM_RF1_REGULATORY_M 0x07 878#define R92C_ROM_RF1_REGULATORY_S 0 879#define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 880#define R92C_ROM_RF1_BOARD_TYPE_S 5 881#define R92C_BOARD_TYPE_DONGLE 0 882#define R92C_BOARD_TYPE_HIGHPA 1 883#define R92C_BOARD_TYPE_MINICARD 2 884#define R92C_BOARD_TYPE_SOLO 3 885#define R92C_BOARD_TYPE_COMBO 4 886 887 uint8_t rf_opt2; 888 uint8_t rf_opt3; 889 uint8_t rf_opt4; 890 uint8_t channel_plan; 891 uint8_t version; 892 uint8_t curstomer_id; 893} __packed; 894 895/* Rx MAC descriptor. */ 896struct r92c_rx_stat { 897 uint32_t rxdw0; 898#define R92C_RXDW0_PKTLEN_M 0x00003fff 899#define R92C_RXDW0_PKTLEN_S 0 900#define R92C_RXDW0_CRCERR 0x00004000 901#define R92C_RXDW0_ICVERR 0x00008000 902#define R92C_RXDW0_INFOSZ_M 0x000f0000 903#define R92C_RXDW0_INFOSZ_S 16 904#define R92C_RXDW0_QOS 0x00800000 905#define R92C_RXDW0_SHIFT_M 0x03000000 906#define R92C_RXDW0_SHIFT_S 24 907#define R92C_RXDW0_PHYST 0x04000000 908#define R92C_RXDW0_DECRYPTED 0x08000000 909 910 uint32_t rxdw1; 911 uint32_t rxdw2; 912#define R92C_RXDW2_PKTCNT_M 0x00ff0000 913#define R92C_RXDW2_PKTCNT_S 16 914 915 uint32_t rxdw3; 916#define R92C_RXDW3_RATE_M 0x0000003f 917#define R92C_RXDW3_RATE_S 0 918#define R92C_RXDW3_HT 0x00000040 919#define R92C_RXDW3_HTC 0x00000400 920 921 uint32_t rxdw4; 922 uint32_t rxdw5; 923} __packed __attribute__((aligned(4))); 924 925/* Rx PHY descriptor. */ 926struct r92c_rx_phystat { 927 uint32_t phydw0; 928 uint32_t phydw1; 929 uint32_t phydw2; 930 uint32_t phydw3; 931 uint32_t phydw4; 932 uint32_t phydw5; 933 uint32_t phydw6; 934 uint32_t phydw7; 935} __packed __attribute__((aligned(4))); 936 937/* Rx PHY CCK descriptor. */ 938struct r92c_rx_cck { 939 uint8_t adc_pwdb[4]; 940 uint8_t sq_rpt; 941 uint8_t agc_rpt; 942} __packed; 943 944/* Tx MAC descriptor. */ 945struct r92c_tx_desc { 946 uint32_t txdw0; 947#define R92C_TXDW0_PKTLEN_M 0x0000ffff 948#define R92C_TXDW0_PKTLEN_S 0 949#define R92C_TXDW0_OFFSET_M 0x00ff0000 950#define R92C_TXDW0_OFFSET_S 16 951#define R92C_TXDW0_BMCAST 0x01000000 952#define R92C_TXDW0_LSG 0x04000000 953#define R92C_TXDW0_FSG 0x08000000 954#define R92C_TXDW0_OWN 0x80000000 955 956 uint32_t txdw1; 957#define R92C_TXDW1_MACID_M 0x0000001f 958#define R92C_TXDW1_MACID_S 0 959#define R92C_TXDW1_AGGEN 0x00000020 960#define R92C_TXDW1_AGGBK 0x00000040 961#define R92C_TXDW1_QSEL_M 0x00001f00 962#define R92C_TXDW1_QSEL_S 8 963#define R92C_TXDW1_QSEL_BE 0x00 964#define R92C_TXDW1_QSEL_MGNT 0x12 965#define R92C_TXDW1_RAID_M 0x000f0000 966#define R92C_TXDW1_RAID_S 16 967#define R92C_TXDW1_CIPHER_M 0x00c00000 968#define R92C_TXDW1_CIPHER_S 22 969#define R92C_TXDW1_CIPHER_NONE 0 970#define R92C_TXDW1_CIPHER_RC4 1 971#define R92C_TXDW1_CIPHER_AES 3 972#define R92C_TXDW1_PKTOFF_M 0x7c000000 973#define R92C_TXDW1_PKTOFF_S 26 974 975 uint32_t txdw2; 976 uint16_t txdw3; 977 uint16_t txdseq; 978 979 uint32_t txdw4; 980#define R92C_TXDW4_RTSRATE_M 0x0000003f 981#define R92C_TXDW4_RTSRATE_S 0 982#define R92C_TXDW4_QOS 0x00000040 983#define R92C_TXDW4_HWSEQ 0x00000080 984#define R92C_TXDW4_DRVRATE 0x00000100 985#define R92C_TXDW4_CTS2SELF 0x00000800 986#define R92C_TXDW4_RTSEN 0x00001000 987#define R92C_TXDW4_HWRTSEN 0x00002000 988#define R92C_TXDW4_SCO_M 0x003f0000 989#define R92C_TXDW4_SCO_S 20 990#define R92C_TXDW4_SCO_SCA 1 991#define R92C_TXDW4_SCO_SCB 2 992#define R92C_TXDW4_40MHZ 0x02000000 993 994 uint32_t txdw5; 995#define R92C_TXDW5_DATARATE_M 0x0000003f 996#define R92C_TXDW5_DATARATE_S 0 997#define R92C_TXDW5_SGI 0x00000040 998#define R92C_TXDW5_AGGNUM_M 0xff000000 999#define R92C_TXDW5_AGGNUM_S 24 1000 1001 uint32_t txdw6; 1002 uint16_t txdsum; 1003 uint16_t pad; 1004} __packed __attribute__((aligned(4))); 1005 1006 1007/* 1008 * Driver definitions. 1009 */ 1010#define URTWN_RX_LIST_COUNT 1 1011#define URTWN_TX_LIST_COUNT 8 1012#define URTWN_HOST_CMD_RING_COUNT 32 1013 1014#define URTWN_RXBUFSZ (16 * 1024) 1015#define URTWN_TXBUFSZ (sizeof(struct r92c_tx_desc) + IEEE80211_MAX_LEN) 1016#define URTWN_RX_DESC_SIZE (sizeof(struct r92c_rx_stat)) 1017#define URTWN_TX_DESC_SIZE (sizeof(struct r92c_tx_desc)) 1018 1019#define URTWN_RIDX_COUNT 28 1020 1021#define URTWN_TX_TIMEOUT 5000 /* ms */ 1022 1023#define URTWN_LED_LINK 0 1024#define URTWN_LED_DATA 1 1025 1026struct urtwn_rx_radiotap_header { 1027 struct ieee80211_radiotap_header wr_ihdr; 1028 uint8_t wr_flags; 1029 uint8_t wr_rate; 1030 uint16_t wr_chan_freq; 1031 uint16_t wr_chan_flags; 1032 uint8_t wr_dbm_antsignal; 1033} __packed __aligned(8); 1034 1035#define URTWN_RX_RADIOTAP_PRESENT \ 1036 (1 << IEEE80211_RADIOTAP_FLAGS | \ 1037 1 << IEEE80211_RADIOTAP_RATE | \ 1038 1 << IEEE80211_RADIOTAP_CHANNEL | \ 1039 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 1040 1041struct urtwn_tx_radiotap_header { 1042 struct ieee80211_radiotap_header wt_ihdr; 1043 uint8_t wt_flags; 1044 uint16_t wt_chan_freq; 1045 uint16_t wt_chan_flags; 1046} __packed __aligned(8); 1047 1048#define URTWN_TX_RADIOTAP_PRESENT \ 1049 (1 << IEEE80211_RADIOTAP_FLAGS | \ 1050 1 << IEEE80211_RADIOTAP_CHANNEL) 1051 1052struct urtwn_softc; 1053 1054struct urtwn_data { 1055 struct urtwn_softc *sc; 1056 uint8_t *buf; 1057 uint16_t buflen; 1058 struct mbuf *m; 1059 struct ieee80211_node *ni; 1060 STAILQ_ENTRY(urtwn_data) next; 1061}; 1062typedef STAILQ_HEAD(, urtwn_data) urtwn_datahead; 1063 1064struct urtwn_cmdq { 1065 void *arg0; 1066 void *arg1; 1067 void (*func)(void *); 1068 struct ieee80211_key *k; 1069 struct ieee80211_key key; 1070 uint8_t mac[IEEE80211_ADDR_LEN]; 1071 uint8_t wcid; 1072}; 1073 1074struct urtwn_fw_info { 1075 const uint8_t *data; 1076 size_t size; 1077}; 1078 1079struct urtwn_vap { 1080 struct ieee80211vap vap; 1081 struct ieee80211_beacon_offsets bo; 1082 1083 int (*newstate)(struct ieee80211vap *, 1084 enum ieee80211_state, int); 1085}; 1086#define URTWN_VAP(vap) ((struct urtwn_vap *)(vap)) 1087 1088struct urtwn_host_cmd { 1089 void (*cb)(struct urtwn_softc *, void *); 1090 uint8_t data[256]; 1091}; 1092 1093struct urtwn_cmd_newstate { 1094 enum ieee80211_state state; 1095 int arg; 1096}; 1097 1098struct urtwn_cmd_key { 1099 struct ieee80211_key key; 1100 uint16_t associd; 1101}; 1102 1103enum { 1104 URTWN_BULK_RX, 1105 URTWN_BULK_TX_BE, /* = WME_AC_BE */ 1106 URTWN_BULK_TX_BK, /* = WME_AC_BK */ 1107 URTWN_BULK_TX_VI, /* = WME_AC_VI */ 1108 URTWN_BULK_TX_VO, /* = WME_AC_VI */ 1109 URTWN_N_TRANSFER = 5, 1110}; 1111 1112#define URTWN_EP_QUEUES URTWN_BULK_RX 1113 1114struct urtwn_softc { 1115 struct ifnet *sc_ifp; 1116 device_t sc_dev; 1117 struct usb_device *sc_udev; 1118 1119 int ac2idx[WME_NUM_AC]; 1120 u_int sc_flags; 1121#define URTWN_FLAG_CCK_HIPWR 0x01 1122 1123 u_int chip; 1124#define URTWN_CHIP_92C 0x01 1125#define URTWN_CHIP_92C_1T2R 0x02 1126#define URTWN_CHIP_UMC 0x04 1127#define URTWN_CHIP_UMC_A_CUT 0x08 1128 1129 uint8_t board_type; 1130 uint8_t regulatory; 1131 uint8_t pa_setting; 1132 int avg_pwdb; 1133 int thcal_state; 1134 int thcal_lctemp; 1135 int ntxchains; 1136 int nrxchains; 1137 int ledlink; 1138 int sc_txtimer; 1139 1140 int fwcur; 1141 struct urtwn_data sc_rx[URTWN_RX_LIST_COUNT]; 1142 urtwn_datahead sc_rx_active; 1143 urtwn_datahead sc_rx_inactive; 1144 struct urtwn_data sc_tx[URTWN_TX_LIST_COUNT]; 1145 urtwn_datahead sc_tx_active; 1146 urtwn_datahead sc_tx_inactive; 1147 urtwn_datahead sc_tx_pending; 1148 1149 const char *fwname; 1150 const struct firmware *fw_fp; 1151 struct urtwn_fw_info fw; 1152 void *fw_virtaddr; 1153 1154 struct r92c_rom rom; 1155 uint8_t sc_bssid[IEEE80211_ADDR_LEN]; 1156 1157 struct callout sc_watchdog_ch; 1158 struct mtx sc_mtx; 1159 1160/* need to be power of 2, otherwise URTWN_CMDQ_GET fails */ 1161#define URTWN_CMDQ_MAX 16 1162#define URTWN_CMDQ_MASQ (URTWN_CMDQ_MAX - 1) 1163 struct urtwn_cmdq cmdq[URTWN_CMDQ_MAX]; 1164 struct task cmdq_task; 1165 uint32_t cmdq_store; 1166 uint8_t cmdq_exec; 1167 uint8_t cmdq_run; 1168 uint8_t cmdq_key_set; 1169#define URTWN_CMDQ_ABORT 0 1170#define URTWN_CMDQ_GO 1 1171 1172 uint32_t rf_chnlbw[R92C_MAX_CHAINS]; 1173 struct usb_xfer *sc_xfer[URTWN_N_TRANSFER]; 1174 1175 struct urtwn_rx_radiotap_header sc_rxtap; 1176 int sc_rxtap_len; 1177 1178 struct urtwn_tx_radiotap_header sc_txtap; 1179 int sc_txtap_len; 1180}; 1181 1182#define URTWN_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 1183#define URTWN_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 1184#define URTWN_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 1185 1186/* 1187 * MAC initialization values. 1188 */ 1189static const struct { 1190 uint16_t reg; 1191 uint8_t val; 1192} rtl8192cu_mac[] = { 1193 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1194 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1195 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1196 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1197 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1198 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1199 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1200 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 }, 1201 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff }, 1202 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1203 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1204 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1205 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1206 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1207 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1208 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x40 }, { 0x547, 0x00 }, 1209 { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, { 0x55a, 0x02 }, 1210 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1211 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0e }, { 0x63e, 0x0a }, 1212 { 0x63f, 0x0e }, { 0x66e, 0x05 }, { 0x700, 0x21 }, { 0x701, 0x43 }, 1213 { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, 1214 { 0x70a, 0x65 }, { 0x70b, 0x87 } 1215}; 1216 1217/* 1218 * Baseband initialization values. 1219 */ 1220struct urtwn_bb_prog { 1221 int count; 1222 const uint16_t *regs; 1223 const uint32_t *vals; 1224 int agccount; 1225 const uint32_t *agcvals; 1226}; 1227 1228/* 1229 * RTL8192CU and RTL8192CE-VAU. 1230 */ 1231static const uint16_t rtl8192ce_bb_regs[] = { 1232 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 1233 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1234 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 1235 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 1236 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 1237 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1238 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, 1239 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 1240 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 1241 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 1242 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 1243 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1244 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 1245 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 1246 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 1247 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 1248 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 1249 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 1250 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 1251 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1252 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 1253}; 1254 1255static const uint32_t rtl8192ce_bb_vals[] = { 1256 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1257 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1258 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1259 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1260 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1261 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1262 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1263 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1264 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1265 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1266 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1267 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1268 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1269 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1270 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1271 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1272 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1273 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1274 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1275 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1276 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1277 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1278 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1279 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1280 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1281 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1282 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1283 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1284 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1285 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1286 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1287 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1288 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1289 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1290 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1291 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1292 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1293 0x00000000, 0x00000300 1294}; 1295 1296static const uint32_t rtl8192ce_agc_vals[] = { 1297 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1298 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1299 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1300 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1301 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1302 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1303 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1304 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1305 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1306 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1307 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1308 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1309 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1310 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1311 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1312 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1313 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1314 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1315 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1316 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1317 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1318 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1319 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1320 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1321 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1322 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1323 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1324 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1325 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1326 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1327 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1328 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1329}; 1330 1331static const struct urtwn_bb_prog rtl8192ce_bb_prog = { 1332 nitems(rtl8192ce_bb_regs), 1333 rtl8192ce_bb_regs, 1334 rtl8192ce_bb_vals, 1335 nitems(rtl8192ce_agc_vals), 1336 rtl8192ce_agc_vals 1337}; 1338 1339/* 1340 * RTL8188CU. 1341 */ 1342static const uint32_t rtl8192cu_bb_vals[] = { 1343 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1344 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1345 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1346 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1347 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1348 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1349 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1350 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1351 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1352 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1353 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1354 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1355 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1356 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1357 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1358 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1359 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1360 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, 1361 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, 1362 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1363 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1364 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1365 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1366 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1367 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1368 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1369 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1370 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1371 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1372 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1373 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1374 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1375 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1376 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1377 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1378 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1379 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1380 0x00000000, 0x00000300 1381}; 1382 1383static const struct urtwn_bb_prog rtl8192cu_bb_prog = { 1384 nitems(rtl8192ce_bb_regs), 1385 rtl8192ce_bb_regs, 1386 rtl8192cu_bb_vals, 1387 nitems(rtl8192ce_agc_vals), 1388 rtl8192ce_agc_vals 1389}; 1390 1391/* 1392 * RTL8188CE-VAU. 1393 */ 1394static const uint32_t rtl8188ce_bb_vals[] = { 1395 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1396 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1397 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1398 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1399 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1400 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1401 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1402 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1403 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1404 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1405 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1406 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1407 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1408 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1409 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1410 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1411 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1412 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1413 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1414 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1415 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1416 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1417 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1418 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1419 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1420 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1421 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1422 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1423 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1424 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1425 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1426 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1427 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1428 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1429 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1430 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1431 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1432 0x00000000, 0x00000300 1433}; 1434 1435static const uint32_t rtl8188ce_agc_vals[] = { 1436 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1437 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1438 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1439 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1440 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1441 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1442 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1443 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1444 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1445 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1446 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1447 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1448 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1449 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1450 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1451 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1452 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1453 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1454 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1455 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1456 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1457 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1458 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1459 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1460 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1461 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1462 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1463 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1464 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1465 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1466 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1467 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1468}; 1469 1470static const struct urtwn_bb_prog rtl8188ce_bb_prog = { 1471 nitems(rtl8192ce_bb_regs), 1472 rtl8192ce_bb_regs, 1473 rtl8188ce_bb_vals, 1474 nitems(rtl8188ce_agc_vals), 1475 rtl8188ce_agc_vals 1476}; 1477 1478static const uint32_t rtl8188cu_bb_vals[] = { 1479 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1480 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1481 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1482 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1483 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1484 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1485 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1486 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1487 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1488 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1489 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1490 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1491 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1492 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1493 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1494 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1495 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1496 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1497 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1498 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1499 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1500 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1501 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1502 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1503 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1504 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1505 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1506 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1507 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1508 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1509 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1510 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1511 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1512 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1513 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1514 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1515 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1516 0x00000000, 0x00000300 1517}; 1518 1519static const struct urtwn_bb_prog rtl8188cu_bb_prog = { 1520 nitems(rtl8192ce_bb_regs), 1521 rtl8192ce_bb_regs, 1522 rtl8188cu_bb_vals, 1523 nitems(rtl8188ce_agc_vals), 1524 rtl8188ce_agc_vals 1525}; 1526 1527/* 1528 * RTL8188RU. 1529 */ 1530static const uint16_t rtl8188ru_bb_regs[] = { 1531 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 1532 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 1533 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1534 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 1535 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 1536 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 1537 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 1538 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 1539 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 1540 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 1541 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 1542 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 1543 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1544 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 1545 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 1546 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 1547 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 1548 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 1549 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 1550 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 1551 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 1552}; 1553 1554static const uint32_t rtl8188ru_bb_vals[] = { 1555 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, 1556 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 1557 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, 1558 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, 1559 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1560 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 1561 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, 1562 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 1563 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, 1564 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 1565 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 1566 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, 1567 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 1568 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, 1569 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 1570 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 1571 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, 1572 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, 1573 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, 1574 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, 1575 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, 1576 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, 1577 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1578 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, 1579 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 1580 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 1581 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, 1582 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 1583 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 1584 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 1585 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 1586 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 1587 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 1588 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 1589 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1590 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 1591 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 1592 0x31555448, 0x00000003, 0x00000000, 0x00000300 1593}; 1594 1595static const uint32_t rtl8188ru_agc_vals[] = { 1596 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1597 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 1598 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, 1599 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, 1600 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, 1601 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, 1602 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 1603 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1604 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1605 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1606 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1607 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1608 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1609 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1610 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, 1611 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, 1612 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, 1613 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, 1614 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 1615 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, 1616 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1617 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1618 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1619 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1620 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1621 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1622 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1623 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1624 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1625 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1626 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1627 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1628}; 1629 1630static const struct urtwn_bb_prog rtl8188ru_bb_prog = { 1631 nitems(rtl8188ru_bb_regs), 1632 rtl8188ru_bb_regs, 1633 rtl8188ru_bb_vals, 1634 nitems(rtl8188ru_agc_vals), 1635 rtl8188ru_agc_vals 1636}; 1637 1638/* 1639 * RF initialization values. 1640 */ 1641struct urtwn_rf_prog { 1642 int count; 1643 const uint8_t *regs; 1644 const uint32_t *vals; 1645}; 1646 1647/* 1648 * RTL8192CU and RTL8192CE-VAU. 1649 */ 1650static const uint8_t rtl8192ce_rf1_regs[] = { 1651 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1652 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 1653 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 1654 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1655 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 1656 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 1657 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 1658 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1659 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 1660 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 1661 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 1662 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 1663 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 1664}; 1665 1666static const uint32_t rtl8192ce_rf1_vals[] = { 1667 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1668 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1669 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1670 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1671 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1672 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1673 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1674 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1675 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1676 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1677 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1678 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1679 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1680 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1681 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1682 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 1683 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 1684 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1685 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1686 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1687 0x30159 1688}; 1689 1690static const uint8_t rtl8192ce_rf2_regs[] = { 1691 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1692 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 1693 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 1694 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 1695}; 1696 1697static const uint32_t rtl8192ce_rf2_vals[] = { 1698 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1699 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 1700 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 1701 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, 1702 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 1703 0xe0330, 0xa0330, 0x60330, 0x20330 1704}; 1705 1706static const struct urtwn_rf_prog rtl8192ce_rf_prog[] = { 1707 { 1708 nitems(rtl8192ce_rf1_regs), 1709 rtl8192ce_rf1_regs, 1710 rtl8192ce_rf1_vals 1711 }, 1712 { 1713 nitems(rtl8192ce_rf2_regs), 1714 rtl8192ce_rf2_regs, 1715 rtl8192ce_rf2_vals 1716 } 1717}; 1718 1719/* 1720 * RTL8188CE-VAU. 1721 */ 1722static const uint32_t rtl8188ce_rf_vals[] = { 1723 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1724 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1725 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1726 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, 1727 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1728 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1729 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1730 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1731 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1732 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1733 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1734 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1735 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1736 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1737 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1738 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1739 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1740 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1741 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1742 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1743 0x30159 1744}; 1745 1746static const struct urtwn_rf_prog rtl8188ce_rf_prog[] = { 1747 { 1748 nitems(rtl8192ce_rf1_regs), 1749 rtl8192ce_rf1_regs, 1750 rtl8188ce_rf_vals 1751 } 1752}; 1753 1754 1755/* 1756 * RTL8188CU. 1757 */ 1758static const uint32_t rtl8188cu_rf_vals[] = { 1759 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1760 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1761 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1762 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1763 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1764 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1765 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1766 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1767 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1768 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1769 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1770 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1771 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1772 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1773 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1774 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1775 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1776 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 1777 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1778 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1779 0x30159 1780}; 1781 1782static const struct urtwn_rf_prog rtl8188cu_rf_prog[] = { 1783 { 1784 nitems(rtl8192ce_rf1_regs), 1785 rtl8192ce_rf1_regs, 1786 rtl8188cu_rf_vals 1787 } 1788}; 1789 1790/* 1791 * RTL8188RU. 1792 */ 1793static const uint32_t rtl8188ru_rf_vals[] = { 1794 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 1795 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 1796 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1797 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, 1798 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1799 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1800 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1801 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1802 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1803 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1804 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1805 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1806 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1807 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1808 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, 1809 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, 1810 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 1811 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 1812 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1813 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1814 0x30159 1815}; 1816 1817static const struct urtwn_rf_prog rtl8188ru_rf_prog[] = { 1818 { 1819 nitems(rtl8192ce_rf1_regs), 1820 rtl8192ce_rf1_regs, 1821 rtl8188ru_rf_vals 1822 } 1823}; 1824 1825struct urtwn_txpwr { 1826 uint8_t pwr[3][28]; 1827}; 1828 1829/* 1830 * Per RF chain/group/rate Tx gain values. 1831 */ 1832static const struct urtwn_txpwr rtl8192cu_txagc[] = { 1833 { { /* Chain 0. */ 1834 { /* Group 0. */ 1835 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1836 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */ 1837 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */ 1838 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */ 1839 }, 1840 { /* Group 1. */ 1841 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1842 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 1843 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1844 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1845 }, 1846 { /* Group 2. */ 1847 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1848 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 1849 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1850 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1851 } 1852 } }, 1853 { { /* Chain 1. */ 1854 { /* Group 0. */ 1855 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1856 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 1857 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1858 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1859 }, 1860 { /* Group 1. */ 1861 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1862 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 1863 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1864 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1865 }, 1866 { /* Group 2. */ 1867 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1868 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 1869 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1870 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1871 } 1872 } } 1873}; 1874 1875static const struct urtwn_txpwr rtl8188ru_txagc[] = { 1876 { { /* Chain 0. */ 1877 { /* Group 0. */ 1878 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1879 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */ 1880 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */ 1881 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */ 1882 }, 1883 { /* Group 1. */ 1884 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1885 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 1886 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1887 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1888 }, 1889 { /* Group 2. */ 1890 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1891 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 1892 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1893 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1894 } 1895 } } 1896}; 1897