1/* $FreeBSD$ */ 2/*- 3 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * This file contains the driver for the AT91 series USB Device 29 * Controller 30 */ 31 32/* 33 * Thanks to "David Brownell" for helping out regarding the hardware 34 * endpoint profiles. 35 */ 36 37/* 38 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is 39 * reset. 40 * 41 * NOTE: When the chip detects BUS-reset it will also reset the 42 * endpoints, Function-address and more. 43 */ 44 45#ifdef USB_GLOBAL_INCLUDE_FILE 46#include USB_GLOBAL_INCLUDE_FILE 47#else 48#include <sys/stdint.h> 49#include <sys/stddef.h> 50#include <sys/param.h> 51#include <sys/queue.h> 52#include <sys/types.h> 53#include <sys/systm.h> 54#include <sys/kernel.h> 55#include <sys/bus.h> 56#include <sys/module.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/condvar.h> 60#include <sys/sysctl.h> 61#include <sys/sx.h> 62#include <sys/unistd.h> 63#include <sys/callout.h> 64#include <sys/malloc.h> 65#include <sys/priv.h> 66 67#include <dev/usb/usb.h> 68#include <dev/usb/usbdi.h> 69 70#define USB_DEBUG_VAR at91dcidebug 71 72#include <dev/usb/usb_core.h> 73#include <dev/usb/usb_debug.h> 74#include <dev/usb/usb_busdma.h> 75#include <dev/usb/usb_process.h> 76#include <dev/usb/usb_transfer.h> 77#include <dev/usb/usb_device.h> 78#include <dev/usb/usb_hub.h> 79#include <dev/usb/usb_util.h> 80 81#include <dev/usb/usb_controller.h> 82#include <dev/usb/usb_bus.h> 83#endif /* USB_GLOBAL_INCLUDE_FILE */ 84 85#include <dev/usb/controller/at91dci.h> 86 87#define AT9100_DCI_BUS2SC(bus) \ 88 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \ 89 ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus)))) 90 91#define AT9100_DCI_PC2SC(pc) \ 92 AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 93 94#ifdef USB_DEBUG 95static int at91dcidebug = 0; 96 97static SYSCTL_NODE(_hw_usb, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci"); 98SYSCTL_INT(_hw_usb_at91dci, OID_AUTO, debug, CTLFLAG_RW, 99 &at91dcidebug, 0, "at91dci debug level"); 100#endif 101 102#define AT9100_DCI_INTR_ENDPT 1 103 104/* prototypes */ 105 106struct usb_bus_methods at91dci_bus_methods; 107struct usb_pipe_methods at91dci_device_bulk_methods; 108struct usb_pipe_methods at91dci_device_ctrl_methods; 109struct usb_pipe_methods at91dci_device_intr_methods; 110struct usb_pipe_methods at91dci_device_isoc_fs_methods; 111 112static at91dci_cmd_t at91dci_setup_rx; 113static at91dci_cmd_t at91dci_data_rx; 114static at91dci_cmd_t at91dci_data_tx; 115static at91dci_cmd_t at91dci_data_tx_sync; 116static void at91dci_device_done(struct usb_xfer *, usb_error_t); 117static void at91dci_do_poll(struct usb_bus *); 118static void at91dci_standard_done(struct usb_xfer *); 119static void at91dci_root_intr(struct at91dci_softc *sc); 120 121/* 122 * NOTE: Some of the bits in the CSR register have inverse meaning so 123 * we need a helper macro when acknowledging events: 124 */ 125#define AT91_CSR_ACK(csr, what) do { \ 126 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \ 127 AT91_UDP_CSR_TXPKTRDY| \ 128 AT91_UDP_CSR_RXBYTECNT) ^ (what));\ 129 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \ 130 AT91_UDP_CSR_RX_DATA_BK1| \ 131 AT91_UDP_CSR_TXCOMP| \ 132 AT91_UDP_CSR_RXSETUP| \ 133 AT91_UDP_CSR_STALLSENT) ^ (what)); \ 134} while (0) 135 136/* 137 * Here is a list of what the chip supports. 138 * Probably it supports more than listed here! 139 */ 140static const struct usb_hw_ep_profile 141 at91dci_ep_profile[AT91_UDP_EP_MAX] = { 142 143 [0] = { 144 .max_in_frame_size = 8, 145 .max_out_frame_size = 8, 146 .is_simplex = 1, 147 .support_control = 1, 148 }, 149 [1] = { 150 .max_in_frame_size = 64, 151 .max_out_frame_size = 64, 152 .is_simplex = 1, 153 .support_multi_buffer = 1, 154 .support_bulk = 1, 155 .support_interrupt = 1, 156 .support_isochronous = 1, 157 .support_in = 1, 158 .support_out = 1, 159 }, 160 [2] = { 161 .max_in_frame_size = 64, 162 .max_out_frame_size = 64, 163 .is_simplex = 1, 164 .support_multi_buffer = 1, 165 .support_bulk = 1, 166 .support_interrupt = 1, 167 .support_isochronous = 1, 168 .support_in = 1, 169 .support_out = 1, 170 }, 171 [3] = { 172 /* can also do BULK */ 173 .max_in_frame_size = 8, 174 .max_out_frame_size = 8, 175 .is_simplex = 1, 176 .support_interrupt = 1, 177 .support_in = 1, 178 .support_out = 1, 179 }, 180 [4] = { 181 .max_in_frame_size = 256, 182 .max_out_frame_size = 256, 183 .is_simplex = 1, 184 .support_multi_buffer = 1, 185 .support_bulk = 1, 186 .support_interrupt = 1, 187 .support_isochronous = 1, 188 .support_in = 1, 189 .support_out = 1, 190 }, 191 [5] = { 192 .max_in_frame_size = 256, 193 .max_out_frame_size = 256, 194 .is_simplex = 1, 195 .support_multi_buffer = 1, 196 .support_bulk = 1, 197 .support_interrupt = 1, 198 .support_isochronous = 1, 199 .support_in = 1, 200 .support_out = 1, 201 }, 202}; 203 204static void 205at91dci_get_hw_ep_profile(struct usb_device *udev, 206 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 207{ 208 if (ep_addr < AT91_UDP_EP_MAX) { 209 *ppf = (at91dci_ep_profile + ep_addr); 210 } else { 211 *ppf = NULL; 212 } 213} 214 215static void 216at91dci_clocks_on(struct at91dci_softc *sc) 217{ 218 if (sc->sc_flags.clocks_off && 219 sc->sc_flags.port_powered) { 220 221 DPRINTFN(5, "\n"); 222 223 if (sc->sc_clocks_on) { 224 (sc->sc_clocks_on) (sc->sc_clocks_arg); 225 } 226 sc->sc_flags.clocks_off = 0; 227 228 /* enable Transceiver */ 229 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0); 230 } 231} 232 233static void 234at91dci_clocks_off(struct at91dci_softc *sc) 235{ 236 if (!sc->sc_flags.clocks_off) { 237 238 DPRINTFN(5, "\n"); 239 240 /* disable Transceiver */ 241 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS); 242 243 if (sc->sc_clocks_off) { 244 (sc->sc_clocks_off) (sc->sc_clocks_arg); 245 } 246 sc->sc_flags.clocks_off = 1; 247 } 248} 249 250static void 251at91dci_pull_up(struct at91dci_softc *sc) 252{ 253 /* pullup D+, if possible */ 254 255 if (!sc->sc_flags.d_pulled_up && 256 sc->sc_flags.port_powered) { 257 sc->sc_flags.d_pulled_up = 1; 258 (sc->sc_pull_up) (sc->sc_pull_arg); 259 } 260} 261 262static void 263at91dci_pull_down(struct at91dci_softc *sc) 264{ 265 /* pulldown D+, if possible */ 266 267 if (sc->sc_flags.d_pulled_up) { 268 sc->sc_flags.d_pulled_up = 0; 269 (sc->sc_pull_down) (sc->sc_pull_arg); 270 } 271} 272 273static void 274at91dci_wakeup_peer(struct at91dci_softc *sc) 275{ 276 if (!(sc->sc_flags.status_suspend)) { 277 return; 278 } 279 280 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR); 281 282 /* wait 8 milliseconds */ 283 /* Wait for reset to complete. */ 284 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 285 286 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0); 287} 288 289static void 290at91dci_set_address(struct at91dci_softc *sc, uint8_t addr) 291{ 292 DPRINTFN(5, "addr=%d\n", addr); 293 294 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr | 295 AT91_UDP_FADDR_EN); 296} 297 298static uint8_t 299at91dci_setup_rx(struct at91dci_td *td) 300{ 301 struct at91dci_softc *sc; 302 struct usb_device_request req; 303 uint32_t csr; 304 uint32_t temp; 305 uint16_t count; 306 307 /* read out FIFO status */ 308 csr = bus_space_read_4(td->io_tag, td->io_hdl, 309 td->status_reg); 310 311 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 312 313 temp = csr; 314 temp &= (AT91_UDP_CSR_RX_DATA_BK0 | 315 AT91_UDP_CSR_RX_DATA_BK1 | 316 AT91_UDP_CSR_STALLSENT | 317 AT91_UDP_CSR_RXSETUP | 318 AT91_UDP_CSR_TXCOMP); 319 320 if (!(csr & AT91_UDP_CSR_RXSETUP)) { 321 goto not_complete; 322 } 323 /* clear did stall */ 324 td->did_stall = 0; 325 326 /* get the packet byte count */ 327 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 328 329 /* verify data length */ 330 if (count != td->remainder) { 331 DPRINTFN(0, "Invalid SETUP packet " 332 "length, %d bytes\n", count); 333 goto not_complete; 334 } 335 if (count != sizeof(req)) { 336 DPRINTFN(0, "Unsupported SETUP packet " 337 "length, %d bytes\n", count); 338 goto not_complete; 339 } 340 /* receive data */ 341 bus_space_read_multi_1(td->io_tag, td->io_hdl, 342 td->fifo_reg, (void *)&req, sizeof(req)); 343 344 /* copy data into real buffer */ 345 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 346 347 td->offset = sizeof(req); 348 td->remainder = 0; 349 350 /* get pointer to softc */ 351 sc = AT9100_DCI_PC2SC(td->pc); 352 353 /* sneak peek the set address */ 354 if ((req.bmRequestType == UT_WRITE_DEVICE) && 355 (req.bRequest == UR_SET_ADDRESS)) { 356 sc->sc_dv_addr = req.wValue[0] & 0x7F; 357 } else { 358 sc->sc_dv_addr = 0xFF; 359 } 360 361 /* sneak peek the endpoint direction */ 362 if (req.bmRequestType & UE_DIR_IN) { 363 csr |= AT91_UDP_CSR_DIR; 364 } else { 365 csr &= ~AT91_UDP_CSR_DIR; 366 } 367 368 /* write the direction of the control transfer */ 369 AT91_CSR_ACK(csr, temp); 370 bus_space_write_4(td->io_tag, td->io_hdl, 371 td->status_reg, csr); 372 return (0); /* complete */ 373 374not_complete: 375 /* abort any ongoing transfer */ 376 if (!td->did_stall) { 377 DPRINTFN(5, "stalling\n"); 378 temp |= AT91_UDP_CSR_FORCESTALL; 379 td->did_stall = 1; 380 } 381 382 /* clear interrupts, if any */ 383 if (temp) { 384 DPRINTFN(5, "clearing 0x%08x\n", temp); 385 AT91_CSR_ACK(csr, temp); 386 bus_space_write_4(td->io_tag, td->io_hdl, 387 td->status_reg, csr); 388 } 389 return (1); /* not complete */ 390 391} 392 393static uint8_t 394at91dci_data_rx(struct at91dci_td *td) 395{ 396 struct usb_page_search buf_res; 397 uint32_t csr; 398 uint32_t temp; 399 uint16_t count; 400 uint8_t to; 401 uint8_t got_short; 402 403 to = 2; /* don't loop forever! */ 404 got_short = 0; 405 406 /* check if any of the FIFO banks have data */ 407repeat: 408 /* read out FIFO status */ 409 csr = bus_space_read_4(td->io_tag, td->io_hdl, 410 td->status_reg); 411 412 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 413 414 if (csr & AT91_UDP_CSR_RXSETUP) { 415 if (td->remainder == 0) { 416 /* 417 * We are actually complete and have 418 * received the next SETUP 419 */ 420 DPRINTFN(5, "faking complete\n"); 421 return (0); /* complete */ 422 } 423 /* 424 * USB Host Aborted the transfer. 425 */ 426 td->error = 1; 427 return (0); /* complete */ 428 } 429 /* Make sure that "STALLSENT" gets cleared */ 430 temp = csr; 431 temp &= AT91_UDP_CSR_STALLSENT; 432 433 /* check status */ 434 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 | 435 AT91_UDP_CSR_RX_DATA_BK1))) { 436 if (temp) { 437 /* write command */ 438 AT91_CSR_ACK(csr, temp); 439 bus_space_write_4(td->io_tag, td->io_hdl, 440 td->status_reg, csr); 441 } 442 return (1); /* not complete */ 443 } 444 /* get the packet byte count */ 445 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 446 447 /* verify the packet byte count */ 448 if (count != td->max_packet_size) { 449 if (count < td->max_packet_size) { 450 /* we have a short packet */ 451 td->short_pkt = 1; 452 got_short = 1; 453 } else { 454 /* invalid USB packet */ 455 td->error = 1; 456 return (0); /* we are complete */ 457 } 458 } 459 /* verify the packet byte count */ 460 if (count > td->remainder) { 461 /* invalid USB packet */ 462 td->error = 1; 463 return (0); /* we are complete */ 464 } 465 while (count > 0) { 466 usbd_get_page(td->pc, td->offset, &buf_res); 467 468 /* get correct length */ 469 if (buf_res.length > count) { 470 buf_res.length = count; 471 } 472 /* receive data */ 473 bus_space_read_multi_1(td->io_tag, td->io_hdl, 474 td->fifo_reg, buf_res.buffer, buf_res.length); 475 476 /* update counters */ 477 count -= buf_res.length; 478 td->offset += buf_res.length; 479 td->remainder -= buf_res.length; 480 } 481 482 /* clear status bits */ 483 if (td->support_multi_buffer) { 484 if (td->fifo_bank) { 485 td->fifo_bank = 0; 486 temp |= AT91_UDP_CSR_RX_DATA_BK1; 487 } else { 488 td->fifo_bank = 1; 489 temp |= AT91_UDP_CSR_RX_DATA_BK0; 490 } 491 } else { 492 temp |= (AT91_UDP_CSR_RX_DATA_BK0 | 493 AT91_UDP_CSR_RX_DATA_BK1); 494 } 495 496 /* write command */ 497 AT91_CSR_ACK(csr, temp); 498 bus_space_write_4(td->io_tag, td->io_hdl, 499 td->status_reg, csr); 500 501 /* 502 * NOTE: We may have to delay a little bit before 503 * proceeding after clearing the DATA_BK bits. 504 */ 505 506 /* check if we are complete */ 507 if ((td->remainder == 0) || got_short) { 508 if (td->short_pkt) { 509 /* we are complete */ 510 return (0); 511 } 512 /* else need to receive a zero length packet */ 513 } 514 if (--to) { 515 goto repeat; 516 } 517 return (1); /* not complete */ 518} 519 520static uint8_t 521at91dci_data_tx(struct at91dci_td *td) 522{ 523 struct usb_page_search buf_res; 524 uint32_t csr; 525 uint32_t temp; 526 uint16_t count; 527 uint8_t to; 528 529 to = 2; /* don't loop forever! */ 530 531repeat: 532 533 /* read out FIFO status */ 534 csr = bus_space_read_4(td->io_tag, td->io_hdl, 535 td->status_reg); 536 537 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 538 539 if (csr & AT91_UDP_CSR_RXSETUP) { 540 /* 541 * The current transfer was aborted 542 * by the USB Host 543 */ 544 td->error = 1; 545 return (0); /* complete */ 546 } 547 /* Make sure that "STALLSENT" gets cleared */ 548 temp = csr; 549 temp &= AT91_UDP_CSR_STALLSENT; 550 551 if (csr & AT91_UDP_CSR_TXPKTRDY) { 552 if (temp) { 553 /* write command */ 554 AT91_CSR_ACK(csr, temp); 555 bus_space_write_4(td->io_tag, td->io_hdl, 556 td->status_reg, csr); 557 } 558 return (1); /* not complete */ 559 } else { 560 /* clear TXCOMP and set TXPKTRDY */ 561 temp |= (AT91_UDP_CSR_TXCOMP | 562 AT91_UDP_CSR_TXPKTRDY); 563 } 564 565 count = td->max_packet_size; 566 if (td->remainder < count) { 567 /* we have a short packet */ 568 td->short_pkt = 1; 569 count = td->remainder; 570 } 571 while (count > 0) { 572 573 usbd_get_page(td->pc, td->offset, &buf_res); 574 575 /* get correct length */ 576 if (buf_res.length > count) { 577 buf_res.length = count; 578 } 579 /* transmit data */ 580 bus_space_write_multi_1(td->io_tag, td->io_hdl, 581 td->fifo_reg, buf_res.buffer, buf_res.length); 582 583 /* update counters */ 584 count -= buf_res.length; 585 td->offset += buf_res.length; 586 td->remainder -= buf_res.length; 587 } 588 589 /* write command */ 590 AT91_CSR_ACK(csr, temp); 591 bus_space_write_4(td->io_tag, td->io_hdl, 592 td->status_reg, csr); 593 594 /* check remainder */ 595 if (td->remainder == 0) { 596 if (td->short_pkt) { 597 return (0); /* complete */ 598 } 599 /* else we need to transmit a short packet */ 600 } 601 if (--to) { 602 goto repeat; 603 } 604 return (1); /* not complete */ 605} 606 607static uint8_t 608at91dci_data_tx_sync(struct at91dci_td *td) 609{ 610 struct at91dci_softc *sc; 611 uint32_t csr; 612 uint32_t temp; 613 614#if 0 615repeat: 616#endif 617 618 /* read out FIFO status */ 619 csr = bus_space_read_4(td->io_tag, td->io_hdl, 620 td->status_reg); 621 622 DPRINTFN(5, "csr=0x%08x\n", csr); 623 624 if (csr & AT91_UDP_CSR_RXSETUP) { 625 DPRINTFN(5, "faking complete\n"); 626 /* Race condition */ 627 return (0); /* complete */ 628 } 629 temp = csr; 630 temp &= (AT91_UDP_CSR_STALLSENT | 631 AT91_UDP_CSR_TXCOMP); 632 633 /* check status */ 634 if (csr & AT91_UDP_CSR_TXPKTRDY) { 635 goto not_complete; 636 } 637 if (!(csr & AT91_UDP_CSR_TXCOMP)) { 638 goto not_complete; 639 } 640 sc = AT9100_DCI_PC2SC(td->pc); 641 if (sc->sc_dv_addr != 0xFF) { 642 /* 643 * The AT91 has a special requirement with regard to 644 * setting the address and that is to write the new 645 * address before clearing TXCOMP: 646 */ 647 at91dci_set_address(sc, sc->sc_dv_addr); 648 } 649 /* write command */ 650 AT91_CSR_ACK(csr, temp); 651 bus_space_write_4(td->io_tag, td->io_hdl, 652 td->status_reg, csr); 653 654 return (0); /* complete */ 655 656not_complete: 657 if (temp) { 658 /* write command */ 659 AT91_CSR_ACK(csr, temp); 660 bus_space_write_4(td->io_tag, td->io_hdl, 661 td->status_reg, csr); 662 } 663 return (1); /* not complete */ 664} 665 666static uint8_t 667at91dci_xfer_do_fifo(struct usb_xfer *xfer) 668{ 669 struct at91dci_softc *sc; 670 struct at91dci_td *td; 671 uint8_t temp; 672 673 DPRINTFN(9, "\n"); 674 675 td = xfer->td_transfer_cache; 676 while (1) { 677 if ((td->func) (td)) { 678 /* operation in progress */ 679 break; 680 } 681 if (((void *)td) == xfer->td_transfer_last) { 682 goto done; 683 } 684 if (td->error) { 685 goto done; 686 } else if (td->remainder > 0) { 687 /* 688 * We had a short transfer. If there is no alternate 689 * next, stop processing ! 690 */ 691 if (!td->alt_next) { 692 goto done; 693 } 694 } 695 /* 696 * Fetch the next transfer descriptor and transfer 697 * some flags to the next transfer descriptor 698 */ 699 temp = 0; 700 if (td->fifo_bank) 701 temp |= 1; 702 td = td->obj_next; 703 xfer->td_transfer_cache = td; 704 if (temp & 1) 705 td->fifo_bank = 1; 706 } 707 return (1); /* not complete */ 708 709done: 710 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 711 temp = (xfer->endpointno & UE_ADDR); 712 713 /* update FIFO bank flag and multi buffer */ 714 if (td->fifo_bank) { 715 sc->sc_ep_flags[temp].fifo_bank = 1; 716 } else { 717 sc->sc_ep_flags[temp].fifo_bank = 0; 718 } 719 720 /* compute all actual lengths */ 721 722 at91dci_standard_done(xfer); 723 724 return (0); /* complete */ 725} 726 727static void 728at91dci_interrupt_poll(struct at91dci_softc *sc) 729{ 730 struct usb_xfer *xfer; 731 732repeat: 733 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 734 if (!at91dci_xfer_do_fifo(xfer)) { 735 /* queue has been modified */ 736 goto repeat; 737 } 738 } 739} 740 741void 742at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on) 743{ 744 DPRINTFN(5, "vbus = %u\n", is_on); 745 746 if (is_on) { 747 if (!sc->sc_flags.status_vbus) { 748 sc->sc_flags.status_vbus = 1; 749 750 /* complete root HUB interrupt endpoint */ 751 at91dci_root_intr(sc); 752 } 753 } else { 754 if (sc->sc_flags.status_vbus) { 755 sc->sc_flags.status_vbus = 0; 756 sc->sc_flags.status_bus_reset = 0; 757 sc->sc_flags.status_suspend = 0; 758 sc->sc_flags.change_suspend = 0; 759 sc->sc_flags.change_connect = 1; 760 761 /* complete root HUB interrupt endpoint */ 762 at91dci_root_intr(sc); 763 } 764 } 765} 766 767void 768at91dci_interrupt(struct at91dci_softc *sc) 769{ 770 uint32_t status; 771 772 USB_BUS_LOCK(&sc->sc_bus); 773 774 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 775 status &= AT91_UDP_INT_DEFAULT; 776 777 if (!status) { 778 USB_BUS_UNLOCK(&sc->sc_bus); 779 return; 780 } 781 /* acknowledge interrupts */ 782 783 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status); 784 785 /* check for any bus state change interrupts */ 786 787 if (status & AT91_UDP_INT_BUS) { 788 789 DPRINTFN(5, "real bus interrupt 0x%08x\n", status); 790 791 if (status & AT91_UDP_INT_END_BR) { 792 793 /* set correct state */ 794 sc->sc_flags.status_bus_reset = 1; 795 sc->sc_flags.status_suspend = 0; 796 sc->sc_flags.change_suspend = 0; 797 sc->sc_flags.change_connect = 1; 798 799 /* disable resume interrupt */ 800 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 801 AT91_UDP_INT_RXRSM); 802 /* enable suspend interrupt */ 803 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 804 AT91_UDP_INT_RXSUSP); 805 } 806 /* 807 * If RXRSM and RXSUSP is set at the same time we interpret 808 * that like RESUME. Resume is set when there is at least 3 809 * milliseconds of inactivity on the USB BUS. 810 */ 811 if (status & AT91_UDP_INT_RXRSM) { 812 if (sc->sc_flags.status_suspend) { 813 sc->sc_flags.status_suspend = 0; 814 sc->sc_flags.change_suspend = 1; 815 816 /* disable resume interrupt */ 817 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 818 AT91_UDP_INT_RXRSM); 819 /* enable suspend interrupt */ 820 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 821 AT91_UDP_INT_RXSUSP); 822 } 823 } else if (status & AT91_UDP_INT_RXSUSP) { 824 if (!sc->sc_flags.status_suspend) { 825 sc->sc_flags.status_suspend = 1; 826 sc->sc_flags.change_suspend = 1; 827 828 /* disable suspend interrupt */ 829 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 830 AT91_UDP_INT_RXSUSP); 831 832 /* enable resume interrupt */ 833 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 834 AT91_UDP_INT_RXRSM); 835 } 836 } 837 /* complete root HUB interrupt endpoint */ 838 at91dci_root_intr(sc); 839 } 840 /* check for any endpoint interrupts */ 841 842 if (status & AT91_UDP_INT_EPS) { 843 844 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status); 845 846 at91dci_interrupt_poll(sc); 847 } 848 USB_BUS_UNLOCK(&sc->sc_bus); 849} 850 851static void 852at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp) 853{ 854 struct at91dci_td *td; 855 856 /* get current Transfer Descriptor */ 857 td = temp->td_next; 858 temp->td = td; 859 860 /* prepare for next TD */ 861 temp->td_next = td->obj_next; 862 863 /* fill out the Transfer Descriptor */ 864 td->func = temp->func; 865 td->pc = temp->pc; 866 td->offset = temp->offset; 867 td->remainder = temp->len; 868 td->fifo_bank = 0; 869 td->error = 0; 870 td->did_stall = temp->did_stall; 871 td->short_pkt = temp->short_pkt; 872 td->alt_next = temp->setup_alt_next; 873} 874 875static void 876at91dci_setup_standard_chain(struct usb_xfer *xfer) 877{ 878 struct at91dci_std_temp temp; 879 struct at91dci_softc *sc; 880 struct at91dci_td *td; 881 uint32_t x; 882 uint8_t ep_no; 883 uint8_t need_sync; 884 885 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 886 xfer->address, UE_GET_ADDR(xfer->endpointno), 887 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 888 889 temp.max_frame_size = xfer->max_frame_size; 890 891 td = xfer->td_start[0]; 892 xfer->td_transfer_first = td; 893 xfer->td_transfer_cache = td; 894 895 /* setup temp */ 896 897 temp.pc = NULL; 898 temp.td = NULL; 899 temp.td_next = xfer->td_start[0]; 900 temp.offset = 0; 901 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 902 temp.did_stall = !xfer->flags_int.control_stall; 903 904 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 905 ep_no = (xfer->endpointno & UE_ADDR); 906 907 /* check if we should prepend a setup message */ 908 909 if (xfer->flags_int.control_xfr) { 910 if (xfer->flags_int.control_hdr) { 911 912 temp.func = &at91dci_setup_rx; 913 temp.len = xfer->frlengths[0]; 914 temp.pc = xfer->frbuffers + 0; 915 temp.short_pkt = temp.len ? 1 : 0; 916 /* check for last frame */ 917 if (xfer->nframes == 1) { 918 /* no STATUS stage yet, SETUP is last */ 919 if (xfer->flags_int.control_act) 920 temp.setup_alt_next = 0; 921 } 922 923 at91dci_setup_standard_chain_sub(&temp); 924 } 925 x = 1; 926 } else { 927 x = 0; 928 } 929 930 if (x != xfer->nframes) { 931 if (xfer->endpointno & UE_DIR_IN) { 932 temp.func = &at91dci_data_tx; 933 need_sync = 1; 934 } else { 935 temp.func = &at91dci_data_rx; 936 need_sync = 0; 937 } 938 939 /* setup "pc" pointer */ 940 temp.pc = xfer->frbuffers + x; 941 } else { 942 need_sync = 0; 943 } 944 while (x != xfer->nframes) { 945 946 /* DATA0 / DATA1 message */ 947 948 temp.len = xfer->frlengths[x]; 949 950 x++; 951 952 if (x == xfer->nframes) { 953 if (xfer->flags_int.control_xfr) { 954 if (xfer->flags_int.control_act) { 955 temp.setup_alt_next = 0; 956 } 957 } else { 958 temp.setup_alt_next = 0; 959 } 960 } 961 if (temp.len == 0) { 962 963 /* make sure that we send an USB packet */ 964 965 temp.short_pkt = 0; 966 967 } else { 968 969 /* regular data transfer */ 970 971 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 972 } 973 974 at91dci_setup_standard_chain_sub(&temp); 975 976 if (xfer->flags_int.isochronous_xfr) { 977 temp.offset += temp.len; 978 } else { 979 /* get next Page Cache pointer */ 980 temp.pc = xfer->frbuffers + x; 981 } 982 } 983 984 /* check for control transfer */ 985 if (xfer->flags_int.control_xfr) { 986 987 /* always setup a valid "pc" pointer for status and sync */ 988 temp.pc = xfer->frbuffers + 0; 989 temp.len = 0; 990 temp.short_pkt = 0; 991 temp.setup_alt_next = 0; 992 993 /* check if we need to sync */ 994 if (need_sync) { 995 /* we need a SYNC point after TX */ 996 temp.func = &at91dci_data_tx_sync; 997 at91dci_setup_standard_chain_sub(&temp); 998 } 999 1000 /* check if we should append a status stage */ 1001 if (!xfer->flags_int.control_act) { 1002 1003 /* 1004 * Send a DATA1 message and invert the current 1005 * endpoint direction. 1006 */ 1007 if (xfer->endpointno & UE_DIR_IN) { 1008 temp.func = &at91dci_data_rx; 1009 need_sync = 0; 1010 } else { 1011 temp.func = &at91dci_data_tx; 1012 need_sync = 1; 1013 } 1014 1015 at91dci_setup_standard_chain_sub(&temp); 1016 if (need_sync) { 1017 /* we need a SYNC point after TX */ 1018 temp.func = &at91dci_data_tx_sync; 1019 at91dci_setup_standard_chain_sub(&temp); 1020 } 1021 } 1022 } 1023 1024 /* must have at least one frame! */ 1025 td = temp.td; 1026 xfer->td_transfer_last = td; 1027 1028 /* setup the correct fifo bank */ 1029 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1030 td = xfer->td_transfer_first; 1031 td->fifo_bank = 1; 1032 } 1033} 1034 1035static void 1036at91dci_timeout(void *arg) 1037{ 1038 struct usb_xfer *xfer = arg; 1039 1040 DPRINTF("xfer=%p\n", xfer); 1041 1042 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1043 1044 /* transfer is transferred */ 1045 at91dci_device_done(xfer, USB_ERR_TIMEOUT); 1046} 1047 1048static void 1049at91dci_start_standard_chain(struct usb_xfer *xfer) 1050{ 1051 DPRINTFN(9, "\n"); 1052 1053 /* poll one time */ 1054 if (at91dci_xfer_do_fifo(xfer)) { 1055 1056 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1057 uint8_t ep_no = xfer->endpointno & UE_ADDR; 1058 1059 /* 1060 * Only enable the endpoint interrupt when we are actually 1061 * waiting for data, hence we are dealing with level 1062 * triggered interrupts ! 1063 */ 1064 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no)); 1065 1066 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no); 1067 1068 /* put transfer on interrupt queue */ 1069 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1070 1071 /* start timeout, if any */ 1072 if (xfer->timeout != 0) { 1073 usbd_transfer_timeout_ms(xfer, 1074 &at91dci_timeout, xfer->timeout); 1075 } 1076 } 1077} 1078 1079static void 1080at91dci_root_intr(struct at91dci_softc *sc) 1081{ 1082 DPRINTFN(9, "\n"); 1083 1084 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1085 1086 /* set port bit */ 1087 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1088 1089 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1090 sizeof(sc->sc_hub_idata)); 1091} 1092 1093static usb_error_t 1094at91dci_standard_done_sub(struct usb_xfer *xfer) 1095{ 1096 struct at91dci_td *td; 1097 uint32_t len; 1098 uint8_t error; 1099 1100 DPRINTFN(9, "\n"); 1101 1102 td = xfer->td_transfer_cache; 1103 1104 do { 1105 len = td->remainder; 1106 1107 if (xfer->aframes != xfer->nframes) { 1108 /* 1109 * Verify the length and subtract 1110 * the remainder from "frlengths[]": 1111 */ 1112 if (len > xfer->frlengths[xfer->aframes]) { 1113 td->error = 1; 1114 } else { 1115 xfer->frlengths[xfer->aframes] -= len; 1116 } 1117 } 1118 /* Check for transfer error */ 1119 if (td->error) { 1120 /* the transfer is finished */ 1121 error = 1; 1122 td = NULL; 1123 break; 1124 } 1125 /* Check for short transfer */ 1126 if (len > 0) { 1127 if (xfer->flags_int.short_frames_ok) { 1128 /* follow alt next */ 1129 if (td->alt_next) { 1130 td = td->obj_next; 1131 } else { 1132 td = NULL; 1133 } 1134 } else { 1135 /* the transfer is finished */ 1136 td = NULL; 1137 } 1138 error = 0; 1139 break; 1140 } 1141 td = td->obj_next; 1142 1143 /* this USB frame is complete */ 1144 error = 0; 1145 break; 1146 1147 } while (0); 1148 1149 /* update transfer cache */ 1150 1151 xfer->td_transfer_cache = td; 1152 1153 return (error ? 1154 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1155} 1156 1157static void 1158at91dci_standard_done(struct usb_xfer *xfer) 1159{ 1160 usb_error_t err = 0; 1161 1162 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1163 xfer, xfer->endpoint); 1164 1165 /* reset scanner */ 1166 1167 xfer->td_transfer_cache = xfer->td_transfer_first; 1168 1169 if (xfer->flags_int.control_xfr) { 1170 1171 if (xfer->flags_int.control_hdr) { 1172 1173 err = at91dci_standard_done_sub(xfer); 1174 } 1175 xfer->aframes = 1; 1176 1177 if (xfer->td_transfer_cache == NULL) { 1178 goto done; 1179 } 1180 } 1181 while (xfer->aframes != xfer->nframes) { 1182 1183 err = at91dci_standard_done_sub(xfer); 1184 xfer->aframes++; 1185 1186 if (xfer->td_transfer_cache == NULL) { 1187 goto done; 1188 } 1189 } 1190 1191 if (xfer->flags_int.control_xfr && 1192 !xfer->flags_int.control_act) { 1193 1194 err = at91dci_standard_done_sub(xfer); 1195 } 1196done: 1197 at91dci_device_done(xfer, err); 1198} 1199 1200/*------------------------------------------------------------------------* 1201 * at91dci_device_done 1202 * 1203 * NOTE: this function can be called more than one time on the 1204 * same USB transfer! 1205 *------------------------------------------------------------------------*/ 1206static void 1207at91dci_device_done(struct usb_xfer *xfer, usb_error_t error) 1208{ 1209 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1210 uint8_t ep_no; 1211 1212 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1213 1214 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1215 xfer, xfer->endpoint, error); 1216 1217 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1218 ep_no = (xfer->endpointno & UE_ADDR); 1219 1220 /* disable endpoint interrupt */ 1221 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no)); 1222 1223 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no); 1224 } 1225 /* dequeue transfer and start next transfer */ 1226 usbd_transfer_done(xfer, error); 1227} 1228 1229static void 1230at91dci_xfer_stall(struct usb_xfer *xfer) 1231{ 1232 at91dci_device_done(xfer, USB_ERR_STALLED); 1233} 1234 1235static void 1236at91dci_set_stall(struct usb_device *udev, 1237 struct usb_endpoint *ep, uint8_t *did_stall) 1238{ 1239 struct at91dci_softc *sc; 1240 uint32_t csr_val; 1241 uint8_t csr_reg; 1242 1243 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1244 1245 DPRINTFN(5, "endpoint=%p\n", ep); 1246 1247 /* set FORCESTALL */ 1248 sc = AT9100_DCI_BUS2SC(udev->bus); 1249 csr_reg = (ep->edesc->bEndpointAddress & UE_ADDR); 1250 csr_reg = AT91_UDP_CSR(csr_reg); 1251 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1252 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL); 1253 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1254} 1255 1256static void 1257at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no, 1258 uint8_t ep_type, uint8_t ep_dir) 1259{ 1260 const struct usb_hw_ep_profile *pf; 1261 uint32_t csr_val; 1262 uint32_t temp; 1263 uint8_t csr_reg; 1264 uint8_t to; 1265 1266 if (ep_type == UE_CONTROL) { 1267 /* clearing stall is not needed */ 1268 return; 1269 } 1270 /* compute CSR register offset */ 1271 csr_reg = AT91_UDP_CSR(ep_no); 1272 1273 /* compute default CSR value */ 1274 csr_val = 0; 1275 AT91_CSR_ACK(csr_val, 0); 1276 1277 /* disable endpoint */ 1278 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1279 1280 /* get endpoint profile */ 1281 at91dci_get_hw_ep_profile(NULL, &pf, ep_no); 1282 1283 /* reset FIFO */ 1284 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no)); 1285 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0); 1286 1287 /* 1288 * NOTE: One would assume that a FIFO reset would release the 1289 * FIFO banks aswell, but it doesn't! We have to do this 1290 * manually! 1291 */ 1292 1293 /* release FIFO banks, if any */ 1294 for (to = 0; to != 2; to++) { 1295 1296 /* get csr value */ 1297 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1298 1299 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 | 1300 AT91_UDP_CSR_RX_DATA_BK1)) { 1301 /* clear status bits */ 1302 if (pf->support_multi_buffer) { 1303 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1304 sc->sc_ep_flags[ep_no].fifo_bank = 0; 1305 temp = AT91_UDP_CSR_RX_DATA_BK1; 1306 } else { 1307 sc->sc_ep_flags[ep_no].fifo_bank = 1; 1308 temp = AT91_UDP_CSR_RX_DATA_BK0; 1309 } 1310 } else { 1311 temp = (AT91_UDP_CSR_RX_DATA_BK0 | 1312 AT91_UDP_CSR_RX_DATA_BK1); 1313 } 1314 } else { 1315 temp = 0; 1316 } 1317 1318 /* clear FORCESTALL */ 1319 temp |= AT91_UDP_CSR_STALLSENT; 1320 1321 AT91_CSR_ACK(csr_val, temp); 1322 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1323 } 1324 1325 /* compute default CSR value */ 1326 csr_val = 0; 1327 AT91_CSR_ACK(csr_val, 0); 1328 1329 /* enable endpoint */ 1330 csr_val &= ~AT91_UDP_CSR_ET_MASK; 1331 csr_val |= AT91_UDP_CSR_EPEDS; 1332 1333 if (ep_type == UE_CONTROL) { 1334 csr_val |= AT91_UDP_CSR_ET_CTRL; 1335 } else { 1336 if (ep_type == UE_BULK) { 1337 csr_val |= AT91_UDP_CSR_ET_BULK; 1338 } else if (ep_type == UE_INTERRUPT) { 1339 csr_val |= AT91_UDP_CSR_ET_INT; 1340 } else { 1341 csr_val |= AT91_UDP_CSR_ET_ISO; 1342 } 1343 if (ep_dir & UE_DIR_IN) { 1344 csr_val |= AT91_UDP_CSR_ET_DIR_IN; 1345 } 1346 } 1347 1348 /* enable endpoint */ 1349 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val); 1350} 1351 1352static void 1353at91dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1354{ 1355 struct at91dci_softc *sc; 1356 struct usb_endpoint_descriptor *ed; 1357 1358 DPRINTFN(5, "endpoint=%p\n", ep); 1359 1360 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1361 1362 /* check mode */ 1363 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1364 /* not supported */ 1365 return; 1366 } 1367 /* get softc */ 1368 sc = AT9100_DCI_BUS2SC(udev->bus); 1369 1370 /* get endpoint descriptor */ 1371 ed = ep->edesc; 1372 1373 /* reset endpoint */ 1374 at91dci_clear_stall_sub(sc, 1375 (ed->bEndpointAddress & UE_ADDR), 1376 (ed->bmAttributes & UE_XFERTYPE), 1377 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1378} 1379 1380usb_error_t 1381at91dci_init(struct at91dci_softc *sc) 1382{ 1383 uint32_t csr_val; 1384 uint8_t n; 1385 1386 DPRINTF("start\n"); 1387 1388 /* set up the bus structure */ 1389 sc->sc_bus.usbrev = USB_REV_1_1; 1390 sc->sc_bus.methods = &at91dci_bus_methods; 1391 1392 USB_BUS_LOCK(&sc->sc_bus); 1393 1394 /* turn on clocks */ 1395 1396 if (sc->sc_clocks_on) { 1397 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1398 } 1399 /* wait a little for things to stabilise */ 1400 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1401 1402 /* disable and clear all interrupts */ 1403 1404 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1405 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1406 1407 /* compute default CSR value */ 1408 1409 csr_val = 0; 1410 AT91_CSR_ACK(csr_val, 0); 1411 1412 /* disable all endpoints */ 1413 1414 for (n = 0; n != AT91_UDP_EP_MAX; n++) { 1415 1416 /* disable endpoint */ 1417 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val); 1418 } 1419 1420 /* enable the control endpoint */ 1421 1422 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL | 1423 AT91_UDP_CSR_EPEDS); 1424 1425 /* write to FIFO control register */ 1426 1427 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val); 1428 1429 /* enable the interrupts we want */ 1430 1431 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS); 1432 1433 /* turn off clocks */ 1434 1435 at91dci_clocks_off(sc); 1436 1437 USB_BUS_UNLOCK(&sc->sc_bus); 1438 1439 /* catch any lost interrupts */ 1440 1441 at91dci_do_poll(&sc->sc_bus); 1442 1443 return (0); /* success */ 1444} 1445 1446void 1447at91dci_uninit(struct at91dci_softc *sc) 1448{ 1449 USB_BUS_LOCK(&sc->sc_bus); 1450 1451 /* disable and clear all interrupts */ 1452 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1453 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1454 1455 sc->sc_flags.port_powered = 0; 1456 sc->sc_flags.status_vbus = 0; 1457 sc->sc_flags.status_bus_reset = 0; 1458 sc->sc_flags.status_suspend = 0; 1459 sc->sc_flags.change_suspend = 0; 1460 sc->sc_flags.change_connect = 1; 1461 1462 at91dci_pull_down(sc); 1463 at91dci_clocks_off(sc); 1464 USB_BUS_UNLOCK(&sc->sc_bus); 1465} 1466 1467static void 1468at91dci_suspend(struct at91dci_softc *sc) 1469{ 1470 /* TODO */ 1471} 1472 1473static void 1474at91dci_resume(struct at91dci_softc *sc) 1475{ 1476 /* TODO */ 1477} 1478 1479static void 1480at91dci_do_poll(struct usb_bus *bus) 1481{ 1482 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1483 1484 USB_BUS_LOCK(&sc->sc_bus); 1485 at91dci_interrupt_poll(sc); 1486 USB_BUS_UNLOCK(&sc->sc_bus); 1487} 1488 1489/*------------------------------------------------------------------------* 1490 * at91dci bulk support 1491 *------------------------------------------------------------------------*/ 1492static void 1493at91dci_device_bulk_open(struct usb_xfer *xfer) 1494{ 1495 return; 1496} 1497 1498static void 1499at91dci_device_bulk_close(struct usb_xfer *xfer) 1500{ 1501 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1502} 1503 1504static void 1505at91dci_device_bulk_enter(struct usb_xfer *xfer) 1506{ 1507 return; 1508} 1509 1510static void 1511at91dci_device_bulk_start(struct usb_xfer *xfer) 1512{ 1513 /* setup TDs */ 1514 at91dci_setup_standard_chain(xfer); 1515 at91dci_start_standard_chain(xfer); 1516} 1517 1518struct usb_pipe_methods at91dci_device_bulk_methods = 1519{ 1520 .open = at91dci_device_bulk_open, 1521 .close = at91dci_device_bulk_close, 1522 .enter = at91dci_device_bulk_enter, 1523 .start = at91dci_device_bulk_start, 1524}; 1525 1526/*------------------------------------------------------------------------* 1527 * at91dci control support 1528 *------------------------------------------------------------------------*/ 1529static void 1530at91dci_device_ctrl_open(struct usb_xfer *xfer) 1531{ 1532 return; 1533} 1534 1535static void 1536at91dci_device_ctrl_close(struct usb_xfer *xfer) 1537{ 1538 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1539} 1540 1541static void 1542at91dci_device_ctrl_enter(struct usb_xfer *xfer) 1543{ 1544 return; 1545} 1546 1547static void 1548at91dci_device_ctrl_start(struct usb_xfer *xfer) 1549{ 1550 /* setup TDs */ 1551 at91dci_setup_standard_chain(xfer); 1552 at91dci_start_standard_chain(xfer); 1553} 1554 1555struct usb_pipe_methods at91dci_device_ctrl_methods = 1556{ 1557 .open = at91dci_device_ctrl_open, 1558 .close = at91dci_device_ctrl_close, 1559 .enter = at91dci_device_ctrl_enter, 1560 .start = at91dci_device_ctrl_start, 1561}; 1562 1563/*------------------------------------------------------------------------* 1564 * at91dci interrupt support 1565 *------------------------------------------------------------------------*/ 1566static void 1567at91dci_device_intr_open(struct usb_xfer *xfer) 1568{ 1569 return; 1570} 1571 1572static void 1573at91dci_device_intr_close(struct usb_xfer *xfer) 1574{ 1575 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1576} 1577 1578static void 1579at91dci_device_intr_enter(struct usb_xfer *xfer) 1580{ 1581 return; 1582} 1583 1584static void 1585at91dci_device_intr_start(struct usb_xfer *xfer) 1586{ 1587 /* setup TDs */ 1588 at91dci_setup_standard_chain(xfer); 1589 at91dci_start_standard_chain(xfer); 1590} 1591 1592struct usb_pipe_methods at91dci_device_intr_methods = 1593{ 1594 .open = at91dci_device_intr_open, 1595 .close = at91dci_device_intr_close, 1596 .enter = at91dci_device_intr_enter, 1597 .start = at91dci_device_intr_start, 1598}; 1599 1600/*------------------------------------------------------------------------* 1601 * at91dci full speed isochronous support 1602 *------------------------------------------------------------------------*/ 1603static void 1604at91dci_device_isoc_fs_open(struct usb_xfer *xfer) 1605{ 1606 return; 1607} 1608 1609static void 1610at91dci_device_isoc_fs_close(struct usb_xfer *xfer) 1611{ 1612 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1613} 1614 1615static void 1616at91dci_device_isoc_fs_enter(struct usb_xfer *xfer) 1617{ 1618 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1619 uint32_t temp; 1620 uint32_t nframes; 1621 1622 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1623 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1624 1625 /* get the current frame index */ 1626 1627 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM); 1628 1629 /* 1630 * check if the frame index is within the window where the frames 1631 * will be inserted 1632 */ 1633 temp = (nframes - xfer->endpoint->isoc_next) & AT91_UDP_FRM_MASK; 1634 1635 if ((xfer->endpoint->is_synced == 0) || 1636 (temp < xfer->nframes)) { 1637 /* 1638 * If there is data underflow or the endpoint queue is 1639 * empty we schedule the transfer a few frames ahead 1640 * of the current frame position. Else two isochronous 1641 * transfers might overlap. 1642 */ 1643 xfer->endpoint->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK; 1644 xfer->endpoint->is_synced = 1; 1645 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1646 } 1647 /* 1648 * compute how many milliseconds the insertion is ahead of the 1649 * current frame position: 1650 */ 1651 temp = (xfer->endpoint->isoc_next - nframes) & AT91_UDP_FRM_MASK; 1652 1653 /* 1654 * pre-compute when the isochronous transfer will be finished: 1655 */ 1656 xfer->isoc_time_complete = 1657 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1658 xfer->nframes; 1659 1660 /* compute frame number for next insertion */ 1661 xfer->endpoint->isoc_next += xfer->nframes; 1662 1663 /* setup TDs */ 1664 at91dci_setup_standard_chain(xfer); 1665} 1666 1667static void 1668at91dci_device_isoc_fs_start(struct usb_xfer *xfer) 1669{ 1670 /* start TD chain */ 1671 at91dci_start_standard_chain(xfer); 1672} 1673 1674struct usb_pipe_methods at91dci_device_isoc_fs_methods = 1675{ 1676 .open = at91dci_device_isoc_fs_open, 1677 .close = at91dci_device_isoc_fs_close, 1678 .enter = at91dci_device_isoc_fs_enter, 1679 .start = at91dci_device_isoc_fs_start, 1680}; 1681 1682/*------------------------------------------------------------------------* 1683 * at91dci root control support 1684 *------------------------------------------------------------------------* 1685 * Simulate a hardware HUB by handling all the necessary requests. 1686 *------------------------------------------------------------------------*/ 1687 1688static const struct usb_device_descriptor at91dci_devd = { 1689 .bLength = sizeof(struct usb_device_descriptor), 1690 .bDescriptorType = UDESC_DEVICE, 1691 .bcdUSB = {0x00, 0x02}, 1692 .bDeviceClass = UDCLASS_HUB, 1693 .bDeviceSubClass = UDSUBCLASS_HUB, 1694 .bDeviceProtocol = UDPROTO_FSHUB, 1695 .bMaxPacketSize = 64, 1696 .bcdDevice = {0x00, 0x01}, 1697 .iManufacturer = 1, 1698 .iProduct = 2, 1699 .bNumConfigurations = 1, 1700}; 1701 1702static const struct at91dci_config_desc at91dci_confd = { 1703 .confd = { 1704 .bLength = sizeof(struct usb_config_descriptor), 1705 .bDescriptorType = UDESC_CONFIG, 1706 .wTotalLength[0] = sizeof(at91dci_confd), 1707 .bNumInterface = 1, 1708 .bConfigurationValue = 1, 1709 .iConfiguration = 0, 1710 .bmAttributes = UC_SELF_POWERED, 1711 .bMaxPower = 0, 1712 }, 1713 .ifcd = { 1714 .bLength = sizeof(struct usb_interface_descriptor), 1715 .bDescriptorType = UDESC_INTERFACE, 1716 .bNumEndpoints = 1, 1717 .bInterfaceClass = UICLASS_HUB, 1718 .bInterfaceSubClass = UISUBCLASS_HUB, 1719 .bInterfaceProtocol = 0, 1720 }, 1721 .endpd = { 1722 .bLength = sizeof(struct usb_endpoint_descriptor), 1723 .bDescriptorType = UDESC_ENDPOINT, 1724 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT), 1725 .bmAttributes = UE_INTERRUPT, 1726 .wMaxPacketSize[0] = 8, 1727 .bInterval = 255, 1728 }, 1729}; 1730 1731#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1732 1733static const struct usb_hub_descriptor_min at91dci_hubd = { 1734 .bDescLength = sizeof(at91dci_hubd), 1735 .bDescriptorType = UDESC_HUB, 1736 .bNbrPorts = 1, 1737 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1738 .bPwrOn2PwrGood = 50, 1739 .bHubContrCurrent = 0, 1740 .DeviceRemovable = {0}, /* port is removable */ 1741}; 1742 1743#define STRING_VENDOR \ 1744 "A\0T\0M\0E\0L" 1745 1746#define STRING_PRODUCT \ 1747 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1748 1749USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor); 1750USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product); 1751 1752static usb_error_t 1753at91dci_roothub_exec(struct usb_device *udev, 1754 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1755{ 1756 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 1757 const void *ptr; 1758 uint16_t len; 1759 uint16_t value; 1760 uint16_t index; 1761 usb_error_t err; 1762 1763 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1764 1765 /* buffer reset */ 1766 ptr = (const void *)&sc->sc_hub_temp; 1767 len = 0; 1768 err = 0; 1769 1770 value = UGETW(req->wValue); 1771 index = UGETW(req->wIndex); 1772 1773 /* demultiplex the control request */ 1774 1775 switch (req->bmRequestType) { 1776 case UT_READ_DEVICE: 1777 switch (req->bRequest) { 1778 case UR_GET_DESCRIPTOR: 1779 goto tr_handle_get_descriptor; 1780 case UR_GET_CONFIG: 1781 goto tr_handle_get_config; 1782 case UR_GET_STATUS: 1783 goto tr_handle_get_status; 1784 default: 1785 goto tr_stalled; 1786 } 1787 break; 1788 1789 case UT_WRITE_DEVICE: 1790 switch (req->bRequest) { 1791 case UR_SET_ADDRESS: 1792 goto tr_handle_set_address; 1793 case UR_SET_CONFIG: 1794 goto tr_handle_set_config; 1795 case UR_CLEAR_FEATURE: 1796 goto tr_valid; /* nop */ 1797 case UR_SET_DESCRIPTOR: 1798 goto tr_valid; /* nop */ 1799 case UR_SET_FEATURE: 1800 default: 1801 goto tr_stalled; 1802 } 1803 break; 1804 1805 case UT_WRITE_ENDPOINT: 1806 switch (req->bRequest) { 1807 case UR_CLEAR_FEATURE: 1808 switch (UGETW(req->wValue)) { 1809 case UF_ENDPOINT_HALT: 1810 goto tr_handle_clear_halt; 1811 case UF_DEVICE_REMOTE_WAKEUP: 1812 goto tr_handle_clear_wakeup; 1813 default: 1814 goto tr_stalled; 1815 } 1816 break; 1817 case UR_SET_FEATURE: 1818 switch (UGETW(req->wValue)) { 1819 case UF_ENDPOINT_HALT: 1820 goto tr_handle_set_halt; 1821 case UF_DEVICE_REMOTE_WAKEUP: 1822 goto tr_handle_set_wakeup; 1823 default: 1824 goto tr_stalled; 1825 } 1826 break; 1827 case UR_SYNCH_FRAME: 1828 goto tr_valid; /* nop */ 1829 default: 1830 goto tr_stalled; 1831 } 1832 break; 1833 1834 case UT_READ_ENDPOINT: 1835 switch (req->bRequest) { 1836 case UR_GET_STATUS: 1837 goto tr_handle_get_ep_status; 1838 default: 1839 goto tr_stalled; 1840 } 1841 break; 1842 1843 case UT_WRITE_INTERFACE: 1844 switch (req->bRequest) { 1845 case UR_SET_INTERFACE: 1846 goto tr_handle_set_interface; 1847 case UR_CLEAR_FEATURE: 1848 goto tr_valid; /* nop */ 1849 case UR_SET_FEATURE: 1850 default: 1851 goto tr_stalled; 1852 } 1853 break; 1854 1855 case UT_READ_INTERFACE: 1856 switch (req->bRequest) { 1857 case UR_GET_INTERFACE: 1858 goto tr_handle_get_interface; 1859 case UR_GET_STATUS: 1860 goto tr_handle_get_iface_status; 1861 default: 1862 goto tr_stalled; 1863 } 1864 break; 1865 1866 case UT_WRITE_CLASS_INTERFACE: 1867 case UT_WRITE_VENDOR_INTERFACE: 1868 /* XXX forward */ 1869 break; 1870 1871 case UT_READ_CLASS_INTERFACE: 1872 case UT_READ_VENDOR_INTERFACE: 1873 /* XXX forward */ 1874 break; 1875 1876 case UT_WRITE_CLASS_DEVICE: 1877 switch (req->bRequest) { 1878 case UR_CLEAR_FEATURE: 1879 goto tr_valid; 1880 case UR_SET_DESCRIPTOR: 1881 case UR_SET_FEATURE: 1882 break; 1883 default: 1884 goto tr_stalled; 1885 } 1886 break; 1887 1888 case UT_WRITE_CLASS_OTHER: 1889 switch (req->bRequest) { 1890 case UR_CLEAR_FEATURE: 1891 goto tr_handle_clear_port_feature; 1892 case UR_SET_FEATURE: 1893 goto tr_handle_set_port_feature; 1894 case UR_CLEAR_TT_BUFFER: 1895 case UR_RESET_TT: 1896 case UR_STOP_TT: 1897 goto tr_valid; 1898 1899 default: 1900 goto tr_stalled; 1901 } 1902 break; 1903 1904 case UT_READ_CLASS_OTHER: 1905 switch (req->bRequest) { 1906 case UR_GET_TT_STATE: 1907 goto tr_handle_get_tt_state; 1908 case UR_GET_STATUS: 1909 goto tr_handle_get_port_status; 1910 default: 1911 goto tr_stalled; 1912 } 1913 break; 1914 1915 case UT_READ_CLASS_DEVICE: 1916 switch (req->bRequest) { 1917 case UR_GET_DESCRIPTOR: 1918 goto tr_handle_get_class_descriptor; 1919 case UR_GET_STATUS: 1920 goto tr_handle_get_class_status; 1921 1922 default: 1923 goto tr_stalled; 1924 } 1925 break; 1926 default: 1927 goto tr_stalled; 1928 } 1929 goto tr_valid; 1930 1931tr_handle_get_descriptor: 1932 switch (value >> 8) { 1933 case UDESC_DEVICE: 1934 if (value & 0xff) { 1935 goto tr_stalled; 1936 } 1937 len = sizeof(at91dci_devd); 1938 ptr = (const void *)&at91dci_devd; 1939 goto tr_valid; 1940 case UDESC_CONFIG: 1941 if (value & 0xff) { 1942 goto tr_stalled; 1943 } 1944 len = sizeof(at91dci_confd); 1945 ptr = (const void *)&at91dci_confd; 1946 goto tr_valid; 1947 case UDESC_STRING: 1948 switch (value & 0xff) { 1949 case 0: /* Language table */ 1950 len = sizeof(usb_string_lang_en); 1951 ptr = (const void *)&usb_string_lang_en; 1952 goto tr_valid; 1953 1954 case 1: /* Vendor */ 1955 len = sizeof(at91dci_vendor); 1956 ptr = (const void *)&at91dci_vendor; 1957 goto tr_valid; 1958 1959 case 2: /* Product */ 1960 len = sizeof(at91dci_product); 1961 ptr = (const void *)&at91dci_product; 1962 goto tr_valid; 1963 default: 1964 break; 1965 } 1966 break; 1967 default: 1968 goto tr_stalled; 1969 } 1970 goto tr_stalled; 1971 1972tr_handle_get_config: 1973 len = 1; 1974 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1975 goto tr_valid; 1976 1977tr_handle_get_status: 1978 len = 2; 1979 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1980 goto tr_valid; 1981 1982tr_handle_set_address: 1983 if (value & 0xFF00) { 1984 goto tr_stalled; 1985 } 1986 sc->sc_rt_addr = value; 1987 goto tr_valid; 1988 1989tr_handle_set_config: 1990 if (value >= 2) { 1991 goto tr_stalled; 1992 } 1993 sc->sc_conf = value; 1994 goto tr_valid; 1995 1996tr_handle_get_interface: 1997 len = 1; 1998 sc->sc_hub_temp.wValue[0] = 0; 1999 goto tr_valid; 2000 2001tr_handle_get_tt_state: 2002tr_handle_get_class_status: 2003tr_handle_get_iface_status: 2004tr_handle_get_ep_status: 2005 len = 2; 2006 USETW(sc->sc_hub_temp.wValue, 0); 2007 goto tr_valid; 2008 2009tr_handle_set_halt: 2010tr_handle_set_interface: 2011tr_handle_set_wakeup: 2012tr_handle_clear_wakeup: 2013tr_handle_clear_halt: 2014 goto tr_valid; 2015 2016tr_handle_clear_port_feature: 2017 if (index != 1) { 2018 goto tr_stalled; 2019 } 2020 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2021 2022 switch (value) { 2023 case UHF_PORT_SUSPEND: 2024 at91dci_wakeup_peer(sc); 2025 break; 2026 2027 case UHF_PORT_ENABLE: 2028 sc->sc_flags.port_enabled = 0; 2029 break; 2030 2031 case UHF_PORT_TEST: 2032 case UHF_PORT_INDICATOR: 2033 case UHF_C_PORT_ENABLE: 2034 case UHF_C_PORT_OVER_CURRENT: 2035 case UHF_C_PORT_RESET: 2036 /* nops */ 2037 break; 2038 case UHF_PORT_POWER: 2039 sc->sc_flags.port_powered = 0; 2040 at91dci_pull_down(sc); 2041 at91dci_clocks_off(sc); 2042 break; 2043 case UHF_C_PORT_CONNECTION: 2044 sc->sc_flags.change_connect = 0; 2045 break; 2046 case UHF_C_PORT_SUSPEND: 2047 sc->sc_flags.change_suspend = 0; 2048 break; 2049 default: 2050 err = USB_ERR_IOERROR; 2051 goto done; 2052 } 2053 goto tr_valid; 2054 2055tr_handle_set_port_feature: 2056 if (index != 1) { 2057 goto tr_stalled; 2058 } 2059 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2060 2061 switch (value) { 2062 case UHF_PORT_ENABLE: 2063 sc->sc_flags.port_enabled = 1; 2064 break; 2065 case UHF_PORT_SUSPEND: 2066 case UHF_PORT_RESET: 2067 case UHF_PORT_TEST: 2068 case UHF_PORT_INDICATOR: 2069 /* nops */ 2070 break; 2071 case UHF_PORT_POWER: 2072 sc->sc_flags.port_powered = 1; 2073 break; 2074 default: 2075 err = USB_ERR_IOERROR; 2076 goto done; 2077 } 2078 goto tr_valid; 2079 2080tr_handle_get_port_status: 2081 2082 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2083 2084 if (index != 1) { 2085 goto tr_stalled; 2086 } 2087 if (sc->sc_flags.status_vbus) { 2088 at91dci_clocks_on(sc); 2089 at91dci_pull_up(sc); 2090 } else { 2091 at91dci_pull_down(sc); 2092 at91dci_clocks_off(sc); 2093 } 2094 2095 /* Select FULL-speed and Device Side Mode */ 2096 2097 value = UPS_PORT_MODE_DEVICE; 2098 2099 if (sc->sc_flags.port_powered) { 2100 value |= UPS_PORT_POWER; 2101 } 2102 if (sc->sc_flags.port_enabled) { 2103 value |= UPS_PORT_ENABLED; 2104 } 2105 if (sc->sc_flags.status_vbus && 2106 sc->sc_flags.status_bus_reset) { 2107 value |= UPS_CURRENT_CONNECT_STATUS; 2108 } 2109 if (sc->sc_flags.status_suspend) { 2110 value |= UPS_SUSPEND; 2111 } 2112 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2113 2114 value = 0; 2115 2116 if (sc->sc_flags.change_connect) { 2117 value |= UPS_C_CONNECT_STATUS; 2118 2119 if (sc->sc_flags.status_vbus && 2120 sc->sc_flags.status_bus_reset) { 2121 /* reset endpoint flags */ 2122 memset(sc->sc_ep_flags, 0, sizeof(sc->sc_ep_flags)); 2123 } 2124 } 2125 if (sc->sc_flags.change_suspend) { 2126 value |= UPS_C_SUSPEND; 2127 } 2128 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2129 len = sizeof(sc->sc_hub_temp.ps); 2130 goto tr_valid; 2131 2132tr_handle_get_class_descriptor: 2133 if (value & 0xFF) { 2134 goto tr_stalled; 2135 } 2136 ptr = (const void *)&at91dci_hubd; 2137 len = sizeof(at91dci_hubd); 2138 goto tr_valid; 2139 2140tr_stalled: 2141 err = USB_ERR_STALLED; 2142tr_valid: 2143done: 2144 *plength = len; 2145 *pptr = ptr; 2146 return (err); 2147} 2148 2149static void 2150at91dci_xfer_setup(struct usb_setup_params *parm) 2151{ 2152 const struct usb_hw_ep_profile *pf; 2153 struct at91dci_softc *sc; 2154 struct usb_xfer *xfer; 2155 void *last_obj; 2156 uint32_t ntd; 2157 uint32_t n; 2158 uint8_t ep_no; 2159 2160 sc = AT9100_DCI_BUS2SC(parm->udev->bus); 2161 xfer = parm->curr_xfer; 2162 2163 /* 2164 * NOTE: This driver does not use any of the parameters that 2165 * are computed from the following values. Just set some 2166 * reasonable dummies: 2167 */ 2168 parm->hc_max_packet_size = 0x500; 2169 parm->hc_max_packet_count = 1; 2170 parm->hc_max_frame_size = 0x500; 2171 2172 usbd_transfer_setup_sub(parm); 2173 2174 /* 2175 * compute maximum number of TDs 2176 */ 2177 if (parm->methods == &at91dci_device_ctrl_methods) { 2178 2179 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2180 + 1 /* SYNC 2 */ ; 2181 2182 } else if (parm->methods == &at91dci_device_bulk_methods) { 2183 2184 ntd = xfer->nframes + 1 /* SYNC */ ; 2185 2186 } else if (parm->methods == &at91dci_device_intr_methods) { 2187 2188 ntd = xfer->nframes + 1 /* SYNC */ ; 2189 2190 } else if (parm->methods == &at91dci_device_isoc_fs_methods) { 2191 2192 ntd = xfer->nframes + 1 /* SYNC */ ; 2193 2194 } else { 2195 2196 ntd = 0; 2197 } 2198 2199 /* 2200 * check if "usbd_transfer_setup_sub" set an error 2201 */ 2202 if (parm->err) { 2203 return; 2204 } 2205 /* 2206 * allocate transfer descriptors 2207 */ 2208 last_obj = NULL; 2209 2210 /* 2211 * get profile stuff 2212 */ 2213 if (ntd) { 2214 2215 ep_no = xfer->endpointno & UE_ADDR; 2216 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2217 2218 if (pf == NULL) { 2219 /* should not happen */ 2220 parm->err = USB_ERR_INVAL; 2221 return; 2222 } 2223 } else { 2224 ep_no = 0; 2225 pf = NULL; 2226 } 2227 2228 /* align data */ 2229 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2230 2231 for (n = 0; n != ntd; n++) { 2232 2233 struct at91dci_td *td; 2234 2235 if (parm->buf) { 2236 2237 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2238 2239 /* init TD */ 2240 td->io_tag = sc->sc_io_tag; 2241 td->io_hdl = sc->sc_io_hdl; 2242 td->max_packet_size = xfer->max_packet_size; 2243 td->status_reg = AT91_UDP_CSR(ep_no); 2244 td->fifo_reg = AT91_UDP_FDR(ep_no); 2245 if (pf->support_multi_buffer) { 2246 td->support_multi_buffer = 1; 2247 } 2248 td->obj_next = last_obj; 2249 2250 last_obj = td; 2251 } 2252 parm->size[0] += sizeof(*td); 2253 } 2254 2255 xfer->td_start[0] = last_obj; 2256} 2257 2258static void 2259at91dci_xfer_unsetup(struct usb_xfer *xfer) 2260{ 2261 return; 2262} 2263 2264static void 2265at91dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2266 struct usb_endpoint *ep) 2267{ 2268 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 2269 2270 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2271 ep, udev->address, 2272 edesc->bEndpointAddress, udev->flags.usb_mode, 2273 sc->sc_rt_addr); 2274 2275 if (udev->device_index != sc->sc_rt_addr) { 2276 2277 if (udev->speed != USB_SPEED_FULL) { 2278 /* not supported */ 2279 return; 2280 } 2281 switch (edesc->bmAttributes & UE_XFERTYPE) { 2282 case UE_CONTROL: 2283 ep->methods = &at91dci_device_ctrl_methods; 2284 break; 2285 case UE_INTERRUPT: 2286 ep->methods = &at91dci_device_intr_methods; 2287 break; 2288 case UE_ISOCHRONOUS: 2289 ep->methods = &at91dci_device_isoc_fs_methods; 2290 break; 2291 case UE_BULK: 2292 ep->methods = &at91dci_device_bulk_methods; 2293 break; 2294 default: 2295 /* do nothing */ 2296 break; 2297 } 2298 } 2299} 2300 2301static void 2302at91dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2303{ 2304 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 2305 2306 switch (state) { 2307 case USB_HW_POWER_SUSPEND: 2308 at91dci_suspend(sc); 2309 break; 2310 case USB_HW_POWER_SHUTDOWN: 2311 at91dci_uninit(sc); 2312 break; 2313 case USB_HW_POWER_RESUME: 2314 at91dci_resume(sc); 2315 break; 2316 default: 2317 break; 2318 } 2319} 2320 2321struct usb_bus_methods at91dci_bus_methods = 2322{ 2323 .endpoint_init = &at91dci_ep_init, 2324 .xfer_setup = &at91dci_xfer_setup, 2325 .xfer_unsetup = &at91dci_xfer_unsetup, 2326 .get_hw_ep_profile = &at91dci_get_hw_ep_profile, 2327 .set_stall = &at91dci_set_stall, 2328 .xfer_stall = &at91dci_xfer_stall, 2329 .clear_stall = &at91dci_clear_stall, 2330 .roothub_exec = &at91dci_roothub_exec, 2331 .xfer_poll = &at91dci_do_poll, 2332 .set_hw_power_sleep = &at91dci_set_hw_power_sleep, 2333}; 2334