1/* $OpenBSD: if_txpreg.h,v 1.30 2001/06/23 04:18:02 jason Exp $ */ 2/* $FreeBSD$ */ 3 4/*- 5 * Copyright (c) 2001 Aaron Campbell <aaron@monkey.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Aaron Campbell. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 31 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * Typhoon registers. 37 */ 38#define TXP_SRR 0x00 /* soft reset register */ 39#define TXP_ISR 0x04 /* interrupt status register */ 40#define TXP_IER 0x08 /* interrupt enable register */ 41#define TXP_IMR 0x0c /* interrupt mask register */ 42#define TXP_SIR 0x10 /* self interrupt register */ 43#define TXP_H2A_7 0x14 /* host->arm comm 7 */ 44#define TXP_H2A_6 0x18 /* host->arm comm 6 */ 45#define TXP_H2A_5 0x1c /* host->arm comm 5 */ 46#define TXP_H2A_4 0x20 /* host->arm comm 4 */ 47#define TXP_H2A_3 0x24 /* host->arm comm 3 */ 48#define TXP_H2A_2 0x28 /* host->arm comm 2 */ 49#define TXP_H2A_1 0x2c /* host->arm comm 1 */ 50#define TXP_H2A_0 0x30 /* host->arm comm 0 */ 51#define TXP_A2H_3 0x34 /* arm->host comm 3 */ 52#define TXP_A2H_2 0x38 /* arm->host comm 2 */ 53#define TXP_A2H_1 0x3c /* arm->host comm 1 */ 54#define TXP_A2H_0 0x40 /* arm->host comm 0 */ 55 56/* 57 * interrupt bits (IMR, ISR, IER) 58 */ 59#define TXP_INT_RESERVED 0xffff0000 60#define TXP_INT_A2H_7 0x00008000 /* arm->host comm 7 */ 61#define TXP_INT_A2H_6 0x00004000 /* arm->host comm 6 */ 62#define TXP_INT_A2H_5 0x00002000 /* arm->host comm 5 */ 63#define TXP_INT_A2H_4 0x00001000 /* arm->host comm 4 */ 64#define TXP_INT_SELF 0x00000800 /* self interrupt */ 65#define TXP_INT_PCI_TABORT 0x00000400 /* pci target abort */ 66#define TXP_INT_PCI_MABORT 0x00000200 /* pci master abort */ 67#define TXP_INT_DMA3 0x00000100 /* dma3 done */ 68#define TXP_INT_DMA2 0x00000080 /* dma2 done */ 69#define TXP_INT_DMA1 0x00000040 /* dma1 done */ 70#define TXP_INT_DMA0 0x00000020 /* dma0 done */ 71#define TXP_INT_A2H_3 0x00000010 /* arm->host comm 3 */ 72#define TXP_INT_A2H_2 0x00000008 /* arm->host comm 2 */ 73#define TXP_INT_A2H_1 0x00000004 /* arm->host comm 1 */ 74#define TXP_INT_A2H_0 0x00000002 /* arm->host comm 0 */ 75#define TXP_INT_LATCH 0x00000001 /* interrupt latch */ 76 77/* 78 * Controller periodically generates TXP_INT_A2H_3 interrupt so 79 * we don't want to see them in interrupt handler. 80 */ 81#define TXP_INTRS 0xFFFFFFEF 82#define TXP_INTR_ALL 0xFFFFFFFF 83#define TXP_INTR_NONE 0x00000000 84 85/* 86 * soft reset register (SRR) 87 */ 88#define TXP_SRR_ALL 0x0000007f /* full reset */ 89 90/* 91 * Typhoon boot commands. 92 */ 93#define TXP_BOOTCMD_NULL 0x00 94#define TXP_BOOTCMD_WAKEUP 0xfa 95#define TXP_BOOTCMD_DOWNLOAD_COMPLETE 0xfb 96#define TXP_BOOTCMD_SEGMENT_AVAILABLE 0xfc 97#define TXP_BOOTCMD_RUNTIME_IMAGE 0xfd 98#define TXP_BOOTCMD_REGISTER_BOOT_RECORD 0xff 99 100/* 101 * Typhoon runtime commands. 102 */ 103#define TXP_CMD_GLOBAL_RESET 0x00 104#define TXP_CMD_TX_ENABLE 0x01 105#define TXP_CMD_TX_DISABLE 0x02 106#define TXP_CMD_RX_ENABLE 0x03 107#define TXP_CMD_RX_DISABLE 0x04 108#define TXP_CMD_RX_FILTER_WRITE 0x05 109#define TXP_CMD_RX_FILTER_READ 0x06 110#define TXP_CMD_READ_STATISTICS 0x07 111#define TXP_CMD_CYCLE_STATISTICS 0x08 112#define TXP_CMD_CLEAR_STATISTICS 0x09 113#define TXP_CMD_MEMORY_READ 0x0a 114#define TXP_CMD_MEMORY_WRITE_SINGLE 0x0b 115#define TXP_CMD_VARIABLE_SECTION_READ 0x0c 116#define TXP_CMD_VARIABLE_SECTION_WRITE 0x0d 117#define TXP_CMD_STATIC_SECTION_READ 0x0e 118#define TXP_CMD_STATIC_SECTION_WRITE 0x0f 119#define TXP_CMD_IMAGE_SECTION_PROGRAM 0x10 120#define TXP_CMD_NVRAM_PAGE_READ 0x11 121#define TXP_CMD_NVRAM_PAGE_WRITE 0x12 122#define TXP_CMD_XCVR_SELECT 0x13 123#define TXP_CMD_TEST_MUX 0x14 124#define TXP_CMD_PHYLOOPBACK_ENABLE 0x15 125#define TXP_CMD_PHYLOOPBACK_DISABLE 0x16 126#define TXP_CMD_MAC_CONTROL_READ 0x17 127#define TXP_CMD_MAC_CONTROL_WRITE 0x18 128#define TXP_CMD_MAX_PKT_SIZE_READ 0x19 129#define TXP_CMD_MAX_PKT_SIZE_WRITE 0x1a 130#define TXP_CMD_MEDIA_STATUS_READ 0x1b 131#define TXP_CMD_MEDIA_STATUS_WRITE 0x1c 132#define TXP_CMD_NETWORK_DIAGS_READ 0x1d 133#define TXP_CMD_NETWORK_DIAGS_WRITE 0x1e 134#define TXP_CMD_PHY_MGMT_READ 0x1f 135#define TXP_CMD_PHY_MGMT_WRITE 0x20 136#define TXP_CMD_VARIABLE_PARAMETER_READ 0x21 137#define TXP_CMD_VARIABLE_PARAMETER_WRITE 0x22 138#define TXP_CMD_GOTO_SLEEP 0x23 139#define TXP_CMD_FIREWALL_CONTROL 0x24 140#define TXP_CMD_MCAST_HASH_MASK_WRITE 0x25 141#define TXP_CMD_STATION_ADDRESS_WRITE 0x26 142#define TXP_CMD_STATION_ADDRESS_READ 0x27 143#define TXP_CMD_STATION_MASK_WRITE 0x28 144#define TXP_CMD_STATION_MASK_READ 0x29 145#define TXP_CMD_VLAN_ETHER_TYPE_READ 0x2a 146#define TXP_CMD_VLAN_ETHER_TYPE_WRITE 0x2b 147#define TXP_CMD_VLAN_MASK_READ 0x2c 148#define TXP_CMD_VLAN_MASK_WRITE 0x2d 149#define TXP_CMD_BCAST_THROTTLE_WRITE 0x2e 150#define TXP_CMD_BCAST_THROTTLE_READ 0x2f 151#define TXP_CMD_DHCP_PREVENT_WRITE 0x30 152#define TXP_CMD_DHCP_PREVENT_READ 0x31 153#define TXP_CMD_RECV_BUFFER_CONTROL 0x32 154#define TXP_CMD_SOFTWARE_RESET 0x33 155#define TXP_CMD_CREATE_SA 0x34 156#define TXP_CMD_DELETE_SA 0x35 157#define TXP_CMD_ENABLE_RX_IP_OPTION 0x36 158#define TXP_CMD_RANDOM_NUMBER_CONTROL 0x37 159#define TXP_CMD_RANDOM_NUMBER_READ 0x38 160#define TXP_CMD_MATRIX_TABLE_MODE_WRITE 0x39 161#define TXP_CMD_MATRIX_DETAIL_READ 0x3a 162#define TXP_CMD_FILTER_ARRAY_READ 0x3b 163#define TXP_CMD_FILTER_DETAIL_READ 0x3c 164#define TXP_CMD_FILTER_TABLE_MODE_WRITE 0x3d 165#define TXP_CMD_FILTER_TCL_WRITE 0x3e 166#define TXP_CMD_FILTER_TBL_READ 0x3f 167#define TXP_CMD_READ_VERSION 0x43 168#define TXP_CMD_FILTER_DEFINE 0x45 169#define TXP_CMD_ADD_WAKEUP_PKT 0x46 170#define TXP_CMD_ADD_SLEEP_PKT 0x47 171#define TXP_CMD_ENABLE_SLEEP_EVENTS 0x48 172#define TXP_CMD_ENABLE_WAKEUP_EVENTS 0x49 173#define TXP_CMD_GET_IP_ADDRESS 0x4a 174#define TXP_CMD_READ_PCI_REG 0x4c 175#define TXP_CMD_WRITE_PCI_REG 0x4d 176#define TXP_CMD_OFFLOAD_READ 0x4e 177#define TXP_CMD_OFFLOAD_WRITE 0x4f 178#define TXP_CMD_HELLO_RESPONSE 0x57 179#define TXP_CMD_ENABLE_RX_FILTER 0x58 180#define TXP_CMD_RX_FILTER_CAPABILITY 0x59 181#define TXP_CMD_HALT 0x5d 182#define TXP_CMD_READ_IPSEC_INFO 0x54 183#define TXP_CMD_GET_IPSEC_ENABLE 0x67 184#define TXP_CMD_INVALID 0xffff 185 186#define TXP_FRAGMENT 0x0000 187#define TXP_TXFRAME 0x0001 188#define TXP_COMMAND 0x0002 189#define TXP_OPTION 0x0003 190#define TXP_RECEIVE 0x0004 191#define TXP_RESPONSE 0x0005 192 193#define TXP_TYPE_IPSEC 0x0000 194#define TXP_TYPE_TCPSEGMENT 0x0001 195 196#define TXP_PFLAG_NOCRC 0x0000 197#define TXP_PFLAG_IPCKSUM 0x0001 198#define TXP_PFLAG_TCPCKSUM 0x0002 199#define TXP_PFLAG_TCPSEGMENT 0x0004 200#define TXP_PFLAG_INSERTVLAN 0x0008 201#define TXP_PFLAG_IPSEC 0x0010 202#define TXP_PFLAG_PRIORITY 0x0020 203#define TXP_PFLAG_UDPCKSUM 0x0040 204#define TXP_PFLAG_PADFRAME 0x0080 205 206#define TXP_MISC_FIRSTDESC 0x0000 207#define TXP_MISC_LASTDESC 0x0001 208 209#define TXP_ERR_INTERNAL 0x0000 210#define TXP_ERR_FIFOUNDERRUN 0x0001 211#define TXP_ERR_BADSSD 0x0002 212#define TXP_ERR_RUNT 0x0003 213#define TXP_ERR_CRC 0x0004 214#define TXP_ERR_OVERSIZE 0x0005 215#define TXP_ERR_ALIGNMENT 0x0006 216#define TXP_ERR_DRIBBLEBIT 0x0007 217 218#define TXP_PROTO_UNKNOWN 0x0000 219#define TXP_PROTO_IP 0x0001 220#define TXP_PROTO_IPX 0x0002 221#define TXP_PROTO_RESERVED 0x0003 222 223#define TXP_STAT_PROTO 0x0001 224#define TXP_STAT_VLAN 0x0002 225#define TXP_STAT_IPFRAGMENT 0x0004 226#define TXP_STAT_IPSEC 0x0008 227#define TXP_STAT_IPCKSUMBAD 0x0010 228#define TXP_STAT_TCPCKSUMBAD 0x0020 229#define TXP_STAT_UDPCKSUMBAD 0x0040 230#define TXP_STAT_IPCKSUMGOOD 0x0080 231#define TXP_STAT_TCPCKSUMGOOD 0x0100 232#define TXP_STAT_UDPCKSUMGOOD 0x0200 233 234struct txp_tx_desc { 235 uint8_t tx_flags; /* type/descriptor flags */ 236 uint8_t tx_numdesc; /* number of descriptors */ 237 uint16_t tx_totlen; /* total packet length */ 238 uint32_t tx_addrlo; /* virt addr low word */ 239 uint32_t tx_addrhi; /* virt addr high word */ 240 uint32_t tx_pflags; /* processing flags */ 241}; 242#define TX_FLAGS_TYPE_M 0x07 /* type mask */ 243#define TX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 244#define TX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 245#define TX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 246#define TX_FLAGS_TYPE_OPT 0x03 /* type: options */ 247#define TX_FLAGS_TYPE_RX 0x04 /* type: command */ 248#define TX_FLAGS_TYPE_RESP 0x05 /* type: response */ 249#define TX_FLAGS_RESP 0x40 /* response requested */ 250#define TX_FLAGS_VALID 0x80 /* valid descriptor */ 251 252#define TX_PFLAGS_DNAC 0x00000001 /* do not add crc */ 253#define TX_PFLAGS_IPCKSUM 0x00000002 /* ip checksum */ 254#define TX_PFLAGS_TCPCKSUM 0x00000004 /* tcp checksum */ 255#define TX_PFLAGS_TCPSEG 0x00000008 /* tcp segmentation */ 256#define TX_PFLAGS_VLAN 0x00000010 /* insert vlan */ 257#define TX_PFLAGS_IPSEC 0x00000020 /* perform ipsec */ 258#define TX_PFLAGS_PRIO 0x00000040 /* priority field valid */ 259#define TX_PFLAGS_UDPCKSUM 0x00000080 /* udp checksum */ 260#define TX_PFLAGS_PADFRAME 0x00000100 /* pad frame */ 261#define TX_PFLAGS_VLANTAG_M 0x0ffff000 /* vlan tag mask */ 262#define TX_PFLAGS_VLANPRI_M 0x00700000 /* vlan priority mask */ 263#define TX_PFLAGS_VLANTAG_S 12 /* amount to shift tag */ 264 265struct txp_rx_desc { 266 uint8_t rx_flags; /* type/descriptor flags */ 267 uint8_t rx_numdesc; /* number of descriptors */ 268 uint16_t rx_len; /* frame length */ 269 uint32_t rx_vaddrlo; /* virtual address, lo word */ 270 uint32_t rx_vaddrhi; /* virtual address, hi word */ 271 uint32_t rx_stat; /* status */ 272 uint16_t rx_filter; /* filter status */ 273 uint16_t rx_hash; /* hash status */ 274 uint32_t rx_vlan; /* vlan tag/priority */ 275}; 276 277/* txp_rx_desc.rx_flags */ 278#define RX_FLAGS_TYPE_M 0x07 /* type mask */ 279#define RX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 280#define RX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 281#define RX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 282#define RX_FLAGS_TYPE_OPT 0x03 /* type: options */ 283#define RX_FLAGS_TYPE_RX 0x04 /* type: command */ 284#define RX_FLAGS_TYPE_RESP 0x05 /* type: response */ 285#define RX_FLAGS_RCV_TYPE_M 0x18 /* rcvtype mask */ 286#define RX_FLAGS_RCV_TYPE_RX 0x00 /* rcvtype: receive */ 287#define RX_FLAGS_RCV_TYPE_RSP 0x08 /* rcvtype: response */ 288#define RX_FLAGS_ERROR 0x40 /* error in packet */ 289 290/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR bit set) */ 291#define RX_ERROR_ADAPTER 0x00000000 /* adapter internal error */ 292#define RX_ERROR_FIFO 0x00000001 /* fifo underrun */ 293#define RX_ERROR_BADSSD 0x00000002 /* bad ssd */ 294#define RX_ERROR_RUNT 0x00000003 /* runt packet */ 295#define RX_ERROR_CRC 0x00000004 /* bad crc */ 296#define RX_ERROR_OVERSIZE 0x00000005 /* oversized packet */ 297#define RX_ERROR_ALIGN 0x00000006 /* alignment error */ 298#define RX_ERROR_DRIBBLE 0x00000007 /* dribble bit */ 299#define RX_ERROR_MASK 0x07 300 301/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR not bit set) */ 302#define RX_STAT_PROTO_M 0x00000003 /* protocol mask */ 303#define RX_STAT_PROTO_UK 0x00000000 /* unknown protocol */ 304#define RX_STAT_PROTO_IPX 0x00000001 /* IPX */ 305#define RX_STAT_PROTO_IP 0x00000002 /* IP */ 306#define RX_STAT_PROTO_RSV 0x00000003 /* reserved */ 307#define RX_STAT_VLAN 0x00000004 /* vlan tag (in rxd) */ 308#define RX_STAT_IPFRAG 0x00000008 /* fragment, ipsec not done */ 309#define RX_STAT_IPSEC 0x00000010 /* ipsec decoded packet */ 310#define RX_STAT_IPCKSUMBAD 0x00000020 /* ip checksum failed */ 311#define RX_STAT_UDPCKSUMBAD 0x00000040 /* udp checksum failed */ 312#define RX_STAT_TCPCKSUMBAD 0x00000080 /* tcp checksum failed */ 313#define RX_STAT_IPCKSUMGOOD 0x00000100 /* ip checksum succeeded */ 314#define RX_STAT_UDPCKSUMGOOD 0x00000200 /* udp checksum succeeded */ 315#define RX_STAT_TCPCKSUMGOOD 0x00000400 /* tcp checksum succeeded */ 316 317 318struct txp_rxbuf_desc { 319 uint32_t rb_paddrlo; 320 uint32_t rb_paddrhi; 321 uint32_t rb_vaddrlo; 322 uint32_t rb_vaddrhi; 323}; 324 325/* Extension descriptor */ 326struct txp_ext_desc { 327 uint32_t ext_1; 328 uint32_t ext_2; 329 uint32_t ext_3; 330 uint32_t ext_4; 331}; 332 333struct txp_cmd_desc { 334 uint8_t cmd_flags; 335 uint8_t cmd_numdesc; 336 uint16_t cmd_id; 337 uint16_t cmd_seq; 338 uint16_t cmd_par1; 339 uint32_t cmd_par2; 340 uint32_t cmd_par3; 341}; 342#define CMD_FLAGS_TYPE_M 0x07 /* type mask */ 343#define CMD_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 344#define CMD_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 345#define CMD_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 346#define CMD_FLAGS_TYPE_OPT 0x03 /* type: options */ 347#define CMD_FLAGS_TYPE_RX 0x04 /* type: command */ 348#define CMD_FLAGS_TYPE_RESP 0x05 /* type: response */ 349#define CMD_FLAGS_RESP 0x40 /* response requested */ 350#define CMD_FLAGS_VALID 0x80 /* valid descriptor */ 351 352struct txp_rsp_desc { 353 uint8_t rsp_flags; 354 uint8_t rsp_numdesc; 355 uint16_t rsp_id; 356 uint16_t rsp_seq; 357 uint16_t rsp_par1; 358 uint32_t rsp_par2; 359 uint32_t rsp_par3; 360}; 361#define RSP_FLAGS_TYPE_M 0x07 /* type mask */ 362#define RSP_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 363#define RSP_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 364#define RSP_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 365#define RSP_FLAGS_TYPE_OPT 0x03 /* type: options */ 366#define RSP_FLAGS_TYPE_RX 0x04 /* type: command */ 367#define RSP_FLAGS_TYPE_RESP 0x05 /* type: response */ 368#define RSP_FLAGS_ERROR 0x40 /* response error */ 369 370struct txp_frag_desc { 371 uint8_t frag_flags; /* type/descriptor flags */ 372 uint8_t frag_rsvd1; 373 uint16_t frag_len; /* bytes in this fragment */ 374 uint32_t frag_addrlo; /* phys addr low word */ 375 uint32_t frag_addrhi; /* phys addr high word */ 376 uint32_t frag_rsvd2; 377}; 378#define FRAG_FLAGS_TYPE_M 0x07 /* type mask */ 379#define FRAG_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 380#define FRAG_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 381#define FRAG_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 382#define FRAG_FLAGS_TYPE_OPT 0x03 /* type: options */ 383#define FRAG_FLAGS_TYPE_RX 0x04 /* type: command */ 384#define FRAG_FLAGS_TYPE_RESP 0x05 /* type: response */ 385 386struct txp_opt_desc { 387 uint8_t opt_desctype:3, 388 opt_rsvd:1, 389 opt_type:4; 390 391 uint8_t opt_num; 392 uint16_t opt_dep1; 393 uint32_t opt_dep2; 394 uint32_t opt_dep3; 395 uint32_t opt_dep4; 396}; 397 398struct txp_ipsec_desc { 399 uint8_t ipsec_desctpe:3, 400 ipsec_rsvd:1, 401 ipsec_type:4; 402 403 uint8_t ipsec_num; 404 uint16_t ipsec_flags; 405 uint16_t ipsec_ah1; 406 uint16_t ipsec_esp1; 407 uint16_t ipsec_ah2; 408 uint16_t ipsec_esp2; 409 uint32_t ipsec_rsvd1; 410}; 411 412struct txp_tcpseg_desc { 413 uint8_t tcpseg_type; 414 uint8_t tcpseg_num; 415 uint16_t tcpseg_mss; 416 uint32_t tcpseg_respaddr; 417 uint32_t tcpseg_txbytes; 418 uint32_t tcpseg_lss; 419}; 420#define TCPSEG_DESC_TYPE_M 0x07 /* type mask */ 421#define TCPSEG_DESC_TYPE_FRAG 0x00 /* type: fragment */ 422#define TCPSEG_DESC_TYPE_DATA 0x01 /* type: data frame */ 423#define TCPSEG_DESC_TYPE_CMD 0x02 /* type: command frame */ 424#define TCPSEG_DESC_TYPE_OPT 0x03 /* type: options */ 425#define TCPSEG_DESC_TYPE_RX 0x04 /* type: command */ 426#define TCPSEG_DESC_TYPE_RESP 0x05 /* type: response */ 427#define TCPSEG_OPT_IPSEC 0x00 428#define TCPSEG_OPT_TSO 0x10 429#define TCPSEG_MSS_MASK 0x0FFF 430#define TCPSEG_MSS_FIRST 0x1000 431#define TCPSEG_MSS_LAST 0x2000 432 433/* 434 * Transceiver types 435 */ 436#define TXP_XCVR_10_HDX 0 437#define TXP_XCVR_10_FDX 1 438#define TXP_XCVR_100_HDX 2 439#define TXP_XCVR_100_FDX 3 440#define TXP_XCVR_AUTO 4 441 442#define TXP_MEDIA_CRC 0x0004 /* crc strip disable */ 443#define TXP_MEDIA_CD 0x0010 /* collision detection */ 444#define TXP_MEDIA_CS 0x0020 /* carrier sense */ 445#define TXP_MEDIA_POL 0x0400 /* polarity reversed */ 446#define TXP_MEDIA_NOLINK 0x0800 /* 0 = link, 1 = no link */ 447 448/* 449 * receive filter bits (par1 to TXP_CMD_RX_FILTER_{READ|WRITE} 450 */ 451#define TXP_RXFILT_DIRECT 0x0001 /* directed packets */ 452#define TXP_RXFILT_ALLMULTI 0x0002 /* all multicast packets */ 453#define TXP_RXFILT_BROADCAST 0x0004 /* broadcast packets */ 454#define TXP_RXFILT_PROMISC 0x0008 /* promiscuous mode */ 455#define TXP_RXFILT_HASHMULTI 0x0010 /* use multicast filter */ 456 457/* 458 * boot record (pointers to rings) 459 */ 460struct txp_boot_record { 461 uint32_t br_hostvar_lo; /* host ring pointer */ 462 uint32_t br_hostvar_hi; 463 uint32_t br_txlopri_lo; /* tx low pri ring */ 464 uint32_t br_txlopri_hi; 465 uint32_t br_txlopri_siz; 466 uint32_t br_txhipri_lo; /* tx high pri ring */ 467 uint32_t br_txhipri_hi; 468 uint32_t br_txhipri_siz; 469 uint32_t br_rxlopri_lo; /* rx low pri ring */ 470 uint32_t br_rxlopri_hi; 471 uint32_t br_rxlopri_siz; 472 uint32_t br_rxbuf_lo; /* rx buffer ring */ 473 uint32_t br_rxbuf_hi; 474 uint32_t br_rxbuf_siz; 475 uint32_t br_cmd_lo; /* command ring */ 476 uint32_t br_cmd_hi; 477 uint32_t br_cmd_siz; 478 uint32_t br_resp_lo; /* response ring */ 479 uint32_t br_resp_hi; 480 uint32_t br_resp_siz; 481 uint32_t br_zero_lo; /* zero word */ 482 uint32_t br_zero_hi; 483 uint32_t br_rxhipri_lo; /* rx high pri ring */ 484 uint32_t br_rxhipri_hi; 485 uint32_t br_rxhipri_siz; 486}; 487 488/* 489 * hostvar structure (shared with typhoon) 490 */ 491struct txp_hostvar { 492 uint32_t hv_rx_hi_read_idx; /* host->arm */ 493 uint32_t hv_rx_lo_read_idx; /* host->arm */ 494 uint32_t hv_rx_buf_write_idx; /* host->arm */ 495 uint32_t hv_resp_read_idx; /* host->arm */ 496 uint32_t hv_tx_lo_desc_read_idx; /* arm->host */ 497 uint32_t hv_tx_hi_desc_read_idx; /* arm->host */ 498 uint32_t hv_rx_lo_write_idx; /* arm->host */ 499 uint32_t hv_rx_buf_read_idx; /* arm->host */ 500 uint32_t hv_cmd_read_idx; /* arm->host */ 501 uint32_t hv_resp_write_idx; /* arm->host */ 502 uint32_t hv_rx_hi_write_idx; /* arm->host */ 503}; 504 505/* 506 * TYPHOON status register state (in TXP_A2H_0) 507 */ 508#define STAT_ROM_CODE 0x00000001 509#define STAT_ROM_EEPROM_LOAD 0x00000002 510#define STAT_WAITING_FOR_BOOT 0x00000007 511#define STAT_RUNNING 0x00000009 512#define STAT_WAITING_FOR_HOST_REQUEST 0x0000000d 513#define STAT_WAITING_FOR_SEGMENT 0x00000010 514#define STAT_SLEEPING 0x00000011 515#define STAT_HALTED 0x00000014 516 517#define TX_ENTRIES 256 518#define RX_ENTRIES 128 519#define RXBUF_ENTRIES 256 520#define CMD_ENTRIES 32 521#define RSP_ENTRIES 32 522 523#define OFFLOAD_TCPCKSUM 0x00000002 /* tcp checksum */ 524#define OFFLOAD_UDPCKSUM 0x00000004 /* udp checksum */ 525#define OFFLOAD_IPCKSUM 0x00000008 /* ip checksum */ 526#define OFFLOAD_IPSEC 0x00000010 /* ipsec enable */ 527#define OFFLOAD_BCAST 0x00000020 /* broadcast throttle */ 528#define OFFLOAD_DHCP 0x00000040 /* dhcp prevention */ 529#define OFFLOAD_VLAN 0x00000080 /* vlan enable */ 530#define OFFLOAD_FILTER 0x00000100 /* filter enable */ 531#define OFFLOAD_TCPSEG 0x00000200 /* tcp segmentation */ 532#define OFFLOAD_MASK 0xfffffffe /* mask off low bit */ 533 534/* 535 * Macros for converting array indices to offsets within the descriptor 536 * arrays. The chip operates on offsets, but it's much easier for us 537 * to operate on indices. Assumes descriptor entries are 16 bytes. 538 */ 539#define TXP_IDX2OFFSET(idx) ((idx) << 4) 540#define TXP_OFFSET2IDX(off) ((off) >> 4) 541 542struct txp_cmd_ring { 543 struct txp_cmd_desc *base; 544 uint32_t lastwrite; 545 uint32_t size; 546}; 547 548struct txp_rsp_ring { 549 struct txp_rsp_desc *base; 550 uint32_t lastwrite; 551 uint32_t size; 552}; 553 554struct txp_tx_ring { 555 struct txp_tx_desc *r_desc; /* base address of descs */ 556 bus_dma_tag_t r_tag; 557 bus_dmamap_t r_map; 558 uint32_t r_reg; /* register to activate */ 559 uint32_t r_prod; /* producer */ 560 uint32_t r_cons; /* consumer */ 561 uint32_t r_cnt; /* # descs in use */ 562 uint32_t *r_off; /* hostvar index pointer */ 563}; 564 565struct txp_swdesc { 566 struct mbuf *sd_mbuf; 567 bus_dmamap_t sd_map; 568}; 569 570struct txp_rx_swdesc { 571 TAILQ_ENTRY(txp_rx_swdesc) sd_next; 572 struct mbuf *sd_mbuf; 573 bus_dmamap_t sd_map; 574}; 575 576struct txp_rx_ring { 577 struct txp_rx_desc *r_desc; /* base address of descs */ 578 bus_dma_tag_t r_tag; 579 bus_dmamap_t r_map; 580 uint32_t *r_roff; /* hv read offset ptr */ 581 uint32_t *r_woff; /* hv write offset ptr */ 582}; 583 584struct txp_ldata { 585 struct txp_boot_record *txp_boot; 586 bus_addr_t txp_boot_paddr; 587 struct txp_hostvar *txp_hostvar; 588 bus_addr_t txp_hostvar_paddr; 589 struct txp_tx_desc *txp_txhiring; 590 bus_addr_t txp_txhiring_paddr; 591 struct txp_tx_desc *txp_txloring; 592 bus_addr_t txp_txloring_paddr; 593 struct txp_rxbuf_desc *txp_rxbufs; 594 bus_addr_t txp_rxbufs_paddr; 595 struct txp_rx_desc *txp_rxhiring; 596 bus_addr_t txp_rxhiring_paddr; 597 struct txp_rx_desc *txp_rxloring; 598 bus_addr_t txp_rxloring_paddr; 599 struct txp_cmd_desc *txp_cmdring; 600 bus_addr_t txp_cmdring_paddr; 601 struct txp_rsp_desc *txp_rspring; 602 bus_addr_t txp_rspring_paddr; 603 uint32_t *txp_zero; 604 bus_addr_t txp_zero_paddr; 605}; 606 607struct txp_chain_data { 608 bus_dma_tag_t txp_parent_tag; 609 bus_dma_tag_t txp_boot_tag; 610 bus_dmamap_t txp_boot_map; 611 bus_dma_tag_t txp_hostvar_tag; 612 bus_dmamap_t txp_hostvar_map; 613 bus_dma_tag_t txp_txhiring_tag; 614 bus_dmamap_t txp_txhiring_map; 615 bus_dma_tag_t txp_txloring_tag; 616 bus_dmamap_t txp_txloring_map; 617 bus_dma_tag_t txp_tx_tag; 618 bus_dma_tag_t txp_rx_tag; 619 bus_dma_tag_t txp_rxbufs_tag; 620 bus_dmamap_t txp_rxbufs_map; 621 bus_dma_tag_t txp_rxhiring_tag; 622 bus_dmamap_t txp_rxhiring_map; 623 bus_dma_tag_t txp_rxloring_tag; 624 bus_dmamap_t txp_rxloring_map; 625 bus_dma_tag_t txp_cmdring_tag; 626 bus_dmamap_t txp_cmdring_map; 627 bus_dma_tag_t txp_rspring_tag; 628 bus_dmamap_t txp_rspring_map; 629 bus_dma_tag_t txp_zero_tag; 630 bus_dmamap_t txp_zero_map; 631}; 632 633struct txp_hw_stats { 634 uint32_t tx_frames; 635 uint64_t tx_bytes; 636 uint32_t tx_deferred; 637 uint32_t tx_late_colls; 638 uint32_t tx_colls; 639 uint32_t tx_carrier_lost; 640 uint32_t tx_multi_colls; 641 uint32_t tx_excess_colls; 642 uint32_t tx_fifo_underruns; 643 uint32_t tx_mcast_oflows; 644 uint32_t tx_filtered; 645 uint32_t rx_frames; 646 uint64_t rx_bytes; 647 uint32_t rx_fifo_oflows; 648 uint32_t rx_badssd; 649 uint32_t rx_crcerrs; 650 uint32_t rx_lenerrs; 651 uint32_t rx_bcast_frames; 652 uint32_t rx_mcast_frames; 653 uint32_t rx_oflows; 654 uint32_t rx_filtered; 655}; 656 657struct txp_softc { 658 struct ifnet *sc_ifp; 659 device_t sc_dev; 660 struct txp_hostvar *sc_hostvar; 661 struct txp_boot_record *sc_boot; 662 struct resource *sc_res; 663 int sc_res_id; 664 int sc_res_type; 665 struct resource *sc_irq; 666 void *sc_intrhand; 667 struct txp_chain_data sc_cdata; 668 struct txp_ldata sc_ldata; 669 int sc_rxbufprod; 670 int sc_process_limit; 671 struct txp_cmd_ring sc_cmdring; 672 struct txp_rsp_ring sc_rspring; 673 struct callout sc_tick; 674 struct ifmedia sc_ifmedia; 675 struct txp_hw_stats sc_ostats; 676 struct txp_hw_stats sc_stats; 677 struct txp_tx_ring sc_txhir, sc_txlor; 678 struct txp_swdesc sc_txd[TX_ENTRIES]; 679 struct txp_rxbuf_desc *sc_rxbufs; 680 struct txp_rx_ring sc_rxhir, sc_rxlor; 681 uint16_t sc_xcvr; 682 uint16_t sc_seq; 683 int sc_watchdog_timer; 684 int sc_if_flags; 685 int sc_flags; 686#define TXP_FLAG_DETACH 0x4000 687#define TXP_FLAG_LINK 0x8000 688 TAILQ_HEAD(, txp_rx_swdesc) sc_free_list; 689 TAILQ_HEAD(, txp_rx_swdesc) sc_busy_list; 690 struct task sc_int_task; 691 struct taskqueue *sc_tq; 692 struct mtx sc_mtx; 693}; 694 695struct txp_fw_file_header { 696 uint8_t magicid[8]; /* TYPHOON\0 */ 697 uint32_t version; 698 uint32_t nsections; 699 uint32_t addr; 700 uint32_t hmac[5]; 701}; 702 703struct txp_fw_section_header { 704 uint32_t nbytes; 705 uint16_t cksum; 706 uint16_t reserved; 707 uint32_t addr; 708}; 709 710#define TXP_MAX_SEGLEN 0xffff 711#define TXP_MAX_PKTLEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) 712 713#define WRITE_REG(sc, reg, val) bus_write_4((sc)->sc_res, reg, val) 714#define READ_REG(sc, reg) bus_read_4((sc)->sc_res, reg) 715#define TXP_BARRIER(sc, o, l, f) bus_barrier((sc)->sc_res, (o), (l), (f)) 716 717#define TXP_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 718#define TXP_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 719#define TXP_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 720 721#define TXP_MAXTXSEGS 16 722#define TXP_RXBUF_ALIGN (sizeof(uint32_t)) 723 724#define TXP_PROC_MIN 16 725#define TXP_PROC_MAX RX_ENTRIES 726#define TXP_PROC_DEFAULT (RX_ENTRIES / 2) 727 728#define TXP_ADDR_HI(x) ((uint64_t)(x) >> 32) 729#define TXP_ADDR_LO(x) ((uint64_t)(x) & 0xffffffff) 730 731/* 732 * 3Com PCI vendor ID. 733 */ 734#define TXP_VENDORID_3COM 0x10B7 735 736/* 737 * 3cR990 device IDs 738 */ 739#define TXP_DEVICEID_3CR990_TX_95 0x9902 740#define TXP_DEVICEID_3CR990_TX_97 0x9903 741#define TXP_DEVICEID_3CR990B_TXM 0x9904 742#define TXP_DEVICEID_3CR990_SRV_95 0x9908 743#define TXP_DEVICEID_3CR990_SRV_97 0x9909 744#define TXP_DEVICEID_3CR990B_SRV 0x990A 745 746struct txp_type { 747 uint16_t txp_vid; 748 uint16_t txp_did; 749 char *txp_name; 750}; 751 752#define TXP_TIMEOUT 10000 753#define TXP_CMD_NOWAIT 0 754#define TXP_CMD_WAIT 1 755#define TXP_TX_TIMEOUT 5 756 757/* 758 * Each frame requires one frame descriptor and one or more 759 * fragment descriptors. If TSO is used frame descriptor block 760 * requires one or two option frame descriptors depending on 761 * number of framents. Therefore we will consume three 762 * additional descriptors at most to use TSO for a frame and 763 * one reserved descriptor in order not to full Tx descriptor 764 * ring. 765 */ 766#define TXP_TXD_RESERVED 4 767 768#define TXP_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 769