1/*- 2 * Copyright (c) 2012 Robert N. M. Watson 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD$"); 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/conf.h> 37#include <sys/consio.h> /* struct vt_mode */ 38#include <sys/endian.h> 39#include <sys/fbio.h> /* video_adapter_t */ 40#include <sys/lock.h> 41#include <sys/mutex.h> 42#include <sys/rman.h> 43#include <sys/systm.h> 44#include <sys/uio.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48#include <machine/vm.h> 49 50#include <dev/terasic/mtl/terasic_mtl.h> 51 52static d_mmap_t terasic_mtl_reg_mmap; 53static d_read_t terasic_mtl_reg_read; 54static d_write_t terasic_mtl_reg_write; 55 56static struct cdevsw terasic_mtl_reg_cdevsw = { 57 .d_version = D_VERSION, 58 .d_mmap = terasic_mtl_reg_mmap, 59 .d_read = terasic_mtl_reg_read, 60 .d_write = terasic_mtl_reg_write, 61 .d_name = "terasic_mtl_reg", 62}; 63 64/* 65 * All I/O to/from the MTL register device must be 32-bit, and aligned to 66 * 32-bit. 67 */ 68static int 69terasic_mtl_reg_read(struct cdev *dev, struct uio *uio, int flag) 70{ 71 struct terasic_mtl_softc *sc; 72 u_long offset, size; 73 uint32_t v; 74 int error; 75 76 if (uio->uio_offset < 0 || uio->uio_offset % 4 != 0 || 77 uio->uio_resid % 4 != 0) 78 return (ENODEV); 79 sc = dev->si_drv1; 80 size = rman_get_size(sc->mtl_reg_res); 81 error = 0; 82 if ((uio->uio_offset + uio->uio_resid < 0) || 83 (uio->uio_offset + uio->uio_resid > size)) 84 return (ENODEV); 85 while (uio->uio_resid > 0) { 86 offset = uio->uio_offset; 87 if (offset + sizeof(v) > size) 88 return (ENODEV); 89 v = bus_read_4(sc->mtl_reg_res, offset); 90 error = uiomove(&v, sizeof(v), uio); 91 if (error) 92 return (error); 93 } 94 return (error); 95} 96 97static int 98terasic_mtl_reg_write(struct cdev *dev, struct uio *uio, int flag) 99{ 100 struct terasic_mtl_softc *sc; 101 u_long offset, size; 102 uint32_t v; 103 int error; 104 105 if (uio->uio_offset < 0 || uio->uio_offset % 4 != 0 || 106 uio->uio_resid % 4 != 0) 107 return (ENODEV); 108 sc = dev->si_drv1; 109 size = rman_get_size(sc->mtl_reg_res); 110 error = 0; 111 while (uio->uio_resid > 0) { 112 offset = uio->uio_offset; 113 if (offset + sizeof(v) > size) 114 return (ENODEV); 115 error = uiomove(&v, sizeof(v), uio); 116 if (error) 117 return (error); 118 bus_write_4(sc->mtl_reg_res, offset, v); 119 } 120 return (error); 121} 122 123static int 124terasic_mtl_reg_mmap(struct cdev *dev, vm_ooffset_t offset, vm_paddr_t *paddr, 125 int nprot, vm_memattr_t *memattr) 126{ 127 struct terasic_mtl_softc *sc; 128 int error; 129 130 sc = dev->si_drv1; 131 error = 0; 132 if (trunc_page(offset) == offset && 133 rman_get_size(sc->mtl_reg_res) >= offset + PAGE_SIZE) { 134 *paddr = rman_get_start(sc->mtl_reg_res) + offset; 135 *memattr = VM_MEMATTR_UNCACHEABLE; 136 } else 137 error = ENODEV; 138 return (error); 139} 140 141void 142terasic_mtl_reg_blend_get(struct terasic_mtl_softc *sc, uint32_t *blendp) 143{ 144 145 *blendp = le32toh(bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_BLEND)); 146} 147 148void 149terasic_mtl_reg_blend_set(struct terasic_mtl_softc *sc, uint32_t blend) 150{ 151 152 bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_BLEND, htole32(blend)); 153} 154 155void 156terasic_mtl_blend_default_set(struct terasic_mtl_softc *sc, uint8_t colour) 157{ 158 uint32_t v; 159 160 TERASIC_MTL_LOCK(sc); 161 terasic_mtl_reg_blend_get(sc, &v); 162 v &= ~TERASIC_MTL_BLEND_DEFAULT_MASK; 163 v |= colour << TERASIC_MTL_BLEND_DEFAULT_SHIFT; 164 terasic_mtl_reg_blend_set(sc, v); 165 TERASIC_MTL_UNLOCK(sc); 166} 167 168void 169terasic_mtl_blend_pixel_set(struct terasic_mtl_softc *sc, uint8_t alpha) 170{ 171 uint32_t v; 172 173 TERASIC_MTL_LOCK(sc); 174 terasic_mtl_reg_blend_get(sc, &v); 175 v &= ~TERASIC_MTL_BLEND_PIXEL_MASK; 176 v |= alpha << TERASIC_MTL_BLEND_PIXEL_SHIFT; 177 terasic_mtl_reg_blend_set(sc, v); 178 TERASIC_MTL_UNLOCK(sc); 179} 180 181void 182terasic_mtl_blend_textfg_set(struct terasic_mtl_softc *sc, uint8_t alpha) 183{ 184 uint32_t v; 185 186 TERASIC_MTL_LOCK(sc); 187 terasic_mtl_reg_blend_get(sc, &v); 188 v &= ~TERASIC_MTL_BLEND_TEXTFG_MASK; 189 v |= alpha << TERASIC_MTL_BLEND_TEXTFG_SHIFT; 190 terasic_mtl_reg_blend_set(sc, v); 191 TERASIC_MTL_UNLOCK(sc); 192} 193 194void 195terasic_mtl_blend_textbg_set(struct terasic_mtl_softc *sc, uint8_t alpha) 196{ 197 uint32_t v; 198 199 TERASIC_MTL_LOCK(sc); 200 terasic_mtl_reg_blend_get(sc, &v); 201 v &= ~TERASIC_MTL_BLEND_TEXTBG_MASK; 202 v |= alpha << TERASIC_MTL_BLEND_TEXTBG_SHIFT; 203 terasic_mtl_reg_blend_set(sc, v); 204 TERASIC_MTL_UNLOCK(sc); 205} 206 207void 208terasic_mtl_reg_textcursor_get(struct terasic_mtl_softc *sc, uint8_t *colp, 209 uint8_t *rowp) 210{ 211 uint32_t v; 212 213 v = bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTCURSOR); 214 v = le32toh(v); 215 *colp = (v & TERASIC_MTL_TEXTCURSOR_COL_MASK) >> 216 TERASIC_MTL_TEXTCURSOR_COL_SHIFT; 217 *rowp = (v & TERASIC_MTL_TEXTCURSOR_ROW_MASK); 218} 219 220void 221terasic_mtl_reg_textcursor_set(struct terasic_mtl_softc *sc, uint8_t col, 222 uint8_t row) 223{ 224 uint32_t v; 225 226 v = (col << TERASIC_MTL_TEXTCURSOR_COL_SHIFT) | row; 227 v = htole32(v); 228 bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTCURSOR, v); 229} 230 231void 232terasic_mtl_reg_blank(struct terasic_mtl_softc *sc) 233{ 234 235 device_printf(sc->mtl_dev, "%s: not yet", __func__); 236} 237 238void 239terasic_mtl_reg_textframebufaddr_get(struct terasic_mtl_softc *sc, 240 uint32_t *addrp) 241{ 242 uint32_t addr; 243 244 addr = bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTFRAMEBUFADDR); 245 *addrp = le32toh(addr); 246} 247 248void 249terasic_mtl_reg_textframebufaddr_set(struct terasic_mtl_softc *sc, 250 uint32_t addr) 251{ 252 253 addr = htole32(addr); 254 bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTFRAMEBUFADDR, addr); 255} 256 257int 258terasic_mtl_reg_attach(struct terasic_mtl_softc *sc) 259{ 260 261 sc->mtl_reg_cdev = make_dev(&terasic_mtl_reg_cdevsw, sc->mtl_unit, 262 UID_ROOT, GID_WHEEL, 0400, "mtl_reg%d", sc->mtl_unit); 263 if (sc->mtl_reg_cdev == NULL) { 264 device_printf(sc->mtl_dev, "%s: make_dev failed\n", __func__); 265 return (ENXIO); 266 } 267 /* XXXRW: Slight race between make_dev(9) and here. */ 268 sc->mtl_reg_cdev->si_drv1 = sc; 269 return (0); 270} 271 272void 273terasic_mtl_reg_detach(struct terasic_mtl_softc *sc) 274{ 275 276 if (sc->mtl_reg_cdev != NULL) 277 destroy_dev(sc->mtl_reg_cdev); 278} 279