1/* $NecBSD: tmc18c30.c,v 1.28.12.3 2001/06/19 04:35:48 honda Exp $ */ 2/* $NetBSD$ */ 3 4#define STG_DEBUG 5#define STG_STATICS 6#define STG_IO_CONTROL_FLAGS (STG_FIFO_INTERRUPTS | STG_WAIT_FOR_SELECT) 7 8/*- 9 * [NetBSD for NEC PC-98 series] 10 * Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001 11 * NetBSD/pc98 porting staff. All rights reserved. 12 * Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001 13 * Naofumi HONDA. All rights reserved. 14 * Copyright (c) 1996, 1997, 1998, 1999 15 * Kouichi Matsuda. All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. The name of the author may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 30 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 31 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 32 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 33 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD$"); 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/kernel.h> 47#include <sys/bio.h> 48#include <sys/buf.h> 49#include <sys/queue.h> 50#include <sys/malloc.h> 51#include <sys/errno.h> 52 53#include <machine/cpu.h> 54#include <machine/bus.h> 55 56#include <cam/scsi/scsi_low.h> 57#include <dev/stg/tmc18c30reg.h> 58#include <dev/stg/tmc18c30var.h> 59 60/*************************************************** 61 * USER SETTINGS 62 ***************************************************/ 63/* DEVICE CONFIGURATION FLAGS (MINOR) 64 * 65 * 0x01 DISCONNECT OFF 66 * 0x02 PARITY LINE OFF 67 * 0x04 IDENTIFY MSG OFF ( = single lun) 68 * 0x08 SYNC TRANSFER OFF 69 */ 70/* #define STG_SYNC_SUPPORT */ /* NOT YET but easy */ 71 72/* For the 512 fifo type: change below */ 73#define TMC18C30_FIFOSZ 0x800 74#define TMC18C30_FCBSZ 0x200 75#define TMC18C50_FIFOSZ 0x2000 76#define TMC18C50_FCBSZ 0x400 77 78#define STG_MAX_DATA_SIZE (64 * 1024) 79#define STG_DELAY_MAX (2 * 1000 * 1000) 80#define STG_DELAY_INTERVAL (1) 81#define STG_DELAY_SELECT_POLLING_MAX (5 * 1000 * 1000) 82 83/*************************************************** 84 * PARAMS 85 ***************************************************/ 86#define STG_NTARGETS 8 87#define STG_NLUNS 8 88 89/*************************************************** 90 * DEBUG 91 ***************************************************/ 92#ifdef STG_DEBUG 93static int stg_debug; 94#endif /* STG_DEBUG */ 95 96#ifdef STG_STATICS 97static struct stg_statics { 98 int arbit_fail_0; 99 int arbit_fail_1; 100 int disconnect; 101 int reselect; 102} stg_statics; 103#endif /* STG_STATICS */ 104 105/*************************************************** 106 * IO control flags 107 ***************************************************/ 108#define STG_FIFO_INTERRUPTS 0x0001 109#define STG_WAIT_FOR_SELECT 0x0100 110 111int stg_io_control = STG_IO_CONTROL_FLAGS; 112 113/*************************************************** 114 * DEVICE STRUCTURE 115 ***************************************************/ 116extern struct cfdriver stg_cd; 117 118/************************************************************** 119 * DECLARE 120 **************************************************************/ 121/* static */ 122static void stg_pio_read(struct stg_softc *, struct targ_info *, u_int); 123static void stg_pio_write(struct stg_softc *, struct targ_info *, u_int); 124static int stg_xfer(struct stg_softc *, u_int8_t *, int, int, int); 125static int stg_msg(struct stg_softc *, struct targ_info *, u_int); 126static int stg_reselected(struct stg_softc *); 127static int stg_disconnected(struct stg_softc *, struct targ_info *); 128static __inline void stg_pdma_end(struct stg_softc *, struct targ_info *); 129static int stghw_select_targ_wait(struct stg_softc *, int); 130static int stghw_check(struct stg_softc *); 131static void stghw_init(struct stg_softc *); 132static int stg_negate_signal(struct stg_softc *, u_int8_t, u_char *); 133static int stg_expect_signal(struct stg_softc *, u_int8_t, u_int8_t); 134static int stg_world_start(struct stg_softc *, int); 135static int stghw_start_selection(struct stg_softc *sc, struct slccb *); 136static void stghw_bus_reset(struct stg_softc *); 137static void stghw_attention(struct stg_softc *); 138static int stg_target_nexus_establish(struct stg_softc *); 139static int stg_lun_nexus_establish(struct stg_softc *); 140static int stg_ccb_nexus_establish(struct stg_softc *); 141static int stg_targ_init(struct stg_softc *, struct targ_info *, int); 142static __inline void stghw_bcr_write_1(struct stg_softc *, u_int8_t); 143static int stg_timeout(struct stg_softc *); 144static void stg_selection_done_and_expect_msgout(struct stg_softc *); 145 146struct scsi_low_funcs stgfuncs = { 147 SC_LOW_INIT_T stg_world_start, 148 SC_LOW_BUSRST_T stghw_bus_reset, 149 SC_LOW_TARG_INIT_T stg_targ_init, 150 SC_LOW_LUN_INIT_T NULL, 151 152 SC_LOW_SELECT_T stghw_start_selection, 153 SC_LOW_NEXUS_T stg_lun_nexus_establish, 154 SC_LOW_NEXUS_T stg_ccb_nexus_establish, 155 156 SC_LOW_ATTEN_T stghw_attention, 157 SC_LOW_MSG_T stg_msg, 158 159 SC_LOW_TIMEOUT_T stg_timeout, 160 SC_LOW_POLL_T stgintr, 161 162 NULL, 163}; 164 165/**************************************************** 166 * hwfuncs 167 ****************************************************/ 168static __inline void 169stghw_bcr_write_1(struct stg_softc *sc, u_int8_t bcv) 170{ 171 172 bus_space_write_1(sc->sc_iot, sc->sc_ioh, tmc_bctl, bcv); 173 sc->sc_busimg = bcv; 174} 175 176static int 177stghw_check(sc) 178 struct stg_softc *sc; 179{ 180 struct scsi_low_softc *slp = &sc->sc_sclow; 181 bus_space_tag_t iot = sc->sc_iot; 182 bus_space_handle_t ioh = sc->sc_ioh; 183 u_int fcbsize, fcb; 184 u_int16_t lsb, msb; 185 186 lsb = bus_space_read_1(iot, ioh, tmc_idlsb); 187 msb = bus_space_read_1(iot, ioh, tmc_idmsb); 188 switch (msb << 8 | lsb) 189 { 190 case 0x6127: 191 /* TMCCHIP_1800 not supported. (it's my policy) */ 192 sc->sc_chip = TMCCHIP_1800; 193 return EINVAL; 194 195 case 0x60e9: 196 if (bus_space_read_1(iot, ioh, tmc_cfg2) & 0x02) 197 { 198 sc->sc_chip = TMCCHIP_18C30; 199 sc->sc_fsz = TMC18C30_FIFOSZ; 200 fcbsize = TMC18C30_FCBSZ; 201 } 202 else 203 { 204 sc->sc_chip = TMCCHIP_18C50; 205 sc->sc_fsz = TMC18C50_FIFOSZ; 206 fcbsize = TMC18C50_FCBSZ; 207 } 208 break; 209 210 default: 211 sc->sc_chip = TMCCHIP_UNK; 212 return ENODEV; 213 } 214 215 sc->sc_fcRinit = FCTL_INTEN; 216 sc->sc_fcWinit = FCTL_PARENB | FCTL_INTEN; 217 218 if (slp->sl_cfgflags & CFG_NOATTEN) 219 sc->sc_imsg = 0; 220 else 221 sc->sc_imsg = BCTL_ATN; 222 sc->sc_busc = BCTL_BUSEN; 223 224 sc->sc_wthold = fcbsize + 256; 225 sc->sc_rthold = fcbsize - 256; 226 sc->sc_maxwsize = sc->sc_fsz; 227 228 fcb = fcbsize / (sc->sc_fsz / 16); 229 sc->sc_icinit = ICTL_CD | ICTL_SEL | ICTL_ARBIT | fcb; 230 return 0; 231} 232 233static void 234stghw_init(sc) 235 struct stg_softc *sc; 236{ 237 bus_space_tag_t iot = sc->sc_iot; 238 bus_space_handle_t ioh = sc->sc_ioh; 239 240 bus_space_write_1(iot, ioh, tmc_ictl, 0); 241 stghw_bcr_write_1(sc, BCTL_BUSFREE); 242 bus_space_write_1(iot, ioh, tmc_fctl, 243 sc->sc_fcRinit | FCTL_CLRFIFO | FCTL_CLRINT); 244 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit); 245 bus_space_write_1(iot, ioh, tmc_ictl, sc->sc_icinit); 246 247 bus_space_write_1(iot, ioh, tmc_ssctl, 0); 248} 249 250static int 251stg_targ_init(sc, ti, action) 252 struct stg_softc *sc; 253 struct targ_info *ti; 254 int action; 255{ 256 struct stg_targ_info *sti = (void *) ti; 257 258 if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE) 259 { 260 ti->ti_width = SCSI_LOW_BUS_WIDTH_8; 261 ti->ti_maxsynch.period = 0; 262 ti->ti_maxsynch.offset = 0; 263 sti->sti_reg_synch = 0; 264 } 265 return 0; 266} 267 268/**************************************************** 269 * scsi low interface 270 ****************************************************/ 271static void 272stghw_attention(sc) 273 struct stg_softc *sc; 274{ 275 276 sc->sc_busc |= BCTL_ATN; 277 sc->sc_busimg |= BCTL_ATN; 278 bus_space_write_1(sc->sc_iot, sc->sc_ioh, tmc_bctl, sc->sc_busimg); 279 DELAY(10); 280} 281 282static void 283stghw_bus_reset(sc) 284 struct stg_softc *sc; 285{ 286 bus_space_tag_t iot = sc->sc_iot; 287 bus_space_handle_t ioh = sc->sc_ioh; 288 289 bus_space_write_1(iot, ioh, tmc_ictl, 0); 290 bus_space_write_1(iot, ioh, tmc_fctl, 0); 291 stghw_bcr_write_1(sc, BCTL_RST); 292 DELAY(100000); 293 stghw_bcr_write_1(sc, BCTL_BUSFREE); 294} 295 296static int 297stghw_start_selection(sc, cb) 298 struct stg_softc *sc; 299 struct slccb *cb; 300{ 301 bus_space_tag_t iot = sc->sc_iot; 302 bus_space_handle_t ioh = sc->sc_ioh; 303 struct targ_info *ti = cb->ti; 304 register u_int8_t stat; 305 int s; 306 307 sc->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000; 308 sc->sc_dataout_timeout = 0; 309 sc->sc_ubf_timeout = 0; 310 stghw_bcr_write_1(sc, BCTL_BUSFREE); 311 bus_space_write_1(iot, ioh, tmc_ictl, sc->sc_icinit); 312 313 s = splhigh(); 314 stat = bus_space_read_1(iot, ioh, tmc_astat); 315 if ((stat & ASTAT_INT) != 0) 316 { 317 splx(s); 318 return SCSI_LOW_START_FAIL; 319 } 320 321 bus_space_write_1(iot, ioh, tmc_scsiid, sc->sc_idbit); 322 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit | FCTL_ARBIT); 323 splx(s); 324 325 SCSI_LOW_SETUP_PHASE(ti, PH_ARBSTART); 326 return SCSI_LOW_START_OK; 327} 328 329static int 330stg_world_start(sc, fdone) 331 struct stg_softc *sc; 332 int fdone; 333{ 334 struct scsi_low_softc *slp = &sc->sc_sclow; 335 int error; 336 337 if ((slp->sl_cfgflags & CFG_NOPARITY) == 0) 338 sc->sc_fcRinit |= FCTL_PARENB; 339 else 340 sc->sc_fcRinit &= ~FCTL_PARENB; 341 342 if ((error = stghw_check(sc)) != 0) 343 return error; 344 345 stghw_init(sc); 346 scsi_low_bus_reset(slp); 347 stghw_init(sc); 348 349 return 0; 350} 351 352static int 353stg_msg(sc, ti, msg) 354 struct stg_softc *sc; 355 struct targ_info *ti; 356 u_int msg; 357{ 358 bus_space_tag_t iot = sc->sc_iot; 359 bus_space_handle_t ioh = sc->sc_ioh; 360 struct stg_targ_info *sti = (void *) ti; 361 u_int period, offset; 362 363 if ((msg & SCSI_LOW_MSG_WIDE) != 0) 364 { 365 if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8) 366 { 367 ti->ti_width = SCSI_LOW_BUS_WIDTH_8; 368 return EINVAL; 369 } 370 return 0; 371 } 372 373 if ((msg & SCSI_LOW_MSG_SYNCH) == 0) 374 return 0; 375 376 period = ti->ti_maxsynch.period; 377 offset = ti->ti_maxsynch.offset; 378 period = period << 2; 379 if (period >= 200) 380 { 381 sti->sti_reg_synch = (period - 200) / 50; 382 if (period % 50) 383 sti->sti_reg_synch ++; 384 sti->sti_reg_synch |= SSCTL_SYNCHEN; 385 } 386 else if (period >= 100) 387 { 388 sti->sti_reg_synch = (period - 100) / 50; 389 if (period % 50) 390 sti->sti_reg_synch ++; 391 sti->sti_reg_synch |= SSCTL_SYNCHEN | SSCTL_FSYNCHEN; 392 } 393 bus_space_write_1(iot, ioh, tmc_ssctl, sti->sti_reg_synch); 394 return 0; 395} 396 397/************************************************************** 398 * General probe attach 399 **************************************************************/ 400int 401stgprobesubr(iot, ioh, dvcfg) 402 bus_space_tag_t iot; 403 bus_space_handle_t ioh; 404 u_int dvcfg; 405{ 406 u_int16_t lsb, msb; 407 408 lsb = bus_space_read_1(iot, ioh, tmc_idlsb); 409 msb = bus_space_read_1(iot, ioh, tmc_idmsb); 410 switch (msb << 8 | lsb) 411 { 412 default: 413 return 0; 414 case 0x6127: 415 /* not support! */ 416 return 0; 417 case 0x60e9: 418 return 1; 419 } 420 return 0; 421} 422 423void 424stgattachsubr(sc) 425 struct stg_softc *sc; 426{ 427 struct scsi_low_softc *slp = &sc->sc_sclow; 428 429 printf("\n"); 430 431 sc->sc_idbit = (1 << slp->sl_hostid); 432 slp->sl_funcs = &stgfuncs; 433 sc->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */ 434 435 slp->sl_flags |= HW_READ_PADDING; 436 slp->sl_cfgflags |= CFG_ASYNC; /* XXX */ 437 438 (void) scsi_low_attach(slp, 0, STG_NTARGETS, STG_NLUNS, 439 sizeof(struct stg_targ_info), 0); 440} 441 442/************************************************************** 443 * PDMA functions 444 **************************************************************/ 445static __inline void 446stg_pdma_end(sc, ti) 447 struct stg_softc *sc; 448 struct targ_info *ti; 449{ 450 struct scsi_low_softc *slp = &sc->sc_sclow; 451 bus_space_tag_t iot = sc->sc_iot; 452 bus_space_handle_t ioh = sc->sc_ioh; 453 struct slccb *cb = slp->sl_Qnexus; 454 u_int len, tres; 455 456 slp->sl_flags &= ~HW_PDMASTART; 457 sc->sc_icinit &= ~ICTL_FIFO; 458 sc->sc_dataout_timeout = 0; 459 460 if (cb == NULL) 461 { 462 slp->sl_error |= PDMAERR; 463 goto out; 464 } 465 466 if (ti->ti_phase == PH_DATA) 467 { 468 len = bus_space_read_2(iot, ioh, tmc_fdcnt); 469 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE) 470 { 471 if (len != 0) 472 { 473 tres = len + slp->sl_scp.scp_datalen; 474 if (tres <= (u_int) cb->ccb_scp.scp_datalen) 475 { 476 slp->sl_scp.scp_data -= len; 477 slp->sl_scp.scp_datalen = tres; 478 } 479 else 480 { 481 slp->sl_error |= PDMAERR; 482 device_printf(slp->sl_dev, 483 "len %x >= datalen %x\n", 484 len, slp->sl_scp.scp_datalen); 485 } 486 } 487 } 488 else if (slp->sl_scp.scp_direction == SCSI_LOW_READ) 489 { 490 if (len != 0) 491 { 492 slp->sl_error |= PDMAERR; 493 device_printf(slp->sl_dev, 494 "len %x left in fifo\n", len); 495 } 496 } 497 scsi_low_data_finish(slp); 498 } 499 else 500 { 501 502 device_printf(slp->sl_dev, "data phase miss\n"); 503 slp->sl_error |= PDMAERR; 504 } 505 506out: 507 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit); 508} 509 510static void 511stg_pio_read(sc, ti, thold) 512 struct stg_softc *sc; 513 struct targ_info *ti; 514 u_int thold; 515{ 516 struct scsi_low_softc *slp = &sc->sc_sclow; 517 bus_space_tag_t iot = sc->sc_iot; 518 bus_space_handle_t ioh = sc->sc_ioh; 519 struct sc_p *sp = &slp->sl_scp; 520 int s, tout; 521 u_int res; 522 u_int8_t stat; 523 524 if ((slp->sl_flags & HW_PDMASTART) == 0) 525 { 526 bus_space_write_1(iot, ioh, tmc_fctl, 527 sc->sc_fcRinit | FCTL_FIFOEN); 528 slp->sl_flags |= HW_PDMASTART; 529 } 530 531 tout = sc->sc_tmaxcnt; 532 while (tout -- > 0) 533 { 534 if (thold > 0) 535 { 536 s = splhigh(); 537 res = bus_space_read_2(iot, ioh, tmc_fdcnt); 538 if (res < thold) 539 { 540 bus_space_write_1(iot, ioh, tmc_ictl, 541 sc->sc_icinit); 542 splx(s); 543 break; 544 } 545 splx(s); 546 } 547 else 548 { 549 stat = bus_space_read_1(iot, ioh, tmc_bstat); 550 res = bus_space_read_2(iot, ioh, tmc_fdcnt); 551 if (res == 0) 552 { 553 if ((stat & PHASE_MASK) != DATA_IN_PHASE) 554 break; 555 if (sp->scp_datalen <= 0) 556 break; 557 DELAY(1); 558 continue; 559 } 560 } 561 562 /* The assumtion res != 0 is valid here */ 563 if (res > sp->scp_datalen) 564 { 565 if (res == (u_int) -1) 566 break; 567 568 slp->sl_error |= PDMAERR; 569 if ((slp->sl_flags & HW_READ_PADDING) == 0) 570 { 571 device_printf(slp->sl_dev, 572 "read padding required\n"); 573 break; 574 } 575 576 sp->scp_datalen = 0; 577 if (res > STG_MAX_DATA_SIZE) 578 res = STG_MAX_DATA_SIZE; 579 while (res -- > 0) 580 { 581 (void) bus_space_read_1(iot, ioh, tmc_rfifo); 582 } 583 continue; 584 } 585 586 sp->scp_datalen -= res; 587 if (res & 1) 588 { 589 *sp->scp_data = bus_space_read_1(iot, ioh, tmc_rfifo); 590 sp->scp_data ++; 591 res --; 592 } 593 594 bus_space_read_multi_2(iot, ioh, tmc_rfifo, 595 (u_int16_t *) sp->scp_data, res >> 1); 596 sp->scp_data += res; 597 } 598 599 if (tout <= 0) 600 device_printf(slp->sl_dev, "pio read timeout\n"); 601} 602 603static void 604stg_pio_write(sc, ti, thold) 605 struct stg_softc *sc; 606 struct targ_info *ti; 607 u_int thold; 608{ 609 struct scsi_low_softc *slp = &sc->sc_sclow; 610 bus_space_tag_t iot = sc->sc_iot; 611 bus_space_handle_t ioh = sc->sc_ioh; 612 struct sc_p *sp = &slp->sl_scp; 613 u_int res; 614 int s, tout; 615 register u_int8_t stat; 616 617 if ((slp->sl_flags & HW_PDMASTART) == 0) 618 { 619 stat = sc->sc_fcWinit | FCTL_FIFOEN | FCTL_FIFOW; 620 bus_space_write_1(iot, ioh, tmc_fctl, stat | FCTL_CLRFIFO); 621 bus_space_write_1(iot, ioh, tmc_fctl, stat); 622 slp->sl_flags |= HW_PDMASTART; 623 } 624 625 tout = sc->sc_tmaxcnt; 626 while (tout -- > 0) 627 { 628 stat = bus_space_read_1(iot, ioh, tmc_bstat); 629 if ((stat & PHASE_MASK) != DATA_OUT_PHASE) 630 break; 631 632 if (sp->scp_datalen <= 0) 633 { 634 if (sc->sc_dataout_timeout == 0) 635 sc->sc_dataout_timeout = SCSI_LOW_TIMEOUT_HZ; 636 break; 637 } 638 639 if (thold > 0) 640 { 641 s = splhigh(); 642 res = bus_space_read_2(iot, ioh, tmc_fdcnt); 643 if (res > thold) 644 { 645 bus_space_write_1(iot, ioh, tmc_ictl, 646 sc->sc_icinit); 647 splx(s); 648 break; 649 } 650 splx(s); 651 } 652 else 653 { 654 res = bus_space_read_2(iot, ioh, tmc_fdcnt); 655 if (res > sc->sc_maxwsize / 2) 656 { 657 DELAY(1); 658 continue; 659 } 660 } 661 662 if (res == (u_int) -1) 663 break; 664 res = sc->sc_maxwsize - res; 665 if (res > sp->scp_datalen) 666 res = sp->scp_datalen; 667 668 sp->scp_datalen -= res; 669 if ((res & 0x1) != 0) 670 { 671 bus_space_write_1(iot, ioh, tmc_wfifo, *sp->scp_data); 672 sp->scp_data ++; 673 res --; 674 } 675 676 bus_space_write_multi_2(iot, ioh, tmc_wfifo, 677 (u_int16_t *) sp->scp_data, res >> 1); 678 sp->scp_data += res; 679 } 680 681 if (tout <= 0) 682 device_printf(slp->sl_dev, "pio write timeout\n"); 683} 684 685static int 686stg_negate_signal(struct stg_softc *sc, u_int8_t mask, u_char *s) 687{ 688 struct scsi_low_softc *slp = &sc->sc_sclow; 689 bus_space_tag_t bst = sc->sc_iot; 690 bus_space_handle_t bsh = sc->sc_ioh; 691 int wc; 692 u_int8_t regv; 693 694 for (wc = 0; wc < STG_DELAY_MAX / STG_DELAY_INTERVAL; wc ++) 695 { 696 regv = bus_space_read_1(bst, bsh, tmc_bstat); 697 if (regv == (u_int8_t) -1) 698 return -1; 699 if ((regv & mask) == 0) 700 return 1; 701 702 DELAY(STG_DELAY_INTERVAL); 703 } 704 705 device_printf(slp->sl_dev, "%s stg_negate_signal timeout\n", s); 706 return -1; 707} 708 709static int 710stg_expect_signal(struct stg_softc *sc, u_int8_t phase, u_int8_t mask) 711{ 712 struct scsi_low_softc *slp = &sc->sc_sclow; 713 bus_space_tag_t bst = sc->sc_iot; 714 bus_space_handle_t bsh = sc->sc_ioh; 715 int wc; 716 u_int8_t ph; 717 718 phase &= PHASE_MASK; 719 for (wc = 0; wc < STG_DELAY_MAX / STG_DELAY_INTERVAL; wc ++) 720 { 721 ph = bus_space_read_1(bst, bsh, tmc_bstat); 722 if (ph == (u_int8_t) -1) 723 return -1; 724 if ((ph & PHASE_MASK) != phase) 725 return 0; 726 if ((ph & mask) != 0) 727 return 1; 728 729 DELAY(STG_DELAY_INTERVAL); 730 } 731 732 device_printf(slp->sl_dev, "stg_expect_signal timeout\n"); 733 return -1; 734} 735 736static int 737stg_xfer(sc, buf, len, phase, clear_atn) 738 struct stg_softc *sc; 739 u_int8_t *buf; 740 int len; 741 int phase; 742 int clear_atn; 743{ 744 bus_space_tag_t iot = sc->sc_iot; 745 bus_space_handle_t ioh = sc->sc_ioh; 746 int rv, ptr; 747 748 if (phase & BSTAT_IO) 749 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit); 750 else 751 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcWinit); 752 753 for (ptr = 0; len > 0; len --) 754 { 755 rv = stg_expect_signal(sc, phase, BSTAT_REQ); 756 if (rv <= 0) 757 goto bad; 758 759 if (len == 1 && clear_atn != 0) 760 { 761 sc->sc_busc &= ~BCTL_ATN; 762 stghw_bcr_write_1(sc, sc->sc_busc); 763 SCSI_LOW_DEASSERT_ATN(&sc->sc_sclow); 764 } 765 766 if (phase & BSTAT_IO) 767 { 768 buf[ptr ++] = bus_space_read_1(iot, ioh, tmc_rdata); 769 } 770 else 771 { 772 bus_space_write_1(iot, ioh, tmc_wdata, buf[ptr ++]); 773 } 774 775 stg_negate_signal(sc, BSTAT_ACK, "xfer<ACK>"); 776 } 777 778bad: 779 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit); 780 return len; 781} 782 783/************************************************************** 784 * disconnect & reselect (HW low) 785 **************************************************************/ 786static int 787stg_reselected(sc) 788 struct stg_softc *sc; 789{ 790 struct scsi_low_softc *slp = &sc->sc_sclow; 791 bus_space_tag_t iot = sc->sc_iot; 792 bus_space_handle_t ioh = sc->sc_ioh; 793 int tout; 794 u_int sid; 795 u_int8_t regv; 796 797 if (slp->sl_selid != NULL) 798 { 799 /* XXX: 800 * Selection vs Reselection conflicts. 801 */ 802 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit); 803 stghw_bcr_write_1(sc, BCTL_BUSFREE); 804 } 805 else if (slp->sl_Tnexus != NULL) 806 { 807 device_printf(slp->sl_dev, "unexpected termination\n"); 808 stg_disconnected(sc, slp->sl_Tnexus); 809 } 810 811 /* XXX: 812 * We should ack the reselection as soon as possible, 813 * because the target would abort the current reselection seq 814 * due to reselection timeout. 815 */ 816 tout = STG_DELAY_SELECT_POLLING_MAX; 817 while (tout -- > 0) 818 { 819 regv = bus_space_read_1(iot, ioh, tmc_bstat); 820 if ((regv & (BSTAT_IO | BSTAT_SEL | BSTAT_BSY)) == 821 (BSTAT_IO | BSTAT_SEL)) 822 { 823 DELAY(1); 824 regv = bus_space_read_1(iot, ioh, tmc_bstat); 825 if ((regv & (BSTAT_IO | BSTAT_SEL | BSTAT_BSY)) == 826 (BSTAT_IO | BSTAT_SEL)) 827 goto reselect_start; 828 } 829 DELAY(1); 830 } 831 device_printf(slp->sl_dev, "reselction timeout I\n"); 832 return EJUSTRETURN; 833 834reselect_start: 835 sid = (u_int) bus_space_read_1(iot, ioh, tmc_scsiid); 836 if ((sid & sc->sc_idbit) == 0) 837 { 838 /* not us */ 839 return EJUSTRETURN; 840 } 841 842 bus_space_write_1(iot, ioh, tmc_fctl, 843 sc->sc_fcRinit | FCTL_CLRFIFO | FCTL_CLRINT); 844 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit); 845 stghw_bcr_write_1(sc, sc->sc_busc | BCTL_BSY); 846 847 while (tout -- > 0) 848 { 849 regv = bus_space_read_1(iot, ioh, tmc_bstat); 850 if ((regv & (BSTAT_SEL | BSTAT_BSY)) == BSTAT_BSY) 851 goto reselected; 852 DELAY(1); 853 } 854 device_printf(slp->sl_dev, "reselction timeout II\n"); 855 return EJUSTRETURN; 856 857reselected: 858 sid &= ~sc->sc_idbit; 859 sid = ffs(sid) - 1; 860 if (scsi_low_reselected(slp, sid) == NULL) 861 return EJUSTRETURN; 862 863#ifdef STG_STATICS 864 stg_statics.reselect ++; 865#endif /* STG_STATICS */ 866 return EJUSTRETURN; 867} 868 869static int 870stg_disconnected(sc, ti) 871 struct stg_softc *sc; 872 struct targ_info *ti; 873{ 874 struct scsi_low_softc *slp = &sc->sc_sclow; 875 bus_space_tag_t iot = sc->sc_iot; 876 bus_space_handle_t ioh = sc->sc_ioh; 877 878 /* clear bus status & fifo */ 879 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit | FCTL_CLRFIFO); 880 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit); 881 stghw_bcr_write_1(sc, BCTL_BUSFREE); 882 sc->sc_icinit &= ~ICTL_FIFO; 883 sc->sc_busc &= ~BCTL_ATN; 884 sc->sc_dataout_timeout = 0; 885 sc->sc_ubf_timeout = 0; 886 887#ifdef STG_STATICS 888 stg_statics.disconnect ++; 889#endif /* STG_STATICS */ 890 scsi_low_disconnected(slp, ti); 891 return 1; 892} 893 894/************************************************************** 895 * SEQUENCER 896 **************************************************************/ 897static int 898stg_target_nexus_establish(sc) 899 struct stg_softc *sc; 900{ 901 struct scsi_low_softc *slp = &sc->sc_sclow; 902 bus_space_tag_t iot = sc->sc_iot; 903 bus_space_handle_t ioh = sc->sc_ioh; 904 struct targ_info *ti = slp->sl_Tnexus; 905 struct stg_targ_info *sti = (void *) ti; 906 907 bus_space_write_1(iot, ioh, tmc_ssctl, sti->sti_reg_synch); 908 if ((stg_io_control & STG_FIFO_INTERRUPTS) != 0) 909 { 910 sc->sc_icinit |= ICTL_FIFO; 911 } 912 return 0; 913} 914 915static int 916stg_lun_nexus_establish(sc) 917 struct stg_softc *sc; 918{ 919 920 return 0; 921} 922 923static int 924stg_ccb_nexus_establish(sc) 925 struct stg_softc *sc; 926{ 927 struct scsi_low_softc *slp = &sc->sc_sclow; 928 struct slccb *cb = slp->sl_Qnexus; 929 930 sc->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000; 931 return 0; 932} 933 934#define STGHW_SELECT_INTERVAL 10 935 936static int 937stghw_select_targ_wait(sc, mu) 938 struct stg_softc *sc; 939 int mu; 940{ 941 bus_space_tag_t iot = sc->sc_iot; 942 bus_space_handle_t ioh = sc->sc_ioh; 943 944 mu = mu / STGHW_SELECT_INTERVAL; 945 while (mu -- > 0) 946 { 947 if ((bus_space_read_1(iot, ioh, tmc_bstat) & BSTAT_BSY) == 0) 948 { 949 DELAY(STGHW_SELECT_INTERVAL); 950 continue; 951 } 952 DELAY(1); 953 if ((bus_space_read_1(iot, ioh, tmc_bstat) & BSTAT_BSY) != 0) 954 { 955 return 0; 956 } 957 } 958 return ENXIO; 959} 960 961static void 962stg_selection_done_and_expect_msgout(sc) 963 struct stg_softc *sc; 964{ 965 struct scsi_low_softc *slp = &sc->sc_sclow; 966 bus_space_tag_t iot = sc->sc_iot; 967 bus_space_handle_t ioh = sc->sc_ioh; 968 969 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit | FCTL_CLRFIFO); 970 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit); 971 stghw_bcr_write_1(sc, sc->sc_imsg | sc->sc_busc); 972 SCSI_LOW_ASSERT_ATN(slp); 973} 974 975int 976stgintr(arg) 977 void *arg; 978{ 979 struct stg_softc *sc = arg; 980 struct scsi_low_softc *slp = &sc->sc_sclow; 981 bus_space_tag_t iot = sc->sc_iot; 982 bus_space_handle_t ioh = sc->sc_ioh; 983 struct targ_info *ti; 984 struct buf *bp; 985 u_int derror, flags; 986 int len, s; 987 u_int8_t status, astatus, regv; 988 989 /******************************************* 990 * interrupt check 991 *******************************************/ 992 if (slp->sl_flags & HW_INACTIVE) 993 return 0; 994 995 astatus = bus_space_read_1(iot, ioh, tmc_astat); 996 status = bus_space_read_1(iot, ioh, tmc_bstat); 997 998 if ((astatus & ASTAT_STATMASK) == 0 || astatus == (u_int8_t) -1) 999 return 0; 1000 1001 bus_space_write_1(iot, ioh, tmc_ictl, 0); 1002 if (astatus & ASTAT_SCSIRST) 1003 { 1004 bus_space_write_1(iot, ioh, tmc_fctl, 1005 sc->sc_fcRinit | FCTL_CLRFIFO); 1006 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit); 1007 bus_space_write_1(iot, ioh, tmc_ictl, 0); 1008 1009 scsi_low_restart(slp, SCSI_LOW_RESTART_SOFT, 1010 "bus reset (power off?)"); 1011 return 1; 1012 } 1013 1014 /******************************************* 1015 * debug section 1016 *******************************************/ 1017#ifdef STG_DEBUG 1018 if (stg_debug) 1019 { 1020 scsi_low_print(slp, NULL); 1021 device_printf(slp->sl_dev, "st %x ist %x\n\n", 1022 status, astatus); 1023#ifdef KDB 1024 if (stg_debug > 1) 1025 kdb_enter(KDB_WHY_CAM, "stg"); 1026#endif /* KDB */ 1027 } 1028#endif /* STG_DEBUG */ 1029 1030 /******************************************* 1031 * reselection & nexus 1032 *******************************************/ 1033 if ((status & RESEL_PHASE_MASK)== PHASE_RESELECTED) 1034 { 1035 if (stg_reselected(sc) == EJUSTRETURN) 1036 goto out; 1037 } 1038 1039 if ((ti = slp->sl_Tnexus) == NULL) 1040 return 0; 1041 1042 derror = 0; 1043 if ((astatus & ASTAT_PARERR) != 0 && ti->ti_phase != PH_ARBSTART && 1044 (sc->sc_fcRinit & FCTL_PARENB) != 0) 1045 { 1046 slp->sl_error |= PARITYERR; 1047 derror = SCSI_LOW_DATA_PE; 1048 if ((status & PHASE_MASK) == MESSAGE_IN_PHASE) 1049 scsi_low_assert_msg(slp, ti, SCSI_LOW_MSG_PARITY, 0); 1050 else 1051 scsi_low_assert_msg(slp, ti, SCSI_LOW_MSG_ERROR, 1); 1052 } 1053 1054 /******************************************* 1055 * aribitration & selection 1056 *******************************************/ 1057 switch (ti->ti_phase) 1058 { 1059 case PH_ARBSTART: 1060 if ((astatus & ASTAT_ARBIT) == 0) 1061 { 1062#ifdef STG_STATICS 1063 stg_statics.arbit_fail_0 ++; 1064#endif /* STG_STATICS */ 1065 goto arb_fail; 1066 } 1067 1068 status = bus_space_read_1(iot, ioh, tmc_bstat); 1069 if ((status & BSTAT_IO) != 0) 1070 { 1071 /* XXX: 1072 * Selection vs Reselection conflicts. 1073 */ 1074#ifdef STG_STATICS 1075 stg_statics.arbit_fail_1 ++; 1076#endif /* STG_STATICS */ 1077arb_fail: 1078 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit); 1079 stghw_bcr_write_1(sc, BCTL_BUSFREE); 1080 scsi_low_arbit_fail(slp, slp->sl_Qnexus); 1081 goto out; 1082 } 1083 1084 /* 1085 * selection assert start. 1086 */ 1087 SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART); 1088 scsi_low_arbit_win(slp); 1089 1090 s = splhigh(); 1091 bus_space_write_1(iot, ioh, tmc_scsiid, 1092 sc->sc_idbit | (1 << ti->ti_id)); 1093 stghw_bcr_write_1(sc, sc->sc_imsg | sc->sc_busc | BCTL_SEL); 1094 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcWinit); 1095 if ((stg_io_control & STG_WAIT_FOR_SELECT) != 0) 1096 { 1097 /* selection abort delay 200 + 100 micro sec */ 1098 if (stghw_select_targ_wait(sc, 300) == 0) 1099 { 1100 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED); 1101 stg_selection_done_and_expect_msgout(sc); 1102 } 1103 } 1104 splx(s); 1105 goto out; 1106 1107 case PH_SELSTART: 1108 if ((status & BSTAT_BSY) == 0) 1109 { 1110 /* selection timeout delay 250 ms */ 1111 if (stghw_select_targ_wait(sc, 250 * 1000) != 0) 1112 { 1113 stg_disconnected(sc, ti); 1114 goto out; 1115 } 1116 } 1117 1118 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED); 1119 stg_selection_done_and_expect_msgout(sc); 1120 goto out; 1121 1122 case PH_SELECTED: 1123 if ((status & BSTAT_REQ) == 0) 1124 goto out; 1125 stg_target_nexus_establish(sc); 1126 break; 1127 1128 case PH_RESEL: 1129 if ((status & BSTAT_REQ) == 0) 1130 goto out; 1131 1132 /* clear a busy line */ 1133 bus_space_write_1(iot, ioh, tmc_fctl, sc->sc_fcRinit); 1134 stghw_bcr_write_1(sc, sc->sc_busc); 1135 stg_target_nexus_establish(sc); 1136 if ((status & PHASE_MASK) != MESSAGE_IN_PHASE) 1137 { 1138 device_printf(slp->sl_dev, 1139 "unexpected phase after reselect\n"); 1140 slp->sl_error |= FATALIO; 1141 scsi_low_assert_msg(slp, ti, SCSI_LOW_MSG_ABORT, 1); 1142 goto out; 1143 } 1144 break; 1145 } 1146 1147 /******************************************* 1148 * data phase 1149 *******************************************/ 1150 if ((slp->sl_flags & HW_PDMASTART) && STG_IS_PHASE_DATA(status) == 0) 1151 { 1152 if (slp->sl_scp.scp_direction == SCSI_LOW_READ) 1153 stg_pio_read(sc, ti, 0); 1154 1155 stg_pdma_end(sc, ti); 1156 } 1157 1158 /******************************************* 1159 * scsi seq 1160 *******************************************/ 1161 switch (status & PHASE_MASK) 1162 { 1163 case COMMAND_PHASE: 1164 if (stg_expect_signal(sc, COMMAND_PHASE, BSTAT_REQ) <= 0) 1165 break; 1166 1167 SCSI_LOW_SETUP_PHASE(ti, PH_CMD); 1168 if (scsi_low_cmd(slp, ti) != 0) 1169 { 1170 scsi_low_attention(slp); 1171 } 1172 1173 if (stg_xfer(sc, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen, 1174 COMMAND_PHASE, 0) != 0) 1175 { 1176 device_printf(slp->sl_dev, "CMDOUT short\n"); 1177 } 1178 break; 1179 1180 case DATA_OUT_PHASE: 1181 SCSI_LOW_SETUP_PHASE(ti, PH_DATA); 1182 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0) 1183 { 1184 scsi_low_attention(slp); 1185 } 1186 1187 if ((sc->sc_icinit & ICTL_FIFO) != 0) 1188 stg_pio_write(sc, ti, sc->sc_wthold); 1189 else 1190 stg_pio_write(sc, ti, 0); 1191 break; 1192 1193 case DATA_IN_PHASE: 1194 SCSI_LOW_SETUP_PHASE(ti, PH_DATA); 1195 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0) 1196 { 1197 scsi_low_attention(slp); 1198 } 1199 1200 if ((sc->sc_icinit & ICTL_FIFO) != 0) 1201 stg_pio_read(sc, ti, sc->sc_rthold); 1202 else 1203 stg_pio_read(sc, ti, 0); 1204 break; 1205 1206 case STATUS_PHASE: 1207 regv = stg_expect_signal(sc, STATUS_PHASE, BSTAT_REQ); 1208 if (regv <= 0) 1209 break; 1210 1211 SCSI_LOW_SETUP_PHASE(ti, PH_STAT); 1212 regv = bus_space_read_1(iot, ioh, tmc_sdna); 1213 if (scsi_low_statusin(slp, ti, regv | derror) != 0) 1214 { 1215 scsi_low_attention(slp); 1216 } 1217 if (regv != bus_space_read_1(iot, ioh, tmc_rdata)) 1218 { 1219 device_printf(slp->sl_dev, "STATIN: data mismatch\n"); 1220 } 1221 stg_negate_signal(sc, BSTAT_ACK, "statin<ACK>"); 1222 break; 1223 1224 case MESSAGE_OUT_PHASE: 1225 if (stg_expect_signal(sc, MESSAGE_OUT_PHASE, BSTAT_REQ) <= 0) 1226 break; 1227 1228 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); 1229 flags = (ti->ti_ophase != ti->ti_phase) ? 1230 SCSI_LOW_MSGOUT_INIT : 0; 1231 len = scsi_low_msgout(slp, ti, flags); 1232 1233 if (len > 1 && slp->sl_atten == 0) 1234 { 1235 scsi_low_attention(slp); 1236 } 1237 1238 if (stg_xfer(sc, ti->ti_msgoutstr, len, MESSAGE_OUT_PHASE, 1239 slp->sl_clear_atten) != 0) 1240 { 1241 device_printf(slp->sl_dev, "MSGOUT short\n"); 1242 } 1243 else 1244 { 1245 if (slp->sl_msgphase >= MSGPH_ABORT) 1246 { 1247 stg_disconnected(sc, ti); 1248 } 1249 } 1250 break; 1251 1252 case MESSAGE_IN_PHASE: 1253 /* confirm phase and req signal */ 1254 if (stg_expect_signal(sc, MESSAGE_IN_PHASE, BSTAT_REQ) <= 0) 1255 break; 1256 1257 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN); 1258 1259 /* read data with NOACK */ 1260 regv = bus_space_read_1(iot, ioh, tmc_sdna); 1261 1262 if (scsi_low_msgin(slp, ti, derror | regv) == 0) 1263 { 1264 if (scsi_low_is_msgout_continue(ti, 0) != 0) 1265 { 1266 scsi_low_attention(slp); 1267 } 1268 } 1269 1270 /* read data with ACK */ 1271 if (regv != bus_space_read_1(iot, ioh, tmc_rdata)) 1272 { 1273 device_printf(slp->sl_dev, "MSGIN: data mismatch\n"); 1274 } 1275 1276 /* wait for the ack negated */ 1277 stg_negate_signal(sc, BSTAT_ACK, "msgin<ACK>"); 1278 1279 if (slp->sl_msgphase != 0 && slp->sl_msgphase < MSGPH_ABORT) 1280 { 1281 stg_disconnected(sc, ti); 1282 } 1283 break; 1284 1285 case BUSFREE_PHASE: 1286 device_printf(slp->sl_dev, "unexpected disconnect\n"); 1287 stg_disconnected(sc, ti); 1288 break; 1289 1290 default: 1291 slp->sl_error |= FATALIO; 1292 device_printf(slp->sl_dev, "unknown phase bus %x intr %x\n", 1293 status, astatus); 1294 break; 1295 } 1296 1297out: 1298 bus_space_write_1(iot, ioh, tmc_ictl, sc->sc_icinit); 1299 return 1; 1300} 1301 1302static int 1303stg_timeout(sc) 1304 struct stg_softc *sc; 1305{ 1306 struct scsi_low_softc *slp = &sc->sc_sclow; 1307 bus_space_tag_t iot = sc->sc_iot; 1308 bus_space_handle_t ioh = sc->sc_ioh; 1309 int tout, count; 1310 u_int8_t status; 1311 1312 if (slp->sl_Tnexus == NULL) 1313 return 0; 1314 1315 status = bus_space_read_1(iot, ioh, tmc_bstat); 1316 if ((status & PHASE_MASK) == 0) 1317 { 1318 if (sc->sc_ubf_timeout ++ == 0) 1319 return 0; 1320 1321 device_printf(slp->sl_dev, "unexpected bus free detected\n"); 1322 slp->sl_error |= FATALIO; 1323 scsi_low_print(slp, slp->sl_Tnexus); 1324 stg_disconnected(sc, slp->sl_Tnexus); 1325 return 0; 1326 } 1327 1328 switch (status & PHASE_MASK) 1329 { 1330 case DATA_OUT_PHASE: 1331 if (sc->sc_dataout_timeout == 0) 1332 break; 1333 if ((status & BSTAT_REQ) == 0) 1334 break; 1335 if (bus_space_read_2(iot, ioh, tmc_fdcnt) != 0) 1336 break; 1337 if ((-- sc->sc_dataout_timeout) > 0) 1338 break; 1339 1340 slp->sl_error |= PDMAERR; 1341 if ((slp->sl_flags & HW_WRITE_PADDING) == 0) 1342 { 1343 device_printf(slp->sl_dev, "write padding required\n"); 1344 break; 1345 } 1346 1347 bus_space_write_1(iot, ioh, tmc_ictl, 0); 1348 1349 tout = STG_DELAY_MAX; 1350 while (tout --) 1351 { 1352 status = bus_space_read_1(iot, ioh, tmc_bstat); 1353 if ((status & PHASE_MASK) != DATA_OUT_PHASE) 1354 break; 1355 1356 if (bus_space_read_2(iot, ioh, tmc_fdcnt) != 0) 1357 { 1358 DELAY(1); 1359 continue; 1360 } 1361 1362 for (count = sc->sc_maxwsize; count > 0; count --) 1363 bus_space_write_1(iot, ioh, tmc_wfifo, 0); 1364 } 1365 1366 status = bus_space_read_1(iot, ioh, tmc_bstat); 1367 if ((status & PHASE_MASK) == DATA_OUT_PHASE) 1368 sc->sc_dataout_timeout = SCSI_LOW_TIMEOUT_HZ; 1369 1370 bus_space_write_1(iot, ioh, tmc_ictl, sc->sc_icinit); 1371 break; 1372 1373 default: 1374 break; 1375 } 1376 return 0; 1377} 1378