1/* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <dev/drm2/drmP.h> 31#include <dev/drm2/drm_crtc_helper.h> 32#include <dev/drm2/radeon/radeon_drm.h> 33#include <dev/drm2/drm_fixed.h> 34#include "radeon.h" 35#include "atom.h" 36#include "atom-bits.h" 37 38static void atombios_overscan_setup(struct drm_crtc *crtc, 39 struct drm_display_mode *mode, 40 struct drm_display_mode *adjusted_mode) 41{ 42 struct drm_device *dev = crtc->dev; 43 struct radeon_device *rdev = dev->dev_private; 44 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 45 SET_CRTC_OVERSCAN_PS_ALLOCATION args; 46 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 47 int a1, a2; 48 49 memset(&args, 0, sizeof(args)); 50 51 args.ucCRTC = radeon_crtc->crtc_id; 52 53 switch (radeon_crtc->rmx_type) { 54 case RMX_CENTER: 55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 59 break; 60 case RMX_ASPECT: 61 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 62 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 63 64 if (a1 > a2) { 65 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 66 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 67 } else if (a2 > a1) { 68 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 69 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 70 } 71 break; 72 case RMX_FULL: 73 default: 74 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 75 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 76 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 77 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 78 break; 79 } 80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 81} 82 83static void atombios_scaler_setup(struct drm_crtc *crtc) 84{ 85 struct drm_device *dev = crtc->dev; 86 struct radeon_device *rdev = dev->dev_private; 87 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 88 ENABLE_SCALER_PS_ALLOCATION args; 89 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 90 struct radeon_encoder *radeon_encoder = 91 to_radeon_encoder(radeon_crtc->encoder); 92 /* fixme - fill in enc_priv for atom dac */ 93 enum radeon_tv_std tv_std = TV_STD_NTSC; 94 bool is_tv = false, is_cv = false; 95 96 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 97 return; 98 99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 101 tv_std = tv_dac->tv_std; 102 is_tv = true; 103 } 104 105 memset(&args, 0, sizeof(args)); 106 107 args.ucScaler = radeon_crtc->crtc_id; 108 109 if (is_tv) { 110 switch (tv_std) { 111 case TV_STD_NTSC: 112 default: 113 args.ucTVStandard = ATOM_TV_NTSC; 114 break; 115 case TV_STD_PAL: 116 args.ucTVStandard = ATOM_TV_PAL; 117 break; 118 case TV_STD_PAL_M: 119 args.ucTVStandard = ATOM_TV_PALM; 120 break; 121 case TV_STD_PAL_60: 122 args.ucTVStandard = ATOM_TV_PAL60; 123 break; 124 case TV_STD_NTSC_J: 125 args.ucTVStandard = ATOM_TV_NTSCJ; 126 break; 127 case TV_STD_SCART_PAL: 128 args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 129 break; 130 case TV_STD_SECAM: 131 args.ucTVStandard = ATOM_TV_SECAM; 132 break; 133 case TV_STD_PAL_CN: 134 args.ucTVStandard = ATOM_TV_PALCN; 135 break; 136 } 137 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 138 } else if (is_cv) { 139 args.ucTVStandard = ATOM_TV_CV; 140 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 141 } else { 142 switch (radeon_crtc->rmx_type) { 143 case RMX_FULL: 144 args.ucEnable = ATOM_SCALER_EXPANSION; 145 break; 146 case RMX_CENTER: 147 args.ucEnable = ATOM_SCALER_CENTER; 148 break; 149 case RMX_ASPECT: 150 args.ucEnable = ATOM_SCALER_EXPANSION; 151 break; 152 default: 153 if (ASIC_IS_AVIVO(rdev)) 154 args.ucEnable = ATOM_SCALER_DISABLE; 155 else 156 args.ucEnable = ATOM_SCALER_CENTER; 157 break; 158 } 159 } 160 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 161 if ((is_tv || is_cv) 162 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 163 atom_rv515_force_tv_scaler(rdev, radeon_crtc); 164 } 165} 166 167static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 168{ 169 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 170 struct drm_device *dev = crtc->dev; 171 struct radeon_device *rdev = dev->dev_private; 172 int index = 173 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 174 ENABLE_CRTC_PS_ALLOCATION args; 175 176 memset(&args, 0, sizeof(args)); 177 178 args.ucCRTC = radeon_crtc->crtc_id; 179 args.ucEnable = lock; 180 181 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 182} 183 184static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 185{ 186 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 187 struct drm_device *dev = crtc->dev; 188 struct radeon_device *rdev = dev->dev_private; 189 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 190 ENABLE_CRTC_PS_ALLOCATION args; 191 192 memset(&args, 0, sizeof(args)); 193 194 args.ucCRTC = radeon_crtc->crtc_id; 195 args.ucEnable = state; 196 197 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 198} 199 200static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 201{ 202 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 203 struct drm_device *dev = crtc->dev; 204 struct radeon_device *rdev = dev->dev_private; 205 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 206 ENABLE_CRTC_PS_ALLOCATION args; 207 208 memset(&args, 0, sizeof(args)); 209 210 args.ucCRTC = radeon_crtc->crtc_id; 211 args.ucEnable = state; 212 213 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 214} 215 216static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 217{ 218 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 219 struct drm_device *dev = crtc->dev; 220 struct radeon_device *rdev = dev->dev_private; 221 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 222 BLANK_CRTC_PS_ALLOCATION args; 223 224 memset(&args, 0, sizeof(args)); 225 226 args.ucCRTC = radeon_crtc->crtc_id; 227 args.ucBlanking = state; 228 229 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 230} 231 232static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) 233{ 234 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 235 struct drm_device *dev = crtc->dev; 236 struct radeon_device *rdev = dev->dev_private; 237 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); 238 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; 239 240 memset(&args, 0, sizeof(args)); 241 242 args.ucDispPipeId = radeon_crtc->crtc_id; 243 args.ucEnable = state; 244 245 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 246} 247 248void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 249{ 250 struct drm_device *dev = crtc->dev; 251 struct radeon_device *rdev = dev->dev_private; 252 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 253 254 switch (mode) { 255 case DRM_MODE_DPMS_ON: 256 radeon_crtc->enabled = true; 257 /* adjust pm to dpms changes BEFORE enabling crtcs */ 258 radeon_pm_compute_clocks(rdev); 259 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) 260 atombios_powergate_crtc(crtc, ATOM_DISABLE); 261 atombios_enable_crtc(crtc, ATOM_ENABLE); 262 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 263 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 264 atombios_blank_crtc(crtc, ATOM_DISABLE); 265 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 266 radeon_crtc_load_lut(crtc); 267 break; 268 case DRM_MODE_DPMS_STANDBY: 269 case DRM_MODE_DPMS_SUSPEND: 270 case DRM_MODE_DPMS_OFF: 271 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 272 if (radeon_crtc->enabled) 273 atombios_blank_crtc(crtc, ATOM_ENABLE); 274 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 275 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 276 atombios_enable_crtc(crtc, ATOM_DISABLE); 277 radeon_crtc->enabled = false; 278 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) 279 atombios_powergate_crtc(crtc, ATOM_ENABLE); 280 /* adjust pm to dpms changes AFTER disabling crtcs */ 281 radeon_pm_compute_clocks(rdev); 282 break; 283 } 284} 285 286static void 287atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 288 struct drm_display_mode *mode) 289{ 290 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 291 struct drm_device *dev = crtc->dev; 292 struct radeon_device *rdev = dev->dev_private; 293 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 294 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 295 u16 misc = 0; 296 297 memset(&args, 0, sizeof(args)); 298 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 299 args.usH_Blanking_Time = 300 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 301 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 302 args.usV_Blanking_Time = 303 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 304 args.usH_SyncOffset = 305 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 306 args.usH_SyncWidth = 307 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 308 args.usV_SyncOffset = 309 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 310 args.usV_SyncWidth = 311 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 312 args.ucH_Border = radeon_crtc->h_border; 313 args.ucV_Border = radeon_crtc->v_border; 314 315 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 316 misc |= ATOM_VSYNC_POLARITY; 317 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 318 misc |= ATOM_HSYNC_POLARITY; 319 if (mode->flags & DRM_MODE_FLAG_CSYNC) 320 misc |= ATOM_COMPOSITESYNC; 321 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 322 misc |= ATOM_INTERLACE; 323 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 324 misc |= ATOM_DOUBLE_CLOCK_MODE; 325 326 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 327 args.ucCRTC = radeon_crtc->crtc_id; 328 329 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 330} 331 332static void atombios_crtc_set_timing(struct drm_crtc *crtc, 333 struct drm_display_mode *mode) 334{ 335 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 336 struct drm_device *dev = crtc->dev; 337 struct radeon_device *rdev = dev->dev_private; 338 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 339 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 340 u16 misc = 0; 341 342 memset(&args, 0, sizeof(args)); 343 args.usH_Total = cpu_to_le16(mode->crtc_htotal); 344 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 345 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 346 args.usH_SyncWidth = 347 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 348 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 349 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 350 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 351 args.usV_SyncWidth = 352 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 353 354 args.ucOverscanRight = radeon_crtc->h_border; 355 args.ucOverscanLeft = radeon_crtc->h_border; 356 args.ucOverscanBottom = radeon_crtc->v_border; 357 args.ucOverscanTop = radeon_crtc->v_border; 358 359 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 360 misc |= ATOM_VSYNC_POLARITY; 361 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 362 misc |= ATOM_HSYNC_POLARITY; 363 if (mode->flags & DRM_MODE_FLAG_CSYNC) 364 misc |= ATOM_COMPOSITESYNC; 365 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 366 misc |= ATOM_INTERLACE; 367 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 368 misc |= ATOM_DOUBLE_CLOCK_MODE; 369 370 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 371 args.ucCRTC = radeon_crtc->crtc_id; 372 373 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 374} 375 376static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) 377{ 378 u32 ss_cntl; 379 380 if (ASIC_IS_DCE4(rdev)) { 381 switch (pll_id) { 382 case ATOM_PPLL1: 383 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 384 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 385 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 386 break; 387 case ATOM_PPLL2: 388 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 389 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 390 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 391 break; 392 case ATOM_DCPLL: 393 case ATOM_PPLL_INVALID: 394 return; 395 } 396 } else if (ASIC_IS_AVIVO(rdev)) { 397 switch (pll_id) { 398 case ATOM_PPLL1: 399 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 400 ss_cntl &= ~1; 401 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 402 break; 403 case ATOM_PPLL2: 404 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 405 ss_cntl &= ~1; 406 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 407 break; 408 case ATOM_DCPLL: 409 case ATOM_PPLL_INVALID: 410 return; 411 } 412 } 413} 414 415 416union atom_enable_ss { 417 ENABLE_LVDS_SS_PARAMETERS lvds_ss; 418 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 419 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 420 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 421 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 422}; 423 424static void atombios_crtc_program_ss(struct radeon_device *rdev, 425 int enable, 426 int pll_id, 427 int crtc_id, 428 struct radeon_atom_ss *ss) 429{ 430 unsigned i; 431 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 432 union atom_enable_ss args; 433 434 if (!enable) { 435 for (i = 0; i < rdev->num_crtc; i++) { 436 if (rdev->mode_info.crtcs[i] && 437 rdev->mode_info.crtcs[i]->enabled && 438 i != crtc_id && 439 pll_id == rdev->mode_info.crtcs[i]->pll_id) { 440 /* one other crtc is using this pll don't turn 441 * off spread spectrum as it might turn off 442 * display on active crtc 443 */ 444 return; 445 } 446 } 447 } 448 449 memset(&args, 0, sizeof(args)); 450 451 if (ASIC_IS_DCE5(rdev)) { 452 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 453 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 454 switch (pll_id) { 455 case ATOM_PPLL1: 456 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 457 break; 458 case ATOM_PPLL2: 459 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 460 break; 461 case ATOM_DCPLL: 462 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 463 break; 464 case ATOM_PPLL_INVALID: 465 return; 466 } 467 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 468 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 469 args.v3.ucEnable = enable; 470 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev)) 471 args.v3.ucEnable = ATOM_DISABLE; 472 } else if (ASIC_IS_DCE4(rdev)) { 473 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 474 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 475 switch (pll_id) { 476 case ATOM_PPLL1: 477 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 478 break; 479 case ATOM_PPLL2: 480 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 481 break; 482 case ATOM_DCPLL: 483 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 484 break; 485 case ATOM_PPLL_INVALID: 486 return; 487 } 488 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 489 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 490 args.v2.ucEnable = enable; 491 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev)) 492 args.v2.ucEnable = ATOM_DISABLE; 493 } else if (ASIC_IS_DCE3(rdev)) { 494 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 495 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 496 args.v1.ucSpreadSpectrumStep = ss->step; 497 args.v1.ucSpreadSpectrumDelay = ss->delay; 498 args.v1.ucSpreadSpectrumRange = ss->range; 499 args.v1.ucPpll = pll_id; 500 args.v1.ucEnable = enable; 501 } else if (ASIC_IS_AVIVO(rdev)) { 502 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 503 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 504 atombios_disable_ss(rdev, pll_id); 505 return; 506 } 507 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 508 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 509 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 510 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 511 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 512 args.lvds_ss_2.ucEnable = enable; 513 } else { 514 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 515 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 516 atombios_disable_ss(rdev, pll_id); 517 return; 518 } 519 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 520 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 521 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 522 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 523 args.lvds_ss.ucEnable = enable; 524 } 525 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 526} 527 528union adjust_pixel_clock { 529 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 530 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 531}; 532 533static u32 atombios_adjust_pll(struct drm_crtc *crtc, 534 struct drm_display_mode *mode) 535{ 536 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 537 struct drm_device *dev = crtc->dev; 538 struct radeon_device *rdev = dev->dev_private; 539 struct drm_encoder *encoder = radeon_crtc->encoder; 540 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 541 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 542 u32 adjusted_clock = mode->clock; 543 int encoder_mode = atombios_get_encoder_mode(encoder); 544 u32 dp_clock = mode->clock; 545 int bpc = radeon_get_monitor_bpc(connector); 546 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); 547 548 /* reset the pll flags */ 549 radeon_crtc->pll_flags = 0; 550 551 if (ASIC_IS_AVIVO(rdev)) { 552 if ((rdev->family == CHIP_RS600) || 553 (rdev->family == CHIP_RS690) || 554 (rdev->family == CHIP_RS740)) 555 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 556 RADEON_PLL_PREFER_CLOSEST_LOWER); 557 558 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 559 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 560 else 561 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 562 563 if (rdev->family < CHIP_RV770) 564 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 565 /* use frac fb div on APUs */ 566 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 567 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 568 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) 569 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 570 } else { 571 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; 572 573 if (mode->clock > 200000) /* range limits??? */ 574 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 575 else 576 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 577 } 578 579 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 580 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { 581 if (connector) { 582 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 583 struct radeon_connector_atom_dig *dig_connector = 584 radeon_connector->con_priv; 585 586 dp_clock = dig_connector->dp_clock; 587 } 588 } 589 590 /* use recommended ref_div for ss */ 591 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 592 if (radeon_crtc->ss_enabled) { 593 if (radeon_crtc->ss.refdiv) { 594 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 595 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; 596 if (ASIC_IS_AVIVO(rdev)) 597 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 598 } 599 } 600 } 601 602 if (ASIC_IS_AVIVO(rdev)) { 603 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 604 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 605 adjusted_clock = mode->clock * 2; 606 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 607 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 608 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 609 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; 610 } else { 611 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 612 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 613 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 614 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 615 } 616 617 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 618 * accordingly based on the encoder/transmitter to work around 619 * special hw requirements. 620 */ 621 if (ASIC_IS_DCE3(rdev)) { 622 union adjust_pixel_clock args; 623 u8 frev, crev; 624 int index; 625 626 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 627 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 628 &crev)) 629 return adjusted_clock; 630 631 memset(&args, 0, sizeof(args)); 632 633 switch (frev) { 634 case 1: 635 switch (crev) { 636 case 1: 637 case 2: 638 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 639 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 640 args.v1.ucEncodeMode = encoder_mode; 641 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 642 args.v1.ucConfig |= 643 ADJUST_DISPLAY_CONFIG_SS_ENABLE; 644 645 atom_execute_table(rdev->mode_info.atom_context, 646 index, (uint32_t *)&args); 647 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 648 break; 649 case 3: 650 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); 651 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 652 args.v3.sInput.ucEncodeMode = encoder_mode; 653 args.v3.sInput.ucDispPllConfig = 0; 654 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 655 args.v3.sInput.ucDispPllConfig |= 656 DISPPLL_CONFIG_SS_ENABLE; 657 if (ENCODER_MODE_IS_DP(encoder_mode)) { 658 args.v3.sInput.ucDispPllConfig |= 659 DISPPLL_CONFIG_COHERENT_MODE; 660 /* 16200 or 27000 */ 661 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 662 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 663 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 664 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) 665 /* deep color support */ 666 args.v3.sInput.usPixelClock = 667 cpu_to_le16((mode->clock * bpc / 8) / 10); 668 if (dig->coherent_mode) 669 args.v3.sInput.ucDispPllConfig |= 670 DISPPLL_CONFIG_COHERENT_MODE; 671 if (is_duallink) 672 args.v3.sInput.ucDispPllConfig |= 673 DISPPLL_CONFIG_DUAL_LINK; 674 } 675 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 676 ENCODER_OBJECT_ID_NONE) 677 args.v3.sInput.ucExtTransmitterID = 678 radeon_encoder_get_dp_bridge_encoder_id(encoder); 679 else 680 args.v3.sInput.ucExtTransmitterID = 0; 681 682 atom_execute_table(rdev->mode_info.atom_context, 683 index, (uint32_t *)&args); 684 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 685 if (args.v3.sOutput.ucRefDiv) { 686 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 687 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 688 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; 689 } 690 if (args.v3.sOutput.ucPostDiv) { 691 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 692 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; 693 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; 694 } 695 break; 696 default: 697 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 698 return adjusted_clock; 699 } 700 break; 701 default: 702 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 703 return adjusted_clock; 704 } 705 } 706 return adjusted_clock; 707} 708 709union set_pixel_clock { 710 SET_PIXEL_CLOCK_PS_ALLOCATION base; 711 PIXEL_CLOCK_PARAMETERS v1; 712 PIXEL_CLOCK_PARAMETERS_V2 v2; 713 PIXEL_CLOCK_PARAMETERS_V3 v3; 714 PIXEL_CLOCK_PARAMETERS_V5 v5; 715 PIXEL_CLOCK_PARAMETERS_V6 v6; 716}; 717 718/* on DCE5, make sure the voltage is high enough to support the 719 * required disp clk. 720 */ 721static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, 722 u32 dispclk) 723{ 724 u8 frev, crev; 725 int index; 726 union set_pixel_clock args; 727 728 memset(&args, 0, sizeof(args)); 729 730 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 731 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 732 &crev)) 733 return; 734 735 switch (frev) { 736 case 1: 737 switch (crev) { 738 case 5: 739 /* if the default dcpll clock is specified, 740 * SetPixelClock provides the dividers 741 */ 742 args.v5.ucCRTC = ATOM_CRTC_INVALID; 743 args.v5.usPixelClock = cpu_to_le16(dispclk); 744 args.v5.ucPpll = ATOM_DCPLL; 745 break; 746 case 6: 747 /* if the default dcpll clock is specified, 748 * SetPixelClock provides the dividers 749 */ 750 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 751 if (ASIC_IS_DCE61(rdev)) 752 args.v6.ucPpll = ATOM_EXT_PLL1; 753 else if (ASIC_IS_DCE6(rdev)) 754 args.v6.ucPpll = ATOM_PPLL0; 755 else 756 args.v6.ucPpll = ATOM_DCPLL; 757 break; 758 default: 759 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 760 return; 761 } 762 break; 763 default: 764 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 765 return; 766 } 767 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 768} 769 770static void atombios_crtc_program_pll(struct drm_crtc *crtc, 771 u32 crtc_id, 772 int pll_id, 773 u32 encoder_mode, 774 u32 encoder_id, 775 u32 clock, 776 u32 ref_div, 777 u32 fb_div, 778 u32 frac_fb_div, 779 u32 post_div, 780 int bpc, 781 bool ss_enabled, 782 struct radeon_atom_ss *ss) 783{ 784 struct drm_device *dev = crtc->dev; 785 struct radeon_device *rdev = dev->dev_private; 786 u8 frev, crev; 787 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 788 union set_pixel_clock args; 789 790 memset(&args, 0, sizeof(args)); 791 792 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 793 &crev)) 794 return; 795 796 switch (frev) { 797 case 1: 798 switch (crev) { 799 case 1: 800 if (clock == ATOM_DISABLE) 801 return; 802 args.v1.usPixelClock = cpu_to_le16(clock / 10); 803 args.v1.usRefDiv = cpu_to_le16(ref_div); 804 args.v1.usFbDiv = cpu_to_le16(fb_div); 805 args.v1.ucFracFbDiv = frac_fb_div; 806 args.v1.ucPostDiv = post_div; 807 args.v1.ucPpll = pll_id; 808 args.v1.ucCRTC = crtc_id; 809 args.v1.ucRefDivSrc = 1; 810 break; 811 case 2: 812 args.v2.usPixelClock = cpu_to_le16(clock / 10); 813 args.v2.usRefDiv = cpu_to_le16(ref_div); 814 args.v2.usFbDiv = cpu_to_le16(fb_div); 815 args.v2.ucFracFbDiv = frac_fb_div; 816 args.v2.ucPostDiv = post_div; 817 args.v2.ucPpll = pll_id; 818 args.v2.ucCRTC = crtc_id; 819 args.v2.ucRefDivSrc = 1; 820 break; 821 case 3: 822 args.v3.usPixelClock = cpu_to_le16(clock / 10); 823 args.v3.usRefDiv = cpu_to_le16(ref_div); 824 args.v3.usFbDiv = cpu_to_le16(fb_div); 825 args.v3.ucFracFbDiv = frac_fb_div; 826 args.v3.ucPostDiv = post_div; 827 args.v3.ucPpll = pll_id; 828 if (crtc_id == ATOM_CRTC2) 829 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; 830 else 831 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; 832 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 833 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; 834 args.v3.ucTransmitterId = encoder_id; 835 args.v3.ucEncoderMode = encoder_mode; 836 break; 837 case 5: 838 args.v5.ucCRTC = crtc_id; 839 args.v5.usPixelClock = cpu_to_le16(clock / 10); 840 args.v5.ucRefDiv = ref_div; 841 args.v5.usFbDiv = cpu_to_le16(fb_div); 842 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 843 args.v5.ucPostDiv = post_div; 844 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 845 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 846 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; 847 switch (bpc) { 848 case 8: 849 default: 850 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; 851 break; 852 case 10: 853 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; 854 break; 855 } 856 args.v5.ucTransmitterID = encoder_id; 857 args.v5.ucEncoderMode = encoder_mode; 858 args.v5.ucPpll = pll_id; 859 break; 860 case 6: 861 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); 862 args.v6.ucRefDiv = ref_div; 863 args.v6.usFbDiv = cpu_to_le16(fb_div); 864 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 865 args.v6.ucPostDiv = post_div; 866 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 867 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 868 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; 869 switch (bpc) { 870 case 8: 871 default: 872 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; 873 break; 874 case 10: 875 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; 876 break; 877 case 12: 878 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; 879 break; 880 case 16: 881 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; 882 break; 883 } 884 args.v6.ucTransmitterID = encoder_id; 885 args.v6.ucEncoderMode = encoder_mode; 886 args.v6.ucPpll = pll_id; 887 break; 888 default: 889 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 890 return; 891 } 892 break; 893 default: 894 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 895 return; 896 } 897 898 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 899} 900 901static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 902{ 903 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 904 struct drm_device *dev = crtc->dev; 905 struct radeon_device *rdev = dev->dev_private; 906 struct radeon_encoder *radeon_encoder = 907 to_radeon_encoder(radeon_crtc->encoder); 908 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 909 910 radeon_crtc->bpc = 8; 911 radeon_crtc->ss_enabled = false; 912 913 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 914 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { 915 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 916 struct drm_connector *connector = 917 radeon_get_connector_for_encoder(radeon_crtc->encoder); 918 struct radeon_connector *radeon_connector = 919 to_radeon_connector(connector); 920 struct radeon_connector_atom_dig *dig_connector = 921 radeon_connector->con_priv; 922 int dp_clock; 923 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); 924 925 switch (encoder_mode) { 926 case ATOM_ENCODER_MODE_DP_MST: 927 case ATOM_ENCODER_MODE_DP: 928 /* DP/eDP */ 929 dp_clock = dig_connector->dp_clock / 10; 930 if (ASIC_IS_DCE4(rdev)) 931 radeon_crtc->ss_enabled = 932 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, 933 ASIC_INTERNAL_SS_ON_DP, 934 dp_clock); 935 else { 936 if (dp_clock == 16200) { 937 radeon_crtc->ss_enabled = 938 radeon_atombios_get_ppll_ss_info(rdev, 939 &radeon_crtc->ss, 940 ATOM_DP_SS_ID2); 941 if (!radeon_crtc->ss_enabled) 942 radeon_crtc->ss_enabled = 943 radeon_atombios_get_ppll_ss_info(rdev, 944 &radeon_crtc->ss, 945 ATOM_DP_SS_ID1); 946 } else 947 radeon_crtc->ss_enabled = 948 radeon_atombios_get_ppll_ss_info(rdev, 949 &radeon_crtc->ss, 950 ATOM_DP_SS_ID1); 951 } 952 break; 953 case ATOM_ENCODER_MODE_LVDS: 954 if (ASIC_IS_DCE4(rdev)) 955 radeon_crtc->ss_enabled = 956 radeon_atombios_get_asic_ss_info(rdev, 957 &radeon_crtc->ss, 958 dig->lcd_ss_id, 959 mode->clock / 10); 960 else 961 radeon_crtc->ss_enabled = 962 radeon_atombios_get_ppll_ss_info(rdev, 963 &radeon_crtc->ss, 964 dig->lcd_ss_id); 965 break; 966 case ATOM_ENCODER_MODE_DVI: 967 if (ASIC_IS_DCE4(rdev)) 968 radeon_crtc->ss_enabled = 969 radeon_atombios_get_asic_ss_info(rdev, 970 &radeon_crtc->ss, 971 ASIC_INTERNAL_SS_ON_TMDS, 972 mode->clock / 10); 973 break; 974 case ATOM_ENCODER_MODE_HDMI: 975 if (ASIC_IS_DCE4(rdev)) 976 radeon_crtc->ss_enabled = 977 radeon_atombios_get_asic_ss_info(rdev, 978 &radeon_crtc->ss, 979 ASIC_INTERNAL_SS_ON_HDMI, 980 mode->clock / 10); 981 break; 982 default: 983 break; 984 } 985 } 986 987 /* adjust pixel clock as needed */ 988 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); 989 990 return true; 991} 992 993static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 994{ 995 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 996 struct drm_device *dev = crtc->dev; 997 struct radeon_device *rdev = dev->dev_private; 998 struct radeon_encoder *radeon_encoder = 999 to_radeon_encoder(radeon_crtc->encoder); 1000 u32 pll_clock = mode->clock; 1001 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 1002 struct radeon_pll *pll; 1003 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 1004 1005 switch (radeon_crtc->pll_id) { 1006 case ATOM_PPLL1: 1007 pll = &rdev->clock.p1pll; 1008 break; 1009 case ATOM_PPLL2: 1010 pll = &rdev->clock.p2pll; 1011 break; 1012 case ATOM_DCPLL: 1013 case ATOM_PPLL_INVALID: 1014 default: 1015 pll = &rdev->clock.dcpll; 1016 break; 1017 } 1018 1019 /* update pll params */ 1020 pll->flags = radeon_crtc->pll_flags; 1021 pll->reference_div = radeon_crtc->pll_reference_div; 1022 pll->post_div = radeon_crtc->pll_post_div; 1023 1024 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1025 /* TV seems to prefer the legacy algo on some boards */ 1026 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1027 &fb_div, &frac_fb_div, &ref_div, &post_div); 1028 else if (ASIC_IS_AVIVO(rdev)) 1029 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, 1030 &fb_div, &frac_fb_div, &ref_div, &post_div); 1031 else 1032 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1033 &fb_div, &frac_fb_div, &ref_div, &post_div); 1034 1035 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, 1036 radeon_crtc->crtc_id, &radeon_crtc->ss); 1037 1038 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1039 encoder_mode, radeon_encoder->encoder_id, mode->clock, 1040 ref_div, fb_div, frac_fb_div, post_div, 1041 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); 1042 1043 if (radeon_crtc->ss_enabled) { 1044 /* calculate ss amount and step size */ 1045 if (ASIC_IS_DCE4(rdev)) { 1046 u32 step_size; 1047 u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000; 1048 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 1049 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1050 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 1051 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 1052 step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1053 (125 * 25 * pll->reference_freq / 100); 1054 else 1055 step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1056 (125 * 25 * pll->reference_freq / 100); 1057 radeon_crtc->ss.step = step_size; 1058 } 1059 1060 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, 1061 radeon_crtc->crtc_id, &radeon_crtc->ss); 1062 } 1063} 1064 1065static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 1066 struct drm_framebuffer *fb, 1067 int x, int y, int atomic) 1068{ 1069 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1070 struct drm_device *dev = crtc->dev; 1071 struct radeon_device *rdev = dev->dev_private; 1072 struct radeon_framebuffer *radeon_fb; 1073 struct drm_framebuffer *target_fb; 1074 struct drm_gem_object *obj; 1075 struct radeon_bo *rbo; 1076 uint64_t fb_location; 1077 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1078 unsigned bankw, bankh, mtaspect, tile_split; 1079 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1080 u32 tmp, viewport_w, viewport_h; 1081 int r; 1082 1083 /* no fb bound */ 1084 if (!atomic && !crtc->fb) { 1085 DRM_DEBUG_KMS("No FB bound\n"); 1086 return 0; 1087 } 1088 1089 if (atomic) { 1090 radeon_fb = to_radeon_framebuffer(fb); 1091 target_fb = fb; 1092 } 1093 else { 1094 radeon_fb = to_radeon_framebuffer(crtc->fb); 1095 target_fb = crtc->fb; 1096 } 1097 1098 /* If atomic, assume fb object is pinned & idle & fenced and 1099 * just update base pointers 1100 */ 1101 obj = radeon_fb->obj; 1102 rbo = gem_to_radeon_bo(obj); 1103 r = radeon_bo_reserve(rbo, false); 1104 if (unlikely(r != 0)) 1105 return r; 1106 1107 if (atomic) 1108 fb_location = radeon_bo_gpu_offset(rbo); 1109 else { 1110 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1111 if (unlikely(r != 0)) { 1112 radeon_bo_unreserve(rbo); 1113 return -EINVAL; 1114 } 1115 } 1116 1117 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1118 radeon_bo_unreserve(rbo); 1119 1120 switch (target_fb->bits_per_pixel) { 1121 case 8: 1122 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1123 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1124 break; 1125 case 15: 1126 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1127 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1128 break; 1129 case 16: 1130 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1131 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1132#ifdef __BIG_ENDIAN 1133 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1134#endif 1135 break; 1136 case 24: 1137 case 32: 1138 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1139 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1140#ifdef __BIG_ENDIAN 1141 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1142#endif 1143 break; 1144 default: 1145 DRM_ERROR("Unsupported screen depth %d\n", 1146 target_fb->bits_per_pixel); 1147 return -EINVAL; 1148 } 1149 1150 if (tiling_flags & RADEON_TILING_MACRO) { 1151 if (rdev->family >= CHIP_TAHITI) 1152 tmp = rdev->config.si.tile_config; 1153 else if (rdev->family >= CHIP_CAYMAN) 1154 tmp = rdev->config.cayman.tile_config; 1155 else 1156 tmp = rdev->config.evergreen.tile_config; 1157 1158 switch ((tmp & 0xf0) >> 4) { 1159 case 0: /* 4 banks */ 1160 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); 1161 break; 1162 case 1: /* 8 banks */ 1163 default: 1164 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); 1165 break; 1166 case 2: /* 16 banks */ 1167 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); 1168 break; 1169 } 1170 1171 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1172 1173 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1174 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); 1175 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1176 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1177 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 1178 } else if (tiling_flags & RADEON_TILING_MICRO) 1179 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1180 1181 if ((rdev->family == CHIP_TAHITI) || 1182 (rdev->family == CHIP_PITCAIRN)) 1183 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); 1184 else if (rdev->family == CHIP_VERDE) 1185 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); 1186 1187 switch (radeon_crtc->crtc_id) { 1188 case 0: 1189 WREG32(AVIVO_D1VGA_CONTROL, 0); 1190 break; 1191 case 1: 1192 WREG32(AVIVO_D2VGA_CONTROL, 0); 1193 break; 1194 case 2: 1195 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1196 break; 1197 case 3: 1198 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1199 break; 1200 case 4: 1201 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1202 break; 1203 case 5: 1204 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1205 break; 1206 default: 1207 break; 1208 } 1209 1210 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1211 upper_32_bits(fb_location)); 1212 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1213 upper_32_bits(fb_location)); 1214 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1215 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1216 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1217 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1218 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1219 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1220 1221 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1222 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1223 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1224 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1225 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1226 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1227 1228 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1229 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1230 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1231 1232 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1233 target_fb->height); 1234 x &= ~3; 1235 y &= ~1; 1236 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1237 (x << 16) | y); 1238 viewport_w = crtc->mode.hdisplay; 1239 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1240 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1241 (viewport_w << 16) | viewport_h); 1242 1243 /* pageflip setup */ 1244 /* make sure flip is at vb rather than hb */ 1245 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1246 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1247 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1248 1249 /* set pageflip to happen anywhere in vblank interval */ 1250 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1251 1252 if (!atomic && fb && fb != crtc->fb) { 1253 radeon_fb = to_radeon_framebuffer(fb); 1254 rbo = gem_to_radeon_bo(radeon_fb->obj); 1255 r = radeon_bo_reserve(rbo, false); 1256 if (unlikely(r != 0)) 1257 return r; 1258 radeon_bo_unpin(rbo); 1259 radeon_bo_unreserve(rbo); 1260 } 1261 1262 /* Bytes per pixel may have changed */ 1263 radeon_bandwidth_update(rdev); 1264 1265 return 0; 1266} 1267 1268static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 1269 struct drm_framebuffer *fb, 1270 int x, int y, int atomic) 1271{ 1272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1273 struct drm_device *dev = crtc->dev; 1274 struct radeon_device *rdev = dev->dev_private; 1275 struct radeon_framebuffer *radeon_fb; 1276 struct drm_gem_object *obj; 1277 struct radeon_bo *rbo; 1278 struct drm_framebuffer *target_fb; 1279 uint64_t fb_location; 1280 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1281 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1282 u32 tmp, viewport_w, viewport_h; 1283 int r; 1284 1285 /* no fb bound */ 1286 if (!atomic && !crtc->fb) { 1287 DRM_DEBUG_KMS("No FB bound\n"); 1288 return 0; 1289 } 1290 1291 if (atomic) { 1292 radeon_fb = to_radeon_framebuffer(fb); 1293 target_fb = fb; 1294 } 1295 else { 1296 radeon_fb = to_radeon_framebuffer(crtc->fb); 1297 target_fb = crtc->fb; 1298 } 1299 1300 obj = radeon_fb->obj; 1301 rbo = gem_to_radeon_bo(obj); 1302 r = radeon_bo_reserve(rbo, false); 1303 if (unlikely(r != 0)) 1304 return r; 1305 1306 /* If atomic, assume fb object is pinned & idle & fenced and 1307 * just update base pointers 1308 */ 1309 if (atomic) 1310 fb_location = radeon_bo_gpu_offset(rbo); 1311 else { 1312 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1313 if (unlikely(r != 0)) { 1314 radeon_bo_unreserve(rbo); 1315 return -EINVAL; 1316 } 1317 } 1318 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1319 radeon_bo_unreserve(rbo); 1320 1321 switch (target_fb->bits_per_pixel) { 1322 case 8: 1323 fb_format = 1324 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1325 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1326 break; 1327 case 15: 1328 fb_format = 1329 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1330 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1331 break; 1332 case 16: 1333 fb_format = 1334 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1335 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1336#ifdef __BIG_ENDIAN 1337 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1338#endif 1339 break; 1340 case 24: 1341 case 32: 1342 fb_format = 1343 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1344 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1345#ifdef __BIG_ENDIAN 1346 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1347#endif 1348 break; 1349 default: 1350 DRM_ERROR("Unsupported screen depth %d\n", 1351 target_fb->bits_per_pixel); 1352 return -EINVAL; 1353 } 1354 1355 if (rdev->family >= CHIP_R600) { 1356 if (tiling_flags & RADEON_TILING_MACRO) 1357 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 1358 else if (tiling_flags & RADEON_TILING_MICRO) 1359 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 1360 } else { 1361 if (tiling_flags & RADEON_TILING_MACRO) 1362 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1363 1364 if (tiling_flags & RADEON_TILING_MICRO) 1365 fb_format |= AVIVO_D1GRPH_TILED; 1366 } 1367 1368 if (radeon_crtc->crtc_id == 0) 1369 WREG32(AVIVO_D1VGA_CONTROL, 0); 1370 else 1371 WREG32(AVIVO_D2VGA_CONTROL, 0); 1372 1373 if (rdev->family >= CHIP_RV770) { 1374 if (radeon_crtc->crtc_id) { 1375 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1376 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1377 } else { 1378 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1379 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1380 } 1381 } 1382 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1383 (u32) fb_location); 1384 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1385 radeon_crtc->crtc_offset, (u32) fb_location); 1386 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1387 if (rdev->family >= CHIP_R600) 1388 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1389 1390 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1391 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1392 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1393 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1394 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1395 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1396 1397 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1398 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1399 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1400 1401 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1402 target_fb->height); 1403 x &= ~3; 1404 y &= ~1; 1405 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1406 (x << 16) | y); 1407 viewport_w = crtc->mode.hdisplay; 1408 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1409 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1410 (viewport_w << 16) | viewport_h); 1411 1412 /* pageflip setup */ 1413 /* make sure flip is at vb rather than hb */ 1414 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1415 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1416 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1417 1418 /* set pageflip to happen anywhere in vblank interval */ 1419 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1420 1421 if (!atomic && fb && fb != crtc->fb) { 1422 radeon_fb = to_radeon_framebuffer(fb); 1423 rbo = gem_to_radeon_bo(radeon_fb->obj); 1424 r = radeon_bo_reserve(rbo, false); 1425 if (unlikely(r != 0)) 1426 return r; 1427 radeon_bo_unpin(rbo); 1428 radeon_bo_unreserve(rbo); 1429 } 1430 1431 /* Bytes per pixel may have changed */ 1432 radeon_bandwidth_update(rdev); 1433 1434 return 0; 1435} 1436 1437int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 1438 struct drm_framebuffer *old_fb) 1439{ 1440 struct drm_device *dev = crtc->dev; 1441 struct radeon_device *rdev = dev->dev_private; 1442 1443 if (ASIC_IS_DCE4(rdev)) 1444 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1445 else if (ASIC_IS_AVIVO(rdev)) 1446 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 1447 else 1448 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 1449} 1450 1451int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 1452 struct drm_framebuffer *fb, 1453 int x, int y, enum mode_set_atomic state) 1454{ 1455 struct drm_device *dev = crtc->dev; 1456 struct radeon_device *rdev = dev->dev_private; 1457 1458 if (ASIC_IS_DCE4(rdev)) 1459 return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 1460 else if (ASIC_IS_AVIVO(rdev)) 1461 return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 1462 else 1463 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 1464} 1465 1466/* properly set additional regs when using atombios */ 1467static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1468{ 1469 struct drm_device *dev = crtc->dev; 1470 struct radeon_device *rdev = dev->dev_private; 1471 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1472 u32 disp_merge_cntl; 1473 1474 switch (radeon_crtc->crtc_id) { 1475 case 0: 1476 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1477 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1478 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1479 break; 1480 case 1: 1481 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1482 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1483 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1484 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1485 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1486 break; 1487 } 1488} 1489 1490/** 1491 * radeon_get_pll_use_mask - look up a mask of which pplls are in use 1492 * 1493 * @crtc: drm crtc 1494 * 1495 * Returns the mask of which PPLLs (Pixel PLLs) are in use. 1496 */ 1497static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 1498{ 1499 struct drm_device *dev = crtc->dev; 1500 struct drm_crtc *test_crtc; 1501 struct radeon_crtc *test_radeon_crtc; 1502 u32 pll_in_use = 0; 1503 1504 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1505 if (crtc == test_crtc) 1506 continue; 1507 1508 test_radeon_crtc = to_radeon_crtc(test_crtc); 1509 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1510 pll_in_use |= (1 << test_radeon_crtc->pll_id); 1511 } 1512 return pll_in_use; 1513} 1514 1515/** 1516 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP 1517 * 1518 * @crtc: drm crtc 1519 * 1520 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 1521 * also in DP mode. For DP, a single PPLL can be used for all DP 1522 * crtcs/encoders. 1523 */ 1524static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 1525{ 1526 struct drm_device *dev = crtc->dev; 1527 struct drm_crtc *test_crtc; 1528 struct radeon_crtc *test_radeon_crtc; 1529 1530 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1531 if (crtc == test_crtc) 1532 continue; 1533 test_radeon_crtc = to_radeon_crtc(test_crtc); 1534 if (test_radeon_crtc->encoder && 1535 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1536 /* for DP use the same PLL for all */ 1537 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1538 return test_radeon_crtc->pll_id; 1539 } 1540 } 1541 return ATOM_PPLL_INVALID; 1542} 1543 1544/** 1545 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc 1546 * 1547 * @crtc: drm crtc 1548 * @encoder: drm encoder 1549 * 1550 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can 1551 * be shared (i.e., same clock). 1552 */ 1553static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 1554{ 1555 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1556 struct drm_device *dev = crtc->dev; 1557 struct drm_crtc *test_crtc; 1558 struct radeon_crtc *test_radeon_crtc; 1559 u32 adjusted_clock, test_adjusted_clock; 1560 1561 adjusted_clock = radeon_crtc->adjusted_clock; 1562 1563 if (adjusted_clock == 0) 1564 return ATOM_PPLL_INVALID; 1565 1566 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1567 if (crtc == test_crtc) 1568 continue; 1569 test_radeon_crtc = to_radeon_crtc(test_crtc); 1570 if (test_radeon_crtc->encoder && 1571 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1572 /* check if we are already driving this connector with another crtc */ 1573 if (test_radeon_crtc->connector == radeon_crtc->connector) { 1574 /* if we are, return that pll */ 1575 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1576 return test_radeon_crtc->pll_id; 1577 } 1578 /* for non-DP check the clock */ 1579 test_adjusted_clock = test_radeon_crtc->adjusted_clock; 1580 if ((crtc->mode.clock == test_crtc->mode.clock) && 1581 (adjusted_clock == test_adjusted_clock) && 1582 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && 1583 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) 1584 return test_radeon_crtc->pll_id; 1585 } 1586 } 1587 return ATOM_PPLL_INVALID; 1588} 1589 1590/** 1591 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. 1592 * 1593 * @crtc: drm crtc 1594 * 1595 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1596 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1597 * monitors a dedicated PPLL must be used. If a particular board has 1598 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1599 * as there is no need to program the PLL itself. If we are not able to 1600 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1601 * avoid messing up an existing monitor. 1602 * 1603 * Asic specific PLL information 1604 * 1605 * DCE 6.1 1606 * - PPLL2 is only available to UNIPHYA (both DP and non-DP) 1607 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) 1608 * 1609 * DCE 6.0 1610 * - PPLL0 is available to all UNIPHY (DP only) 1611 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1612 * 1613 * DCE 5.0 1614 * - DCPLL is available to all UNIPHY (DP only) 1615 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1616 * 1617 * DCE 3.0/4.0/4.1 1618 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1619 * 1620 */ 1621static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1622{ 1623 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1624 struct drm_device *dev = crtc->dev; 1625 struct radeon_device *rdev = dev->dev_private; 1626 struct radeon_encoder *radeon_encoder = 1627 to_radeon_encoder(radeon_crtc->encoder); 1628 u32 pll_in_use; 1629 int pll; 1630 1631 if (ASIC_IS_DCE61(rdev)) { 1632 struct radeon_encoder_atom_dig *dig = 1633 radeon_encoder->enc_priv; 1634 1635 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1636 (dig->linkb == false)) 1637 /* UNIPHY A uses PPLL2 */ 1638 return ATOM_PPLL2; 1639 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1640 /* UNIPHY B/C/D/E/F */ 1641 if (rdev->clock.dp_extclk) 1642 /* skip PPLL programming if using ext clock */ 1643 return ATOM_PPLL_INVALID; 1644 else { 1645 /* use the same PPLL for all DP monitors */ 1646 pll = radeon_get_shared_dp_ppll(crtc); 1647 if (pll != ATOM_PPLL_INVALID) 1648 return pll; 1649 } 1650 } else { 1651 /* use the same PPLL for all monitors with the same clock */ 1652 pll = radeon_get_shared_nondp_ppll(crtc); 1653 if (pll != ATOM_PPLL_INVALID) 1654 return pll; 1655 } 1656 /* UNIPHY B/C/D/E/F */ 1657 pll_in_use = radeon_get_pll_use_mask(crtc); 1658 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1659 return ATOM_PPLL0; 1660 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1661 return ATOM_PPLL1; 1662 DRM_ERROR("unable to allocate a PPLL\n"); 1663 return ATOM_PPLL_INVALID; 1664 } else if (ASIC_IS_DCE4(rdev)) { 1665 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1666 * depending on the asic: 1667 * DCE4: PPLL or ext clock 1668 * DCE5: PPLL, DCPLL, or ext clock 1669 * DCE6: PPLL, PPLL0, or ext clock 1670 * 1671 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1672 * PPLL/DCPLL programming and only program the DP DTO for the 1673 * crtc virtual pixel clock. 1674 */ 1675 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1676 if (rdev->clock.dp_extclk) 1677 /* skip PPLL programming if using ext clock */ 1678 return ATOM_PPLL_INVALID; 1679 else if (ASIC_IS_DCE6(rdev)) 1680 /* use PPLL0 for all DP */ 1681 return ATOM_PPLL0; 1682 else if (ASIC_IS_DCE5(rdev)) 1683 /* use DCPLL for all DP */ 1684 return ATOM_DCPLL; 1685 else { 1686 /* use the same PPLL for all DP monitors */ 1687 pll = radeon_get_shared_dp_ppll(crtc); 1688 if (pll != ATOM_PPLL_INVALID) 1689 return pll; 1690 } 1691 } else { 1692 /* use the same PPLL for all monitors with the same clock */ 1693 pll = radeon_get_shared_nondp_ppll(crtc); 1694 if (pll != ATOM_PPLL_INVALID) 1695 return pll; 1696 } 1697 /* all other cases */ 1698 pll_in_use = radeon_get_pll_use_mask(crtc); 1699 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1700 return ATOM_PPLL1; 1701 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1702 return ATOM_PPLL2; 1703 DRM_ERROR("unable to allocate a PPLL\n"); 1704 return ATOM_PPLL_INVALID; 1705 } else { 1706 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ 1707 /* some atombios (observed in some DCE2/DCE3) code have a bug, 1708 * the matching btw pll and crtc is done through 1709 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the 1710 * pll (1 or 2) to select which register to write. ie if using 1711 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 1712 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to 1713 * choose which value to write. Which is reverse order from 1714 * register logic. So only case that works is when pllid is 1715 * same as crtcid or when both pll and crtc are enabled and 1716 * both use same clock. 1717 * 1718 * So just return crtc id as if crtc and pll were hard linked 1719 * together even if they aren't 1720 */ 1721 return radeon_crtc->crtc_id; 1722 } 1723} 1724 1725void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) 1726{ 1727 /* always set DCPLL */ 1728 if (ASIC_IS_DCE6(rdev)) 1729 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 1730 else if (ASIC_IS_DCE4(rdev)) { 1731 struct radeon_atom_ss ss; 1732 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 1733 ASIC_INTERNAL_SS_ON_DCPLL, 1734 rdev->clock.default_dispclk); 1735 if (ss_enabled) 1736 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); 1737 /* XXX: DCE5, make sure voltage, dispclk is high enough */ 1738 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 1739 if (ss_enabled) 1740 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); 1741 } 1742 1743} 1744 1745int atombios_crtc_mode_set(struct drm_crtc *crtc, 1746 struct drm_display_mode *mode, 1747 struct drm_display_mode *adjusted_mode, 1748 int x, int y, struct drm_framebuffer *old_fb) 1749{ 1750 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1751 struct drm_device *dev = crtc->dev; 1752 struct radeon_device *rdev = dev->dev_private; 1753 struct radeon_encoder *radeon_encoder = 1754 to_radeon_encoder(radeon_crtc->encoder); 1755 bool is_tvcv = false; 1756 1757 if (radeon_encoder->active_device & 1758 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1759 is_tvcv = true; 1760 1761 atombios_crtc_set_pll(crtc, adjusted_mode); 1762 1763 if (ASIC_IS_DCE4(rdev)) 1764 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1765 else if (ASIC_IS_AVIVO(rdev)) { 1766 if (is_tvcv) 1767 atombios_crtc_set_timing(crtc, adjusted_mode); 1768 else 1769 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1770 } else { 1771 atombios_crtc_set_timing(crtc, adjusted_mode); 1772 if (radeon_crtc->crtc_id == 0) 1773 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1774 radeon_legacy_atom_fixup(crtc); 1775 } 1776 atombios_crtc_set_base(crtc, x, y, old_fb); 1777 atombios_overscan_setup(crtc, mode, adjusted_mode); 1778 atombios_scaler_setup(crtc); 1779 return 0; 1780} 1781 1782static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 1783 const struct drm_display_mode *mode, 1784 struct drm_display_mode *adjusted_mode) 1785{ 1786 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1787 struct drm_device *dev = crtc->dev; 1788 struct drm_encoder *encoder; 1789 1790 /* assign the encoder to the radeon crtc to avoid repeated lookups later */ 1791 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1792 if (encoder->crtc == crtc) { 1793 radeon_crtc->encoder = encoder; 1794 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); 1795 break; 1796 } 1797 } 1798 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { 1799 radeon_crtc->encoder = NULL; 1800 radeon_crtc->connector = NULL; 1801 return false; 1802 } 1803 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1804 return false; 1805 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) 1806 return false; 1807 /* pick pll */ 1808 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 1809 /* if we can't get a PPLL for a non-DP encoder, fail */ 1810 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && 1811 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) 1812 return false; 1813 1814 return true; 1815} 1816 1817static void atombios_crtc_prepare(struct drm_crtc *crtc) 1818{ 1819 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1820 struct drm_device *dev = crtc->dev; 1821 struct radeon_device *rdev = dev->dev_private; 1822 1823 radeon_crtc->in_mode_set = true; 1824 1825 /* disable crtc pair power gating before programming */ 1826 if (ASIC_IS_DCE6(rdev)) 1827 atombios_powergate_crtc(crtc, ATOM_DISABLE); 1828 1829 atombios_lock_crtc(crtc, ATOM_ENABLE); 1830 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1831} 1832 1833static void atombios_crtc_commit(struct drm_crtc *crtc) 1834{ 1835 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1836 1837 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 1838 atombios_lock_crtc(crtc, ATOM_DISABLE); 1839 radeon_crtc->in_mode_set = false; 1840} 1841 1842static void atombios_crtc_disable(struct drm_crtc *crtc) 1843{ 1844 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1845 struct drm_device *dev = crtc->dev; 1846 struct radeon_device *rdev = dev->dev_private; 1847 struct radeon_atom_ss ss; 1848 int i; 1849 1850 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1851 1852 for (i = 0; i < rdev->num_crtc; i++) { 1853 if (rdev->mode_info.crtcs[i] && 1854 rdev->mode_info.crtcs[i]->enabled && 1855 i != radeon_crtc->crtc_id && 1856 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { 1857 /* one other crtc is using this pll don't turn 1858 * off the pll 1859 */ 1860 goto done; 1861 } 1862 } 1863 1864 switch (radeon_crtc->pll_id) { 1865 case ATOM_PPLL1: 1866 case ATOM_PPLL2: 1867 /* disable the ppll */ 1868 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1869 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 1870 break; 1871 case ATOM_PPLL0: 1872 /* disable the ppll */ 1873 if (ASIC_IS_DCE61(rdev)) 1874 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1875 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 1876 break; 1877 default: 1878 break; 1879 } 1880done: 1881 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 1882 radeon_crtc->adjusted_clock = 0; 1883 radeon_crtc->encoder = NULL; 1884 radeon_crtc->connector = NULL; 1885} 1886 1887static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1888 .dpms = atombios_crtc_dpms, 1889 .mode_fixup = atombios_crtc_mode_fixup, 1890 .mode_set = atombios_crtc_mode_set, 1891 .mode_set_base = atombios_crtc_set_base, 1892 .mode_set_base_atomic = atombios_crtc_set_base_atomic, 1893 .prepare = atombios_crtc_prepare, 1894 .commit = atombios_crtc_commit, 1895 .load_lut = radeon_crtc_load_lut, 1896 .disable = atombios_crtc_disable, 1897}; 1898 1899void radeon_atombios_init_crtc(struct drm_device *dev, 1900 struct radeon_crtc *radeon_crtc) 1901{ 1902 struct radeon_device *rdev = dev->dev_private; 1903 1904 if (ASIC_IS_DCE4(rdev)) { 1905 switch (radeon_crtc->crtc_id) { 1906 case 0: 1907 default: 1908 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 1909 break; 1910 case 1: 1911 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 1912 break; 1913 case 2: 1914 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 1915 break; 1916 case 3: 1917 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 1918 break; 1919 case 4: 1920 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 1921 break; 1922 case 5: 1923 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 1924 break; 1925 } 1926 } else { 1927 if (radeon_crtc->crtc_id == 1) 1928 radeon_crtc->crtc_offset = 1929 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 1930 else 1931 radeon_crtc->crtc_offset = 0; 1932 } 1933 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 1934 radeon_crtc->adjusted_clock = 0; 1935 radeon_crtc->encoder = NULL; 1936 radeon_crtc->connector = NULL; 1937 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 1938} 1939