1/*-
2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
25 */
26
27/*
28 * Device driver for Intel's On Die thermal sensor via MSR.
29 * First introduced in Intel's Core line of processors.
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD$");
34
35#include <sys/param.h>
36#include <sys/bus.h>
37#include <sys/systm.h>
38#include <sys/types.h>
39#include <sys/module.h>
40#include <sys/conf.h>
41#include <sys/kernel.h>
42#include <sys/sysctl.h>
43#include <sys/proc.h>	/* for curthread */
44#include <sys/sched.h>
45
46#include <machine/specialreg.h>
47#include <machine/cpufunc.h>
48#include <machine/cputypes.h>
49#include <machine/md_var.h>
50
51#define	TZ_ZEROC			2732
52
53#define	THERM_STATUS_LOG		0x02
54#define	THERM_STATUS			0x01
55#define	THERM_STATUS_TEMP_SHIFT		16
56#define	THERM_STATUS_TEMP_MASK		0x7f
57#define	THERM_STATUS_RES_SHIFT		27
58#define	THERM_STATUS_RES_MASK		0x0f
59#define	THERM_STATUS_VALID_SHIFT	31
60#define	THERM_STATUS_VALID_MASK		0x01
61
62struct coretemp_softc {
63	device_t	sc_dev;
64	int		sc_tjmax;
65	unsigned int	sc_throttle_log;
66};
67
68/*
69 * Device methods.
70 */
71static void	coretemp_identify(driver_t *driver, device_t parent);
72static int	coretemp_probe(device_t dev);
73static int	coretemp_attach(device_t dev);
74static int	coretemp_detach(device_t dev);
75
76static uint64_t	coretemp_get_thermal_msr(int cpu);
77static void	coretemp_clear_thermal_msr(int cpu);
78static int	coretemp_get_val_sysctl(SYSCTL_HANDLER_ARGS);
79static int	coretemp_throttle_log_sysctl(SYSCTL_HANDLER_ARGS);
80
81static device_method_t coretemp_methods[] = {
82	/* Device interface */
83	DEVMETHOD(device_identify,	coretemp_identify),
84	DEVMETHOD(device_probe,		coretemp_probe),
85	DEVMETHOD(device_attach,	coretemp_attach),
86	DEVMETHOD(device_detach,	coretemp_detach),
87
88	DEVMETHOD_END
89};
90
91static driver_t coretemp_driver = {
92	"coretemp",
93	coretemp_methods,
94	sizeof(struct coretemp_softc),
95};
96
97enum therm_info {
98	CORETEMP_TEMP,
99	CORETEMP_DELTA,
100	CORETEMP_RESOLUTION,
101	CORETEMP_TJMAX,
102};
103
104static devclass_t coretemp_devclass;
105DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL,
106    NULL);
107
108static void
109coretemp_identify(driver_t *driver, device_t parent)
110{
111	device_t child;
112	u_int regs[4];
113
114	/* Make sure we're not being doubly invoked. */
115	if (device_find_child(parent, "coretemp", -1) != NULL)
116		return;
117
118	/* Check that CPUID 0x06 is supported and the vendor is Intel.*/
119	if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL)
120		return;
121	/*
122	 * CPUID 0x06 returns 1 if the processor has on-die thermal
123	 * sensors. EBX[0:3] contains the number of sensors.
124	 */
125	do_cpuid(0x06, regs);
126	if ((regs[0] & 0x1) != 1)
127		return;
128
129	/*
130	 * We add a child for each CPU since settings must be performed
131	 * on each CPU in the SMP case.
132	 */
133	child = device_add_child(parent, "coretemp", -1);
134	if (child == NULL)
135		device_printf(parent, "add coretemp child failed\n");
136}
137
138static int
139coretemp_probe(device_t dev)
140{
141	if (resource_disabled("coretemp", 0))
142		return (ENXIO);
143
144	device_set_desc(dev, "CPU On-Die Thermal Sensors");
145
146	return (BUS_PROBE_GENERIC);
147}
148
149static int
150coretemp_attach(device_t dev)
151{
152	struct coretemp_softc *sc = device_get_softc(dev);
153	device_t pdev;
154	uint64_t msr;
155	int cpu_model, cpu_stepping;
156	int ret, tjtarget;
157	struct sysctl_oid *oid;
158	struct sysctl_ctx_list *ctx;
159
160	sc->sc_dev = dev;
161	pdev = device_get_parent(dev);
162	cpu_model = CPUID_TO_MODEL(cpu_id);
163	cpu_stepping = cpu_id & CPUID_STEPPING;
164
165	/*
166	 * Some CPUs, namely the PIII, don't have thermal sensors, but
167	 * report them when the CPUID check is performed in
168	 * coretemp_identify(). This leads to a later GPF when the sensor
169	 * is queried via a MSR, so we stop here.
170	 */
171	if (cpu_model < 0xe)
172		return (ENXIO);
173
174#if 0 /*
175       * XXXrpaulo: I have this CPU model and when it returns from C3
176       * coretemp continues to function properly.
177       */
178
179	/*
180	 * Check for errata AE18.
181	 * "Processor Digital Thermal Sensor (DTS) Readout stops
182	 *  updating upon returning from C3/C4 state."
183	 *
184	 * Adapted from the Linux coretemp driver.
185	 */
186	if (cpu_model == 0xe && cpu_stepping < 0xc) {
187		msr = rdmsr(MSR_BIOS_SIGN);
188		msr = msr >> 32;
189		if (msr < 0x39) {
190			device_printf(dev, "not supported (Intel errata "
191			    "AE18), try updating your BIOS\n");
192			return (ENXIO);
193		}
194	}
195#endif
196
197	/*
198	 * Use 100C as the initial value.
199	 */
200	sc->sc_tjmax = 100;
201
202	if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) {
203		/*
204		 * On some Core 2 CPUs, there's an undocumented MSR that
205		 * can tell us if Tj(max) is 100 or 85.
206		 *
207		 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted
208		 * from the Linux coretemp driver.
209		 */
210		msr = rdmsr(MSR_IA32_EXT_CONFIG);
211		if (msr & (1 << 30))
212			sc->sc_tjmax = 85;
213	} else if (cpu_model == 0x17) {
214		switch (cpu_stepping) {
215		case 0x6:	/* Mobile Core 2 Duo */
216			sc->sc_tjmax = 105;
217			break;
218		default:	/* Unknown stepping */
219			break;
220		}
221	} else if (cpu_model == 0x1c) {
222		switch (cpu_stepping) {
223		case 0xa:	/* 45nm Atom D400, N400 and D500 series */
224			sc->sc_tjmax = 100;
225			break;
226		default:
227			sc->sc_tjmax = 90;
228			break;
229		}
230	} else {
231		/*
232		 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
233		 *
234		 * This method is described in Intel white paper "CPU
235		 * Monitoring With DTS/PECI". (#322683)
236		 */
237		ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
238		if (ret == 0) {
239			tjtarget = (msr >> 16) & 0xff;
240
241			/*
242			 * On earlier generation of processors, the value
243			 * obtained from IA32_TEMPERATURE_TARGET register is
244			 * an offset that needs to be summed with a model
245			 * specific base.  It is however not clear what
246			 * these numbers are, with the publicly available
247			 * documents from Intel.
248			 *
249			 * For now, we consider [70, 110]C range, as
250			 * described in #322683, as "reasonable" and accept
251			 * these values whenever the MSR is available for
252			 * read, regardless the CPU model.
253			 */
254			if (tjtarget >= 70 && tjtarget <= 110)
255				sc->sc_tjmax = tjtarget;
256			else
257				device_printf(dev, "Tj(target) value %d "
258				    "does not seem right.\n", tjtarget);
259		} else
260			device_printf(dev, "Can not get Tj(target) "
261			    "from your CPU, using 100C.\n");
262	}
263
264	if (bootverbose)
265		device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax);
266
267	ctx = device_get_sysctl_ctx(dev);
268
269	oid = SYSCTL_ADD_NODE(ctx,
270	    SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)), OID_AUTO,
271	    "coretemp", CTLFLAG_RD, NULL, "Per-CPU thermal information");
272
273	/*
274	 * Add the MIBs to dev.cpu.N and dev.cpu.N.coretemp.
275	 */
276	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)),
277	    OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
278	    dev, CORETEMP_TEMP, coretemp_get_val_sysctl, "IK",
279	    "Current temperature");
280	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "delta",
281	    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_DELTA,
282	    coretemp_get_val_sysctl, "I",
283	    "Delta between TCC activation and current temperature");
284	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "resolution",
285	    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_RESOLUTION,
286	    coretemp_get_val_sysctl, "I",
287	    "Resolution of CPU thermal sensor");
288	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "tjmax",
289	    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_TJMAX,
290	    coretemp_get_val_sysctl, "IK",
291	    "TCC activation temperature");
292	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
293	    "throttle_log", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev, 0,
294	    coretemp_throttle_log_sysctl, "I",
295	    "Set to 1 if the thermal sensor has tripped");
296
297	return (0);
298}
299
300static int
301coretemp_detach(device_t dev)
302{
303	return (0);
304}
305
306static uint64_t
307coretemp_get_thermal_msr(int cpu)
308{
309	uint64_t msr;
310
311	thread_lock(curthread);
312	sched_bind(curthread, cpu);
313	thread_unlock(curthread);
314
315	/*
316	 * The digital temperature reading is located at bit 16
317	 * of MSR_THERM_STATUS.
318	 *
319	 * There is a bit on that MSR that indicates whether the
320	 * temperature is valid or not.
321	 *
322	 * The temperature is computed by subtracting the temperature
323	 * reading by Tj(max).
324	 */
325	msr = rdmsr(MSR_THERM_STATUS);
326
327	thread_lock(curthread);
328	sched_unbind(curthread);
329	thread_unlock(curthread);
330
331	return (msr);
332}
333
334static void
335coretemp_clear_thermal_msr(int cpu)
336{
337	thread_lock(curthread);
338	sched_bind(curthread, cpu);
339	thread_unlock(curthread);
340
341	wrmsr(MSR_THERM_STATUS, 0);
342
343	thread_lock(curthread);
344	sched_unbind(curthread);
345	thread_unlock(curthread);
346}
347
348static int
349coretemp_get_val_sysctl(SYSCTL_HANDLER_ARGS)
350{
351	device_t dev;
352	uint64_t msr;
353	int val, tmp;
354	struct coretemp_softc *sc;
355	enum therm_info type;
356	char stemp[16];
357
358	dev = (device_t) arg1;
359	msr = coretemp_get_thermal_msr(device_get_unit(dev));
360	sc = device_get_softc(dev);
361	type = arg2;
362
363	if (((msr >> THERM_STATUS_VALID_SHIFT) & THERM_STATUS_VALID_MASK) != 1) {
364		val = -1;
365	} else {
366		switch (type) {
367		case CORETEMP_TEMP:
368			tmp = (msr >> THERM_STATUS_TEMP_SHIFT) &
369			    THERM_STATUS_TEMP_MASK;
370			val = (sc->sc_tjmax - tmp) * 10 + TZ_ZEROC;
371			break;
372		case CORETEMP_DELTA:
373			val = (msr >> THERM_STATUS_TEMP_SHIFT) &
374			    THERM_STATUS_TEMP_MASK;
375			break;
376		case CORETEMP_RESOLUTION:
377			val = (msr >> THERM_STATUS_RES_SHIFT) &
378			    THERM_STATUS_RES_MASK;
379			break;
380		case CORETEMP_TJMAX:
381			val = sc->sc_tjmax * 10 + TZ_ZEROC;
382			break;
383		}
384	}
385
386	if (msr & THERM_STATUS_LOG) {
387		coretemp_clear_thermal_msr(device_get_unit(dev));
388		sc->sc_throttle_log = 1;
389
390		/*
391		 * Check for Critical Temperature Status and Critical
392		 * Temperature Log.  It doesn't really matter if the
393		 * current temperature is invalid because the "Critical
394		 * Temperature Log" bit will tell us if the Critical
395		 * Temperature has * been reached in past. It's not
396		 * directly related to the current temperature.
397		 *
398		 * If we reach a critical level, allow devctl(4)
399		 * to catch this and shutdown the system.
400		 */
401		if (msr & THERM_STATUS) {
402			tmp = (msr >> THERM_STATUS_TEMP_SHIFT) &
403			    THERM_STATUS_TEMP_MASK;
404			tmp = (sc->sc_tjmax - tmp) * 10 + TZ_ZEROC;
405			device_printf(dev, "critical temperature detected, "
406			    "suggest system shutdown\n");
407			snprintf(stemp, sizeof(stemp), "%d", tmp);
408			devctl_notify("coretemp", "Thermal", stemp,
409			    "notify=0xcc");
410		}
411	}
412
413	return (sysctl_handle_int(oidp, &val, 0, req));
414}
415
416static int
417coretemp_throttle_log_sysctl(SYSCTL_HANDLER_ARGS)
418{
419	device_t dev;
420	uint64_t msr;
421	int error, val;
422	struct coretemp_softc *sc;
423
424	dev = (device_t) arg1;
425	msr = coretemp_get_thermal_msr(device_get_unit(dev));
426	sc = device_get_softc(dev);
427
428	if (msr & THERM_STATUS_LOG) {
429		coretemp_clear_thermal_msr(device_get_unit(dev));
430		sc->sc_throttle_log = 1;
431	}
432
433	val = sc->sc_throttle_log;
434
435	error = sysctl_handle_int(oidp, &val, 0, req);
436
437	if (error || !req->newptr)
438		return (error);
439	else if (val != 0)
440		return (EINVAL);
441
442	coretemp_clear_thermal_msr(device_get_unit(dev));
443	sc->sc_throttle_log = 0;
444
445	return (0);
446}
447