1/*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include <dev/ata/ata-all.h> 50#include <dev/ata/ata-pci.h> 51#include <ata_if.h> 52 53/* local prototypes */ 54static int ata_intel_chipinit(device_t dev); 55static int ata_intel_chipdeinit(device_t dev); 56static int ata_intel_ch_attach(device_t dev); 57static void ata_intel_reset(device_t dev); 58static int ata_intel_old_setmode(device_t dev, int target, int mode); 59static int ata_intel_new_setmode(device_t dev, int target, int mode); 60static int ata_intel_sch_setmode(device_t dev, int target, int mode); 61static int ata_intel_sata_getrev(device_t dev, int target); 62static int ata_intel_sata_status(device_t dev); 63static int ata_intel_sata_ahci_read(device_t dev, int port, 64 int reg, u_int32_t *result); 65static int ata_intel_sata_cscr_read(device_t dev, int port, 66 int reg, u_int32_t *result); 67static int ata_intel_sata_sidpr_read(device_t dev, int port, 68 int reg, u_int32_t *result); 69static int ata_intel_sata_ahci_write(device_t dev, int port, 70 int reg, u_int32_t result); 71static int ata_intel_sata_cscr_write(device_t dev, int port, 72 int reg, u_int32_t result); 73static int ata_intel_sata_sidpr_write(device_t dev, int port, 74 int reg, u_int32_t result); 75static int ata_intel_sata_sidpr_test(device_t dev); 76static int ata_intel_31244_ch_attach(device_t dev); 77static int ata_intel_31244_ch_detach(device_t dev); 78static int ata_intel_31244_status(device_t dev); 79static void ata_intel_31244_tf_write(struct ata_request *request); 80static void ata_intel_31244_reset(device_t dev); 81 82/* misc defines */ 83#define INTEL_AHCI 1 84#define INTEL_ICH5 2 85#define INTEL_6CH 4 86#define INTEL_6CH2 8 87#define INTEL_ICH7 16 88 89struct ata_intel_data { 90 struct mtx lock; 91 u_char smap[4]; 92}; 93 94#define ATA_INTEL_SMAP(ctlr, ch) \ 95 &((struct ata_intel_data *)((ctlr)->chipset_data))->smap[(ch)->unit * 2] 96#define ATA_INTEL_LOCK(ctlr) \ 97 mtx_lock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 98#define ATA_INTEL_UNLOCK(ctlr) \ 99 mtx_unlock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 100 101/* 102 * Intel chipset support functions 103 */ 104static int 105ata_intel_probe(device_t dev) 106{ 107 struct ata_pci_controller *ctlr = device_get_softc(dev); 108 static const struct ata_chip_id ids[] = 109 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 110 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 111 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 112 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 113 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 114 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 115 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 116 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 117 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 118 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 119 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 120 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 121 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 122 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 123 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 124 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 125 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 126 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 127 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 128 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 129 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 130 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 131 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 132 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 133 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 134 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 135 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 136 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 137 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 138 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 139 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 140 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 141 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 142 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 143 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 144 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 145 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 146 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 147 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 148 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 149 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 150 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 151 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 152 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 153 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 154 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 155 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 156 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 157 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 158 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 159 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 160 { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 161 { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 162 { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 163 { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 164 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 165 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 166 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 167 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 168 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 169 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 170 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 171 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 172 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 173 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 174 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 175 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 176 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 177 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 178 { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 179 { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 180 { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 181 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 182 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 183 { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 184 { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 185 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 186 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 187 { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 188 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 189 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 190 { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 191 { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 192 { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 193 { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 194 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 195 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 196 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" }, 197 { ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 198 { ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 199 { ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 200 { ATA_PBG_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 201 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, 202 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 203 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 204 { ATA_PPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 205 { ATA_PPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 206 { ATA_PPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 207 { ATA_PPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 208 { ATA_PPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 209 { ATA_PPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 210 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 211 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 212 { ATA_PPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 213 { ATA_PPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 214 { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, 215 { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, 216 { ATA_LPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 217 { ATA_LPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 218 { ATA_LPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 219 { ATA_LPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 220 { ATA_LPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 221 { ATA_LPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 222 { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, 223 { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, 224 { ATA_LPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 225 { ATA_LPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 226 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 227 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 228 { ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" }, 229 { ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 230 { ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 231 { ATA_COLETOCRK_AH1,0, INTEL_AHCI, 0, ATA_SA300, "COLETOCRK" }, 232 { 0, 0, 0, 0, 0, 0}}; 233 234 if (pci_get_vendor(dev) != ATA_INTEL_ID) 235 return ENXIO; 236 237 if (!(ctlr->chip = ata_match_chip(dev, ids))) 238 return ENXIO; 239 240 ata_set_desc(dev); 241 ctlr->chipinit = ata_intel_chipinit; 242 ctlr->chipdeinit = ata_intel_chipdeinit; 243 return (BUS_PROBE_DEFAULT); 244} 245 246static int 247ata_intel_chipinit(device_t dev) 248{ 249 struct ata_pci_controller *ctlr = device_get_softc(dev); 250 struct ata_intel_data *data; 251 252 if (ata_setup_interrupt(dev, ata_generic_intr)) 253 return ENXIO; 254 255 data = malloc(sizeof(struct ata_intel_data), M_ATAPCI, M_WAITOK | M_ZERO); 256 mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF); 257 ctlr->chipset_data = (void *)data; 258 259 /* good old PIIX needs special treatment (not implemented) */ 260 if (ctlr->chip->chipid == ATA_I82371FB) { 261 ctlr->setmode = ata_intel_old_setmode; 262 } 263 264 /* the intel 31244 needs special care if in DPA mode */ 265 else if (ctlr->chip->chipid == ATA_I31244) { 266 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 267 ctlr->r_type2 = SYS_RES_MEMORY; 268 ctlr->r_rid2 = PCIR_BAR(0); 269 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 270 &ctlr->r_rid2, 271 RF_ACTIVE))) 272 return ENXIO; 273 ctlr->channels = 4; 274 ctlr->ch_attach = ata_intel_31244_ch_attach; 275 ctlr->ch_detach = ata_intel_31244_ch_detach; 276 ctlr->reset = ata_intel_31244_reset; 277 } 278 ctlr->setmode = ata_sata_setmode; 279 ctlr->getrev = ata_sata_getrev; 280 } 281 /* SCH */ 282 else if (ctlr->chip->chipid == ATA_ISCH) { 283 ctlr->channels = 1; 284 ctlr->ch_attach = ata_intel_ch_attach; 285 ctlr->ch_detach = ata_pci_ch_detach; 286 ctlr->setmode = ata_intel_sch_setmode; 287 } 288 /* non SATA intel chips goes here */ 289 else if (ctlr->chip->max_dma < ATA_SA150) { 290 ctlr->channels = ctlr->chip->cfg2; 291 ctlr->ch_attach = ata_intel_ch_attach; 292 ctlr->ch_detach = ata_pci_ch_detach; 293 ctlr->setmode = ata_intel_new_setmode; 294 } 295 296 /* SATA parts can be either compat or AHCI */ 297 else { 298 /* force all ports active "the legacy way" */ 299 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 300 301 ctlr->ch_attach = ata_intel_ch_attach; 302 ctlr->ch_detach = ata_pci_ch_detach; 303 ctlr->reset = ata_intel_reset; 304 305 /* 306 * if we have AHCI capability and AHCI or RAID mode enabled 307 * in BIOS we try for AHCI mode 308 */ 309 if ((ctlr->chip->cfg1 & INTEL_AHCI) && 310 (pci_read_config(dev, 0x90, 1) & 0xc0) && 311 (ata_ahci_chipinit(dev) != ENXIO)) 312 return 0; 313 314 /* BAR(5) may point to SATA interface registers */ 315 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 316 ctlr->r_type2 = SYS_RES_MEMORY; 317 ctlr->r_rid2 = PCIR_BAR(5); 318 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 319 &ctlr->r_rid2, RF_ACTIVE); 320 if (ctlr->r_res2 != NULL) { 321 /* Set SCRAE bit to enable registers access. */ 322 pci_write_config(dev, 0x94, 323 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 324 /* Set Ports Implemented register bits. */ 325 ATA_OUTL(ctlr->r_res2, 0x0C, 326 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 327 } 328 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */ 329 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 || 330 pci_get_subvendor(dev) != 0x106b) { 331 ctlr->r_type2 = SYS_RES_IOPORT; 332 ctlr->r_rid2 = PCIR_BAR(5); 333 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 334 &ctlr->r_rid2, RF_ACTIVE); 335 } 336 if (ctlr->r_res2 != NULL || 337 (ctlr->chip->cfg1 & INTEL_ICH5)) 338 ctlr->getrev = ata_intel_sata_getrev; 339 ctlr->setmode = ata_sata_setmode; 340 } 341 return 0; 342} 343 344static int 345ata_intel_chipdeinit(device_t dev) 346{ 347 struct ata_pci_controller *ctlr = device_get_softc(dev); 348 struct ata_intel_data *data; 349 350 data = ctlr->chipset_data; 351 mtx_destroy(&data->lock); 352 free(data, M_ATAPCI); 353 ctlr->chipset_data = NULL; 354 return (0); 355} 356 357static int 358ata_intel_ch_attach(device_t dev) 359{ 360 struct ata_pci_controller *ctlr; 361 struct ata_channel *ch; 362 u_char *smap; 363 u_int map; 364 365 /* setup the usual register normal pci style */ 366 if (ata_pci_ch_attach(dev)) 367 return (ENXIO); 368 369 ctlr = device_get_softc(device_get_parent(dev)); 370 ch = device_get_softc(dev); 371 372 /* if r_res2 is valid it points to SATA interface registers */ 373 if (ctlr->r_res2) { 374 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 375 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 376 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 377 ch->r_io[ATA_IDX_DATA].offset = 0x04; 378 } 379 380 ch->flags |= ATA_ALWAYS_DMASTAT; 381 if (ctlr->chip->max_dma >= ATA_SA150) { 382 smap = ATA_INTEL_SMAP(ctlr, ch); 383 map = pci_read_config(device_get_parent(dev), 0x90, 1); 384 if (ctlr->chip->cfg1 & INTEL_ICH5) { 385 map &= 0x07; 386 if ((map & 0x04) == 0) { 387 ch->flags |= ATA_SATA; 388 ch->flags |= ATA_NO_SLAVE; 389 smap[0] = (map & 0x01) ^ ch->unit; 390 smap[1] = 0; 391 } else if ((map & 0x02) == 0 && ch->unit == 0) { 392 ch->flags |= ATA_SATA; 393 smap[0] = (map & 0x01) ? 1 : 0; 394 smap[1] = (map & 0x01) ? 0 : 1; 395 } else if ((map & 0x02) != 0 && ch->unit == 1) { 396 ch->flags |= ATA_SATA; 397 smap[0] = (map & 0x01) ? 1 : 0; 398 smap[1] = (map & 0x01) ? 0 : 1; 399 } 400 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 401 ch->flags |= ATA_SATA; 402 ch->flags |= ATA_NO_SLAVE; 403 smap[0] = (ch->unit == 0) ? 0 : 1; 404 smap[1] = 0; 405 } else { 406 map &= 0x03; 407 if (map == 0x00) { 408 ch->flags |= ATA_SATA; 409 smap[0] = (ch->unit == 0) ? 0 : 1; 410 smap[1] = (ch->unit == 0) ? 2 : 3; 411 } else if (map == 0x02 && ch->unit == 0) { 412 ch->flags |= ATA_SATA; 413 smap[0] = 0; 414 smap[1] = 2; 415 } else if (map == 0x01 && ch->unit == 1) { 416 ch->flags |= ATA_SATA; 417 smap[0] = 1; 418 smap[1] = 3; 419 } 420 } 421 if (ch->flags & ATA_SATA) { 422 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 423 ch->hw.pm_read = ata_intel_sata_cscr_read; 424 ch->hw.pm_write = ata_intel_sata_cscr_write; 425 } else if (ctlr->r_res2) { 426 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 427 ch->hw.pm_read = ata_intel_sata_ahci_read; 428 ch->hw.pm_write = ata_intel_sata_ahci_write; 429 } else if (ata_intel_sata_sidpr_test(dev)) { 430 ch->hw.pm_read = ata_intel_sata_sidpr_read; 431 ch->hw.pm_write = ata_intel_sata_sidpr_write; 432 }; 433 } 434 if (ch->hw.pm_write != NULL) { 435 ch->flags |= ATA_PERIODIC_POLL; 436 ch->hw.status = ata_intel_sata_status; 437 ata_sata_scr_write(ch, 0, 438 ATA_SERROR, 0xffffffff); 439 if ((ch->flags & ATA_NO_SLAVE) == 0) { 440 ata_sata_scr_write(ch, 1, 441 ATA_SERROR, 0xffffffff); 442 } 443 } 444 } else 445 ctlr->setmode = ata_intel_new_setmode; 446 } else if (ctlr->chip->chipid != ATA_ISCH) 447 ch->flags |= ATA_CHECKS_CABLE; 448 return (0); 449} 450 451static void 452ata_intel_reset(device_t dev) 453{ 454 device_t parent = device_get_parent(dev); 455 struct ata_pci_controller *ctlr = device_get_softc(parent); 456 struct ata_channel *ch = device_get_softc(dev); 457 int mask, pshift, timeout, devs; 458 u_char *smap; 459 uint16_t pcs; 460 461 /* In combined mode, skip SATA stuff for PATA channel. */ 462 if ((ch->flags & ATA_SATA) == 0) 463 return (ata_generic_reset(dev)); 464 465 /* Do hard-reset on respective SATA ports. */ 466 smap = ATA_INTEL_SMAP(ctlr, ch); 467 mask = 1 << smap[0]; 468 if ((ch->flags & ATA_NO_SLAVE) == 0) 469 mask |= (1 << smap[1]); 470 pci_write_config(parent, 0x92, 471 pci_read_config(parent, 0x92, 2) & ~mask, 2); 472 DELAY(10); 473 pci_write_config(parent, 0x92, 474 pci_read_config(parent, 0x92, 2) | mask, 2); 475 476 /* Wait up to 1 sec for "connect well". */ 477 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 478 pshift = 8; 479 else 480 pshift = 4; 481 for (timeout = 0; timeout < 100 ; timeout++) { 482 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask; 483 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 484 break; 485 ata_udelay(10000); 486 } 487 488 if (bootverbose) 489 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs); 490 /* If any device found, do soft-reset. */ 491 if (ch->hw.pm_read != NULL) { 492 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0; 493 if ((ch->flags & ATA_NO_SLAVE) == 0) 494 devs |= ata_sata_phy_reset(dev, 1, 2) ? 495 ATA_ATA_SLAVE : 0; 496 } else { 497 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0; 498 if ((ch->flags & ATA_NO_SLAVE) == 0) 499 devs |= (pcs & (1 << smap[1])) ? 500 ATA_ATA_SLAVE : 0; 501 } 502 if (devs) { 503 ata_generic_reset(dev); 504 /* Reset may give fake slave when only ATAPI master present. */ 505 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER)); 506 } else 507 ch->devices = 0; 508} 509 510static int 511ata_intel_old_setmode(device_t dev, int target, int mode) 512{ 513 device_t parent = device_get_parent(dev); 514 struct ata_pci_controller *ctlr = device_get_softc(parent); 515 516 mode = min(mode, ctlr->chip->max_dma); 517 return (mode); 518} 519 520static int 521ata_intel_new_setmode(device_t dev, int target, int mode) 522{ 523 device_t parent = device_get_parent(dev); 524 struct ata_pci_controller *ctlr = device_get_softc(parent); 525 struct ata_channel *ch = device_get_softc(dev); 526 int devno = (ch->unit << 1) + target; 527 int piomode; 528 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 529 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 530 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 531 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 532 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 533 u_int32_t mask40 = 0, new40 = 0; 534 u_int8_t mask44 = 0, new44 = 0; 535 static const uint8_t timings[] = 536 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 537 static const uint8_t utimings[] = 538 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 539 540 /* In combined mode, skip PATA stuff for SATA channel. */ 541 if (ch->flags & ATA_SATA) 542 return (ata_sata_setmode(dev, target, mode)); 543 544 mode = min(mode, ctlr->chip->max_dma); 545 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 546 !(reg54 & (0x10 << devno))) { 547 ata_print_cable(dev, "controller"); 548 mode = ATA_UDMA2; 549 } 550 /* Enable/disable UDMA and set timings. */ 551 if (mode >= ATA_UDMA0) { 552 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 553 pci_write_config(parent, 0x4a, 554 (reg4a & ~(0x3 << (devno << 2))) | 555 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 556 piomode = ATA_PIO4; 557 } else { 558 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 559 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 560 piomode = mode; 561 } 562 reg54 |= 0x0400; 563 /* Set UDMA reference clock (33/66/133MHz). */ 564 reg54 &= ~(0x1001 << devno); 565 if (mode >= ATA_UDMA5) 566 reg54 |= (0x1000 << devno); 567 else if (mode >= ATA_UDMA3) 568 reg54 |= (0x1 << devno); 569 pci_write_config(parent, 0x54, reg54, 2); 570 /* Allow PIO/WDMA timing controls. */ 571 reg40 &= ~0x00ff00ff; 572 reg40 |= 0x40774077; 573 /* Set PIO/WDMA timings. */ 574 if (target == 0) { 575 mask40 = 0x3300; 576 new40 = timings[ata_mode2idx(piomode)] << 8; 577 } else { 578 mask44 = 0x0f; 579 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 580 (timings[ata_mode2idx(piomode)] & 0x03); 581 } 582 if (ch->unit) { 583 mask40 <<= 16; 584 new40 <<= 16; 585 mask44 <<= 4; 586 new44 <<= 4; 587 } 588 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 589 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 590 return (mode); 591} 592 593static int 594ata_intel_sch_setmode(device_t dev, int target, int mode) 595{ 596 device_t parent = device_get_parent(dev); 597 struct ata_pci_controller *ctlr = device_get_softc(parent); 598 u_int8_t dtim = 0x80 + (target << 2); 599 u_int32_t tim = pci_read_config(parent, dtim, 4); 600 int piomode; 601 602 mode = min(mode, ctlr->chip->max_dma); 603 if (mode >= ATA_UDMA0) { 604 tim |= (0x1 << 31); 605 tim &= ~(0x7 << 16); 606 tim |= ((mode & ATA_MODE_MASK) << 16); 607 piomode = ATA_PIO4; 608 } else if (mode >= ATA_WDMA0) { 609 tim &= ~(0x1 << 31); 610 tim &= ~(0x3 << 8); 611 tim |= ((mode & ATA_MODE_MASK) << 8); 612 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 613 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 614 } else 615 piomode = mode; 616 tim &= ~(0x7); 617 tim |= (piomode & 0x7); 618 pci_write_config(parent, dtim, tim, 4); 619 return (mode); 620} 621 622static int 623ata_intel_sata_getrev(device_t dev, int target) 624{ 625 struct ata_channel *ch = device_get_softc(dev); 626 uint32_t status; 627 628 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 629 return ((status & 0x0f0) >> 4); 630 return (0xff); 631} 632 633static int 634ata_intel_sata_status(device_t dev) 635{ 636 struct ata_channel *ch = device_get_softc(dev); 637 638 ata_sata_phy_check_events(dev, 0); 639 if ((ch->flags & ATA_NO_SLAVE) == 0) 640 ata_sata_phy_check_events(dev, 1); 641 642 return ata_pci_status(dev); 643} 644 645static int 646ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 647{ 648 struct ata_pci_controller *ctlr; 649 struct ata_channel *ch; 650 device_t parent; 651 u_char *smap; 652 int offset; 653 654 parent = device_get_parent(dev); 655 ctlr = device_get_softc(parent); 656 ch = device_get_softc(dev); 657 port = (port == 1) ? 1 : 0; 658 smap = ATA_INTEL_SMAP(ctlr, ch); 659 offset = 0x100 + smap[port] * 0x80; 660 switch (reg) { 661 case ATA_SSTATUS: 662 reg = 0x28; 663 break; 664 case ATA_SCONTROL: 665 reg = 0x2c; 666 break; 667 case ATA_SERROR: 668 reg = 0x30; 669 break; 670 default: 671 return (EINVAL); 672 } 673 *result = ATA_INL(ctlr->r_res2, offset + reg); 674 return (0); 675} 676 677static int 678ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 679{ 680 struct ata_pci_controller *ctlr; 681 struct ata_channel *ch; 682 device_t parent; 683 u_char *smap; 684 685 parent = device_get_parent(dev); 686 ctlr = device_get_softc(parent); 687 ch = device_get_softc(dev); 688 smap = ATA_INTEL_SMAP(ctlr, ch); 689 port = (port == 1) ? 1 : 0; 690 switch (reg) { 691 case ATA_SSTATUS: 692 reg = 0; 693 break; 694 case ATA_SERROR: 695 reg = 1; 696 break; 697 case ATA_SCONTROL: 698 reg = 2; 699 break; 700 default: 701 return (EINVAL); 702 } 703 ATA_INTEL_LOCK(ctlr); 704 pci_write_config(parent, 0xa0, 705 0x50 + smap[port] * 0x10 + reg * 4, 4); 706 *result = pci_read_config(parent, 0xa4, 4); 707 ATA_INTEL_UNLOCK(ctlr); 708 return (0); 709} 710 711static int 712ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 713{ 714 struct ata_pci_controller *ctlr; 715 struct ata_channel *ch; 716 device_t parent; 717 718 parent = device_get_parent(dev); 719 ctlr = device_get_softc(parent); 720 ch = device_get_softc(dev); 721 port = (port == 1) ? 1 : 0; 722 switch (reg) { 723 case ATA_SSTATUS: 724 reg = 0; 725 break; 726 case ATA_SCONTROL: 727 reg = 1; 728 break; 729 case ATA_SERROR: 730 reg = 2; 731 break; 732 default: 733 return (EINVAL); 734 } 735 ATA_INTEL_LOCK(ctlr); 736 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 737 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 738 ATA_INTEL_UNLOCK(ctlr); 739 return (0); 740} 741 742static int 743ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 744{ 745 struct ata_pci_controller *ctlr; 746 struct ata_channel *ch; 747 device_t parent; 748 u_char *smap; 749 int offset; 750 751 parent = device_get_parent(dev); 752 ctlr = device_get_softc(parent); 753 ch = device_get_softc(dev); 754 port = (port == 1) ? 1 : 0; 755 smap = ATA_INTEL_SMAP(ctlr, ch); 756 offset = 0x100 + smap[port] * 0x80; 757 switch (reg) { 758 case ATA_SSTATUS: 759 reg = 0x28; 760 break; 761 case ATA_SCONTROL: 762 reg = 0x2c; 763 break; 764 case ATA_SERROR: 765 reg = 0x30; 766 break; 767 default: 768 return (EINVAL); 769 } 770 ATA_OUTL(ctlr->r_res2, offset + reg, value); 771 return (0); 772} 773 774static int 775ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 776{ 777 struct ata_pci_controller *ctlr; 778 struct ata_channel *ch; 779 device_t parent; 780 u_char *smap; 781 782 parent = device_get_parent(dev); 783 ctlr = device_get_softc(parent); 784 ch = device_get_softc(dev); 785 smap = ATA_INTEL_SMAP(ctlr, ch); 786 port = (port == 1) ? 1 : 0; 787 switch (reg) { 788 case ATA_SSTATUS: 789 reg = 0; 790 break; 791 case ATA_SERROR: 792 reg = 1; 793 break; 794 case ATA_SCONTROL: 795 reg = 2; 796 break; 797 default: 798 return (EINVAL); 799 } 800 ATA_INTEL_LOCK(ctlr); 801 pci_write_config(parent, 0xa0, 802 0x50 + smap[port] * 0x10 + reg * 4, 4); 803 pci_write_config(parent, 0xa4, value, 4); 804 ATA_INTEL_UNLOCK(ctlr); 805 return (0); 806} 807 808static int 809ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 810{ 811 struct ata_pci_controller *ctlr; 812 struct ata_channel *ch; 813 device_t parent; 814 815 parent = device_get_parent(dev); 816 ctlr = device_get_softc(parent); 817 ch = device_get_softc(dev); 818 port = (port == 1) ? 1 : 0; 819 switch (reg) { 820 case ATA_SSTATUS: 821 reg = 0; 822 break; 823 case ATA_SCONTROL: 824 reg = 1; 825 break; 826 case ATA_SERROR: 827 reg = 2; 828 break; 829 default: 830 return (EINVAL); 831 } 832 ATA_INTEL_LOCK(ctlr); 833 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 834 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 835 ATA_INTEL_UNLOCK(ctlr); 836 return (0); 837} 838 839static int 840ata_intel_sata_sidpr_test(device_t dev) 841{ 842 struct ata_channel *ch = device_get_softc(dev); 843 int port; 844 uint32_t val; 845 846 port = (ch->flags & ATA_NO_SLAVE) ? 0 : 1; 847 for (; port >= 0; port--) { 848 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 849 if ((val & ATA_SC_IPM_MASK) == 850 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 851 return (1); 852 val |= ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER; 853 ata_intel_sata_sidpr_write(dev, port, ATA_SCONTROL, val); 854 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 855 if ((val & ATA_SC_IPM_MASK) == 856 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 857 return (1); 858 } 859 if (bootverbose) 860 device_printf(dev, 861 "SControl registers are not functional: %08x\n", val); 862 return (0); 863} 864 865static int 866ata_intel_31244_ch_attach(device_t dev) 867{ 868 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 869 struct ata_channel *ch = device_get_softc(dev); 870 int i; 871 int ch_offset; 872 873 ata_pci_dmainit(dev); 874 875 ch_offset = 0x200 + ch->unit * 0x200; 876 877 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 878 ch->r_io[i].res = ctlr->r_res2; 879 880 /* setup ATA registers */ 881 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 882 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 883 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 884 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 885 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 886 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 887 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 888 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 889 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 890 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 891 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 892 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 893 894 /* setup DMA registers */ 895 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 896 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 897 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 898 899 /* setup SATA registers */ 900 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 901 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 902 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 903 904 ch->flags |= ATA_NO_SLAVE; 905 ch->flags |= ATA_SATA; 906 ata_pci_hw(dev); 907 ch->hw.status = ata_intel_31244_status; 908 ch->hw.tf_write = ata_intel_31244_tf_write; 909 910 /* enable PHY state change interrupt */ 911 ATA_OUTL(ctlr->r_res2, 0x4, 912 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 913 return 0; 914} 915 916static int 917ata_intel_31244_ch_detach(device_t dev) 918{ 919 920 ata_pci_dmafini(dev); 921 return (0); 922} 923 924static int 925ata_intel_31244_status(device_t dev) 926{ 927 /* do we have any PHY events ? */ 928 ata_sata_phy_check_events(dev, -1); 929 930 /* any drive action to take care of ? */ 931 return ata_pci_status(dev); 932} 933 934static void 935ata_intel_31244_tf_write(struct ata_request *request) 936{ 937 struct ata_channel *ch = device_get_softc(request->parent); 938 939 if (request->flags & ATA_R_48BIT) { 940 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 941 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 942 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 943 (request->u.ata.lba & 0x00ff)); 944 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 945 ((request->u.ata.lba >> 8) & 0x00ff)); 946 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 947 ((request->u.ata.lba >> 16) & 0x00ff)); 948 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 949 } 950 else { 951 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 952 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 953 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 954 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 955 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 956 ATA_IDX_OUTB(ch, ATA_DRIVE, 957 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 958 ((request->u.ata.lba >> 24) & 0x0f)); 959 } 960} 961 962static void 963ata_intel_31244_reset(device_t dev) 964{ 965 struct ata_channel *ch = device_get_softc(dev); 966 967 if (ata_sata_phy_reset(dev, -1, 1)) 968 ata_generic_reset(dev); 969 else 970 ch->devices = 0; 971} 972 973ATA_DECLARE_DRIVER(ata_intel); 974MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 975