1/*-
2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer,
10 *    without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD$");
29
30#include <sys/param.h>
31#include <sys/module.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
34#include <sys/ata.h>
35#include <sys/bus.h>
36#include <sys/endian.h>
37#include <sys/malloc.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <sys/sema.h>
41#include <sys/taskqueue.h>
42#include <vm/uma.h>
43#include <machine/stdarg.h>
44#include <machine/resource.h>
45#include <machine/bus.h>
46#include <sys/rman.h>
47#include <dev/pci/pcivar.h>
48#include <dev/pci/pcireg.h>
49#include <dev/ata/ata-all.h>
50#include <dev/ata/ata-pci.h>
51#include <ata_if.h>
52
53/* local prototypes */
54static int ata_ali_chipinit(device_t dev);
55static int ata_ali_chipdeinit(device_t dev);
56static int ata_ali_ch_attach(device_t dev);
57static int ata_ali_sata_ch_attach(device_t dev);
58static void ata_ali_reset(device_t dev);
59static int ata_ali_setmode(device_t dev, int target, int mode);
60
61/* misc defines */
62#define ALI_OLD		0x01
63#define ALI_NEW		0x02
64#define ALI_SATA	0x04
65
66struct ali_sata_resources {
67	struct resource *bars[4];
68};
69
70/*
71 * Acer Labs Inc (ALI) chipset support functions
72 */
73static int
74ata_ali_probe(device_t dev)
75{
76    struct ata_pci_controller *ctlr = device_get_softc(dev);
77    static const struct ata_chip_id ids[] =
78    {{ ATA_ALI_5289, 0x00, 2, ALI_SATA, ATA_SA150, "M5289" },
79     { ATA_ALI_5288, 0x00, 4, ALI_SATA, ATA_SA300, "M5288" },
80     { ATA_ALI_5287, 0x00, 4, ALI_SATA, ATA_SA150, "M5287" },
81     { ATA_ALI_5281, 0x00, 2, ALI_SATA, ATA_SA150, "M5281" },
82     { ATA_ALI_5228, 0xc5, 0, ALI_NEW,  ATA_UDMA6, "M5228" },
83     { ATA_ALI_5229, 0xc5, 0, ALI_NEW,  ATA_UDMA6, "M5229" },
84     { ATA_ALI_5229, 0xc4, 0, ALI_NEW,  ATA_UDMA5, "M5229" },
85     { ATA_ALI_5229, 0xc2, 0, ALI_NEW,  ATA_UDMA4, "M5229" },
86     { ATA_ALI_5229, 0x20, 0, ALI_OLD,  ATA_UDMA2, "M5229" },
87     { ATA_ALI_5229, 0x00, 0, ALI_OLD,  ATA_WDMA2, "M5229" },
88     { 0, 0, 0, 0, 0, 0}};
89
90    if (pci_get_vendor(dev) != ATA_ACER_LABS_ID)
91	return ENXIO;
92
93    if (!(ctlr->chip = ata_match_chip(dev, ids)))
94	return ENXIO;
95
96    ata_set_desc(dev);
97    ctlr->chipinit = ata_ali_chipinit;
98    ctlr->chipdeinit = ata_ali_chipdeinit;
99    return (BUS_PROBE_DEFAULT);
100}
101
102static int
103ata_ali_chipinit(device_t dev)
104{
105    struct ata_pci_controller *ctlr = device_get_softc(dev);
106    struct ali_sata_resources *res;
107    int i, rid;
108
109    if (ata_setup_interrupt(dev, ata_generic_intr))
110	return ENXIO;
111
112    switch (ctlr->chip->cfg2) {
113    case ALI_SATA:
114	ctlr->channels = ctlr->chip->cfg1;
115	ctlr->ch_attach = ata_ali_sata_ch_attach;
116	ctlr->ch_detach = ata_pci_ch_detach;
117	ctlr->setmode = ata_sata_setmode;
118	ctlr->getrev = ata_sata_getrev;
119
120	/* AHCI mode is correctly supported only on the ALi 5288. */
121	if ((ctlr->chip->chipid == ATA_ALI_5288) &&
122	    (ata_ahci_chipinit(dev) != ENXIO))
123            return 0;
124
125	/* Allocate resources for later use by channel attach routines. */
126	res = malloc(sizeof(struct ali_sata_resources), M_ATAPCI, M_WAITOK);
127	for (i = 0; i < 4; i++) {
128		rid = PCIR_BAR(i);
129		res->bars[i] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
130		    RF_ACTIVE);
131		if (res->bars[i] == NULL) {
132			device_printf(dev, "Failed to allocate BAR %d\n", i);
133			for (i--; i >=0; i--)
134				bus_release_resource(dev, SYS_RES_IOPORT,
135				    PCIR_BAR(i), res->bars[i]);
136			free(res, M_ATAPCI);
137			return ENXIO;
138		}
139	}
140	ctlr->chipset_data = res;
141	break;
142
143    case ALI_NEW:
144	/* use device interrupt as byte count end */
145	pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
146
147	/* enable cable detection and UDMA support on revisions < 0xc7 */
148	if (ctlr->chip->chiprev < 0xc7)
149	    pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) |
150		0x09, 1);
151
152	/* enable ATAPI UDMA mode (even if we are going to do PIO) */
153	pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) |
154	    (ctlr->chip->chiprev >= 0xc7 ? 0x03 : 0x01), 1);
155
156	/* only chips with revision > 0xc4 can do 48bit DMA */
157	if (ctlr->chip->chiprev <= 0xc4)
158	    device_printf(dev,
159			  "using PIO transfers above 137GB as workaround for "
160			  "48bit DMA access bug, expect reduced performance\n");
161	ctlr->ch_attach = ata_ali_ch_attach;
162	ctlr->ch_detach = ata_pci_ch_detach;
163	ctlr->reset = ata_ali_reset;
164	ctlr->setmode = ata_ali_setmode;
165	break;
166
167    case ALI_OLD:
168	/* deactivate the ATAPI FIFO and enable ATAPI UDMA */
169	pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
170	ctlr->setmode = ata_ali_setmode;
171	break;
172    }
173    return 0;
174}
175
176static int
177ata_ali_chipdeinit(device_t dev)
178{
179	struct ata_pci_controller *ctlr = device_get_softc(dev);
180	struct ali_sata_resources *res;
181	int i;
182
183	if (ctlr->chip->cfg2 == ALI_SATA) {
184		res = ctlr->chipset_data;
185		for (i = 0; i < 4; i++) {
186			if (res->bars[i] != NULL) {
187				bus_release_resource(dev, SYS_RES_IOPORT,
188				    PCIR_BAR(i), res->bars[i]);
189			}
190		}
191		free(res, M_ATAPCI);
192		ctlr->chipset_data = NULL;
193	}
194	return (0);
195}
196
197static int
198ata_ali_ch_attach(device_t dev)
199{
200    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
201    struct ata_channel *ch = device_get_softc(dev);
202
203    /* setup the usual register normal pci style */
204    if (ata_pci_ch_attach(dev))
205	return ENXIO;
206
207    if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7)
208	ch->flags |= ATA_CHECKS_CABLE;
209    /* older chips can't do 48bit DMA transfers */
210    if (ctlr->chip->chiprev <= 0xc4) {
211	ch->flags |= ATA_NO_48BIT_DMA;
212	if (ch->dma.max_iosize > 256 * 512)
213		ch->dma.max_iosize = 256 * 512;
214    }
215	if (ctlr->chip->cfg2 & ALI_NEW)
216		ch->flags |= ATA_NO_ATAPI_DMA;
217
218    return 0;
219}
220
221static int
222ata_ali_sata_ch_attach(device_t dev)
223{
224    device_t parent = device_get_parent(dev);
225    struct ata_pci_controller *ctlr = device_get_softc(parent);
226    struct ata_channel *ch = device_get_softc(dev);
227    struct ali_sata_resources *res;
228    struct resource *io = NULL, *ctlio = NULL;
229    int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
230    int i;
231
232    res = ctlr->chipset_data;
233    if (unit01) {
234	    io = res->bars[2];
235	    ctlio = res->bars[3];
236    } else {
237	    io = res->bars[0];
238	    ctlio = res->bars[1];
239    }
240    ata_pci_dmainit(dev);
241    for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
242	ch->r_io[i].res = io;
243	ch->r_io[i].offset = i + (unit10 ? 8 : 0);
244    }
245    ch->r_io[ATA_CONTROL].res = ctlio;
246    ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
247    ch->r_io[ATA_IDX_ADDR].res = io;
248    ata_default_registers(dev);
249    if (ctlr->r_res1) {
250	for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
251	    ch->r_io[i].res = ctlr->r_res1;
252	    ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
253	}
254    }
255    ch->flags |= ATA_NO_SLAVE;
256    ch->flags |= ATA_SATA;
257
258    /* XXX SOS PHY handling awkward in ALI chip not supported yet */
259    ata_pci_hw(dev);
260    return 0;
261}
262
263static void
264ata_ali_reset(device_t dev)
265{
266    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
267    struct ata_channel *ch = device_get_softc(dev);
268    device_t *children;
269    int nchildren, i;
270
271    ata_generic_reset(dev);
272
273    /*
274     * workaround for datacorruption bug found on at least SUN Blade-100
275     * find the ISA function on the southbridge and disable then enable
276     * the ATA channel tristate buffer
277     */
278    if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
279	if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
280	    for (i = 0; i < nchildren; i++) {
281		if (pci_get_devid(children[i]) == ATA_ALI_1533) {
282		    pci_write_config(children[i], 0x58,
283				     pci_read_config(children[i], 0x58, 1) &
284				     ~(0x04 << ch->unit), 1);
285		    pci_write_config(children[i], 0x58,
286				     pci_read_config(children[i], 0x58, 1) |
287				     (0x04 << ch->unit), 1);
288		    break;
289		}
290	    }
291	    free(children, M_TEMP);
292	}
293    }
294}
295
296static int
297ata_ali_setmode(device_t dev, int target, int mode)
298{
299	device_t parent = device_get_parent(dev);
300	struct ata_pci_controller *ctlr = device_get_softc(parent);
301	struct ata_channel *ch = device_get_softc(dev);
302	int devno = (ch->unit << 1) + target;
303	int piomode;
304	static const uint32_t piotimings[] =
305		{ 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
306		  0x00310001, 0x006d0003, 0x00330001, 0x00310001 };
307	static const uint8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f,
308	    0x0d};
309	uint32_t word54;
310
311        mode = min(mode, ctlr->chip->max_dma);
312
313	if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) {
314		if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
315		    pci_read_config(parent, 0x4a, 1) & (1 << ch->unit)) {
316			ata_print_cable(dev, "controller");
317			mode = ATA_UDMA2;
318		}
319	}
320	if (ctlr->chip->cfg2 & ALI_OLD) {
321		/* doesn't support ATAPI DMA on write */
322		ch->flags |= ATA_ATAPI_DMA_RO;
323		if (ch->devices & ATA_ATAPI_MASTER &&
324		    ch->devices & ATA_ATAPI_SLAVE) {
325		        /* doesn't support ATAPI DMA on two ATAPI devices */
326		        device_printf(dev, "two atapi devices on this channel,"
327			    " no DMA\n");
328		        mode = min(mode, ATA_PIO_MAX);
329		}
330	}
331	/* Set UDMA mode */
332	word54 = pci_read_config(parent, 0x54, 4);
333	if (mode >= ATA_UDMA0) {
334	    word54 &= ~(0x000f000f << (devno << 2));
335	    word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
336	    piomode = ATA_PIO4;
337	}
338	else {
339	    word54 &= ~(0x0008000f << (devno << 2));
340	    piomode = mode;
341	}
342	pci_write_config(parent, 0x54, word54, 4);
343	/* Set PIO/WDMA mode */
344	pci_write_config(parent, 0x58 + (ch->unit << 2),
345	    piotimings[ata_mode2idx(piomode)], 4);
346	return (mode);
347}
348
349ATA_DECLARE_DRIVER(ata_ali);
350MODULE_DEPEND(ata_ali, ata_ahci, 1, 1, 1);
351