1/*- 2 * Copyright (c) 2011 3 * Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/** 29 * Driver for the MMC/SD/SDIO module on the TI OMAP series of SoCs. 30 * 31 * This driver is heavily based on the SD/MMC driver for the AT91 (at91_mci.c). 32 * 33 * It's important to realise that the MMC state machine is already in the kernel 34 * and this driver only exposes the specific interfaces of the controller. 35 * 36 * This driver is still very much a work in progress, I've verified that basic 37 * sector reading can be performed. But I've yet to test it with a file system 38 * or even writing. In addition I've only tested the driver with an SD card, 39 * I've no idea if MMC cards work. 40 * 41 */ 42#include <sys/cdefs.h> 43__FBSDID("$FreeBSD$"); 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bio.h> 48#include <sys/bus.h> 49#include <sys/conf.h> 50#include <sys/endian.h> 51#include <sys/kernel.h> 52#include <sys/kthread.h> 53#include <sys/lock.h> 54#include <sys/malloc.h> 55#include <sys/module.h> 56#include <sys/mutex.h> 57#include <sys/queue.h> 58#include <sys/resource.h> 59#include <sys/rman.h> 60#include <sys/time.h> 61#include <sys/timetc.h> 62#include <sys/gpio.h> 63 64#include <machine/bus.h> 65#include <machine/cpu.h> 66#include <machine/cpufunc.h> 67#include <machine/resource.h> 68#include <machine/frame.h> 69#include <machine/intr.h> 70 71#include <dev/mmc/bridge.h> 72#include <dev/mmc/mmcreg.h> 73#include <dev/mmc/mmcbrvar.h> 74 75#include <dev/fdt/fdt_common.h> 76#include <dev/ofw/openfirm.h> 77#include <dev/ofw/ofw_bus.h> 78#include <dev/ofw/ofw_bus_subr.h> 79 80#include "gpio_if.h" 81 82#include "mmcbr_if.h" 83#include "mmcbus_if.h" 84 85#include <arm/ti/ti_sdma.h> 86#include <arm/ti/ti_edma3.h> 87#include <arm/ti/ti_mmchs.h> 88#include <arm/ti/ti_cpuid.h> 89#include <arm/ti/ti_prcm.h> 90 91#include <arm/ti/twl/twl.h> 92#include <arm/ti/twl/twl_vreg.h> 93 94#ifdef DEBUG 95#define ti_mmchs_dbg(sc, fmt, args...) \ 96 device_printf((sc)->sc_dev, fmt, ## args); 97#else 98#define ti_mmchs_dbg(sc, fmt, args...) 99#endif 100 101/** 102 * Structure that stores the driver context 103 */ 104struct ti_mmchs_softc { 105 device_t sc_dev; 106 uint32_t device_id; 107 struct resource* sc_irq_res; 108 struct resource* sc_mem_res; 109 110 void* sc_irq_h; 111 112 bus_dma_tag_t sc_dmatag; 113 bus_dmamap_t sc_dmamap; 114 int sc_dmamapped; 115 116 unsigned int sc_dmach_rd; 117 unsigned int sc_dmach_wr; 118 int dma_rx_trig; 119 int dma_tx_trig; 120 121 device_t sc_gpio_dev; 122 int sc_wp_gpio_pin; /* GPIO pin for MMC write protect */ 123 124 device_t sc_vreg_dev; 125 const char* sc_vreg_name; 126 127 struct mtx sc_mtx; 128 129 struct mmc_host host; 130 struct mmc_request* req; 131 struct mmc_command* curcmd; 132 133 int flags; 134#define CMD_STARTED 1 135#define STOP_STARTED 2 136 137 int bus_busy; /* TODO: Needed ? */ 138 139 void* sc_cmd_data_vaddr; 140 int sc_cmd_data_len; 141 142 /* The offset applied to each of the register base addresses, OMAP4 143 * register sets are offset 0x100 from the OMAP3 series. 144 */ 145 unsigned long sc_reg_off; 146 147 /* The physical address of the MMCHS_DATA register, used for the DMA xfers */ 148 unsigned long sc_data_reg_paddr; 149 150 /* The reference clock frequency */ 151 unsigned int sc_ref_freq; 152 153 enum mmc_power_mode sc_cur_power_mode; 154}; 155 156/** 157 * Macros for driver mutex locking 158 */ 159#define TI_MMCHS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 160#define TI_MMCHS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 161#define TI_MMCHS_LOCK_INIT(_sc) \ 162 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 163 "ti_mmchs", MTX_DEF) 164#define TI_MMCHS_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 165#define TI_MMCHS_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 166#define TI_MMCHS_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 167 168static void ti_mmchs_start(struct ti_mmchs_softc *sc); 169 170/** 171 * ti_mmchs_read_4 - reads a 32-bit value from a register 172 * ti_mmchs_write_4 - writes a 32-bit value to a register 173 * @sc: pointer to the driver context 174 * @off: register offset to read from 175 * @val: the value to write into the register 176 * 177 * LOCKING: 178 * None 179 * 180 * RETURNS: 181 * The 32-bit value read from the register 182 */ 183static inline uint32_t 184ti_mmchs_read_4(struct ti_mmchs_softc *sc, bus_size_t off) 185{ 186 return bus_read_4(sc->sc_mem_res, (sc->sc_reg_off + off)); 187} 188 189static inline void 190ti_mmchs_write_4(struct ti_mmchs_softc *sc, bus_size_t off, uint32_t val) 191{ 192 bus_write_4(sc->sc_mem_res, (sc->sc_reg_off + off), val); 193} 194 195/** 196 * ti_mmchs_reset_controller - 197 * @arg: caller supplied arg 198 * @segs: array of segments (although in our case should only be one) 199 * @nsegs: number of segments (in our case should be 1) 200 * @error: 201 * 202 * 203 * 204 */ 205static void 206ti_mmchs_reset_controller(struct ti_mmchs_softc *sc, uint32_t bit) 207{ 208 unsigned long attempts; 209 uint32_t sysctl; 210 211 ti_mmchs_dbg(sc, "reseting controller - bit 0x%08x\n", bit); 212 213 sysctl = ti_mmchs_read_4(sc, MMCHS_SYSCTL); 214 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl | bit); 215 /* 216 * AM335x and OMAP4 >= ES2 have an updated reset logic. 217 * Monitor a 0->1 transition first. 218 */ 219 if ((ti_chip() == CHIP_AM335X) || 220 ((ti_chip() == CHIP_OMAP_4) && (ti_revision() > OMAP4430_REV_ES1_0))) { 221 attempts = 10000; 222 while (!(ti_mmchs_read_4(sc, MMCHS_SYSCTL) & bit) && (attempts-- > 0)) 223 continue; 224 } 225 226 attempts = 10000; 227 while ((ti_mmchs_read_4(sc, MMCHS_SYSCTL) & bit) && (attempts-- > 0)) 228 continue; 229 230 if (ti_mmchs_read_4(sc, MMCHS_SYSCTL) & bit) 231 device_printf(sc->sc_dev, "Error - Timeout waiting on controller reset\n"); 232} 233 234/** 235 * ti_mmchs_getaddr - called by the DMA function to simply return the phys addr 236 * @arg: caller supplied arg 237 * @segs: array of segments (although in our case should only be one) 238 * @nsegs: number of segments (in our case should be 1) 239 * @error: 240 * 241 * This function is called by bus_dmamap_load() after it has compiled an array 242 * of segments, each segment is a phsyical chunk of memory. However in our case 243 * we should only have one segment, because we don't (yet?) support DMA scatter 244 * gather. To ensure we only have one segment, the DMA tag was created by 245 * bus_dma_tag_create() (called from ti_mmchs_attach) with nsegments set to 1. 246 * 247 */ 248static void 249ti_mmchs_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 250{ 251 if (error != 0) 252 return; 253 254 *(bus_addr_t *)arg = segs[0].ds_addr; 255} 256 257#ifndef SOC_TI_AM335X 258/** 259 * ti_mmchs_dma_intr - interrupt handler for DMA events triggered by the controller 260 * @ch: the dma channel number 261 * @status: bit field of the status bytes 262 * @data: callback data, in this case a pointer to the controller struct 263 * 264 * 265 * LOCKING: 266 * Called from interrupt context 267 * 268 */ 269static void 270ti_mmchs_dma_intr(unsigned int ch, uint32_t status, void *data) 271{ 272 /* Ignore for now ... we don't need this interrupt as we already have the 273 * interrupt from the MMC controller. 274 */ 275} 276#endif 277 278/** 279 * ti_mmchs_intr_xfer_compl - called if a 'transfer complete' IRQ was received 280 * @sc: pointer to the driver context 281 * @cmd: the command that was sent previously 282 * 283 * This function is simply responsible for syncing up the DMA buffer. 284 * 285 * LOCKING: 286 * Called from interrupt context 287 * 288 * RETURNS: 289 * Return value indicates if the transaction is complete, not done = 0, done != 0 290 */ 291static int 292ti_mmchs_intr_xfer_compl(struct ti_mmchs_softc *sc, struct mmc_command *cmd) 293{ 294 uint32_t cmd_reg; 295 296 /* Read command register to test whether this command was a read or write. */ 297 cmd_reg = ti_mmchs_read_4(sc, MMCHS_CMD); 298 299 /* Sync-up the DMA buffer so the caller can access the new memory */ 300 if (cmd_reg & MMCHS_CMD_DDIR) { 301 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_POSTREAD); 302 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 303 } 304 else { 305 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_POSTWRITE); 306 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 307 } 308 sc->sc_dmamapped--; 309 310 /* Debugging dump of the data received */ 311#if 0 312 { 313 int i; 314 uint8_t *p = (uint8_t*) sc->sc_cmd_data_vaddr; 315 for (i=0; i<sc->sc_cmd_data_len; i++) { 316 if ((i % 16) == 0) 317 printf("\n0x%04x : ", i); 318 printf("%02X ", *p++); 319 } 320 printf("\n"); 321 } 322#endif 323 324 /* We are done, transfer complete */ 325 return 1; 326} 327 328/** 329 * ti_mmchs_intr_cmd_compl - called if a 'command complete' IRQ was received 330 * @sc: pointer to the driver context 331 * @cmd: the command that was sent previously 332 * 333 * 334 * LOCKING: 335 * Called from interrupt context 336 * 337 * RETURNS: 338 * Return value indicates if the transaction is complete, not done = 0, done != 0 339 */ 340static int 341ti_mmchs_intr_cmd_compl(struct ti_mmchs_softc *sc, struct mmc_command *cmd) 342{ 343 uint32_t cmd_reg; 344 345 /* Copy the response into the request struct ... if a response was 346 * expected */ 347 if (cmd != NULL && (cmd->flags & MMC_RSP_PRESENT)) { 348 if (cmd->flags & MMC_RSP_136) { 349 cmd->resp[3] = ti_mmchs_read_4(sc, MMCHS_RSP10); 350 cmd->resp[2] = ti_mmchs_read_4(sc, MMCHS_RSP32); 351 cmd->resp[1] = ti_mmchs_read_4(sc, MMCHS_RSP54); 352 cmd->resp[0] = ti_mmchs_read_4(sc, MMCHS_RSP76); 353 } else { 354 cmd->resp[0] = ti_mmchs_read_4(sc, MMCHS_RSP10); 355 } 356 } 357 358 /* Check if the command was expecting some data transfer, if not 359 * we are done. */ 360 cmd_reg = ti_mmchs_read_4(sc, MMCHS_CMD); 361 return ((cmd_reg & MMCHS_CMD_DP) == 0); 362} 363 364/** 365 * ti_mmchs_intr_error - handles error interrupts 366 * @sc: pointer to the driver context 367 * @cmd: the command that was sent previously 368 * @stat_reg: the value that was in the status register 369 * 370 * 371 * LOCKING: 372 * Called from interrupt context 373 * 374 * RETURNS: 375 * Return value indicates if the transaction is complete, not done = 0, done != 0 376 */ 377static int 378ti_mmchs_intr_error(struct ti_mmchs_softc *sc, struct mmc_command *cmd, 379 uint32_t stat_reg) 380{ 381 ti_mmchs_dbg(sc, "error in xfer - stat 0x%08x\n", stat_reg); 382 383 /* Ignore CRC errors on CMD2 and ACMD47, per relevant standards */ 384 if ((stat_reg & MMCHS_STAT_CCRC) && (cmd->opcode == MMC_SEND_OP_COND || 385 cmd->opcode == ACMD_SD_SEND_OP_COND)) 386 cmd->error = MMC_ERR_NONE; 387 else if (stat_reg & (MMCHS_STAT_CTO | MMCHS_STAT_DTO)) 388 cmd->error = MMC_ERR_TIMEOUT; 389 else if (stat_reg & (MMCHS_STAT_CCRC | MMCHS_STAT_DCRC)) 390 cmd->error = MMC_ERR_BADCRC; 391 else 392 cmd->error = MMC_ERR_FAILED; 393 394 /* If a dma transaction we should also stop the dma transfer */ 395 if (ti_mmchs_read_4(sc, MMCHS_CMD) & MMCHS_CMD_DE) { 396 397 /* Abort the DMA transfer (DDIR bit tells direction) */ 398 if (ti_mmchs_read_4(sc, MMCHS_CMD) & MMCHS_CMD_DDIR) 399#ifdef SOC_TI_AM335X 400 printf("%s: DMA unimplemented\n", __func__); 401#else 402 ti_sdma_stop_xfer(sc->sc_dmach_rd); 403#endif 404 else 405#ifdef SOC_TI_AM335X 406 printf("%s: DMA unimplemented\n", __func__); 407#else 408 ti_sdma_stop_xfer(sc->sc_dmach_wr); 409#endif 410 411 /* If an error occure abort the DMA operation and free the dma map */ 412 if ((sc->sc_dmamapped > 0) && (cmd->error != MMC_ERR_NONE)) { 413 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 414 sc->sc_dmamapped--; 415 } 416 } 417 418 /* Command error occured? ... if so issue a soft reset for the cmd fsm */ 419 if (stat_reg & (MMCHS_STAT_CCRC | MMCHS_STAT_CTO)) { 420 ti_mmchs_reset_controller(sc, MMCHS_SYSCTL_SRC); 421 } 422 423 /* Data error occured? ... if so issue a soft reset for the data line */ 424 if (stat_reg & (MMCHS_STAT_DEB | MMCHS_STAT_DCRC | MMCHS_STAT_DTO)) { 425 ti_mmchs_reset_controller(sc, MMCHS_SYSCTL_SRD); 426 } 427 428 /* On any error the command is cancelled ... so we are done */ 429 return 1; 430} 431 432/** 433 * ti_mmchs_intr - interrupt handler for MMC/SD/SDIO controller 434 * @arg: pointer to the driver context 435 * 436 * Interrupt handler for the MMC/SD/SDIO controller, responsible for handling 437 * the IRQ and clearing the status flags. 438 * 439 * LOCKING: 440 * Called from interrupt context 441 * 442 * RETURNS: 443 * nothing 444 */ 445static void 446ti_mmchs_intr(void *arg) 447{ 448 struct ti_mmchs_softc *sc = (struct ti_mmchs_softc *) arg; 449 uint32_t stat_reg; 450 int done = 0; 451 452 TI_MMCHS_LOCK(sc); 453 454 stat_reg = ti_mmchs_read_4(sc, MMCHS_STAT) & (ti_mmchs_read_4(sc, 455 MMCHS_IE) | MMCHS_STAT_ERRI); 456 457 if (sc->curcmd == NULL) { 458 device_printf(sc->sc_dev, "Error: current cmd NULL, already done?\n"); 459 ti_mmchs_write_4(sc, MMCHS_STAT, stat_reg); 460 TI_MMCHS_UNLOCK(sc); 461 return; 462 } 463 464 if (stat_reg & MMCHS_STAT_ERRI) { 465 /* An error has been tripped in the status register */ 466 done = ti_mmchs_intr_error(sc, sc->curcmd, stat_reg); 467 468 } else { 469 470 /* NOTE: This implementation could be a bit inefficent, I don't think 471 * it is necessary to handle both the 'command complete' and 'transfer 472 * complete' for data transfers ... presumably just transfer complete 473 * is enough. 474 */ 475 476 /* No error */ 477 sc->curcmd->error = MMC_ERR_NONE; 478 479 /* Check if the command completed */ 480 if (stat_reg & MMCHS_STAT_CC) { 481 done = ti_mmchs_intr_cmd_compl(sc, sc->curcmd); 482 } 483 484 /* Check if the transfer has completed */ 485 if (stat_reg & MMCHS_STAT_TC) { 486 done = ti_mmchs_intr_xfer_compl(sc, sc->curcmd); 487 } 488 489 } 490 491 /* Clear all the interrupt status bits by writing the value back */ 492 ti_mmchs_write_4(sc, MMCHS_STAT, stat_reg); 493 494 /* This may mark the command as done if there is no stop request */ 495 /* TODO: This is a bit ugly, needs fix-up */ 496 if (done) { 497 ti_mmchs_start(sc); 498 } 499 500 TI_MMCHS_UNLOCK(sc); 501} 502 503#ifdef SOC_TI_AM335X 504static void 505ti_mmchs_edma3_rx_xfer_setup(struct ti_mmchs_softc *sc, uint32_t src_paddr, 506 uint32_t dst_paddr, uint16_t blk_size, uint16_t num_blks) 507{ 508 struct ti_edma3cc_param_set ps; 509 510 bzero(&ps, sizeof(struct ti_edma3cc_param_set)); 511 ps.src = src_paddr; 512 ps.dst = dst_paddr; 513 ps.dstbidx = 4; 514 ps.dstcidx = blk_size; 515 ps.acnt = 4; 516 ps.bcnt = blk_size/4; 517 ps.ccnt = num_blks; 518 ps.link = 0xffff; 519 ps.opt.tcc = sc->dma_rx_trig; 520 ps.opt.tcinten = 1; 521 ps.opt.fwid = 2; /* fifo width is 32 */ 522 ps.opt.sam = 1; 523 ps.opt.syncdim = 1; 524 525 ti_edma3_param_write(sc->dma_rx_trig, &ps); 526 ti_edma3_enable_transfer_event(sc->dma_rx_trig); 527} 528 529static void 530ti_mmchs_edma3_tx_xfer_setup(struct ti_mmchs_softc *sc, uint32_t src_paddr, 531 uint32_t dst_paddr, uint16_t blk_size, uint16_t num_blks) 532{ 533 struct ti_edma3cc_param_set ps; 534 535 bzero(&ps, sizeof(struct ti_edma3cc_param_set)); 536 ps.src = src_paddr; 537 ps.dst = dst_paddr; 538 ps.srccidx = blk_size; 539 ps.bcnt = blk_size/4; 540 ps.ccnt = num_blks; 541 ps.srcbidx = 4; 542 ps.acnt = 0x4; 543 ps.link = 0xffff; 544 ps.opt.tcc = sc->dma_tx_trig; 545 ps.opt.tcinten = 1; 546 ps.opt.fwid = 2; /* fifo width is 32 */ 547 ps.opt.dam = 1; 548 ps.opt.syncdim = 1; 549 550 ti_edma3_param_write(sc->dma_tx_trig, &ps); 551 ti_edma3_enable_transfer_event(sc->dma_tx_trig); 552} 553#endif 554 555/** 556 * ti_mmchs_start_cmd - starts the given command 557 * @sc: pointer to the driver context 558 * @cmd: the command to start 559 * 560 * The call tree for this function is 561 * - ti_mmchs_start_cmd 562 * - ti_mmchs_start 563 * - ti_mmchs_request 564 * 565 * LOCKING: 566 * Caller should be holding the OMAP_MMC lock. 567 * 568 * RETURNS: 569 * nothing 570 */ 571static void 572ti_mmchs_start_cmd(struct ti_mmchs_softc *sc, struct mmc_command *cmd) 573{ 574 uint32_t cmd_reg, con_reg, ise_reg; 575 struct mmc_data *data; 576 struct mmc_request *req; 577 void *vaddr; 578 bus_addr_t paddr; 579#ifndef SOC_TI_AM335X 580 uint32_t pktsize; 581#endif 582 sc->curcmd = cmd; 583 data = cmd->data; 584 req = cmd->mrq; 585 586 /* Ensure the STR and MIT bits are cleared, these are only used for special 587 * command types. 588 */ 589 con_reg = ti_mmchs_read_4(sc, MMCHS_CON); 590 con_reg &= ~(MMCHS_CON_STR | MMCHS_CON_MIT); 591 592 /* Load the command into bits 29:24 of the CMD register */ 593 cmd_reg = (uint32_t)(cmd->opcode & 0x3F) << 24; 594 595 /* Set the default set of interrupts */ 596 ise_reg = (MMCHS_STAT_CERR | MMCHS_STAT_CTO | MMCHS_STAT_CC | MMCHS_STAT_CEB); 597 598 /* Enable CRC checking if requested */ 599 if (cmd->flags & MMC_RSP_CRC) 600 ise_reg |= MMCHS_STAT_CCRC; 601 602 /* Enable reply index checking if the response supports it */ 603 if (cmd->flags & MMC_RSP_OPCODE) 604 ise_reg |= MMCHS_STAT_CIE; 605 606 /* Set the expected response length */ 607 if (MMC_RSP(cmd->flags) == MMC_RSP_NONE) { 608 cmd_reg |= MMCHS_CMD_RSP_TYPE_NO; 609 } else { 610 if (cmd->flags & MMC_RSP_136) 611 cmd_reg |= MMCHS_CMD_RSP_TYPE_136; 612 else if (cmd->flags & MMC_RSP_BUSY) 613 cmd_reg |= MMCHS_CMD_RSP_TYPE_48_BSY; 614 else 615 cmd_reg |= MMCHS_CMD_RSP_TYPE_48; 616 617 /* Enable command index/crc checks if necessary expected */ 618 if (cmd->flags & MMC_RSP_CRC) 619 cmd_reg |= MMCHS_CMD_CCCE; 620 if (cmd->flags & MMC_RSP_OPCODE) 621 cmd_reg |= MMCHS_CMD_CICE; 622 } 623 624 /* Set the bits for the special commands CMD12 (MMC_STOP_TRANSMISSION) and 625 * CMD52 (SD_IO_RW_DIRECT) */ 626 if (cmd->opcode == MMC_STOP_TRANSMISSION) 627 cmd_reg |= MMCHS_CMD_CMD_TYPE_IO_ABORT; 628 629 /* Check if there is any data to write */ 630 if (data == NULL) { 631 /* Clear the block count */ 632 ti_mmchs_write_4(sc, MMCHS_BLK, 0); 633 634 /* The no data case is fairly simple */ 635 ti_mmchs_write_4(sc, MMCHS_CON, con_reg); 636 ti_mmchs_write_4(sc, MMCHS_IE, ise_reg); 637 ti_mmchs_write_4(sc, MMCHS_ISE, ise_reg); 638 ti_mmchs_write_4(sc, MMCHS_ARG, cmd->arg); 639 ti_mmchs_write_4(sc, MMCHS_CMD, cmd_reg); 640 return; 641 } 642 643 /* Indicate that data is present */ 644 cmd_reg |= MMCHS_CMD_DP | MMCHS_CMD_MSBS | MMCHS_CMD_BCE; 645 646 /* Indicate a read operation */ 647 if (data->flags & MMC_DATA_READ) 648 cmd_reg |= MMCHS_CMD_DDIR; 649 650 /* Streaming mode */ 651 if (data->flags & MMC_DATA_STREAM) { 652 con_reg |= MMCHS_CON_STR; 653 } 654 655 /* Multi-block mode */ 656 if (data->flags & MMC_DATA_MULTI) { 657 cmd_reg |= MMCHS_CMD_MSBS; 658 } 659 660 /* Enable extra interrupt sources for the transfer */ 661 ise_reg |= (MMCHS_STAT_TC | MMCHS_STAT_DTO | MMCHS_STAT_DEB | MMCHS_STAT_CEB); 662 if (cmd->flags & MMC_RSP_CRC) 663 ise_reg |= MMCHS_STAT_DCRC; 664 665 /* Enable the DMA transfer bit */ 666 cmd_reg |= MMCHS_CMD_DE; 667 668 /* Set the block size and block count */ 669 ti_mmchs_write_4(sc, MMCHS_BLK, (1 << 16) | data->len); 670 671 /* Setup the DMA stuff */ 672 if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) { 673 674 vaddr = data->data; 675 data->xfer_len = 0; 676 677 /* Map the buffer buf into bus space using the dmamap map. */ 678 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, vaddr, data->len, 679 ti_mmchs_getaddr, &paddr, 0) != 0) { 680 681 if (req->cmd->flags & STOP_STARTED) 682 req->stop->error = MMC_ERR_NO_MEMORY; 683 else 684 req->cmd->error = MMC_ERR_NO_MEMORY; 685 sc->req = NULL; 686 sc->curcmd = NULL; 687 req->done(req); 688 return; 689 } 690 691#ifndef SOC_TI_AM335X 692 /* Calculate the packet size, the max packet size is 512 bytes 693 * (or 128 32-bit elements). 694 */ 695 pktsize = min((data->len / 4), (512 / 4)); 696#endif 697 /* Sync the DMA buffer and setup the DMA controller */ 698 if (data->flags & MMC_DATA_READ) { 699 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_PREREAD); 700#ifdef SOC_TI_AM335X 701 ti_mmchs_edma3_rx_xfer_setup(sc, sc->sc_data_reg_paddr, 702 paddr, data->len, 1); 703#else 704 ti_sdma_start_xfer_packet(sc->sc_dmach_rd, sc->sc_data_reg_paddr, 705 paddr, 1, (data->len / 4), pktsize); 706#endif 707 } else { 708 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_PREWRITE); 709#ifdef SOC_TI_AM335X 710 ti_mmchs_edma3_tx_xfer_setup(sc, paddr, 711 sc->sc_data_reg_paddr, data->len, 1); 712#else 713 ti_sdma_start_xfer_packet(sc->sc_dmach_wr, paddr, 714 sc->sc_data_reg_paddr, 1, (data->len / 4), pktsize); 715#endif 716 } 717 718 /* Increase the mapped count */ 719 sc->sc_dmamapped++; 720 721 sc->sc_cmd_data_vaddr = vaddr; 722 sc->sc_cmd_data_len = data->len; 723 } 724 725 /* Finally kick off the command */ 726 ti_mmchs_write_4(sc, MMCHS_CON, con_reg); 727 ti_mmchs_write_4(sc, MMCHS_IE, ise_reg); 728 ti_mmchs_write_4(sc, MMCHS_ISE, ise_reg); 729 ti_mmchs_write_4(sc, MMCHS_ARG, cmd->arg); 730 ti_mmchs_write_4(sc, MMCHS_CMD, cmd_reg); 731 732 /* and we're done */ 733} 734 735/** 736 * ti_mmchs_start - starts a request stored in the driver context 737 * @sc: pointer to the driver context 738 * 739 * This function is called by ti_mmchs_request() in response to a read/write 740 * request from the MMC core module. 741 * 742 * LOCKING: 743 * Caller should be holding the OMAP_MMC lock. 744 * 745 * RETURNS: 746 * nothing 747 */ 748static void 749ti_mmchs_start(struct ti_mmchs_softc *sc) 750{ 751 struct mmc_request *req; 752 753 /* Sanity check we have a request */ 754 req = sc->req; 755 if (req == NULL) 756 return; 757 758 /* assert locked */ 759 if (!(sc->flags & CMD_STARTED)) { 760 sc->flags |= CMD_STARTED; 761 ti_mmchs_start_cmd(sc, req->cmd); 762 return; 763 } 764 765 if (!(sc->flags & STOP_STARTED) && req->stop) { 766 sc->flags |= STOP_STARTED; 767 ti_mmchs_start_cmd(sc, req->stop); 768 return; 769 } 770 771 /* We must be done -- bad idea to do this while locked? */ 772 sc->req = NULL; 773 sc->curcmd = NULL; 774 req->done(req); 775} 776 777/** 778 * ti_mmchs_request - entry point for all read/write/cmd requests 779 * @brdev: mmc bridge device handle 780 * @reqdev: the device doing the requesting ? 781 * @req: the action requested 782 * 783 * LOCKING: 784 * None, internally takes the OMAP_MMC lock. 785 * 786 * RETURNS: 787 * 0 on success 788 * EBUSY if the driver is already performing a request 789 */ 790static int 791ti_mmchs_request(device_t brdev, device_t reqdev, struct mmc_request *req) 792{ 793 struct ti_mmchs_softc *sc = device_get_softc(brdev); 794 795 TI_MMCHS_LOCK(sc); 796 797 /* 798 * XXX do we want to be able to queue up multiple commands? 799 * XXX sounds like a good idea, but all protocols are sync, so 800 * XXX maybe the idea is naive... 801 */ 802 if (sc->req != NULL) { 803 TI_MMCHS_UNLOCK(sc); 804 return (EBUSY); 805 } 806 807 /* Store the request and start the command */ 808 sc->req = req; 809 sc->flags = 0; 810 ti_mmchs_start(sc); 811 812 TI_MMCHS_UNLOCK(sc); 813 814 return (0); 815} 816 817/** 818 * ti_mmchs_get_ro - returns the status of the read-only setting 819 * @brdev: mmc bridge device handle 820 * @reqdev: device doing the request 821 * 822 * This function is relies on hint'ed values to determine which GPIO is used 823 * to determine if the write protect is enabled. On the BeagleBoard the pin 824 * is GPIO_23. 825 * 826 * LOCKING: 827 * - 828 * 829 * RETURNS: 830 * 0 if not read-only 831 * 1 if read only 832 */ 833static int 834ti_mmchs_get_ro(device_t brdev, device_t reqdev) 835{ 836 struct ti_mmchs_softc *sc = device_get_softc(brdev); 837 unsigned int readonly = 0; 838 839 TI_MMCHS_LOCK(sc); 840 841 if ((sc->sc_wp_gpio_pin != -1) && (sc->sc_gpio_dev != NULL)) { 842 if (GPIO_PIN_GET(sc->sc_gpio_dev, sc->sc_wp_gpio_pin, &readonly) != 0) 843 readonly = 0; 844 else 845 readonly = (readonly == 0) ? 0 : 1; 846 } 847 848 TI_MMCHS_UNLOCK(sc); 849 850 return (readonly); 851} 852 853/** 854 * ti_mmchs_send_init_stream - sets bus/controller settings 855 * @brdev: mmc bridge device handle 856 * @reqdev: device doing the request 857 * 858 * Send init stream sequence to card before sending IDLE command 859 * 860 * LOCKING: 861 * 862 * 863 * RETURNS: 864 * 0 if function succeeded 865 */ 866static void 867ti_mmchs_send_init_stream(struct ti_mmchs_softc *sc) 868{ 869 unsigned long timeout; 870 uint32_t ie, ise, con; 871 872 ti_mmchs_dbg(sc, "Performing init sequence\n"); 873 874 /* Prior to issuing any command, the MMCHS controller has to execute a 875 * special INIT procedure. The MMCHS controller has to generate a clock 876 * during 1ms. During the INIT procedure, the MMCHS controller generates 80 877 * clock periods. In order to keep the 1ms gap, the MMCHS controller should 878 * be configured to generate a clock whose frequency is smaller or equal to 879 * 80 KHz. If the MMCHS controller divider bitfield width doesn't allow to 880 * choose big values, the MMCHS controller driver should perform the INIT 881 * procedure twice or three times. Twice is generally enough. 882 * 883 * The INIt procedure is executed by setting MMCHS1.MMCHS_CON[1] INIT 884 * bitfield to 1 and by sending a dummy command, writing 0x00000000 in 885 * MMCHS1.MMCHS_CMD register. 886 */ 887 888 /* Disable interrupt status events but enable interrupt generation. 889 * This doesn't seem right to me, but if the interrupt generation is not 890 * enabled the CC bit doesn't seem to be set in the STAT register. 891 */ 892 893 /* Enable interrupt generation */ 894 ie = ti_mmchs_read_4(sc, MMCHS_IE); 895 ti_mmchs_write_4(sc, MMCHS_IE, 0x307F0033); 896 897 /* Disable generation of status events (stops interrupt triggering) */ 898 ise = ti_mmchs_read_4(sc, MMCHS_ISE); 899 ti_mmchs_write_4(sc, MMCHS_ISE, 0); 900 901 /* Set the initialise stream bit */ 902 con = ti_mmchs_read_4(sc, MMCHS_CON); 903 con |= MMCHS_CON_INIT; 904 ti_mmchs_write_4(sc, MMCHS_CON, con); 905 906 /* Write a dummy command 0x00 */ 907 ti_mmchs_write_4(sc, MMCHS_CMD, 0x00000000); 908 909 /* Loop waiting for the command to finish */ 910 timeout = hz; 911 do { 912 pause("MMCINIT", 1); 913 if (timeout-- == 0) { 914 device_printf(sc->sc_dev, "Error: first stream init timed out\n"); 915 break; 916 } 917 } while (!(ti_mmchs_read_4(sc, MMCHS_STAT) & MMCHS_STAT_CC)); 918 919 /* Clear the command complete status bit */ 920 ti_mmchs_write_4(sc, MMCHS_STAT, MMCHS_STAT_CC); 921 922 /* Write another dummy command 0x00 */ 923 ti_mmchs_write_4(sc, MMCHS_CMD, 0x00000000); 924 925 /* Loop waiting for the second command to finish */ 926 timeout = hz; 927 do { 928 pause("MMCINIT", 1); 929 if (timeout-- == 0) { 930 device_printf(sc->sc_dev, "Error: second stream init timed out\n"); 931 break; 932 } 933 } while (!(ti_mmchs_read_4(sc, MMCHS_STAT) & MMCHS_STAT_CC)); 934 935 /* Clear the stream init bit */ 936 con &= ~MMCHS_CON_INIT; 937 ti_mmchs_write_4(sc, MMCHS_CON, con); 938 939 /* Clear the status register, then restore the IE and ISE registers */ 940 ti_mmchs_write_4(sc, MMCHS_STAT, 0xffffffff); 941 ti_mmchs_read_4(sc, MMCHS_STAT); 942 943 ti_mmchs_write_4(sc, MMCHS_ISE, ise); 944 ti_mmchs_write_4(sc, MMCHS_IE, ie); 945} 946 947/** 948 * ti_mmchs_update_ios - sets bus/controller settings 949 * @brdev: mmc bridge device handle 950 * @reqdev: device doing the request 951 * 952 * Called to set the bus and controller settings that need to be applied to 953 * the actual HW. Currently this function just sets the bus width and the 954 * clock speed. 955 * 956 * LOCKING: 957 * 958 * 959 * RETURNS: 960 * 0 if function succeeded 961 */ 962static int 963ti_mmchs_update_ios(device_t brdev, device_t reqdev) 964{ 965 struct ti_mmchs_softc *sc; 966 struct mmc_host *host; 967 struct mmc_ios *ios; 968 uint32_t clkdiv; 969 uint32_t hctl_reg; 970 uint32_t con_reg; 971 uint32_t sysctl_reg; 972#ifndef SOC_TI_AM335X 973 uint16_t mv; 974#endif 975 unsigned long timeout; 976 int do_card_init = 0; 977 978 sc = device_get_softc(brdev); 979 host = &sc->host; 980 ios = &host->ios; 981 982 /* Read the initial values of the registers */ 983 hctl_reg = ti_mmchs_read_4(sc, MMCHS_HCTL); 984 con_reg = ti_mmchs_read_4(sc, MMCHS_CON); 985 986 /* Set the bus width */ 987 switch (ios->bus_width) { 988 case bus_width_1: 989 hctl_reg &= ~MMCHS_HCTL_DTW; 990 con_reg &= ~MMCHS_CON_DW8; 991 break; 992 case bus_width_4: 993 hctl_reg |= MMCHS_HCTL_DTW; 994 con_reg &= ~MMCHS_CON_DW8; 995 break; 996 case bus_width_8: 997 con_reg |= MMCHS_CON_DW8; 998 break; 999 } 1000 1001 /* Finally write all these settings back to the registers */ 1002 ti_mmchs_write_4(sc, MMCHS_HCTL, hctl_reg); 1003 ti_mmchs_write_4(sc, MMCHS_CON, con_reg); 1004 1005 /* Check if we need to change the external voltage regulator */ 1006 if (sc->sc_cur_power_mode != ios->power_mode) { 1007 1008 if (ios->power_mode == power_up) { 1009 1010 /* Set the power level */ 1011 hctl_reg = ti_mmchs_read_4(sc, MMCHS_HCTL); 1012 hctl_reg &= ~(MMCHS_HCTL_SDVS_MASK | MMCHS_HCTL_SDBP); 1013 1014 if ((ios->vdd == -1) || (ios->vdd >= vdd_240)) { 1015#ifndef SOC_TI_AM335X 1016 mv = 3000; 1017#endif 1018 hctl_reg |= MMCHS_HCTL_SDVS_V30; 1019 } else { 1020#ifndef SOC_TI_AM335X 1021 mv = 1800; 1022#endif 1023 hctl_reg |= MMCHS_HCTL_SDVS_V18; 1024 } 1025 1026 ti_mmchs_write_4(sc, MMCHS_HCTL, hctl_reg); 1027 1028#ifdef SOC_TI_AM335X 1029 printf("%s: TWL unimplemented\n", __func__); 1030#else 1031 /* Set the desired voltage on the regulator */ 1032 if (sc->sc_vreg_dev && sc->sc_vreg_name) 1033 twl_vreg_set_voltage(sc->sc_vreg_dev, sc->sc_vreg_name, mv); 1034#endif 1035 /* Enable the bus power */ 1036 ti_mmchs_write_4(sc, MMCHS_HCTL, (hctl_reg | MMCHS_HCTL_SDBP)); 1037 timeout = hz; 1038 while (!(ti_mmchs_read_4(sc, MMCHS_HCTL) & MMCHS_HCTL_SDBP)) { 1039 if (timeout-- == 0) 1040 break; 1041 pause("MMC_PWRON", 1); 1042 } 1043 1044 } else if (ios->power_mode == power_off) { 1045 /* Disable the bus power */ 1046 hctl_reg = ti_mmchs_read_4(sc, MMCHS_HCTL); 1047 ti_mmchs_write_4(sc, MMCHS_HCTL, (hctl_reg & ~MMCHS_HCTL_SDBP)); 1048 1049#ifdef SOC_TI_AM335X 1050 printf("%s: TWL unimplemented\n", __func__); 1051#else 1052 /* Turn the power off on the voltage regulator */ 1053 if (sc->sc_vreg_dev && sc->sc_vreg_name) 1054 twl_vreg_set_voltage(sc->sc_vreg_dev, sc->sc_vreg_name, 0); 1055#endif 1056 } else if (ios->power_mode == power_on) { 1057 /* Force a card re-initialisation sequence */ 1058 do_card_init = 1; 1059 } 1060 1061 /* Save the new power state */ 1062 sc->sc_cur_power_mode = ios->power_mode; 1063 } 1064 1065 /* need the MMCHS_SYSCTL register */ 1066 sysctl_reg = ti_mmchs_read_4(sc, MMCHS_SYSCTL); 1067 1068 /* Just in case this hasn't been setup before, set the timeout to the default */ 1069 sysctl_reg &= ~MMCHS_SYSCTL_DTO_MASK; 1070 sysctl_reg |= MMCHS_SYSCTL_DTO(0xe); 1071 1072 /* Disable the clock output while configuring the new clock */ 1073 sysctl_reg &= ~(MMCHS_SYSCTL_ICE | MMCHS_SYSCTL_CEN); 1074 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl_reg); 1075 1076 /* bus mode? */ 1077 if (ios->clock == 0) { 1078 clkdiv = 0; 1079 } else { 1080 clkdiv = sc->sc_ref_freq / ios->clock; 1081 if (clkdiv < 1) 1082 clkdiv = 1; 1083 if ((sc->sc_ref_freq / clkdiv) > ios->clock) 1084 clkdiv += 1; 1085 if (clkdiv > 250) 1086 clkdiv = 250; 1087 } 1088 1089 /* Set the new clock divider */ 1090 sysctl_reg &= ~MMCHS_SYSCTL_CLKD_MASK; 1091 sysctl_reg |= MMCHS_SYSCTL_CLKD(clkdiv); 1092 1093 /* Write the new settings ... */ 1094 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl_reg); 1095 /* ... write the internal clock enable bit ... */ 1096 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl_reg | MMCHS_SYSCTL_ICE); 1097 /* ... wait for the clock to stablise ... */ 1098 while (((sysctl_reg = ti_mmchs_read_4(sc, MMCHS_SYSCTL)) & 1099 MMCHS_SYSCTL_ICS) == 0) { 1100 continue; 1101 } 1102 /* ... then enable */ 1103 sysctl_reg |= MMCHS_SYSCTL_CEN; 1104 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl_reg); 1105 1106 /* If the power state has changed to 'power_on' then run the init sequence*/ 1107 if (do_card_init) { 1108 ti_mmchs_send_init_stream(sc); 1109 } 1110 1111 /* Set the bus mode (opendrain or normal) */ 1112 con_reg = ti_mmchs_read_4(sc, MMCHS_CON); 1113 if (ios->bus_mode == opendrain) 1114 con_reg |= MMCHS_CON_OD; 1115 else 1116 con_reg &= ~MMCHS_CON_OD; 1117 ti_mmchs_write_4(sc, MMCHS_CON, con_reg); 1118 1119 return (0); 1120} 1121 1122/** 1123 * ti_mmchs_acquire_host - 1124 * @brdev: mmc bridge device handle 1125 * @reqdev: device doing the request 1126 * 1127 * TODO: Is this function needed ? 1128 * 1129 * LOCKING: 1130 * none 1131 * 1132 * RETURNS: 1133 * 0 function succeeded 1134 * 1135 */ 1136static int 1137ti_mmchs_acquire_host(device_t brdev, device_t reqdev) 1138{ 1139 struct ti_mmchs_softc *sc = device_get_softc(brdev); 1140 int err = 0; 1141 1142 TI_MMCHS_LOCK(sc); 1143 1144 while (sc->bus_busy) { 1145 msleep(sc, &sc->sc_mtx, PZERO, "mmc", hz / 5); 1146 } 1147 1148 sc->bus_busy++; 1149 1150 TI_MMCHS_UNLOCK(sc); 1151 1152 return (err); 1153} 1154 1155/** 1156 * ti_mmchs_release_host - 1157 * @brdev: mmc bridge device handle 1158 * @reqdev: device doing the request 1159 * 1160 * TODO: Is this function needed ? 1161 * 1162 * LOCKING: 1163 * none 1164 * 1165 * RETURNS: 1166 * 0 function succeeded 1167 * 1168 */ 1169static int 1170ti_mmchs_release_host(device_t brdev, device_t reqdev) 1171{ 1172 struct ti_mmchs_softc *sc = device_get_softc(brdev); 1173 1174 TI_MMCHS_LOCK(sc); 1175 1176 sc->bus_busy--; 1177 wakeup(sc); 1178 1179 TI_MMCHS_UNLOCK(sc); 1180 1181 return (0); 1182} 1183 1184/** 1185 * ti_mmchs_read_ivar - returns driver conf variables 1186 * @bus: 1187 * @child: 1188 * @which: The variable to get the result for 1189 * @result: Upon return will store the variable value 1190 * 1191 * 1192 * 1193 * LOCKING: 1194 * None, caller must hold locks 1195 * 1196 * RETURNS: 1197 * 0 on success 1198 * EINVAL if the variable requested is invalid 1199 */ 1200static int 1201ti_mmchs_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1202{ 1203 struct ti_mmchs_softc *sc = device_get_softc(bus); 1204 1205 switch (which) { 1206 case MMCBR_IVAR_BUS_MODE: 1207 *(int *)result = sc->host.ios.bus_mode; 1208 break; 1209 case MMCBR_IVAR_BUS_WIDTH: 1210 *(int *)result = sc->host.ios.bus_width; 1211 break; 1212 case MMCBR_IVAR_CHIP_SELECT: 1213 *(int *)result = sc->host.ios.chip_select; 1214 break; 1215 case MMCBR_IVAR_CLOCK: 1216 *(int *)result = sc->host.ios.clock; 1217 break; 1218 case MMCBR_IVAR_F_MIN: 1219 *(int *)result = sc->host.f_min; 1220 break; 1221 case MMCBR_IVAR_F_MAX: 1222 *(int *)result = sc->host.f_max; 1223 break; 1224 case MMCBR_IVAR_HOST_OCR: 1225 *(int *)result = sc->host.host_ocr; 1226 break; 1227 case MMCBR_IVAR_MODE: 1228 *(int *)result = sc->host.mode; 1229 break; 1230 case MMCBR_IVAR_OCR: 1231 *(int *)result = sc->host.ocr; 1232 break; 1233 case MMCBR_IVAR_POWER_MODE: 1234 *(int *)result = sc->host.ios.power_mode; 1235 break; 1236 case MMCBR_IVAR_VDD: 1237 *(int *)result = sc->host.ios.vdd; 1238 break; 1239 case MMCBR_IVAR_CAPS: 1240 *(int *)result = sc->host.caps; 1241 break; 1242 case MMCBR_IVAR_MAX_DATA: 1243 *(int *)result = 1; 1244 break; 1245 default: 1246 return (EINVAL); 1247 } 1248 return (0); 1249} 1250 1251/** 1252 * ti_mmchs_write_ivar - writes a driver conf variables 1253 * @bus: 1254 * @child: 1255 * @which: The variable to set 1256 * @value: The value to write into the variable 1257 * 1258 * 1259 * 1260 * LOCKING: 1261 * None, caller must hold locks 1262 * 1263 * RETURNS: 1264 * 0 on success 1265 * EINVAL if the variable requested is invalid 1266 */ 1267static int 1268ti_mmchs_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1269{ 1270 struct ti_mmchs_softc *sc = device_get_softc(bus); 1271 1272 switch (which) { 1273 case MMCBR_IVAR_BUS_MODE: 1274 sc->host.ios.bus_mode = value; 1275 break; 1276 case MMCBR_IVAR_BUS_WIDTH: 1277 sc->host.ios.bus_width = value; 1278 break; 1279 case MMCBR_IVAR_CHIP_SELECT: 1280 sc->host.ios.chip_select = value; 1281 break; 1282 case MMCBR_IVAR_CLOCK: 1283 sc->host.ios.clock = value; 1284 break; 1285 case MMCBR_IVAR_MODE: 1286 sc->host.mode = value; 1287 break; 1288 case MMCBR_IVAR_OCR: 1289 sc->host.ocr = value; 1290 break; 1291 case MMCBR_IVAR_POWER_MODE: 1292 sc->host.ios.power_mode = value; 1293 break; 1294 case MMCBR_IVAR_VDD: 1295 sc->host.ios.vdd = value; 1296 break; 1297 /* These are read-only */ 1298 case MMCBR_IVAR_CAPS: 1299 case MMCBR_IVAR_HOST_OCR: 1300 case MMCBR_IVAR_F_MIN: 1301 case MMCBR_IVAR_F_MAX: 1302 case MMCBR_IVAR_MAX_DATA: 1303 return (EINVAL); 1304 default: 1305 return (EINVAL); 1306 } 1307 return (0); 1308} 1309 1310/** 1311 * ti_mmchs_hw_init - initialises the MMC/SD/SIO controller 1312 * @dev: mmc device handle 1313 * 1314 * Called by the driver attach function during driver initialisation. This 1315 * function is responsibly to setup the controller ready for transactions. 1316 * 1317 * LOCKING: 1318 * No locking, assumed to only be called during initialisation. 1319 * 1320 * RETURNS: 1321 * nothing 1322 */ 1323static void 1324ti_mmchs_hw_init(device_t dev) 1325{ 1326 struct ti_mmchs_softc *sc = device_get_softc(dev); 1327 clk_ident_t clk; 1328 unsigned long timeout; 1329 uint32_t sysctl; 1330 uint32_t capa; 1331 uint32_t con, sysconfig; 1332 1333 /* 1: Enable the controller and interface/functional clocks */ 1334 clk = MMC0_CLK + sc->device_id; 1335 1336 if (ti_prcm_clk_enable(clk) != 0) { 1337 device_printf(dev, "Error: failed to enable MMC clock\n"); 1338 return; 1339 } 1340 1341 /* 1a: Get the frequency of the source clock */ 1342 if (ti_prcm_clk_get_source_freq(clk, &sc->sc_ref_freq) != 0) { 1343 device_printf(dev, "Error: failed to get source clock freq\n"); 1344 return; 1345 } 1346 1347 /* 2: Issue a softreset to the controller */ 1348 sysconfig = ti_mmchs_read_4(sc, MMCHS_SYSCONFIG); 1349 sysconfig |= MMCHS_SYSCONFIG_SRST; 1350 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, sysconfig); 1351 timeout = 100; 1352 while ((ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & 0x01) == 0x0) { 1353 DELAY(1000); 1354 if (timeout-- == 0) { 1355 device_printf(dev, "Error: reset operation timed out\n"); 1356 return; 1357 } 1358 } 1359 1360 /* 3: Reset both the command and data state machines */ 1361 sysctl = ti_mmchs_read_4(sc, MMCHS_SYSCTL); 1362 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl | MMCHS_SYSCTL_SRA); 1363 timeout = 100; 1364 while ((ti_mmchs_read_4(sc, MMCHS_SYSCTL) & MMCHS_SYSCTL_SRA) != 0x0) { 1365 DELAY(1000); 1366 if (timeout-- == 0) { 1367 device_printf(dev, "Error: reset operation timed out\n"); 1368 return; 1369 } 1370 } 1371 1372 /* 4: Set initial host configuration (1-bit mode, pwroff) and capabilities */ 1373 ti_mmchs_write_4(sc, MMCHS_HCTL, MMCHS_HCTL_SDVS_V30); 1374 1375 capa = ti_mmchs_read_4(sc, MMCHS_CAPA); 1376 ti_mmchs_write_4(sc, MMCHS_CAPA, capa | MMCHS_CAPA_VS30 | MMCHS_CAPA_VS18); 1377 1378 /* 5: Set the initial bus configuration 1379 * 0 CTPL_MMC_SD : Control Power for DAT1 line 1380 * 0 WPP_ACTIVE_HIGH : Write protect polarity 1381 * 0 CDP_ACTIVE_HIGH : Card detect polarity 1382 * 0 CTO_ENABLED : MMC interrupt command 1383 * 0 DW8_DISABLED : 8-bit mode MMC select 1384 * 0 MODE_FUNC : Mode select 1385 * 0 STREAM_DISABLED : Stream command 1386 * 0 HR_DISABLED : Broadcast host response 1387 * 0 INIT_DISABLED : Send initialization stream 1388 * 0 OD_DISABLED : No Open Drain 1389 */ 1390 con = ti_mmchs_read_4(sc, MMCHS_CON) & MMCHS_CON_DVAL_MASK; 1391 ti_mmchs_write_4(sc, MMCHS_CON, con); 1392 1393} 1394 1395/** 1396 * ti_mmchs_fini - shutdown the MMC/SD/SIO controller 1397 * @dev: mmc device handle 1398 * 1399 * Responsible for shutting done the MMC controller, this function may be 1400 * called as part of a reset sequence. 1401 * 1402 * LOCKING: 1403 * No locking, assumed to be called during tear-down/reset. 1404 * 1405 * RETURNS: 1406 * nothing 1407 */ 1408static void 1409ti_mmchs_hw_fini(device_t dev) 1410{ 1411 struct ti_mmchs_softc *sc = device_get_softc(dev); 1412 1413 /* Disable all interrupts */ 1414 ti_mmchs_write_4(sc, MMCHS_ISE, 0x00000000); 1415 ti_mmchs_write_4(sc, MMCHS_IE, 0x00000000); 1416 1417 /* Disable the functional and interface clocks */ 1418 ti_prcm_clk_disable(MMC0_CLK + sc->device_id); 1419} 1420 1421/** 1422 * ti_mmchs_init_dma_channels - initalise the DMA channels 1423 * @sc: driver soft context 1424 * 1425 * Attempts to activate an RX and TX DMA channel for the MMC device. 1426 * 1427 * LOCKING: 1428 * No locking, assumed to be called during tear-down/reset. 1429 * 1430 * RETURNS: 1431 * 0 on success, a negative error code on failure. 1432 */ 1433static int 1434ti_mmchs_init_dma_channels(struct ti_mmchs_softc *sc) 1435{ 1436#ifdef SOC_TI_AM335X 1437 switch (sc->device_id) { 1438 case 0: 1439 sc->dma_tx_trig = TI_EDMA3_EVENT_SDTXEVT0; 1440 sc->dma_rx_trig = TI_EDMA3_EVENT_SDRXEVT0; 1441 break; 1442 case 1: 1443 sc->dma_tx_trig = TI_EDMA3_EVENT_SDTXEVT1; 1444 sc->dma_rx_trig = TI_EDMA3_EVENT_SDRXEVT1; 1445 break; 1446 default: 1447 return(EINVAL); 1448 } 1449 1450#define EVTQNUM 0 1451 /* TODO EDMA3 have 3 queues, so we need some queue allocation call */ 1452 ti_edma3_init(EVTQNUM); 1453 ti_edma3_request_dma_ch(sc->dma_tx_trig, sc->dma_tx_trig, EVTQNUM); 1454 ti_edma3_request_dma_ch(sc->dma_rx_trig, sc->dma_rx_trig, EVTQNUM); 1455#else 1456 int err; 1457 uint32_t rev; 1458 1459 /* Get the current chip revision */ 1460 rev = ti_revision(); 1461 if ((OMAP_REV_DEVICE(rev) != OMAP4430_DEV) && (sc->device_id > 3)) 1462 return(EINVAL); 1463 1464 /* Get the DMA MMC triggers */ 1465 switch (sc->device_id) { 1466 case 1: 1467 sc->dma_tx_trig = 60; 1468 sc->dma_rx_trig = 61; 1469 break; 1470 case 2: 1471 sc->dma_tx_trig = 46; 1472 sc->dma_rx_trig = 47; 1473 break; 1474 case 3: 1475 sc->dma_tx_trig = 76; 1476 sc->dma_rx_trig = 77; 1477 break; 1478 /* The following are OMAP4 only */ 1479 case 4: 1480 sc->dma_tx_trig = 56; 1481 sc->dma_rx_trig = 57; 1482 break; 1483 case 5: 1484 sc->dma_tx_trig = 58; 1485 sc->dma_rx_trig = 59; 1486 break; 1487 default: 1488 return(EINVAL); 1489 } 1490 1491 /* Activate a RX channel from the OMAP DMA driver */ 1492 err = ti_sdma_activate_channel(&sc->sc_dmach_rd, ti_mmchs_dma_intr, sc); 1493 if (err != 0) 1494 return(err); 1495 1496 /* Setup the RX channel for MMC data transfers */ 1497 ti_sdma_set_xfer_burst(sc->sc_dmach_rd, TI_SDMA_BURST_NONE, 1498 TI_SDMA_BURST_64); 1499 ti_sdma_set_xfer_data_type(sc->sc_dmach_rd, TI_SDMA_DATA_32BITS_SCALAR); 1500 ti_sdma_sync_params(sc->sc_dmach_rd, sc->dma_rx_trig, 1501 TI_SDMA_SYNC_PACKET | TI_SDMA_SYNC_TRIG_ON_SRC); 1502 ti_sdma_set_addr_mode(sc->sc_dmach_rd, TI_SDMA_ADDR_CONSTANT, 1503 TI_SDMA_ADDR_POST_INCREMENT); 1504 1505 /* Activate and configure the TX DMA channel */ 1506 err = ti_sdma_activate_channel(&sc->sc_dmach_wr, ti_mmchs_dma_intr, sc); 1507 if (err != 0) 1508 return(err); 1509 1510 /* Setup the TX channel for MMC data transfers */ 1511 ti_sdma_set_xfer_burst(sc->sc_dmach_wr, TI_SDMA_BURST_64, 1512 TI_SDMA_BURST_NONE); 1513 ti_sdma_set_xfer_data_type(sc->sc_dmach_wr, TI_SDMA_DATA_32BITS_SCALAR); 1514 ti_sdma_sync_params(sc->sc_dmach_wr, sc->dma_tx_trig, 1515 TI_SDMA_SYNC_PACKET | TI_SDMA_SYNC_TRIG_ON_DST); 1516 ti_sdma_set_addr_mode(sc->sc_dmach_wr, TI_SDMA_ADDR_POST_INCREMENT, 1517 TI_SDMA_ADDR_CONSTANT); 1518#endif 1519 return(0); 1520} 1521 1522/** 1523 * ti_mmchs_deactivate - deactivates the driver 1524 * @dev: mmc device handle 1525 * 1526 * Unmaps the register set and releases the IRQ resource. 1527 * 1528 * LOCKING: 1529 * None required 1530 * 1531 * RETURNS: 1532 * nothing 1533 */ 1534static void 1535ti_mmchs_deactivate(device_t dev) 1536{ 1537 struct ti_mmchs_softc *sc= device_get_softc(dev); 1538 1539 /* Remove the IRQ handler */ 1540 if (sc->sc_irq_h != NULL) { 1541 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); 1542 sc->sc_irq_h = NULL; 1543 } 1544 1545 /* Do the generic detach */ 1546 bus_generic_detach(sc->sc_dev); 1547 1548#ifdef SOC_TI_AM335X 1549 printf("%s: DMA unimplemented\n", __func__); 1550#else 1551 /* Deactivate the DMA channels */ 1552 ti_sdma_deactivate_channel(sc->sc_dmach_rd); 1553 ti_sdma_deactivate_channel(sc->sc_dmach_wr); 1554#endif 1555 1556 /* Unmap the MMC controller registers */ 1557 if (sc->sc_mem_res != 0) { 1558 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->sc_irq_res), 1559 sc->sc_mem_res); 1560 sc->sc_mem_res = NULL; 1561 } 1562 1563 /* Release the IRQ resource */ 1564 if (sc->sc_irq_res != NULL) { 1565 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->sc_irq_res), 1566 sc->sc_irq_res); 1567 sc->sc_irq_res = NULL; 1568 } 1569 1570 return; 1571} 1572 1573/** 1574 * ti_mmchs_activate - activates the driver 1575 * @dev: mmc device handle 1576 * 1577 * Maps in the register set and requests an IRQ handler for the MMC controller. 1578 * 1579 * LOCKING: 1580 * None required 1581 * 1582 * RETURNS: 1583 * 0 on sucess 1584 * ENOMEM if failed to map register set 1585 */ 1586static int 1587ti_mmchs_activate(device_t dev) 1588{ 1589 struct ti_mmchs_softc *sc = device_get_softc(dev); 1590 int rid; 1591 int err; 1592 1593 /* Get the memory resource for the register mapping */ 1594 rid = 0; 1595 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1596 RF_ACTIVE); 1597 if (sc->sc_mem_res == NULL) 1598 panic("%s: Cannot map registers", device_get_name(dev)); 1599 1600 /* Allocate an IRQ resource for the MMC controller */ 1601 rid = 0; 1602 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1603 RF_ACTIVE | RF_SHAREABLE); 1604 if (sc->sc_irq_res == NULL) 1605 goto errout; 1606 1607 /* Allocate DMA tags and maps */ 1608 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1609 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1610 NULL, MAXPHYS, 1, MAXPHYS, BUS_DMA_ALLOCNOW, NULL, 1611 NULL, &sc->sc_dmatag); 1612 if (err != 0) 1613 goto errout; 1614 1615 err = bus_dmamap_create(sc->sc_dmatag, 0, &sc->sc_dmamap); 1616 if (err != 0) 1617 goto errout; 1618 1619 /* Initialise the DMA channels to be used by the controller */ 1620 err = ti_mmchs_init_dma_channels(sc); 1621 if (err != 0) 1622 goto errout; 1623 1624 /* Set the register offset */ 1625 if (ti_chip() == CHIP_OMAP_3) 1626 sc->sc_reg_off = OMAP3_MMCHS_REG_OFFSET; 1627 else if (ti_chip() == CHIP_OMAP_4) 1628 sc->sc_reg_off = OMAP4_MMCHS_REG_OFFSET; 1629 else if (ti_chip() == CHIP_AM335X) 1630 sc->sc_reg_off = AM335X_MMCHS_REG_OFFSET; 1631 else 1632 panic("Unknown OMAP device\n"); 1633 1634 /* Get the physical address of the MMC data register, needed for DMA */ 1635 sc->sc_data_reg_paddr = BUS_SPACE_PHYSADDR(sc->sc_mem_res, 1636 sc->sc_reg_off + MMCHS_DATA); 1637 1638 /* Set the initial power state to off */ 1639 sc->sc_cur_power_mode = power_off; 1640 1641 return (0); 1642 1643errout: 1644 ti_mmchs_deactivate(dev); 1645 return (ENOMEM); 1646} 1647 1648/** 1649 * ti_mmchs_probe - probe function for the driver 1650 * @dev: mmc device handle 1651 * 1652 * 1653 * 1654 * RETURNS: 1655 * always returns 0 1656 */ 1657static int 1658ti_mmchs_probe(device_t dev) 1659{ 1660 if (!ofw_bus_is_compatible(dev, "ti,mmchs")) 1661 return (ENXIO); 1662 1663 device_set_desc(dev, "TI MMC/SD/SDIO High Speed Interface"); 1664 return (0); 1665} 1666 1667/** 1668 * ti_mmchs_attach - attach function for the driver 1669 * @dev: mmc device handle 1670 * 1671 * Driver initialisation, sets-up the bus mappings, DMA mapping/channels and 1672 * the actual controller by calling ti_mmchs_init(). 1673 * 1674 * RETURNS: 1675 * Returns 0 on success or a negative error code. 1676 */ 1677static int 1678ti_mmchs_attach(device_t dev) 1679{ 1680 struct ti_mmchs_softc *sc = device_get_softc(dev); 1681 int unit = device_get_unit(dev); 1682 phandle_t node; 1683 pcell_t did; 1684 int err; 1685 1686 /* Save the device and bus tag */ 1687 sc->sc_dev = dev; 1688 1689 /* Get the mmchs device id from FDT */ 1690 node = ofw_bus_get_node(dev); 1691 if ((OF_getprop(node, "mmchs-device-id", &did, sizeof(did))) <= 0) { 1692 device_printf(dev, "missing mmchs-device-id attribute in FDT\n"); 1693 return (ENXIO); 1694 } 1695 sc->device_id = fdt32_to_cpu(did); 1696 1697 /* Initiate the mtex lock */ 1698 TI_MMCHS_LOCK_INIT(sc); 1699 1700 /* Indicate the DMA channels haven't yet been allocated */ 1701 sc->sc_dmach_rd = (unsigned int)-1; 1702 sc->sc_dmach_wr = (unsigned int)-1; 1703 1704 /* Get the hint'ed write detect pin */ 1705 /* TODO: take this from FDT */ 1706 if (resource_int_value("ti_mmchs", unit, "wp_gpio", &sc->sc_wp_gpio_pin) != 0){ 1707 sc->sc_wp_gpio_pin = -1; 1708 } else { 1709 /* Get the GPIO device, we need this for the write protect pin */ 1710 sc->sc_gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 1711 if (sc->sc_gpio_dev == NULL) 1712 device_printf(dev, "Error: failed to get the GPIO device\n"); 1713 else 1714 GPIO_PIN_SETFLAGS(sc->sc_gpio_dev, sc->sc_wp_gpio_pin, 1715 GPIO_PIN_INPUT); 1716 } 1717 1718 /* Get the TWL voltage regulator device, we need this to for setting the 1719 * voltage of the bus on certain OMAP platforms. 1720 */ 1721 sc->sc_vreg_name = NULL; 1722 1723 /* TODO: add voltage regulator knob to FDT */ 1724#ifdef notyet 1725 sc->sc_vreg_dev = devclass_get_device(devclass_find("twl_vreg"), 0); 1726 if (sc->sc_vreg_dev == NULL) { 1727 device_printf(dev, "Error: failed to get the votlage regulator" 1728 " device\n"); 1729 sc->sc_vreg_name = NULL; 1730 } 1731#endif 1732 1733 /* Activate the device */ 1734 err = ti_mmchs_activate(dev); 1735 if (err) 1736 goto out; 1737 1738 /* Initialise the controller */ 1739 ti_mmchs_hw_init(dev); 1740 1741 /* Activate the interrupt and attach a handler */ 1742 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 1743 NULL, ti_mmchs_intr, sc, &sc->sc_irq_h); 1744 if (err != 0) 1745 goto out; 1746 1747 /* Add host details */ 1748 sc->host.f_min = sc->sc_ref_freq / 1023; 1749 sc->host.f_max = sc->sc_ref_freq; 1750 sc->host.host_ocr = MMC_OCR_290_300 | MMC_OCR_300_310; 1751 sc->host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 1752 1753 device_add_child(dev, "mmc", 0); 1754 1755 device_set_ivars(dev, &sc->host); 1756 err = bus_generic_attach(dev); 1757 1758out: 1759 if (err) { 1760 TI_MMCHS_LOCK_DESTROY(sc); 1761 ti_mmchs_deactivate(dev); 1762 1763#ifdef SOC_TI_AM335X 1764 printf("%s: DMA unimplemented\n", __func__); 1765#else 1766 if (sc->sc_dmach_rd != (unsigned int)-1) 1767 ti_sdma_deactivate_channel(sc->sc_dmach_rd); 1768 if (sc->sc_dmach_wr != (unsigned int)-1) 1769 ti_sdma_deactivate_channel(sc->sc_dmach_wr); 1770#endif 1771 } 1772 1773 return (err); 1774} 1775 1776/** 1777 * ti_mmchs_detach - dettach function for the driver 1778 * @dev: mmc device handle 1779 * 1780 * Shutdowns the controll and release resources allocated by the driver. 1781 * 1782 * RETURNS: 1783 * Always returns 0. 1784 */ 1785static int 1786ti_mmchs_detach(device_t dev) 1787{ 1788#ifndef SOC_TI_AM335X 1789 struct ti_mmchs_softc *sc = device_get_softc(dev); 1790#endif 1791 1792 ti_mmchs_hw_fini(dev); 1793 ti_mmchs_deactivate(dev); 1794 1795#ifdef SOC_TI_AM335X 1796 printf("%s: DMA unimplemented\n", __func__); 1797#else 1798 ti_sdma_deactivate_channel(sc->sc_dmach_wr); 1799 ti_sdma_deactivate_channel(sc->sc_dmach_rd); 1800#endif 1801 1802 return (0); 1803} 1804 1805static device_method_t ti_mmchs_methods[] = { 1806 /* device_if */ 1807 DEVMETHOD(device_probe, ti_mmchs_probe), 1808 DEVMETHOD(device_attach, ti_mmchs_attach), 1809 DEVMETHOD(device_detach, ti_mmchs_detach), 1810 1811 /* Bus interface */ 1812 DEVMETHOD(bus_read_ivar, ti_mmchs_read_ivar), 1813 DEVMETHOD(bus_write_ivar, ti_mmchs_write_ivar), 1814 1815 /* mmcbr_if - MMC state machine callbacks */ 1816 DEVMETHOD(mmcbr_update_ios, ti_mmchs_update_ios), 1817 DEVMETHOD(mmcbr_request, ti_mmchs_request), 1818 DEVMETHOD(mmcbr_get_ro, ti_mmchs_get_ro), 1819 DEVMETHOD(mmcbr_acquire_host, ti_mmchs_acquire_host), 1820 DEVMETHOD(mmcbr_release_host, ti_mmchs_release_host), 1821 1822 {0, 0}, 1823}; 1824 1825static driver_t ti_mmchs_driver = { 1826 "ti_mmchs", 1827 ti_mmchs_methods, 1828 sizeof(struct ti_mmchs_softc), 1829}; 1830static devclass_t ti_mmchs_devclass; 1831 1832DRIVER_MODULE(ti_mmchs, simplebus, ti_mmchs_driver, ti_mmchs_devclass, 0, 0); 1833MODULE_DEPEND(ti_mmchs, ti_prcm, 1, 1, 1); 1834#ifdef SOC_TI_AM335X 1835MODULE_DEPEND(ti_mmchs, ti_edma, 1, 1, 1); 1836#else 1837MODULE_DEPEND(ti_mmchs, ti_sdma, 1, 1, 1); 1838#endif 1839MODULE_DEPEND(ti_mmchs, ti_gpio, 1, 1, 1); 1840 1841/* FIXME: MODULE_DEPEND(ti_mmchs, twl_vreg, 1, 1, 1); */ 1842