1/*- 2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by Oleksandr Rybalko 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD$"); 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/kernel.h> 38#include <sys/module.h> 39#include <sys/resource.h> 40 41#include <machine/bus.h> 42#include <machine/resource.h> 43#include <sys/rman.h> 44 45#include <sys/lock.h> 46#include <sys/mutex.h> 47 48#include <dev/iicbus/iiconf.h> 49#include <dev/iicbus/iicbus.h> 50#include "iicbus_if.h" 51 52#include <dev/fdt/fdt_common.h> 53#include <dev/ofw/openfirm.h> 54#include <dev/ofw/ofw_bus.h> 55#include <dev/ofw/ofw_bus_subr.h> 56 57#define I2C_ADDR_REG 0x00 /* I2C slave address register */ 58#define I2C_FDR_REG 0x04 /* I2C frequency divider register */ 59#define I2C_CONTROL_REG 0x08 /* I2C control register */ 60#define I2C_STATUS_REG 0x0C /* I2C status register */ 61#define I2C_DATA_REG 0x10 /* I2C data register */ 62#define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ 63 64#define I2CCR_MEN (1 << 7) /* Module enable */ 65#define I2CCR_MSTA (1 << 5) /* Master/slave mode */ 66#define I2CCR_MTX (1 << 4) /* Transmit/receive mode */ 67#define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */ 68#define I2CCR_RSTA (1 << 2) /* Repeated START */ 69 70#define I2CSR_MCF (1 << 7) /* Data transfer */ 71#define I2CSR_MASS (1 << 6) /* Addressed as a slave */ 72#define I2CSR_MBB (1 << 5) /* Bus busy */ 73#define I2CSR_MAL (1 << 4) /* Arbitration lost */ 74#define I2CSR_SRW (1 << 2) /* Slave read/write */ 75#define I2CSR_MIF (1 << 1) /* Module interrupt */ 76#define I2CSR_RXAK (1 << 0) /* Received acknowledge */ 77 78#define I2C_BAUD_RATE_FAST 0x31 79#define I2C_BAUD_RATE_DEF 0x3F 80#define I2C_DFSSR_DIV 0x10 81 82#ifdef DEBUG 83#define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 84 printf(fmt,##args); } while (0) 85#else 86#define debugf(fmt, args...) 87#endif 88 89struct i2c_softc { 90 device_t dev; 91 device_t iicbus; 92 struct resource *res; 93 struct mtx mutex; 94 int rid; 95 bus_space_handle_t bsh; 96 bus_space_tag_t bst; 97}; 98 99static phandle_t i2c_get_node(device_t, device_t); 100static int i2c_probe(device_t); 101static int i2c_attach(device_t); 102 103static int i2c_repeated_start(device_t, u_char, int); 104static int i2c_start(device_t, u_char, int); 105static int i2c_stop(device_t); 106static int i2c_reset(device_t, u_char, u_char, u_char *); 107static int i2c_read(device_t, char *, int, int *, int, int); 108static int i2c_write(device_t, const char *, int, int *, int); 109 110static device_method_t i2c_methods[] = { 111 DEVMETHOD(device_probe, i2c_probe), 112 DEVMETHOD(device_attach, i2c_attach), 113 114 /* OFW methods */ 115 DEVMETHOD(ofw_bus_get_node, i2c_get_node), 116 117 DEVMETHOD(iicbus_callback, iicbus_null_callback), 118 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 119 DEVMETHOD(iicbus_start, i2c_start), 120 DEVMETHOD(iicbus_stop, i2c_stop), 121 DEVMETHOD(iicbus_reset, i2c_reset), 122 DEVMETHOD(iicbus_read, i2c_read), 123 DEVMETHOD(iicbus_write, i2c_write), 124 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 125 126 { 0, 0 } 127}; 128 129static driver_t i2c_driver = { 130 "iichb", 131 i2c_methods, 132 sizeof(struct i2c_softc), 133}; 134static devclass_t i2c_devclass; 135 136DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); 137DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); 138 139static phandle_t 140i2c_get_node(device_t bus, device_t dev) 141{ 142 /* 143 * Share controller node with iicbus device 144 */ 145 return ofw_bus_get_node(bus); 146} 147 148static __inline void 149i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) 150{ 151 152 bus_space_write_1(sc->bst, sc->bsh, off, val); 153} 154 155static __inline uint8_t 156i2c_read_reg(struct i2c_softc *sc, bus_size_t off) 157{ 158 159 return (bus_space_read_1(sc->bst, sc->bsh, off)); 160} 161 162static __inline void 163i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) 164{ 165 uint8_t status; 166 167 status = i2c_read_reg(sc, off); 168 status |= mask; 169 i2c_write_reg(sc, off, status); 170} 171 172/* Wait for transfer interrupt flag */ 173static int 174wait_for_iif(struct i2c_softc *sc) 175{ 176 int retry; 177 178 retry = 1000; 179 while (retry --) { 180 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MIF) 181 return (IIC_NOERR); 182 DELAY(10); 183 } 184 185 return (IIC_ETIMEOUT); 186} 187 188/* Wait for free bus */ 189static int 190wait_for_nibb(struct i2c_softc *sc) 191{ 192 int retry; 193 194 retry = 1000; 195 while (retry --) { 196 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) 197 return (IIC_NOERR); 198 DELAY(10); 199 } 200 201 return (IIC_ETIMEOUT); 202} 203 204/* Wait for transfer complete+interrupt flag */ 205static int 206wait_for_icf(struct i2c_softc *sc) 207{ 208 int retry; 209 210 retry = 1000; 211 while (retry --) { 212 213 if ((i2c_read_reg(sc, I2C_STATUS_REG) & 214 (I2CSR_MCF|I2CSR_MIF)) == (I2CSR_MCF|I2CSR_MIF)) 215 return (IIC_NOERR); 216 DELAY(10); 217 } 218 219 return (IIC_ETIMEOUT); 220} 221 222static int 223i2c_probe(device_t dev) 224{ 225 struct i2c_softc *sc; 226 227 if (!ofw_bus_is_compatible(dev, "fsl,imx-i2c")) 228 return (ENXIO); 229 230 sc = device_get_softc(dev); 231 sc->rid = 0; 232 233 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, 234 RF_ACTIVE); 235 if (sc->res == NULL) { 236 device_printf(dev, "could not allocate resources\n"); 237 return (ENXIO); 238 } 239 240 sc->bst = rman_get_bustag(sc->res); 241 sc->bsh = rman_get_bushandle(sc->res); 242 243 /* Enable I2C */ 244 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 245 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res); 246 device_set_desc(dev, "I2C bus controller"); 247 248 return (BUS_PROBE_DEFAULT); 249} 250 251static int 252i2c_attach(device_t dev) 253{ 254 struct i2c_softc *sc; 255 256 sc = device_get_softc(dev); 257 sc->dev = dev; 258 sc->rid = 0; 259 260 mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF); 261 262 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, 263 RF_ACTIVE); 264 if (sc->res == NULL) { 265 device_printf(dev, "could not allocate resources"); 266 mtx_destroy(&sc->mutex); 267 return (ENXIO); 268 } 269 270 sc->bst = rman_get_bustag(sc->res); 271 sc->bsh = rman_get_bushandle(sc->res); 272 273 sc->iicbus = device_add_child(dev, "iicbus", -1); 274 if (sc->iicbus == NULL) { 275 device_printf(dev, "could not add iicbus child"); 276 mtx_destroy(&sc->mutex); 277 return (ENXIO); 278 } 279 280 bus_generic_attach(dev); 281 return (IIC_NOERR); 282} 283 284static int 285i2c_repeated_start(device_t dev, u_char slave, int timeout) 286{ 287 struct i2c_softc *sc; 288 int error; 289 290 sc = device_get_softc(dev); 291 292 mtx_lock(&sc->mutex); 293 294 i2c_write_reg(sc, I2C_ADDR_REG, slave); 295 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) { 296 mtx_unlock(&sc->mutex); 297 return (IIC_EBUSBSY); 298 } 299 300 /* Set repeated start condition */ 301 DELAY(10); 302 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA); 303 DELAY(10); 304 /* Clear status */ 305 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 306 /* Write target address - LSB is R/W bit */ 307 i2c_write_reg(sc, I2C_DATA_REG, slave); 308 309 error = wait_for_iif(sc); 310 311 /* Clear status */ 312 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 313 314 mtx_unlock(&sc->mutex); 315 316 if (error) 317 return (error); 318 319 return (IIC_NOERR); 320} 321 322static int 323i2c_start(device_t dev, u_char slave, int timeout) 324{ 325 struct i2c_softc *sc; 326 int error; 327 328 sc = device_get_softc(dev); 329 330 mtx_lock(&sc->mutex); 331 i2c_write_reg(sc, I2C_ADDR_REG, slave); 332 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) { 333 mtx_unlock(&sc->mutex); 334 return (IIC_EBUSBSY); 335 } 336 337 /* Set start condition */ 338 i2c_write_reg(sc, I2C_CONTROL_REG, 339 I2CCR_MEN | I2CCR_MSTA | I2CCR_TXAK); 340 DELAY(100); 341 i2c_write_reg(sc, I2C_CONTROL_REG, 342 I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX | I2CCR_TXAK); 343 /* Clear status */ 344 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 345 /* Write target address - LSB is R/W bit */ 346 i2c_write_reg(sc, I2C_DATA_REG, slave); 347 348 error = wait_for_iif(sc); 349 350 mtx_unlock(&sc->mutex); 351 if (error) 352 return (error); 353 354 return (IIC_NOERR); 355} 356 357 358static int 359i2c_stop(device_t dev) 360{ 361 struct i2c_softc *sc; 362 363 sc = device_get_softc(dev); 364 mtx_lock(&sc->mutex); 365 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK); 366 DELAY(100); 367 /* Reset controller if bus still busy after STOP */ 368 if (wait_for_nibb(sc) == IIC_ETIMEOUT) { 369 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 370 DELAY(1000); 371 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK); 372 373 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 374 } 375 mtx_unlock(&sc->mutex); 376 377 return (IIC_NOERR); 378} 379 380static int 381i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 382{ 383 struct i2c_softc *sc; 384 uint8_t baud_rate; 385 386 sc = device_get_softc(dev); 387 388 switch (speed) { 389 case IIC_FAST: 390 baud_rate = I2C_BAUD_RATE_FAST; 391 break; 392 case IIC_SLOW: 393 case IIC_UNKNOWN: 394 case IIC_FASTEST: 395 default: 396 baud_rate = I2C_BAUD_RATE_DEF; 397 break; 398 } 399 400 mtx_lock(&sc->mutex); 401 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 402 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 403 DELAY(1000); 404 405 i2c_write_reg(sc, I2C_FDR_REG, 20); 406 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 407 DELAY(1000); 408 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 409 mtx_unlock(&sc->mutex); 410 411 return (IIC_NOERR); 412} 413 414static int 415i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 416{ 417 struct i2c_softc *sc; 418 int error, reg; 419 420 sc = device_get_softc(dev); 421 *read = 0; 422 423 mtx_lock(&sc->mutex); 424 425 if (len) { 426 if (len == 1) 427 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 428 I2CCR_MSTA | I2CCR_TXAK); 429 430 else 431 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 432 I2CCR_MSTA); 433 434 /* dummy read */ 435 i2c_read_reg(sc, I2C_DATA_REG); 436 DELAY(1000); 437 } 438 439 while (*read < len) { 440 error = wait_for_icf(sc); 441 if (error) { 442 mtx_unlock(&sc->mutex); 443 return (error); 444 } 445 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 446 if ((*read == len - 2) && last) { 447 /* NO ACK on last byte */ 448 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 449 I2CCR_MSTA | I2CCR_TXAK); 450 } 451 452 if ((*read == len - 1) && last) { 453 /* Transfer done, remove master bit */ 454 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 455 I2CCR_TXAK); 456 } 457 458 reg = i2c_read_reg(sc, I2C_DATA_REG); 459 *buf++ = reg; 460 (*read)++; 461 } 462 mtx_unlock(&sc->mutex); 463 464 return (IIC_NOERR); 465} 466 467static int 468i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 469{ 470 struct i2c_softc *sc; 471 int error; 472 473 sc = device_get_softc(dev); 474 *sent = 0; 475 476 mtx_lock(&sc->mutex); 477 while (*sent < len) { 478 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 479 i2c_write_reg(sc, I2C_DATA_REG, *buf++); 480 481 error = wait_for_iif(sc); 482 if (error) { 483 mtx_unlock(&sc->mutex); 484 return (error); 485 } 486 487 (*sent)++; 488 } 489 mtx_unlock(&sc->mutex); 490 491 return (IIC_NOERR); 492} 493