1/*-
2 * Copyright (c) KATO Takenori, 1997, 1998.
3 *
4 * All rights reserved.  Unpublished rights reserved under the copyright
5 * laws of Japan.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer as
13 *    the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD$");
32
33#include "opt_cpu.h"
34
35#include <sys/param.h>
36#include <sys/kernel.h>
37#include <sys/pcpu.h>
38#include <sys/systm.h>
39#include <sys/sysctl.h>
40
41#include <machine/cputypes.h>
42#include <machine/md_var.h>
43#include <machine/specialreg.h>
44
45#include <vm/vm.h>
46#include <vm/pmap.h>
47
48static int	hw_instruction_sse;
49SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
50    &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
51/*
52 * -1: automatic (default)
53 *  0: keep enable CLFLUSH
54 *  1: force disable CLFLUSH
55 */
56static int	hw_clflush_disable = -1;
57
58int	cpu;			/* Are we 386, 386sx, 486, etc? */
59u_int	cpu_feature;		/* Feature flags */
60u_int	cpu_feature2;		/* Feature flags */
61u_int	amd_feature;		/* AMD feature flags */
62u_int	amd_feature2;		/* AMD feature flags */
63u_int	amd_pminfo;		/* AMD advanced power management info */
64u_int	via_feature_rng;	/* VIA RNG features */
65u_int	via_feature_xcrypt;	/* VIA ACE features */
66u_int	cpu_high;		/* Highest arg to CPUID */
67u_int	cpu_exthigh;		/* Highest arg to extended CPUID */
68u_int	cpu_id;			/* Stepping ID */
69u_int	cpu_procinfo;		/* HyperThreading Info / Brand Index / CLFUSH */
70u_int	cpu_procinfo2;		/* Multicore info */
71char	cpu_vendor[20];		/* CPU Origin code */
72u_int	cpu_vendor_id;		/* CPU vendor ID */
73u_int	cpu_fxsr;		/* SSE enabled */
74u_int	cpu_mxcsr_mask;		/* Valid bits in mxcsr */
75u_int	cpu_clflush_line_size = 32;
76u_int	cpu_stdext_feature;
77u_int	cpu_max_ext_state_size;
78u_int	cpu_mon_mwait_flags;	/* MONITOR/MWAIT flags (CPUID.05H.ECX) */
79u_int	cpu_mon_min_size;	/* MONITOR minimum range size, bytes */
80u_int	cpu_mon_max_size;	/* MONITOR minimum range size, bytes */
81
82SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
83	&via_feature_rng, 0, "VIA RNG feature available in CPU");
84SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
85	&via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
86
87static void
88init_amd(void)
89{
90
91	/*
92	 * Work around Erratum 721 for Family 10h and 12h processors.
93	 * These processors may incorrectly update the stack pointer
94	 * after a long series of push and/or near-call instructions,
95	 * or a long series of pop and/or near-return instructions.
96	 *
97	 * http://support.amd.com/us/Processor_TechDocs/41322_10h_Rev_Gd.pdf
98	 * http://support.amd.com/us/Processor_TechDocs/44739_12h_Rev_Gd.pdf
99	 *
100	 * Hypervisors do not provide access to the errata MSR,
101	 * causing #GP exception on attempt to apply the errata.  The
102	 * MSR write shall be done on host and persist globally
103	 * anyway, so do not try to do it when under virtualization.
104	 */
105	switch (CPUID_TO_FAMILY(cpu_id)) {
106	case 0x10:
107	case 0x12:
108		if ((cpu_feature2 & CPUID2_HV) == 0)
109			wrmsr(0xc0011029, rdmsr(0xc0011029) | 1);
110		break;
111	}
112}
113
114/*
115 * Initialize special VIA features
116 */
117static void
118init_via(void)
119{
120	u_int regs[4], val;
121
122	/*
123	 * Check extended CPUID for PadLock features.
124	 *
125	 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
126	 */
127	do_cpuid(0xc0000000, regs);
128	if (regs[0] >= 0xc0000001) {
129		do_cpuid(0xc0000001, regs);
130		val = regs[3];
131	} else
132		return;
133
134	/* Enable RNG if present. */
135	if ((val & VIA_CPUID_HAS_RNG) != 0) {
136		via_feature_rng = VIA_HAS_RNG;
137		wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
138	}
139
140	/* Enable PadLock if present. */
141	if ((val & VIA_CPUID_HAS_ACE) != 0)
142		via_feature_xcrypt |= VIA_HAS_AES;
143	if ((val & VIA_CPUID_HAS_ACE2) != 0)
144		via_feature_xcrypt |= VIA_HAS_AESCTR;
145	if ((val & VIA_CPUID_HAS_PHE) != 0)
146		via_feature_xcrypt |= VIA_HAS_SHA;
147	if ((val & VIA_CPUID_HAS_PMM) != 0)
148		via_feature_xcrypt |= VIA_HAS_MM;
149	if (via_feature_xcrypt != 0)
150		wrmsr(0x1107, rdmsr(0x1107) | (1 << 28));
151}
152
153/*
154 * Initialize CPU control registers
155 */
156void
157initializecpu(void)
158{
159	uint64_t msr;
160	uint32_t cr4;
161
162	cr4 = rcr4();
163	if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
164		cr4 |= CR4_FXSR | CR4_XMM;
165		cpu_fxsr = hw_instruction_sse = 1;
166	}
167	if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE)
168		cr4 |= CR4_FSGSBASE;
169
170	/*
171	 * Postpone enabling the SMEP on the boot CPU until the page
172	 * tables are switched from the boot loader identity mapping
173	 * to the kernel tables.  The boot loader enables the U bit in
174	 * its tables.
175	 */
176	if (!IS_BSP() && (cpu_stdext_feature & CPUID_STDEXT_SMEP))
177		cr4 |= CR4_SMEP;
178	load_cr4(cr4);
179	if ((amd_feature & AMDID_NX) != 0) {
180		msr = rdmsr(MSR_EFER) | EFER_NXE;
181		wrmsr(MSR_EFER, msr);
182		pg_nx = PG_NX;
183	}
184	switch (cpu_vendor_id) {
185	case CPU_VENDOR_AMD:
186		init_amd();
187		break;
188	case CPU_VENDOR_CENTAUR:
189		init_via();
190		break;
191	}
192}
193
194void
195initializecpucache(void)
196{
197
198	/*
199	 * CPUID with %eax = 1, %ebx returns
200	 * Bits 15-8: CLFLUSH line size
201	 * 	(Value * 8 = cache line size in bytes)
202	 */
203	if ((cpu_feature & CPUID_CLFSH) != 0)
204		cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
205	/*
206	 * XXXKIB: (temporary) hack to work around traps generated
207	 * when CLFLUSHing APIC register window under virtualization
208	 * environments.  These environments tend to disable the
209	 * CPUID_SS feature even though the native CPU supports it.
210	 */
211	TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
212	if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1)
213		cpu_feature &= ~CPUID_CLFSH;
214	/*
215	 * Allow to disable CLFLUSH feature manually by
216	 * hw.clflush_disable tunable.
217	 */
218	if (hw_clflush_disable == 1)
219		cpu_feature &= ~CPUID_CLFSH;
220}
221