1//===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements a simple VLIW packetizer using DFA. The packetizer works on
11// machine basic blocks. For each instruction I in BB, the packetizer consults
12// the DFA to see if machine resources are available to execute I. If so, the
13// packetizer checks if I depends on any instruction J in the current packet.
14// If no dependency is found, I is added to current packet and machine resource
15// is marked as taken. If any dependency is found, a target API call is made to
16// prune the dependence.
17//
18//===----------------------------------------------------------------------===//
19#define DEBUG_TYPE "packets"
20#include "llvm/CodeGen/DFAPacketizer.h"
21#include "llvm/CodeGen/Passes.h"
22#include "llvm/CodeGen/MachineDominators.h"
23#include "llvm/CodeGen/MachineFunctionPass.h"
24#include "llvm/CodeGen/MachineLoopInfo.h"
25#include "llvm/CodeGen/ScheduleDAG.h"
26#include "llvm/CodeGen/ScheduleDAGInstrs.h"
27#include "llvm/CodeGen/LatencyPriorityQueue.h"
28#include "llvm/CodeGen/SchedulerRegistry.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/MachineFunctionAnalysis.h"
33#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetRegisterInfo.h"
37#include "llvm/ADT/DenseMap.h"
38#include "llvm/ADT/Statistic.h"
39#include "llvm/Support/MathExtras.h"
40#include "llvm/MC/MCInstrItineraries.h"
41#include "llvm/Support/Compiler.h"
42#include "llvm/Support/CommandLine.h"
43#include "llvm/Support/Debug.h"
44#include "Hexagon.h"
45#include "HexagonTargetMachine.h"
46#include "HexagonRegisterInfo.h"
47#include "HexagonSubtarget.h"
48#include "HexagonMachineFunctionInfo.h"
49
50#include <map>
51#include <vector>
52
53using namespace llvm;
54
55static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
56      cl::ZeroOrMore, cl::Hidden, cl::init(true),
57      cl::desc("Allow non-solo packetization of volatile memory references"));
58
59namespace llvm {
60  void initializeHexagonPacketizerPass(PassRegistry&);
61}
62
63
64namespace {
65  class HexagonPacketizer : public MachineFunctionPass {
66
67  public:
68    static char ID;
69    HexagonPacketizer() : MachineFunctionPass(ID) {
70      initializeHexagonPacketizerPass(*PassRegistry::getPassRegistry());
71    }
72
73    void getAnalysisUsage(AnalysisUsage &AU) const {
74      AU.setPreservesCFG();
75      AU.addRequired<MachineDominatorTree>();
76      AU.addRequired<MachineBranchProbabilityInfo>();
77      AU.addPreserved<MachineDominatorTree>();
78      AU.addRequired<MachineLoopInfo>();
79      AU.addPreserved<MachineLoopInfo>();
80      MachineFunctionPass::getAnalysisUsage(AU);
81    }
82
83    const char *getPassName() const {
84      return "Hexagon Packetizer";
85    }
86
87    bool runOnMachineFunction(MachineFunction &Fn);
88  };
89  char HexagonPacketizer::ID = 0;
90
91  class HexagonPacketizerList : public VLIWPacketizerList {
92
93  private:
94
95    // Has the instruction been promoted to a dot-new instruction.
96    bool PromotedToDotNew;
97
98    // Has the instruction been glued to allocframe.
99    bool GlueAllocframeStore;
100
101    // Has the feeder instruction been glued to new value jump.
102    bool GlueToNewValueJump;
103
104    // Check if there is a dependence between some instruction already in this
105    // packet and this instruction.
106    bool Dependence;
107
108    // Only check for dependence if there are resources available to
109    // schedule this instruction.
110    bool FoundSequentialDependence;
111
112    /// \brief A handle to the branch probability pass.
113   const MachineBranchProbabilityInfo *MBPI;
114
115   // Track MIs with ignored dependece.
116   std::vector<MachineInstr*> IgnoreDepMIs;
117
118  public:
119    // Ctor.
120    HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
121                          MachineDominatorTree &MDT,
122                          const MachineBranchProbabilityInfo *MBPI);
123
124    // initPacketizerState - initialize some internal flags.
125    void initPacketizerState();
126
127    // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
128    bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
129
130    // isSoloInstruction - return true if instruction MI can not be packetized
131    // with any other instruction, which means that MI itself is a packet.
132    bool isSoloInstruction(MachineInstr *MI);
133
134    // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
135    // together.
136    bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);
137
138    // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
139    // and SUJ.
140    bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);
141
142    MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
143  private:
144    bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
145    bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
146                         MachineBasicBlock::iterator &MII,
147                         const TargetRegisterClass* RC);
148    bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
149                            unsigned DepReg,
150                            std::map <MachineInstr*, SUnit*> MIToSUnit,
151                            MachineBasicBlock::iterator &MII,
152                            const TargetRegisterClass* RC);
153    bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
154                              unsigned DepReg,
155                              std::map <MachineInstr*, SUnit*> MIToSUnit,
156                              MachineBasicBlock::iterator &MII);
157    bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
158                                   unsigned DepReg,
159                                   std::map <MachineInstr*, SUnit*> MIToSUnit);
160    bool DemoteToDotOld(MachineInstr* MI);
161    bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
162                    std::map <MachineInstr*, SUnit*> MIToSUnit);
163    bool RestrictingDepExistInPacket(MachineInstr*,
164                    unsigned, std::map <MachineInstr*, SUnit*>);
165    bool isNewifiable(MachineInstr* MI);
166    bool isCondInst(MachineInstr* MI);
167    bool IsNewifyStore (MachineInstr* MI);
168    bool tryAllocateResourcesForConstExt(MachineInstr* MI);
169    bool canReserveResourcesForConstExt(MachineInstr *MI);
170    void reserveResourcesForConstExt(MachineInstr* MI);
171    bool isNewValueInst(MachineInstr* MI);
172  };
173}
174
175INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
176                      false, false)
177INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
178INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
179INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
180INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
181INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
182                    false, false)
183
184
185// HexagonPacketizerList Ctor.
186HexagonPacketizerList::HexagonPacketizerList(
187  MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT,
188  const MachineBranchProbabilityInfo *MBPI)
189  : VLIWPacketizerList(MF, MLI, MDT, true){
190  this->MBPI = MBPI;
191}
192
193bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
194  const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
195  MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
196  MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
197  const MachineBranchProbabilityInfo *MBPI =
198    &getAnalysis<MachineBranchProbabilityInfo>();
199  // Instantiate the packetizer.
200  HexagonPacketizerList Packetizer(Fn, MLI, MDT, MBPI);
201
202  // DFA state table should not be empty.
203  assert(Packetizer.getResourceTracker() && "Empty DFA table!");
204
205  //
206  // Loop over all basic blocks and remove KILL pseudo-instructions
207  // These instructions confuse the dependence analysis. Consider:
208  // D0 = ...   (Insn 0)
209  // R0 = KILL R0, D0 (Insn 1)
210  // R0 = ... (Insn 2)
211  // Here, Insn 1 will result in the dependence graph not emitting an output
212  // dependence between Insn 0 and Insn 2. This can lead to incorrect
213  // packetization
214  //
215  for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
216       MBB != MBBe; ++MBB) {
217    MachineBasicBlock::iterator End = MBB->end();
218    MachineBasicBlock::iterator MI = MBB->begin();
219    while (MI != End) {
220      if (MI->isKill()) {
221        MachineBasicBlock::iterator DeleteMI = MI;
222        ++MI;
223        MBB->erase(DeleteMI);
224        End = MBB->end();
225        continue;
226      }
227      ++MI;
228    }
229  }
230
231  // Loop over all of the basic blocks.
232  for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
233       MBB != MBBe; ++MBB) {
234    // Find scheduling regions and schedule / packetize each region.
235    unsigned RemainingCount = MBB->size();
236    for(MachineBasicBlock::iterator RegionEnd = MBB->end();
237        RegionEnd != MBB->begin();) {
238      // The next region starts above the previous region. Look backward in the
239      // instruction stream until we find the nearest boundary.
240      MachineBasicBlock::iterator I = RegionEnd;
241      for(;I != MBB->begin(); --I, --RemainingCount) {
242        if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
243          break;
244      }
245      I = MBB->begin();
246
247      // Skip empty scheduling regions.
248      if (I == RegionEnd) {
249        RegionEnd = llvm::prior(RegionEnd);
250        --RemainingCount;
251        continue;
252      }
253      // Skip regions with one instruction.
254      if (I == llvm::prior(RegionEnd)) {
255        RegionEnd = llvm::prior(RegionEnd);
256        continue;
257      }
258
259      Packetizer.PacketizeMIs(MBB, I, RegionEnd);
260      RegionEnd = I;
261    }
262  }
263
264  return true;
265}
266
267
268static bool IsIndirectCall(MachineInstr* MI) {
269  return ((MI->getOpcode() == Hexagon::CALLR) ||
270          (MI->getOpcode() == Hexagon::CALLRv3));
271}
272
273// Reserve resources for constant extender. Trigure an assertion if
274// reservation fail.
275void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
276  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
277  MachineFunction *MF = MI->getParent()->getParent();
278  MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
279                                                  MI->getDebugLoc());
280
281  if (ResourceTracker->canReserveResources(PseudoMI)) {
282    ResourceTracker->reserveResources(PseudoMI);
283    MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
284  } else {
285    MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
286    llvm_unreachable("can not reserve resources for constant extender.");
287  }
288  return;
289}
290
291bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
292  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
293  assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
294         "Should only be called for constant extended instructions");
295  MachineFunction *MF = MI->getParent()->getParent();
296  MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
297                                                  MI->getDebugLoc());
298  bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
299  MF->DeleteMachineInstr(PseudoMI);
300  return CanReserve;
301}
302
303// Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
304// true, otherwise, return false.
305bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
306  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
307  MachineFunction *MF = MI->getParent()->getParent();
308  MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
309                                                  MI->getDebugLoc());
310
311  if (ResourceTracker->canReserveResources(PseudoMI)) {
312    ResourceTracker->reserveResources(PseudoMI);
313    MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
314    return true;
315  } else {
316    MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
317    return false;
318  }
319}
320
321
322bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
323                                          SDep::Kind DepType,
324                                          unsigned DepReg) {
325
326  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
327  const HexagonRegisterInfo* QRI =
328              (const HexagonRegisterInfo *) TM.getRegisterInfo();
329
330  // Check for lr dependence
331  if (DepReg == QRI->getRARegister()) {
332    return true;
333  }
334
335  if (QII->isDeallocRet(MI)) {
336    if (DepReg == QRI->getFrameRegister() ||
337        DepReg == QRI->getStackRegister())
338      return true;
339  }
340
341  // Check if this is a predicate dependence
342  const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
343  if (RC == &Hexagon::PredRegsRegClass) {
344    return true;
345  }
346
347  //
348  // Lastly check for an operand used in an indirect call
349  // If we had an attribute for checking if an instruction is an indirect call,
350  // then we could have avoided this relatively brittle implementation of
351  // IsIndirectCall()
352  //
353  // Assumes that the first operand of the CALLr is the function address
354  //
355  if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
356    MachineOperand MO = MI->getOperand(0);
357    if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
358      return true;
359    }
360  }
361
362  return false;
363}
364
365static bool IsRegDependence(const SDep::Kind DepType) {
366  return (DepType == SDep::Data || DepType == SDep::Anti ||
367          DepType == SDep::Output);
368}
369
370static bool IsDirectJump(MachineInstr* MI) {
371  return (MI->getOpcode() == Hexagon::JMP);
372}
373
374static bool IsSchedBarrier(MachineInstr* MI) {
375  switch (MI->getOpcode()) {
376  case Hexagon::BARRIER:
377    return true;
378  }
379  return false;
380}
381
382static bool IsControlFlow(MachineInstr* MI) {
383  return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
384}
385
386// Function returns true if an instruction can be promoted to the new-value
387// store. It will always return false for v2 and v3.
388// It lists all the conditional and unconditional stores that can be promoted
389// to the new-value stores.
390
391bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
392  const HexagonRegisterInfo* QRI =
393                          (const HexagonRegisterInfo *) TM.getRegisterInfo();
394  switch (MI->getOpcode())
395  {
396    // store byte
397    case Hexagon::STrib:
398    case Hexagon::STrib_indexed:
399    case Hexagon::STrib_indexed_shl_V4:
400    case Hexagon::STrib_shl_V4:
401    case Hexagon::STb_GP_V4:
402    case Hexagon::POST_STbri:
403    case Hexagon::STrib_cPt:
404    case Hexagon::STrib_cdnPt_V4:
405    case Hexagon::STrib_cNotPt:
406    case Hexagon::STrib_cdnNotPt_V4:
407    case Hexagon::STrib_indexed_cPt:
408    case Hexagon::STrib_indexed_cdnPt_V4:
409    case Hexagon::STrib_indexed_cNotPt:
410    case Hexagon::STrib_indexed_cdnNotPt_V4:
411    case Hexagon::STrib_indexed_shl_cPt_V4:
412    case Hexagon::STrib_indexed_shl_cdnPt_V4:
413    case Hexagon::STrib_indexed_shl_cNotPt_V4:
414    case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
415    case Hexagon::POST_STbri_cPt:
416    case Hexagon::POST_STbri_cdnPt_V4:
417    case Hexagon::POST_STbri_cNotPt:
418    case Hexagon::POST_STbri_cdnNotPt_V4:
419    case Hexagon::STb_GP_cPt_V4:
420    case Hexagon::STb_GP_cNotPt_V4:
421    case Hexagon::STb_GP_cdnPt_V4:
422    case Hexagon::STb_GP_cdnNotPt_V4:
423
424    // store halfword
425    case Hexagon::STrih:
426    case Hexagon::STrih_indexed:
427    case Hexagon::STrih_indexed_shl_V4:
428    case Hexagon::STrih_shl_V4:
429    case Hexagon::STh_GP_V4:
430    case Hexagon::POST_SThri:
431    case Hexagon::STrih_cPt:
432    case Hexagon::STrih_cdnPt_V4:
433    case Hexagon::STrih_cNotPt:
434    case Hexagon::STrih_cdnNotPt_V4:
435    case Hexagon::STrih_indexed_cPt:
436    case Hexagon::STrih_indexed_cdnPt_V4:
437    case Hexagon::STrih_indexed_cNotPt:
438    case Hexagon::STrih_indexed_cdnNotPt_V4:
439    case Hexagon::STrih_indexed_shl_cPt_V4:
440    case Hexagon::STrih_indexed_shl_cdnPt_V4:
441    case Hexagon::STrih_indexed_shl_cNotPt_V4:
442    case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
443    case Hexagon::POST_SThri_cPt:
444    case Hexagon::POST_SThri_cdnPt_V4:
445    case Hexagon::POST_SThri_cNotPt:
446    case Hexagon::POST_SThri_cdnNotPt_V4:
447    case Hexagon::STh_GP_cPt_V4:
448    case Hexagon::STh_GP_cNotPt_V4:
449    case Hexagon::STh_GP_cdnPt_V4:
450    case Hexagon::STh_GP_cdnNotPt_V4:
451
452    // store word
453    case Hexagon::STriw:
454    case Hexagon::STriw_indexed:
455    case Hexagon::STriw_indexed_shl_V4:
456    case Hexagon::STriw_shl_V4:
457    case Hexagon::STw_GP_V4:
458    case Hexagon::POST_STwri:
459    case Hexagon::STriw_cPt:
460    case Hexagon::STriw_cdnPt_V4:
461    case Hexagon::STriw_cNotPt:
462    case Hexagon::STriw_cdnNotPt_V4:
463    case Hexagon::STriw_indexed_cPt:
464    case Hexagon::STriw_indexed_cdnPt_V4:
465    case Hexagon::STriw_indexed_cNotPt:
466    case Hexagon::STriw_indexed_cdnNotPt_V4:
467    case Hexagon::STriw_indexed_shl_cPt_V4:
468    case Hexagon::STriw_indexed_shl_cdnPt_V4:
469    case Hexagon::STriw_indexed_shl_cNotPt_V4:
470    case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
471    case Hexagon::POST_STwri_cPt:
472    case Hexagon::POST_STwri_cdnPt_V4:
473    case Hexagon::POST_STwri_cNotPt:
474    case Hexagon::POST_STwri_cdnNotPt_V4:
475    case Hexagon::STw_GP_cPt_V4:
476    case Hexagon::STw_GP_cNotPt_V4:
477    case Hexagon::STw_GP_cdnPt_V4:
478    case Hexagon::STw_GP_cdnNotPt_V4:
479        return QRI->Subtarget.hasV4TOps();
480  }
481  return false;
482}
483
484static bool IsLoopN(MachineInstr *MI) {
485  return (MI->getOpcode() == Hexagon::LOOP0_i ||
486          MI->getOpcode() == Hexagon::LOOP0_r);
487}
488
489/// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
490/// callee-saved register.
491static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
492                                     const TargetRegisterInfo *TRI) {
493  for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
494    unsigned CalleeSavedReg = *CSR;
495    if (MI->modifiesRegister(CalleeSavedReg, TRI))
496      return true;
497  }
498  return false;
499}
500
501// Return the new value instruction for a given store.
502static int GetDotNewOp(const int opc) {
503  switch (opc) {
504  default: llvm_unreachable("Unknown .new type");
505  // store new value byte
506  case Hexagon::STrib:
507    return Hexagon::STrib_nv_V4;
508
509  case Hexagon::STrib_indexed:
510    return Hexagon::STrib_indexed_nv_V4;
511
512  case Hexagon::STrib_indexed_shl_V4:
513    return Hexagon::STrib_indexed_shl_nv_V4;
514
515  case Hexagon::STrib_shl_V4:
516    return Hexagon::STrib_shl_nv_V4;
517
518  case Hexagon::STb_GP_V4:
519    return Hexagon::STb_GP_nv_V4;
520
521  case Hexagon::POST_STbri:
522    return Hexagon::POST_STbri_nv_V4;
523
524  case Hexagon::STrib_cPt:
525    return Hexagon::STrib_cPt_nv_V4;
526
527  case Hexagon::STrib_cdnPt_V4:
528    return Hexagon::STrib_cdnPt_nv_V4;
529
530  case Hexagon::STrib_cNotPt:
531    return Hexagon::STrib_cNotPt_nv_V4;
532
533  case Hexagon::STrib_cdnNotPt_V4:
534    return Hexagon::STrib_cdnNotPt_nv_V4;
535
536  case Hexagon::STrib_indexed_cPt:
537    return Hexagon::STrib_indexed_cPt_nv_V4;
538
539  case Hexagon::STrib_indexed_cdnPt_V4:
540    return Hexagon::STrib_indexed_cdnPt_nv_V4;
541
542  case Hexagon::STrib_indexed_cNotPt:
543    return Hexagon::STrib_indexed_cNotPt_nv_V4;
544
545  case Hexagon::STrib_indexed_cdnNotPt_V4:
546    return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
547
548  case Hexagon::STrib_indexed_shl_cPt_V4:
549    return Hexagon::STrib_indexed_shl_cPt_nv_V4;
550
551  case Hexagon::STrib_indexed_shl_cdnPt_V4:
552    return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
553
554  case Hexagon::STrib_indexed_shl_cNotPt_V4:
555    return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;
556
557  case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
558    return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
559
560  case Hexagon::POST_STbri_cPt:
561    return Hexagon::POST_STbri_cPt_nv_V4;
562
563  case Hexagon::POST_STbri_cdnPt_V4:
564    return Hexagon::POST_STbri_cdnPt_nv_V4;
565
566  case Hexagon::POST_STbri_cNotPt:
567    return Hexagon::POST_STbri_cNotPt_nv_V4;
568
569  case Hexagon::POST_STbri_cdnNotPt_V4:
570    return Hexagon::POST_STbri_cdnNotPt_nv_V4;
571
572  case Hexagon::STb_GP_cPt_V4:
573    return Hexagon::STb_GP_cPt_nv_V4;
574
575  case Hexagon::STb_GP_cNotPt_V4:
576    return Hexagon::STb_GP_cNotPt_nv_V4;
577
578  case Hexagon::STb_GP_cdnPt_V4:
579    return Hexagon::STb_GP_cdnPt_nv_V4;
580
581  case Hexagon::STb_GP_cdnNotPt_V4:
582    return Hexagon::STb_GP_cdnNotPt_nv_V4;
583
584  // store new value halfword
585  case Hexagon::STrih:
586    return Hexagon::STrih_nv_V4;
587
588  case Hexagon::STrih_indexed:
589    return Hexagon::STrih_indexed_nv_V4;
590
591  case Hexagon::STrih_indexed_shl_V4:
592    return Hexagon::STrih_indexed_shl_nv_V4;
593
594  case Hexagon::STrih_shl_V4:
595    return Hexagon::STrih_shl_nv_V4;
596
597  case Hexagon::STh_GP_V4:
598    return Hexagon::STh_GP_nv_V4;
599
600  case Hexagon::POST_SThri:
601    return Hexagon::POST_SThri_nv_V4;
602
603  case Hexagon::STrih_cPt:
604    return Hexagon::STrih_cPt_nv_V4;
605
606  case Hexagon::STrih_cdnPt_V4:
607    return Hexagon::STrih_cdnPt_nv_V4;
608
609  case Hexagon::STrih_cNotPt:
610    return Hexagon::STrih_cNotPt_nv_V4;
611
612  case Hexagon::STrih_cdnNotPt_V4:
613    return Hexagon::STrih_cdnNotPt_nv_V4;
614
615  case Hexagon::STrih_indexed_cPt:
616    return Hexagon::STrih_indexed_cPt_nv_V4;
617
618  case Hexagon::STrih_indexed_cdnPt_V4:
619    return Hexagon::STrih_indexed_cdnPt_nv_V4;
620
621  case Hexagon::STrih_indexed_cNotPt:
622    return Hexagon::STrih_indexed_cNotPt_nv_V4;
623
624  case Hexagon::STrih_indexed_cdnNotPt_V4:
625    return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
626
627  case Hexagon::STrih_indexed_shl_cPt_V4:
628    return Hexagon::STrih_indexed_shl_cPt_nv_V4;
629
630  case Hexagon::STrih_indexed_shl_cdnPt_V4:
631    return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
632
633  case Hexagon::STrih_indexed_shl_cNotPt_V4:
634    return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;
635
636  case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
637    return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
638
639  case Hexagon::POST_SThri_cPt:
640    return Hexagon::POST_SThri_cPt_nv_V4;
641
642  case Hexagon::POST_SThri_cdnPt_V4:
643    return Hexagon::POST_SThri_cdnPt_nv_V4;
644
645  case Hexagon::POST_SThri_cNotPt:
646    return Hexagon::POST_SThri_cNotPt_nv_V4;
647
648  case Hexagon::POST_SThri_cdnNotPt_V4:
649    return Hexagon::POST_SThri_cdnNotPt_nv_V4;
650
651  case Hexagon::STh_GP_cPt_V4:
652    return Hexagon::STh_GP_cPt_nv_V4;
653
654  case Hexagon::STh_GP_cNotPt_V4:
655    return Hexagon::STh_GP_cNotPt_nv_V4;
656
657  case Hexagon::STh_GP_cdnPt_V4:
658    return Hexagon::STh_GP_cdnPt_nv_V4;
659
660  case Hexagon::STh_GP_cdnNotPt_V4:
661    return Hexagon::STh_GP_cdnNotPt_nv_V4;
662
663  // store new value word
664  case Hexagon::STriw:
665    return Hexagon::STriw_nv_V4;
666
667  case Hexagon::STriw_indexed:
668    return Hexagon::STriw_indexed_nv_V4;
669
670  case Hexagon::STriw_indexed_shl_V4:
671    return Hexagon::STriw_indexed_shl_nv_V4;
672
673  case Hexagon::STriw_shl_V4:
674    return Hexagon::STriw_shl_nv_V4;
675
676  case Hexagon::STw_GP_V4:
677    return Hexagon::STw_GP_nv_V4;
678
679  case Hexagon::POST_STwri:
680    return Hexagon::POST_STwri_nv_V4;
681
682  case Hexagon::STriw_cPt:
683    return Hexagon::STriw_cPt_nv_V4;
684
685  case Hexagon::STriw_cdnPt_V4:
686    return Hexagon::STriw_cdnPt_nv_V4;
687
688  case Hexagon::STriw_cNotPt:
689    return Hexagon::STriw_cNotPt_nv_V4;
690
691  case Hexagon::STriw_cdnNotPt_V4:
692    return Hexagon::STriw_cdnNotPt_nv_V4;
693
694  case Hexagon::STriw_indexed_cPt:
695    return Hexagon::STriw_indexed_cPt_nv_V4;
696
697  case Hexagon::STriw_indexed_cdnPt_V4:
698    return Hexagon::STriw_indexed_cdnPt_nv_V4;
699
700  case Hexagon::STriw_indexed_cNotPt:
701    return Hexagon::STriw_indexed_cNotPt_nv_V4;
702
703  case Hexagon::STriw_indexed_cdnNotPt_V4:
704    return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
705
706  case Hexagon::STriw_indexed_shl_cPt_V4:
707    return Hexagon::STriw_indexed_shl_cPt_nv_V4;
708
709  case Hexagon::STriw_indexed_shl_cdnPt_V4:
710    return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
711
712  case Hexagon::STriw_indexed_shl_cNotPt_V4:
713    return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;
714
715  case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
716    return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
717
718  case Hexagon::POST_STwri_cPt:
719    return Hexagon::POST_STwri_cPt_nv_V4;
720
721  case Hexagon::POST_STwri_cdnPt_V4:
722    return Hexagon::POST_STwri_cdnPt_nv_V4;
723
724  case Hexagon::POST_STwri_cNotPt:
725    return Hexagon::POST_STwri_cNotPt_nv_V4;
726
727  case Hexagon::POST_STwri_cdnNotPt_V4:
728    return Hexagon::POST_STwri_cdnNotPt_nv_V4;
729
730  case Hexagon::STw_GP_cPt_V4:
731    return Hexagon::STw_GP_cPt_nv_V4;
732
733  case Hexagon::STw_GP_cNotPt_V4:
734    return Hexagon::STw_GP_cNotPt_nv_V4;
735
736  case Hexagon::STw_GP_cdnPt_V4:
737    return Hexagon::STw_GP_cdnPt_nv_V4;
738
739  case Hexagon::STw_GP_cdnNotPt_V4:
740    return Hexagon::STw_GP_cdnNotPt_nv_V4;
741
742  }
743}
744
745// Return .new predicate version for an instruction
746static int GetDotNewPredOp(MachineInstr *MI,
747                           const MachineBranchProbabilityInfo *MBPI,
748                           const HexagonInstrInfo *QII) {
749  switch (MI->getOpcode()) {
750  default: llvm_unreachable("Unknown .new type");
751  // Conditional stores
752  // Store byte conditionally
753  case Hexagon::STrib_cPt :
754    return Hexagon::STrib_cdnPt_V4;
755
756  case Hexagon::STrib_cNotPt :
757    return Hexagon::STrib_cdnNotPt_V4;
758
759  case Hexagon::STrib_indexed_cPt :
760    return Hexagon::STrib_indexed_cdnPt_V4;
761
762  case Hexagon::STrib_indexed_cNotPt :
763    return Hexagon::STrib_indexed_cdnNotPt_V4;
764
765  case Hexagon::STrib_imm_cPt_V4 :
766    return Hexagon::STrib_imm_cdnPt_V4;
767
768  case Hexagon::STrib_imm_cNotPt_V4 :
769    return Hexagon::STrib_imm_cdnNotPt_V4;
770
771  case Hexagon::POST_STbri_cPt :
772    return Hexagon::POST_STbri_cdnPt_V4;
773
774  case Hexagon::POST_STbri_cNotPt :
775    return Hexagon::POST_STbri_cdnNotPt_V4;
776
777  case Hexagon::STrib_indexed_shl_cPt_V4 :
778    return Hexagon::STrib_indexed_shl_cdnPt_V4;
779
780  case Hexagon::STrib_indexed_shl_cNotPt_V4 :
781    return Hexagon::STrib_indexed_shl_cdnNotPt_V4;
782
783  case Hexagon::STb_GP_cPt_V4 :
784    return Hexagon::STb_GP_cdnPt_V4;
785
786  case Hexagon::STb_GP_cNotPt_V4 :
787    return Hexagon::STb_GP_cdnNotPt_V4;
788
789  // Store doubleword conditionally
790  case Hexagon::STrid_cPt :
791    return Hexagon::STrid_cdnPt_V4;
792
793  case Hexagon::STrid_cNotPt :
794    return Hexagon::STrid_cdnNotPt_V4;
795
796  case Hexagon::STrid_indexed_cPt :
797    return Hexagon::STrid_indexed_cdnPt_V4;
798
799  case Hexagon::STrid_indexed_cNotPt :
800    return Hexagon::STrid_indexed_cdnNotPt_V4;
801
802  case Hexagon::STrid_indexed_shl_cPt_V4 :
803    return Hexagon::STrid_indexed_shl_cdnPt_V4;
804
805  case Hexagon::STrid_indexed_shl_cNotPt_V4 :
806    return Hexagon::STrid_indexed_shl_cdnNotPt_V4;
807
808  case Hexagon::POST_STdri_cPt :
809    return Hexagon::POST_STdri_cdnPt_V4;
810
811  case Hexagon::POST_STdri_cNotPt :
812    return Hexagon::POST_STdri_cdnNotPt_V4;
813
814  case Hexagon::STd_GP_cPt_V4 :
815    return Hexagon::STd_GP_cdnPt_V4;
816
817  case Hexagon::STd_GP_cNotPt_V4 :
818    return Hexagon::STd_GP_cdnNotPt_V4;
819
820  // Store halfword conditionally
821  case Hexagon::STrih_cPt :
822    return Hexagon::STrih_cdnPt_V4;
823
824  case Hexagon::STrih_cNotPt :
825    return Hexagon::STrih_cdnNotPt_V4;
826
827  case Hexagon::STrih_indexed_cPt :
828    return Hexagon::STrih_indexed_cdnPt_V4;
829
830  case Hexagon::STrih_indexed_cNotPt :
831    return Hexagon::STrih_indexed_cdnNotPt_V4;
832
833  case Hexagon::STrih_imm_cPt_V4 :
834    return Hexagon::STrih_imm_cdnPt_V4;
835
836  case Hexagon::STrih_imm_cNotPt_V4 :
837    return Hexagon::STrih_imm_cdnNotPt_V4;
838
839  case Hexagon::STrih_indexed_shl_cPt_V4 :
840    return Hexagon::STrih_indexed_shl_cdnPt_V4;
841
842  case Hexagon::STrih_indexed_shl_cNotPt_V4 :
843    return Hexagon::STrih_indexed_shl_cdnNotPt_V4;
844
845  case Hexagon::POST_SThri_cPt :
846    return Hexagon::POST_SThri_cdnPt_V4;
847
848  case Hexagon::POST_SThri_cNotPt :
849    return Hexagon::POST_SThri_cdnNotPt_V4;
850
851  case Hexagon::STh_GP_cPt_V4 :
852    return Hexagon::STh_GP_cdnPt_V4;
853
854  case Hexagon::STh_GP_cNotPt_V4 :
855    return Hexagon::STh_GP_cdnNotPt_V4;
856
857  // Store word conditionally
858  case Hexagon::STriw_cPt :
859    return Hexagon::STriw_cdnPt_V4;
860
861  case Hexagon::STriw_cNotPt :
862    return Hexagon::STriw_cdnNotPt_V4;
863
864  case Hexagon::STriw_indexed_cPt :
865    return Hexagon::STriw_indexed_cdnPt_V4;
866
867  case Hexagon::STriw_indexed_cNotPt :
868    return Hexagon::STriw_indexed_cdnNotPt_V4;
869
870  case Hexagon::STriw_imm_cPt_V4 :
871    return Hexagon::STriw_imm_cdnPt_V4;
872
873  case Hexagon::STriw_imm_cNotPt_V4 :
874    return Hexagon::STriw_imm_cdnNotPt_V4;
875
876  case Hexagon::STriw_indexed_shl_cPt_V4 :
877    return Hexagon::STriw_indexed_shl_cdnPt_V4;
878
879  case Hexagon::STriw_indexed_shl_cNotPt_V4 :
880    return Hexagon::STriw_indexed_shl_cdnNotPt_V4;
881
882  case Hexagon::POST_STwri_cPt :
883    return Hexagon::POST_STwri_cdnPt_V4;
884
885  case Hexagon::POST_STwri_cNotPt :
886    return Hexagon::POST_STwri_cdnNotPt_V4;
887
888  case Hexagon::STw_GP_cPt_V4 :
889    return Hexagon::STw_GP_cdnPt_V4;
890
891  case Hexagon::STw_GP_cNotPt_V4 :
892    return Hexagon::STw_GP_cdnNotPt_V4;
893
894  // Condtional Jumps
895  case Hexagon::JMP_t:
896  case Hexagon::JMP_f:
897    return QII->getDotNewPredJumpOp(MI, MBPI);
898
899  case Hexagon::JMPR_t:
900    return Hexagon::JMPR_tnew_tV3;
901
902  case Hexagon::JMPR_f:
903    return Hexagon::JMPR_fnew_tV3;
904
905  // Conditional Transfers
906  case Hexagon::TFR_cPt:
907    return Hexagon::TFR_cdnPt;
908
909  case Hexagon::TFR_cNotPt:
910    return Hexagon::TFR_cdnNotPt;
911
912  case Hexagon::TFRI_cPt:
913    return Hexagon::TFRI_cdnPt;
914
915  case Hexagon::TFRI_cNotPt:
916    return Hexagon::TFRI_cdnNotPt;
917
918  // Load double word
919  case Hexagon::LDrid_cPt :
920    return Hexagon::LDrid_cdnPt;
921
922  case Hexagon::LDrid_cNotPt :
923    return Hexagon::LDrid_cdnNotPt;
924
925  case Hexagon::LDrid_indexed_cPt :
926    return Hexagon::LDrid_indexed_cdnPt;
927
928  case Hexagon::LDrid_indexed_cNotPt :
929    return Hexagon::LDrid_indexed_cdnNotPt;
930
931  case Hexagon::POST_LDrid_cPt :
932    return Hexagon::POST_LDrid_cdnPt_V4;
933
934  case Hexagon::POST_LDrid_cNotPt :
935    return Hexagon::POST_LDrid_cdnNotPt_V4;
936
937  // Load word
938  case Hexagon::LDriw_cPt :
939    return Hexagon::LDriw_cdnPt;
940
941  case Hexagon::LDriw_cNotPt :
942    return Hexagon::LDriw_cdnNotPt;
943
944  case Hexagon::LDriw_indexed_cPt :
945    return Hexagon::LDriw_indexed_cdnPt;
946
947  case Hexagon::LDriw_indexed_cNotPt :
948    return Hexagon::LDriw_indexed_cdnNotPt;
949
950  case Hexagon::POST_LDriw_cPt :
951    return Hexagon::POST_LDriw_cdnPt_V4;
952
953  case Hexagon::POST_LDriw_cNotPt :
954    return Hexagon::POST_LDriw_cdnNotPt_V4;
955
956  // Load halfword
957  case Hexagon::LDrih_cPt :
958    return Hexagon::LDrih_cdnPt;
959
960  case Hexagon::LDrih_cNotPt :
961    return Hexagon::LDrih_cdnNotPt;
962
963  case Hexagon::LDrih_indexed_cPt :
964    return Hexagon::LDrih_indexed_cdnPt;
965
966  case Hexagon::LDrih_indexed_cNotPt :
967    return Hexagon::LDrih_indexed_cdnNotPt;
968
969  case Hexagon::POST_LDrih_cPt :
970    return Hexagon::POST_LDrih_cdnPt_V4;
971
972  case Hexagon::POST_LDrih_cNotPt :
973    return Hexagon::POST_LDrih_cdnNotPt_V4;
974
975  // Load byte
976  case Hexagon::LDrib_cPt :
977    return Hexagon::LDrib_cdnPt;
978
979  case Hexagon::LDrib_cNotPt :
980    return Hexagon::LDrib_cdnNotPt;
981
982  case Hexagon::LDrib_indexed_cPt :
983    return Hexagon::LDrib_indexed_cdnPt;
984
985  case Hexagon::LDrib_indexed_cNotPt :
986    return Hexagon::LDrib_indexed_cdnNotPt;
987
988  case Hexagon::POST_LDrib_cPt :
989    return Hexagon::POST_LDrib_cdnPt_V4;
990
991  case Hexagon::POST_LDrib_cNotPt :
992    return Hexagon::POST_LDrib_cdnNotPt_V4;
993
994  // Load unsigned halfword
995  case Hexagon::LDriuh_cPt :
996    return Hexagon::LDriuh_cdnPt;
997
998  case Hexagon::LDriuh_cNotPt :
999    return Hexagon::LDriuh_cdnNotPt;
1000
1001  case Hexagon::LDriuh_indexed_cPt :
1002    return Hexagon::LDriuh_indexed_cdnPt;
1003
1004  case Hexagon::LDriuh_indexed_cNotPt :
1005    return Hexagon::LDriuh_indexed_cdnNotPt;
1006
1007  case Hexagon::POST_LDriuh_cPt :
1008    return Hexagon::POST_LDriuh_cdnPt_V4;
1009
1010  case Hexagon::POST_LDriuh_cNotPt :
1011    return Hexagon::POST_LDriuh_cdnNotPt_V4;
1012
1013  // Load unsigned byte
1014  case Hexagon::LDriub_cPt :
1015    return Hexagon::LDriub_cdnPt;
1016
1017  case Hexagon::LDriub_cNotPt :
1018    return Hexagon::LDriub_cdnNotPt;
1019
1020  case Hexagon::LDriub_indexed_cPt :
1021    return Hexagon::LDriub_indexed_cdnPt;
1022
1023  case Hexagon::LDriub_indexed_cNotPt :
1024    return Hexagon::LDriub_indexed_cdnNotPt;
1025
1026  case Hexagon::POST_LDriub_cPt :
1027    return Hexagon::POST_LDriub_cdnPt_V4;
1028
1029  case Hexagon::POST_LDriub_cNotPt :
1030    return Hexagon::POST_LDriub_cdnNotPt_V4;
1031
1032  // V4 indexed+scaled load
1033
1034  case Hexagon::LDrid_indexed_shl_cPt_V4 :
1035    return Hexagon::LDrid_indexed_shl_cdnPt_V4;
1036
1037  case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1038    return Hexagon::LDrid_indexed_shl_cdnNotPt_V4;
1039
1040  case Hexagon::LDrib_indexed_shl_cPt_V4 :
1041    return Hexagon::LDrib_indexed_shl_cdnPt_V4;
1042
1043  case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1044    return Hexagon::LDrib_indexed_shl_cdnNotPt_V4;
1045
1046  case Hexagon::LDriub_indexed_shl_cPt_V4 :
1047    return Hexagon::LDriub_indexed_shl_cdnPt_V4;
1048
1049  case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1050    return Hexagon::LDriub_indexed_shl_cdnNotPt_V4;
1051
1052  case Hexagon::LDrih_indexed_shl_cPt_V4 :
1053    return Hexagon::LDrih_indexed_shl_cdnPt_V4;
1054
1055  case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1056    return Hexagon::LDrih_indexed_shl_cdnNotPt_V4;
1057
1058  case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1059    return Hexagon::LDriuh_indexed_shl_cdnPt_V4;
1060
1061  case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1062    return Hexagon::LDriuh_indexed_shl_cdnNotPt_V4;
1063
1064  case Hexagon::LDriw_indexed_shl_cPt_V4 :
1065    return Hexagon::LDriw_indexed_shl_cdnPt_V4;
1066
1067  case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1068    return Hexagon::LDriw_indexed_shl_cdnNotPt_V4;
1069
1070  // V4 global address load
1071
1072  case Hexagon::LDd_GP_cPt_V4:
1073    return Hexagon::LDd_GP_cdnPt_V4;
1074
1075  case Hexagon::LDd_GP_cNotPt_V4:
1076    return Hexagon::LDd_GP_cdnNotPt_V4;
1077
1078  case Hexagon::LDb_GP_cPt_V4:
1079    return Hexagon::LDb_GP_cdnPt_V4;
1080
1081  case Hexagon::LDb_GP_cNotPt_V4:
1082    return Hexagon::LDb_GP_cdnNotPt_V4;
1083
1084  case Hexagon::LDub_GP_cPt_V4:
1085    return Hexagon::LDub_GP_cdnPt_V4;
1086
1087  case Hexagon::LDub_GP_cNotPt_V4:
1088    return Hexagon::LDub_GP_cdnNotPt_V4;
1089
1090  case Hexagon::LDh_GP_cPt_V4:
1091    return Hexagon::LDh_GP_cdnPt_V4;
1092
1093  case Hexagon::LDh_GP_cNotPt_V4:
1094    return Hexagon::LDh_GP_cdnNotPt_V4;
1095
1096  case Hexagon::LDuh_GP_cPt_V4:
1097    return Hexagon::LDuh_GP_cdnPt_V4;
1098
1099  case Hexagon::LDuh_GP_cNotPt_V4:
1100    return Hexagon::LDuh_GP_cdnNotPt_V4;
1101
1102  case Hexagon::LDw_GP_cPt_V4:
1103    return Hexagon::LDw_GP_cdnPt_V4;
1104
1105  case Hexagon::LDw_GP_cNotPt_V4:
1106    return Hexagon::LDw_GP_cdnNotPt_V4;
1107
1108  // Conditional store new-value byte
1109  case Hexagon::STrib_cPt_nv_V4 :
1110    return Hexagon::STrib_cdnPt_nv_V4;
1111  case Hexagon::STrib_cNotPt_nv_V4 :
1112    return Hexagon::STrib_cdnNotPt_nv_V4;
1113
1114  case Hexagon::STrib_indexed_cPt_nv_V4 :
1115    return Hexagon::STrib_indexed_cdnPt_nv_V4;
1116  case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1117    return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
1118
1119  case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1120    return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
1121  case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1122    return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
1123
1124  case Hexagon::POST_STbri_cPt_nv_V4 :
1125    return Hexagon::POST_STbri_cdnPt_nv_V4;
1126  case Hexagon::POST_STbri_cNotPt_nv_V4 :
1127    return Hexagon::POST_STbri_cdnNotPt_nv_V4;
1128
1129  case Hexagon::STb_GP_cPt_nv_V4 :
1130    return Hexagon::STb_GP_cdnPt_nv_V4;
1131
1132  case Hexagon::STb_GP_cNotPt_nv_V4 :
1133    return Hexagon::STb_GP_cdnNotPt_nv_V4;
1134
1135  // Conditional store new-value halfword
1136  case Hexagon::STrih_cPt_nv_V4 :
1137    return Hexagon::STrih_cdnPt_nv_V4;
1138  case Hexagon::STrih_cNotPt_nv_V4 :
1139    return Hexagon::STrih_cdnNotPt_nv_V4;
1140
1141  case Hexagon::STrih_indexed_cPt_nv_V4 :
1142    return Hexagon::STrih_indexed_cdnPt_nv_V4;
1143  case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1144    return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
1145
1146  case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1147    return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
1148  case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1149    return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
1150
1151  case Hexagon::POST_SThri_cPt_nv_V4 :
1152    return Hexagon::POST_SThri_cdnPt_nv_V4;
1153  case Hexagon::POST_SThri_cNotPt_nv_V4 :
1154    return Hexagon::POST_SThri_cdnNotPt_nv_V4;
1155
1156  case Hexagon::STh_GP_cPt_nv_V4 :
1157    return Hexagon::STh_GP_cdnPt_nv_V4;
1158
1159  case Hexagon::STh_GP_cNotPt_nv_V4 :
1160    return Hexagon::STh_GP_cdnNotPt_nv_V4;
1161
1162  // Conditional store new-value word
1163  case Hexagon::STriw_cPt_nv_V4 :
1164    return  Hexagon::STriw_cdnPt_nv_V4;
1165  case Hexagon::STriw_cNotPt_nv_V4 :
1166    return Hexagon::STriw_cdnNotPt_nv_V4;
1167
1168  case Hexagon::STriw_indexed_cPt_nv_V4 :
1169    return Hexagon::STriw_indexed_cdnPt_nv_V4;
1170  case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1171    return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
1172
1173  case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1174    return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
1175  case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1176    return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
1177
1178  case Hexagon::POST_STwri_cPt_nv_V4 :
1179    return Hexagon::POST_STwri_cdnPt_nv_V4;
1180  case Hexagon::POST_STwri_cNotPt_nv_V4:
1181    return Hexagon::POST_STwri_cdnNotPt_nv_V4;
1182
1183  case Hexagon::STw_GP_cPt_nv_V4 :
1184    return Hexagon::STw_GP_cdnPt_nv_V4;
1185
1186  case Hexagon::STw_GP_cNotPt_nv_V4 :
1187    return Hexagon::STw_GP_cdnNotPt_nv_V4;
1188
1189  // Conditional add
1190  case Hexagon::ADD_ri_cPt :
1191    return Hexagon::ADD_ri_cdnPt;
1192  case Hexagon::ADD_ri_cNotPt :
1193    return Hexagon::ADD_ri_cdnNotPt;
1194
1195  case Hexagon::ADD_rr_cPt :
1196    return Hexagon::ADD_rr_cdnPt;
1197  case Hexagon::ADD_rr_cNotPt :
1198    return Hexagon::ADD_rr_cdnNotPt;
1199
1200  // Conditional logical Operations
1201  case Hexagon::XOR_rr_cPt :
1202    return Hexagon::XOR_rr_cdnPt;
1203  case Hexagon::XOR_rr_cNotPt :
1204    return Hexagon::XOR_rr_cdnNotPt;
1205
1206  case Hexagon::AND_rr_cPt :
1207    return Hexagon::AND_rr_cdnPt;
1208  case Hexagon::AND_rr_cNotPt :
1209    return Hexagon::AND_rr_cdnNotPt;
1210
1211  case Hexagon::OR_rr_cPt :
1212    return Hexagon::OR_rr_cdnPt;
1213  case Hexagon::OR_rr_cNotPt :
1214    return Hexagon::OR_rr_cdnNotPt;
1215
1216  // Conditional Subtract
1217  case Hexagon::SUB_rr_cPt :
1218    return Hexagon::SUB_rr_cdnPt;
1219  case Hexagon::SUB_rr_cNotPt :
1220    return Hexagon::SUB_rr_cdnNotPt;
1221
1222  // Conditional combine
1223  case Hexagon::COMBINE_rr_cPt :
1224    return Hexagon::COMBINE_rr_cdnPt;
1225  case Hexagon::COMBINE_rr_cNotPt :
1226    return Hexagon::COMBINE_rr_cdnNotPt;
1227
1228  case Hexagon::ASLH_cPt_V4 :
1229    return Hexagon::ASLH_cdnPt_V4;
1230  case Hexagon::ASLH_cNotPt_V4 :
1231    return Hexagon::ASLH_cdnNotPt_V4;
1232
1233  case Hexagon::ASRH_cPt_V4 :
1234    return Hexagon::ASRH_cdnPt_V4;
1235  case Hexagon::ASRH_cNotPt_V4 :
1236    return Hexagon::ASRH_cdnNotPt_V4;
1237
1238  case Hexagon::SXTB_cPt_V4 :
1239    return Hexagon::SXTB_cdnPt_V4;
1240  case Hexagon::SXTB_cNotPt_V4 :
1241    return Hexagon::SXTB_cdnNotPt_V4;
1242
1243  case Hexagon::SXTH_cPt_V4 :
1244    return Hexagon::SXTH_cdnPt_V4;
1245  case Hexagon::SXTH_cNotPt_V4 :
1246    return Hexagon::SXTH_cdnNotPt_V4;
1247
1248  case Hexagon::ZXTB_cPt_V4 :
1249    return Hexagon::ZXTB_cdnPt_V4;
1250  case Hexagon::ZXTB_cNotPt_V4 :
1251    return Hexagon::ZXTB_cdnNotPt_V4;
1252
1253  case Hexagon::ZXTH_cPt_V4 :
1254    return Hexagon::ZXTH_cdnPt_V4;
1255  case Hexagon::ZXTH_cNotPt_V4 :
1256    return Hexagon::ZXTH_cdnNotPt_V4;
1257  }
1258}
1259
1260// Returns true if an instruction can be promoted to .new predicate
1261// or new-value store.
1262bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
1263  if ( isCondInst(MI) || IsNewifyStore(MI))
1264    return true;
1265  else
1266    return false;
1267}
1268
1269bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
1270  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1271  const MCInstrDesc& TID = MI->getDesc();
1272                                    // bug 5670: until that is fixed,
1273                                    // this portion is disabled.
1274  if (   TID.isConditionalBranch()  // && !IsRegisterJump(MI)) ||
1275      || QII->isConditionalTransfer(MI)
1276      || QII->isConditionalALU32(MI)
1277      || QII->isConditionalLoad(MI)
1278      || QII->isConditionalStore(MI)) {
1279    return true;
1280  }
1281  return false;
1282}
1283
1284
1285// Promote an instructiont to its .new form.
1286// At this time, we have already made a call to CanPromoteToDotNew
1287// and made sure that it can *indeed* be promoted.
1288bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
1289                        SDep::Kind DepType, MachineBasicBlock::iterator &MII,
1290                        const TargetRegisterClass* RC) {
1291
1292  assert (DepType == SDep::Data);
1293  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1294
1295  int NewOpcode;
1296  if (RC == &Hexagon::PredRegsRegClass)
1297    NewOpcode = GetDotNewPredOp(MI, MBPI, QII);
1298  else
1299    NewOpcode = GetDotNewOp(MI->getOpcode());
1300  MI->setDesc(QII->get(NewOpcode));
1301
1302  return true;
1303}
1304
1305// Returns the most basic instruction for the .new predicated instructions and
1306// new-value stores.
1307// For example, all of the following instructions will be converted back to the
1308// same instruction:
1309// 1) if (p0.new) memw(R0+#0) = R1.new  --->
1310// 2) if (p0) memw(R0+#0)= R1.new      -------> if (p0) memw(R0+#0) = R1
1311// 3) if (p0.new) memw(R0+#0) = R1      --->
1312//
1313// To understand the translation of instruction 1 to its original form, consider
1314// a packet with 3 instructions.
1315// { p0 = cmp.eq(R0,R1)
1316//   if (p0.new) R2 = add(R3, R4)
1317//   R5 = add (R3, R1)
1318//   }
1319// if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
1320//
1321// This instruction can be part of the previous packet only if both p0 and R2
1322// are promoted to .new values. This promotion happens in steps, first
1323// predicate register is promoted to .new and in the next iteration R2 is
1324// promoted. Therefore, in case of dependence check failure (due to R5) during
1325// next iteration, it should be converted back to its most basic form.
1326
1327static int GetDotOldOp(const int opc) {
1328  switch (opc) {
1329  default: llvm_unreachable("Unknown .old type");
1330  case Hexagon::TFR_cdnPt:
1331    return Hexagon::TFR_cPt;
1332
1333  case Hexagon::TFR_cdnNotPt:
1334    return Hexagon::TFR_cNotPt;
1335
1336  case Hexagon::TFRI_cdnPt:
1337    return Hexagon::TFRI_cPt;
1338
1339  case Hexagon::TFRI_cdnNotPt:
1340    return Hexagon::TFRI_cNotPt;
1341
1342  case Hexagon::JMP_tnew_t:
1343    return Hexagon::JMP_t;
1344
1345  case Hexagon::JMP_fnew_t:
1346    return Hexagon::JMP_f;
1347
1348  case Hexagon::JMPR_tnew_tV3:
1349    return Hexagon::JMPR_t;
1350
1351  case Hexagon::JMPR_fnew_tV3:
1352    return Hexagon::JMPR_f;
1353
1354  // Load double word
1355
1356  case Hexagon::LDrid_cdnPt :
1357    return Hexagon::LDrid_cPt;
1358
1359  case Hexagon::LDrid_cdnNotPt :
1360    return Hexagon::LDrid_cNotPt;
1361
1362  case Hexagon::LDrid_indexed_cdnPt :
1363    return Hexagon::LDrid_indexed_cPt;
1364
1365  case Hexagon::LDrid_indexed_cdnNotPt :
1366    return Hexagon::LDrid_indexed_cNotPt;
1367
1368  case Hexagon::POST_LDrid_cdnPt_V4 :
1369    return Hexagon::POST_LDrid_cPt;
1370
1371  case Hexagon::POST_LDrid_cdnNotPt_V4 :
1372    return Hexagon::POST_LDrid_cNotPt;
1373
1374  // Load word
1375
1376  case Hexagon::LDriw_cdnPt :
1377    return Hexagon::LDriw_cPt;
1378
1379  case Hexagon::LDriw_cdnNotPt :
1380    return Hexagon::LDriw_cNotPt;
1381
1382  case Hexagon::LDriw_indexed_cdnPt :
1383    return Hexagon::LDriw_indexed_cPt;
1384
1385  case Hexagon::LDriw_indexed_cdnNotPt :
1386    return Hexagon::LDriw_indexed_cNotPt;
1387
1388  case Hexagon::POST_LDriw_cdnPt_V4 :
1389    return Hexagon::POST_LDriw_cPt;
1390
1391  case Hexagon::POST_LDriw_cdnNotPt_V4 :
1392    return Hexagon::POST_LDriw_cNotPt;
1393
1394  // Load half
1395
1396  case Hexagon::LDrih_cdnPt :
1397    return Hexagon::LDrih_cPt;
1398
1399  case Hexagon::LDrih_cdnNotPt :
1400    return Hexagon::LDrih_cNotPt;
1401
1402  case Hexagon::LDrih_indexed_cdnPt :
1403    return Hexagon::LDrih_indexed_cPt;
1404
1405  case Hexagon::LDrih_indexed_cdnNotPt :
1406    return Hexagon::LDrih_indexed_cNotPt;
1407
1408  case Hexagon::POST_LDrih_cdnPt_V4 :
1409    return Hexagon::POST_LDrih_cPt;
1410
1411  case Hexagon::POST_LDrih_cdnNotPt_V4 :
1412    return Hexagon::POST_LDrih_cNotPt;
1413
1414  // Load byte
1415
1416  case Hexagon::LDrib_cdnPt :
1417    return Hexagon::LDrib_cPt;
1418
1419  case Hexagon::LDrib_cdnNotPt :
1420    return Hexagon::LDrib_cNotPt;
1421
1422  case Hexagon::LDrib_indexed_cdnPt :
1423    return Hexagon::LDrib_indexed_cPt;
1424
1425  case Hexagon::LDrib_indexed_cdnNotPt :
1426    return Hexagon::LDrib_indexed_cNotPt;
1427
1428  case Hexagon::POST_LDrib_cdnPt_V4 :
1429    return Hexagon::POST_LDrib_cPt;
1430
1431  case Hexagon::POST_LDrib_cdnNotPt_V4 :
1432    return Hexagon::POST_LDrib_cNotPt;
1433
1434  // Load unsigned half
1435
1436  case Hexagon::LDriuh_cdnPt :
1437    return Hexagon::LDriuh_cPt;
1438
1439  case Hexagon::LDriuh_cdnNotPt :
1440    return Hexagon::LDriuh_cNotPt;
1441
1442  case Hexagon::LDriuh_indexed_cdnPt :
1443    return Hexagon::LDriuh_indexed_cPt;
1444
1445  case Hexagon::LDriuh_indexed_cdnNotPt :
1446    return Hexagon::LDriuh_indexed_cNotPt;
1447
1448  case Hexagon::POST_LDriuh_cdnPt_V4 :
1449    return Hexagon::POST_LDriuh_cPt;
1450
1451  case Hexagon::POST_LDriuh_cdnNotPt_V4 :
1452    return Hexagon::POST_LDriuh_cNotPt;
1453
1454  // Load unsigned byte
1455  case Hexagon::LDriub_cdnPt :
1456    return Hexagon::LDriub_cPt;
1457
1458  case Hexagon::LDriub_cdnNotPt :
1459    return Hexagon::LDriub_cNotPt;
1460
1461  case Hexagon::LDriub_indexed_cdnPt :
1462    return Hexagon::LDriub_indexed_cPt;
1463
1464  case Hexagon::LDriub_indexed_cdnNotPt :
1465    return Hexagon::LDriub_indexed_cNotPt;
1466
1467  case Hexagon::POST_LDriub_cdnPt_V4 :
1468    return Hexagon::POST_LDriub_cPt;
1469
1470  case Hexagon::POST_LDriub_cdnNotPt_V4 :
1471    return Hexagon::POST_LDriub_cNotPt;
1472
1473  // V4 indexed+scaled Load
1474
1475  case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1476    return Hexagon::LDrid_indexed_shl_cPt_V4;
1477
1478  case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
1479    return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1480
1481  case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1482    return Hexagon::LDrib_indexed_shl_cPt_V4;
1483
1484  case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
1485    return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1486
1487  case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1488    return Hexagon::LDriub_indexed_shl_cPt_V4;
1489
1490  case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
1491    return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1492
1493  case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1494    return Hexagon::LDrih_indexed_shl_cPt_V4;
1495
1496  case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
1497    return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1498
1499  case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1500    return Hexagon::LDriuh_indexed_shl_cPt_V4;
1501
1502  case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
1503    return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1504
1505  case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1506    return Hexagon::LDriw_indexed_shl_cPt_V4;
1507
1508  case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
1509    return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1510
1511  // V4 global address load
1512
1513  case Hexagon::LDd_GP_cdnPt_V4:
1514    return Hexagon::LDd_GP_cPt_V4;
1515
1516  case Hexagon::LDd_GP_cdnNotPt_V4:
1517    return Hexagon::LDd_GP_cNotPt_V4;
1518
1519  case Hexagon::LDb_GP_cdnPt_V4:
1520    return Hexagon::LDb_GP_cPt_V4;
1521
1522  case Hexagon::LDb_GP_cdnNotPt_V4:
1523    return Hexagon::LDb_GP_cNotPt_V4;
1524
1525  case Hexagon::LDub_GP_cdnPt_V4:
1526    return Hexagon::LDub_GP_cPt_V4;
1527
1528  case Hexagon::LDub_GP_cdnNotPt_V4:
1529    return Hexagon::LDub_GP_cNotPt_V4;
1530
1531  case Hexagon::LDh_GP_cdnPt_V4:
1532    return Hexagon::LDh_GP_cPt_V4;
1533
1534  case Hexagon::LDh_GP_cdnNotPt_V4:
1535    return Hexagon::LDh_GP_cNotPt_V4;
1536
1537  case Hexagon::LDuh_GP_cdnPt_V4:
1538    return Hexagon::LDuh_GP_cPt_V4;
1539
1540  case Hexagon::LDuh_GP_cdnNotPt_V4:
1541    return Hexagon::LDuh_GP_cNotPt_V4;
1542
1543  case Hexagon::LDw_GP_cdnPt_V4:
1544    return Hexagon::LDw_GP_cPt_V4;
1545
1546  case Hexagon::LDw_GP_cdnNotPt_V4:
1547    return Hexagon::LDw_GP_cNotPt_V4;
1548
1549  // Conditional add
1550
1551  case Hexagon::ADD_ri_cdnPt :
1552    return Hexagon::ADD_ri_cPt;
1553  case Hexagon::ADD_ri_cdnNotPt :
1554    return Hexagon::ADD_ri_cNotPt;
1555
1556  case Hexagon::ADD_rr_cdnPt :
1557    return Hexagon::ADD_rr_cPt;
1558  case Hexagon::ADD_rr_cdnNotPt:
1559    return Hexagon::ADD_rr_cNotPt;
1560
1561  // Conditional logical Operations
1562
1563  case Hexagon::XOR_rr_cdnPt :
1564    return Hexagon::XOR_rr_cPt;
1565  case Hexagon::XOR_rr_cdnNotPt :
1566    return Hexagon::XOR_rr_cNotPt;
1567
1568  case Hexagon::AND_rr_cdnPt :
1569    return Hexagon::AND_rr_cPt;
1570  case Hexagon::AND_rr_cdnNotPt :
1571    return Hexagon::AND_rr_cNotPt;
1572
1573  case Hexagon::OR_rr_cdnPt :
1574    return Hexagon::OR_rr_cPt;
1575  case Hexagon::OR_rr_cdnNotPt :
1576    return Hexagon::OR_rr_cNotPt;
1577
1578  // Conditional Subtract
1579
1580  case Hexagon::SUB_rr_cdnPt :
1581    return Hexagon::SUB_rr_cPt;
1582  case Hexagon::SUB_rr_cdnNotPt :
1583    return Hexagon::SUB_rr_cNotPt;
1584
1585  // Conditional combine
1586
1587  case Hexagon::COMBINE_rr_cdnPt :
1588    return Hexagon::COMBINE_rr_cPt;
1589  case Hexagon::COMBINE_rr_cdnNotPt :
1590    return Hexagon::COMBINE_rr_cNotPt;
1591
1592// Conditional shift operations
1593
1594  case Hexagon::ASLH_cdnPt_V4 :
1595    return Hexagon::ASLH_cPt_V4;
1596  case Hexagon::ASLH_cdnNotPt_V4 :
1597    return Hexagon::ASLH_cNotPt_V4;
1598
1599  case Hexagon::ASRH_cdnPt_V4 :
1600    return Hexagon::ASRH_cPt_V4;
1601  case Hexagon::ASRH_cdnNotPt_V4 :
1602    return Hexagon::ASRH_cNotPt_V4;
1603
1604  case Hexagon::SXTB_cdnPt_V4 :
1605    return Hexagon::SXTB_cPt_V4;
1606  case Hexagon::SXTB_cdnNotPt_V4 :
1607    return Hexagon::SXTB_cNotPt_V4;
1608
1609  case Hexagon::SXTH_cdnPt_V4 :
1610    return Hexagon::SXTH_cPt_V4;
1611  case Hexagon::SXTH_cdnNotPt_V4 :
1612    return Hexagon::SXTH_cNotPt_V4;
1613
1614  case Hexagon::ZXTB_cdnPt_V4 :
1615    return Hexagon::ZXTB_cPt_V4;
1616  case Hexagon::ZXTB_cdnNotPt_V4 :
1617    return Hexagon::ZXTB_cNotPt_V4;
1618
1619  case Hexagon::ZXTH_cdnPt_V4 :
1620    return Hexagon::ZXTH_cPt_V4;
1621  case Hexagon::ZXTH_cdnNotPt_V4 :
1622    return Hexagon::ZXTH_cNotPt_V4;
1623
1624  // Store byte
1625
1626  case Hexagon::STrib_imm_cdnPt_V4 :
1627    return Hexagon::STrib_imm_cPt_V4;
1628
1629  case Hexagon::STrib_imm_cdnNotPt_V4 :
1630    return Hexagon::STrib_imm_cNotPt_V4;
1631
1632  case Hexagon::STrib_cdnPt_nv_V4 :
1633  case Hexagon::STrib_cPt_nv_V4 :
1634  case Hexagon::STrib_cdnPt_V4 :
1635    return Hexagon::STrib_cPt;
1636
1637  case Hexagon::STrib_cdnNotPt_nv_V4 :
1638  case Hexagon::STrib_cNotPt_nv_V4 :
1639  case Hexagon::STrib_cdnNotPt_V4 :
1640    return Hexagon::STrib_cNotPt;
1641
1642  case Hexagon::STrib_indexed_cdnPt_V4 :
1643  case Hexagon::STrib_indexed_cPt_nv_V4 :
1644  case Hexagon::STrib_indexed_cdnPt_nv_V4 :
1645    return Hexagon::STrib_indexed_cPt;
1646
1647  case Hexagon::STrib_indexed_cdnNotPt_V4 :
1648  case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1649  case Hexagon::STrib_indexed_cdnNotPt_nv_V4 :
1650    return Hexagon::STrib_indexed_cNotPt;
1651
1652  case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1653  case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1654  case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1655    return Hexagon::STrib_indexed_shl_cPt_V4;
1656
1657  case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1658  case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1659  case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
1660    return Hexagon::STrib_indexed_shl_cNotPt_V4;
1661
1662  case Hexagon::POST_STbri_cdnPt_nv_V4 :
1663  case Hexagon::POST_STbri_cPt_nv_V4 :
1664  case Hexagon::POST_STbri_cdnPt_V4 :
1665    return Hexagon::POST_STbri_cPt;
1666
1667  case Hexagon::POST_STbri_cdnNotPt_nv_V4 :
1668  case Hexagon::POST_STbri_cNotPt_nv_V4:
1669  case Hexagon::POST_STbri_cdnNotPt_V4 :
1670    return Hexagon::POST_STbri_cNotPt;
1671
1672  case Hexagon::STb_GP_cdnPt_nv_V4:
1673  case Hexagon::STb_GP_cdnPt_V4:
1674  case Hexagon::STb_GP_cPt_nv_V4:
1675    return Hexagon::STb_GP_cPt_V4;
1676
1677  case Hexagon::STb_GP_cdnNotPt_nv_V4:
1678  case Hexagon::STb_GP_cdnNotPt_V4:
1679  case Hexagon::STb_GP_cNotPt_nv_V4:
1680    return Hexagon::STb_GP_cNotPt_V4;
1681
1682  // Store new-value byte - unconditional
1683  case Hexagon::STrib_nv_V4:
1684    return Hexagon::STrib;
1685
1686  case Hexagon::STrib_indexed_nv_V4:
1687    return Hexagon::STrib_indexed;
1688
1689  case Hexagon::STrib_indexed_shl_nv_V4:
1690    return Hexagon::STrib_indexed_shl_V4;
1691
1692  case Hexagon::STrib_shl_nv_V4:
1693    return Hexagon::STrib_shl_V4;
1694
1695  case Hexagon::STb_GP_nv_V4:
1696    return Hexagon::STb_GP_V4;
1697
1698  case Hexagon::POST_STbri_nv_V4:
1699    return Hexagon::POST_STbri;
1700
1701  // Store halfword
1702  case Hexagon::STrih_imm_cdnPt_V4 :
1703    return Hexagon::STrih_imm_cPt_V4;
1704
1705  case Hexagon::STrih_imm_cdnNotPt_V4 :
1706    return Hexagon::STrih_imm_cNotPt_V4;
1707
1708  case Hexagon::STrih_cdnPt_nv_V4 :
1709  case Hexagon::STrih_cPt_nv_V4 :
1710  case Hexagon::STrih_cdnPt_V4 :
1711    return Hexagon::STrih_cPt;
1712
1713  case Hexagon::STrih_cdnNotPt_nv_V4 :
1714  case Hexagon::STrih_cNotPt_nv_V4 :
1715  case Hexagon::STrih_cdnNotPt_V4 :
1716    return Hexagon::STrih_cNotPt;
1717
1718  case Hexagon::STrih_indexed_cdnPt_nv_V4:
1719  case Hexagon::STrih_indexed_cPt_nv_V4 :
1720  case Hexagon::STrih_indexed_cdnPt_V4 :
1721    return Hexagon::STrih_indexed_cPt;
1722
1723  case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1724  case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1725  case Hexagon::STrih_indexed_cdnNotPt_V4 :
1726    return Hexagon::STrih_indexed_cNotPt;
1727
1728  case Hexagon::STrih_indexed_shl_cdnPt_nv_V4 :
1729  case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1730  case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1731    return Hexagon::STrih_indexed_shl_cPt_V4;
1732
1733  case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4 :
1734  case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1735  case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
1736    return Hexagon::STrih_indexed_shl_cNotPt_V4;
1737
1738  case Hexagon::POST_SThri_cdnPt_nv_V4 :
1739  case Hexagon::POST_SThri_cPt_nv_V4 :
1740  case Hexagon::POST_SThri_cdnPt_V4 :
1741    return Hexagon::POST_SThri_cPt;
1742
1743  case Hexagon::POST_SThri_cdnNotPt_nv_V4 :
1744  case Hexagon::POST_SThri_cNotPt_nv_V4 :
1745  case Hexagon::POST_SThri_cdnNotPt_V4 :
1746    return Hexagon::POST_SThri_cNotPt;
1747
1748  case Hexagon::STh_GP_cdnPt_nv_V4:
1749  case Hexagon::STh_GP_cdnPt_V4:
1750  case Hexagon::STh_GP_cPt_nv_V4:
1751    return Hexagon::STh_GP_cPt_V4;
1752
1753  case Hexagon::STh_GP_cdnNotPt_nv_V4:
1754  case Hexagon::STh_GP_cdnNotPt_V4:
1755  case Hexagon::STh_GP_cNotPt_nv_V4:
1756    return Hexagon::STh_GP_cNotPt_V4;
1757
1758  // Store new-value halfword - unconditional
1759
1760  case Hexagon::STrih_nv_V4:
1761    return Hexagon::STrih;
1762
1763  case Hexagon::STrih_indexed_nv_V4:
1764    return Hexagon::STrih_indexed;
1765
1766  case Hexagon::STrih_indexed_shl_nv_V4:
1767    return Hexagon::STrih_indexed_shl_V4;
1768
1769  case Hexagon::STrih_shl_nv_V4:
1770    return Hexagon::STrih_shl_V4;
1771
1772  case Hexagon::STh_GP_nv_V4:
1773    return Hexagon::STh_GP_V4;
1774
1775  case Hexagon::POST_SThri_nv_V4:
1776    return Hexagon::POST_SThri;
1777
1778   // Store word
1779
1780   case Hexagon::STriw_imm_cdnPt_V4 :
1781    return Hexagon::STriw_imm_cPt_V4;
1782
1783  case Hexagon::STriw_imm_cdnNotPt_V4 :
1784    return Hexagon::STriw_imm_cNotPt_V4;
1785
1786  case Hexagon::STriw_cdnPt_nv_V4 :
1787  case Hexagon::STriw_cPt_nv_V4 :
1788  case Hexagon::STriw_cdnPt_V4 :
1789    return Hexagon::STriw_cPt;
1790
1791  case Hexagon::STriw_cdnNotPt_nv_V4 :
1792  case Hexagon::STriw_cNotPt_nv_V4 :
1793  case Hexagon::STriw_cdnNotPt_V4 :
1794    return Hexagon::STriw_cNotPt;
1795
1796  case Hexagon::STriw_indexed_cdnPt_nv_V4 :
1797  case Hexagon::STriw_indexed_cPt_nv_V4 :
1798  case Hexagon::STriw_indexed_cdnPt_V4 :
1799    return Hexagon::STriw_indexed_cPt;
1800
1801  case Hexagon::STriw_indexed_cdnNotPt_nv_V4 :
1802  case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1803  case Hexagon::STriw_indexed_cdnNotPt_V4 :
1804    return Hexagon::STriw_indexed_cNotPt;
1805
1806  case Hexagon::STriw_indexed_shl_cdnPt_nv_V4 :
1807  case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1808  case Hexagon::STriw_indexed_shl_cdnPt_V4 :
1809    return Hexagon::STriw_indexed_shl_cPt_V4;
1810
1811  case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4 :
1812  case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1813  case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
1814    return Hexagon::STriw_indexed_shl_cNotPt_V4;
1815
1816  case Hexagon::POST_STwri_cdnPt_nv_V4 :
1817  case Hexagon::POST_STwri_cPt_nv_V4 :
1818  case Hexagon::POST_STwri_cdnPt_V4 :
1819    return Hexagon::POST_STwri_cPt;
1820
1821  case Hexagon::POST_STwri_cdnNotPt_nv_V4 :
1822  case Hexagon::POST_STwri_cNotPt_nv_V4 :
1823  case Hexagon::POST_STwri_cdnNotPt_V4 :
1824    return Hexagon::POST_STwri_cNotPt;
1825
1826  case Hexagon::STw_GP_cdnPt_nv_V4:
1827  case Hexagon::STw_GP_cdnPt_V4:
1828  case Hexagon::STw_GP_cPt_nv_V4:
1829    return Hexagon::STw_GP_cPt_V4;
1830
1831  case Hexagon::STw_GP_cdnNotPt_nv_V4:
1832  case Hexagon::STw_GP_cdnNotPt_V4:
1833  case Hexagon::STw_GP_cNotPt_nv_V4:
1834    return Hexagon::STw_GP_cNotPt_V4;
1835
1836  // Store new-value word - unconditional
1837
1838  case Hexagon::STriw_nv_V4:
1839    return Hexagon::STriw;
1840
1841  case Hexagon::STriw_indexed_nv_V4:
1842    return Hexagon::STriw_indexed;
1843
1844  case Hexagon::STriw_indexed_shl_nv_V4:
1845    return Hexagon::STriw_indexed_shl_V4;
1846
1847  case Hexagon::STriw_shl_nv_V4:
1848    return Hexagon::STriw_shl_V4;
1849
1850  case Hexagon::STw_GP_nv_V4:
1851    return Hexagon::STw_GP_V4;
1852
1853  case Hexagon::POST_STwri_nv_V4:
1854    return Hexagon::POST_STwri;
1855
1856 // Store doubleword
1857
1858  case Hexagon::STrid_cdnPt_V4 :
1859    return Hexagon::STrid_cPt;
1860
1861  case Hexagon::STrid_cdnNotPt_V4 :
1862    return Hexagon::STrid_cNotPt;
1863
1864  case Hexagon::STrid_indexed_cdnPt_V4 :
1865    return Hexagon::STrid_indexed_cPt;
1866
1867  case Hexagon::STrid_indexed_cdnNotPt_V4 :
1868    return Hexagon::STrid_indexed_cNotPt;
1869
1870  case Hexagon::STrid_indexed_shl_cdnPt_V4 :
1871    return Hexagon::STrid_indexed_shl_cPt_V4;
1872
1873  case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
1874    return Hexagon::STrid_indexed_shl_cNotPt_V4;
1875
1876  case Hexagon::POST_STdri_cdnPt_V4 :
1877    return Hexagon::POST_STdri_cPt;
1878
1879  case Hexagon::POST_STdri_cdnNotPt_V4 :
1880    return Hexagon::POST_STdri_cNotPt;
1881
1882  case Hexagon::STd_GP_cdnPt_V4 :
1883    return Hexagon::STd_GP_cPt_V4;
1884
1885  case Hexagon::STd_GP_cdnNotPt_V4 :
1886    return Hexagon::STd_GP_cNotPt_V4;
1887
1888  }
1889}
1890
1891bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
1892  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1893  int NewOpcode = GetDotOldOp(MI->getOpcode());
1894  MI->setDesc(QII->get(NewOpcode));
1895  return true;
1896}
1897
1898// Returns true if an instruction is predicated on p0 and false if it's
1899// predicated on !p0.
1900
1901static bool GetPredicateSense(MachineInstr* MI,
1902                              const HexagonInstrInfo *QII) {
1903
1904  switch (MI->getOpcode()) {
1905  default: llvm_unreachable("Unknown predicate sense of the instruction");
1906  case Hexagon::TFR_cPt:
1907  case Hexagon::TFR_cdnPt:
1908  case Hexagon::TFRI_cPt:
1909  case Hexagon::TFRI_cdnPt:
1910  case Hexagon::STrib_cPt :
1911  case Hexagon::STrib_cdnPt_V4 :
1912  case Hexagon::STrib_indexed_cPt :
1913  case Hexagon::STrib_indexed_cdnPt_V4 :
1914  case Hexagon::STrib_indexed_shl_cPt_V4 :
1915  case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1916  case Hexagon::POST_STbri_cPt :
1917  case Hexagon::POST_STbri_cdnPt_V4 :
1918  case Hexagon::STrih_cPt :
1919  case Hexagon::STrih_cdnPt_V4 :
1920  case Hexagon::STrih_indexed_cPt :
1921  case Hexagon::STrih_indexed_cdnPt_V4 :
1922  case Hexagon::STrih_indexed_shl_cPt_V4 :
1923  case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1924  case Hexagon::POST_SThri_cPt :
1925  case Hexagon::POST_SThri_cdnPt_V4 :
1926  case Hexagon::STriw_cPt :
1927  case Hexagon::STriw_cdnPt_V4 :
1928  case Hexagon::STriw_indexed_cPt :
1929  case Hexagon::STriw_indexed_cdnPt_V4 :
1930  case Hexagon::STriw_indexed_shl_cPt_V4 :
1931  case Hexagon::STriw_indexed_shl_cdnPt_V4 :
1932  case Hexagon::POST_STwri_cPt :
1933  case Hexagon::POST_STwri_cdnPt_V4 :
1934  case Hexagon::STrib_imm_cPt_V4 :
1935  case Hexagon::STrib_imm_cdnPt_V4 :
1936  case Hexagon::STrid_cPt :
1937  case Hexagon::STrid_cdnPt_V4 :
1938  case Hexagon::STrid_indexed_cPt :
1939  case Hexagon::STrid_indexed_cdnPt_V4 :
1940  case Hexagon::STrid_indexed_shl_cPt_V4 :
1941  case Hexagon::STrid_indexed_shl_cdnPt_V4 :
1942  case Hexagon::POST_STdri_cPt :
1943  case Hexagon::POST_STdri_cdnPt_V4 :
1944  case Hexagon::STrih_imm_cPt_V4 :
1945  case Hexagon::STrih_imm_cdnPt_V4 :
1946  case Hexagon::STriw_imm_cPt_V4 :
1947  case Hexagon::STriw_imm_cdnPt_V4 :
1948  case Hexagon::JMP_tnew_t :
1949  case Hexagon::LDrid_cPt :
1950  case Hexagon::LDrid_cdnPt :
1951  case Hexagon::LDrid_indexed_cPt :
1952  case Hexagon::LDrid_indexed_cdnPt :
1953  case Hexagon::POST_LDrid_cPt :
1954  case Hexagon::POST_LDrid_cdnPt_V4 :
1955  case Hexagon::LDriw_cPt :
1956  case Hexagon::LDriw_cdnPt :
1957  case Hexagon::LDriw_indexed_cPt :
1958  case Hexagon::LDriw_indexed_cdnPt :
1959  case Hexagon::POST_LDriw_cPt :
1960  case Hexagon::POST_LDriw_cdnPt_V4 :
1961  case Hexagon::LDrih_cPt :
1962  case Hexagon::LDrih_cdnPt :
1963  case Hexagon::LDrih_indexed_cPt :
1964  case Hexagon::LDrih_indexed_cdnPt :
1965  case Hexagon::POST_LDrih_cPt :
1966  case Hexagon::POST_LDrih_cdnPt_V4 :
1967  case Hexagon::LDrib_cPt :
1968  case Hexagon::LDrib_cdnPt :
1969  case Hexagon::LDrib_indexed_cPt :
1970  case Hexagon::LDrib_indexed_cdnPt :
1971  case Hexagon::POST_LDrib_cPt :
1972  case Hexagon::POST_LDrib_cdnPt_V4 :
1973  case Hexagon::LDriuh_cPt :
1974  case Hexagon::LDriuh_cdnPt :
1975  case Hexagon::LDriuh_indexed_cPt :
1976  case Hexagon::LDriuh_indexed_cdnPt :
1977  case Hexagon::POST_LDriuh_cPt :
1978  case Hexagon::POST_LDriuh_cdnPt_V4 :
1979  case Hexagon::LDriub_cPt :
1980  case Hexagon::LDriub_cdnPt :
1981  case Hexagon::LDriub_indexed_cPt :
1982  case Hexagon::LDriub_indexed_cdnPt :
1983  case Hexagon::POST_LDriub_cPt :
1984  case Hexagon::POST_LDriub_cdnPt_V4 :
1985  case Hexagon::LDrid_indexed_shl_cPt_V4 :
1986  case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1987  case Hexagon::LDrib_indexed_shl_cPt_V4 :
1988  case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1989  case Hexagon::LDriub_indexed_shl_cPt_V4 :
1990  case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1991  case Hexagon::LDrih_indexed_shl_cPt_V4 :
1992  case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1993  case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1994  case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1995  case Hexagon::LDriw_indexed_shl_cPt_V4 :
1996  case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1997  case Hexagon::ADD_ri_cPt :
1998  case Hexagon::ADD_ri_cdnPt :
1999  case Hexagon::ADD_rr_cPt :
2000  case Hexagon::ADD_rr_cdnPt :
2001  case Hexagon::XOR_rr_cPt :
2002  case Hexagon::XOR_rr_cdnPt :
2003  case Hexagon::AND_rr_cPt :
2004  case Hexagon::AND_rr_cdnPt :
2005  case Hexagon::OR_rr_cPt :
2006  case Hexagon::OR_rr_cdnPt :
2007  case Hexagon::SUB_rr_cPt :
2008  case Hexagon::SUB_rr_cdnPt :
2009  case Hexagon::COMBINE_rr_cPt :
2010  case Hexagon::COMBINE_rr_cdnPt :
2011  case Hexagon::ASLH_cPt_V4 :
2012  case Hexagon::ASLH_cdnPt_V4 :
2013  case Hexagon::ASRH_cPt_V4 :
2014  case Hexagon::ASRH_cdnPt_V4 :
2015  case Hexagon::SXTB_cPt_V4 :
2016  case Hexagon::SXTB_cdnPt_V4 :
2017  case Hexagon::SXTH_cPt_V4 :
2018  case Hexagon::SXTH_cdnPt_V4 :
2019  case Hexagon::ZXTB_cPt_V4 :
2020  case Hexagon::ZXTB_cdnPt_V4 :
2021  case Hexagon::ZXTH_cPt_V4 :
2022  case Hexagon::ZXTH_cdnPt_V4 :
2023  case Hexagon::LDd_GP_cPt_V4 :
2024  case Hexagon::LDb_GP_cPt_V4 :
2025  case Hexagon::LDub_GP_cPt_V4 :
2026  case Hexagon::LDh_GP_cPt_V4 :
2027  case Hexagon::LDuh_GP_cPt_V4 :
2028  case Hexagon::LDw_GP_cPt_V4 :
2029  case Hexagon::STd_GP_cPt_V4 :
2030  case Hexagon::STb_GP_cPt_V4 :
2031  case Hexagon::STh_GP_cPt_V4 :
2032  case Hexagon::STw_GP_cPt_V4 :
2033  case Hexagon::LDd_GP_cdnPt_V4 :
2034  case Hexagon::LDb_GP_cdnPt_V4 :
2035  case Hexagon::LDub_GP_cdnPt_V4 :
2036  case Hexagon::LDh_GP_cdnPt_V4 :
2037  case Hexagon::LDuh_GP_cdnPt_V4 :
2038  case Hexagon::LDw_GP_cdnPt_V4 :
2039  case Hexagon::STd_GP_cdnPt_V4 :
2040  case Hexagon::STb_GP_cdnPt_V4 :
2041  case Hexagon::STh_GP_cdnPt_V4 :
2042  case Hexagon::STw_GP_cdnPt_V4 :
2043    return true;
2044
2045  case Hexagon::TFR_cNotPt:
2046  case Hexagon::TFR_cdnNotPt:
2047  case Hexagon::TFRI_cNotPt:
2048  case Hexagon::TFRI_cdnNotPt:
2049  case Hexagon::STrib_cNotPt :
2050  case Hexagon::STrib_cdnNotPt_V4 :
2051  case Hexagon::STrib_indexed_cNotPt :
2052  case Hexagon::STrib_indexed_cdnNotPt_V4 :
2053  case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2054  case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2055  case Hexagon::POST_STbri_cNotPt :
2056  case Hexagon::POST_STbri_cdnNotPt_V4 :
2057  case Hexagon::STrih_cNotPt :
2058  case Hexagon::STrih_cdnNotPt_V4 :
2059  case Hexagon::STrih_indexed_cNotPt :
2060  case Hexagon::STrih_indexed_cdnNotPt_V4 :
2061  case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2062  case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2063  case Hexagon::POST_SThri_cNotPt :
2064  case Hexagon::POST_SThri_cdnNotPt_V4 :
2065  case Hexagon::STriw_cNotPt :
2066  case Hexagon::STriw_cdnNotPt_V4 :
2067  case Hexagon::STriw_indexed_cNotPt :
2068  case Hexagon::STriw_indexed_cdnNotPt_V4 :
2069  case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2070  case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2071  case Hexagon::POST_STwri_cNotPt :
2072  case Hexagon::POST_STwri_cdnNotPt_V4 :
2073  case Hexagon::STrib_imm_cNotPt_V4 :
2074  case Hexagon::STrib_imm_cdnNotPt_V4 :
2075  case Hexagon::STrid_cNotPt :
2076  case Hexagon::STrid_cdnNotPt_V4 :
2077  case Hexagon::STrid_indexed_cdnNotPt_V4 :
2078  case Hexagon::STrid_indexed_cNotPt :
2079  case Hexagon::STrid_indexed_shl_cNotPt_V4 :
2080  case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2081  case Hexagon::POST_STdri_cNotPt :
2082  case Hexagon::POST_STdri_cdnNotPt_V4 :
2083  case Hexagon::STrih_imm_cNotPt_V4 :
2084  case Hexagon::STrih_imm_cdnNotPt_V4 :
2085  case Hexagon::STriw_imm_cNotPt_V4 :
2086  case Hexagon::STriw_imm_cdnNotPt_V4 :
2087  case Hexagon::JMP_fnew_t :
2088  case Hexagon::LDrid_cNotPt :
2089  case Hexagon::LDrid_cdnNotPt :
2090  case Hexagon::LDrid_indexed_cNotPt :
2091  case Hexagon::LDrid_indexed_cdnNotPt :
2092  case Hexagon::POST_LDrid_cNotPt :
2093  case Hexagon::POST_LDrid_cdnNotPt_V4 :
2094  case Hexagon::LDriw_cNotPt :
2095  case Hexagon::LDriw_cdnNotPt :
2096  case Hexagon::LDriw_indexed_cNotPt :
2097  case Hexagon::LDriw_indexed_cdnNotPt :
2098  case Hexagon::POST_LDriw_cNotPt :
2099  case Hexagon::POST_LDriw_cdnNotPt_V4 :
2100  case Hexagon::LDrih_cNotPt :
2101  case Hexagon::LDrih_cdnNotPt :
2102  case Hexagon::LDrih_indexed_cNotPt :
2103  case Hexagon::LDrih_indexed_cdnNotPt :
2104  case Hexagon::POST_LDrih_cNotPt :
2105  case Hexagon::POST_LDrih_cdnNotPt_V4 :
2106  case Hexagon::LDrib_cNotPt :
2107  case Hexagon::LDrib_cdnNotPt :
2108  case Hexagon::LDrib_indexed_cNotPt :
2109  case Hexagon::LDrib_indexed_cdnNotPt :
2110  case Hexagon::POST_LDrib_cNotPt :
2111  case Hexagon::POST_LDrib_cdnNotPt_V4 :
2112  case Hexagon::LDriuh_cNotPt :
2113  case Hexagon::LDriuh_cdnNotPt :
2114  case Hexagon::LDriuh_indexed_cNotPt :
2115  case Hexagon::LDriuh_indexed_cdnNotPt :
2116  case Hexagon::POST_LDriuh_cNotPt :
2117  case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2118  case Hexagon::LDriub_cNotPt :
2119  case Hexagon::LDriub_cdnNotPt :
2120  case Hexagon::LDriub_indexed_cNotPt :
2121  case Hexagon::LDriub_indexed_cdnNotPt :
2122  case Hexagon::POST_LDriub_cNotPt :
2123  case Hexagon::POST_LDriub_cdnNotPt_V4 :
2124  case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2125  case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2126  case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2127  case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2128  case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2129  case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2130  case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2131  case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2132  case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2133  case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2134  case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2135  case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2136  case Hexagon::ADD_ri_cNotPt :
2137  case Hexagon::ADD_ri_cdnNotPt :
2138  case Hexagon::ADD_rr_cNotPt :
2139  case Hexagon::ADD_rr_cdnNotPt :
2140  case Hexagon::XOR_rr_cNotPt :
2141  case Hexagon::XOR_rr_cdnNotPt :
2142  case Hexagon::AND_rr_cNotPt :
2143  case Hexagon::AND_rr_cdnNotPt :
2144  case Hexagon::OR_rr_cNotPt :
2145  case Hexagon::OR_rr_cdnNotPt :
2146  case Hexagon::SUB_rr_cNotPt :
2147  case Hexagon::SUB_rr_cdnNotPt :
2148  case Hexagon::COMBINE_rr_cNotPt :
2149  case Hexagon::COMBINE_rr_cdnNotPt :
2150  case Hexagon::ASLH_cNotPt_V4 :
2151  case Hexagon::ASLH_cdnNotPt_V4 :
2152  case Hexagon::ASRH_cNotPt_V4 :
2153  case Hexagon::ASRH_cdnNotPt_V4 :
2154  case Hexagon::SXTB_cNotPt_V4 :
2155  case Hexagon::SXTB_cdnNotPt_V4 :
2156  case Hexagon::SXTH_cNotPt_V4 :
2157  case Hexagon::SXTH_cdnNotPt_V4 :
2158  case Hexagon::ZXTB_cNotPt_V4 :
2159  case Hexagon::ZXTB_cdnNotPt_V4 :
2160  case Hexagon::ZXTH_cNotPt_V4 :
2161  case Hexagon::ZXTH_cdnNotPt_V4 :
2162
2163  case Hexagon::LDd_GP_cNotPt_V4 :
2164  case Hexagon::LDb_GP_cNotPt_V4 :
2165  case Hexagon::LDub_GP_cNotPt_V4 :
2166  case Hexagon::LDh_GP_cNotPt_V4 :
2167  case Hexagon::LDuh_GP_cNotPt_V4 :
2168  case Hexagon::LDw_GP_cNotPt_V4 :
2169  case Hexagon::STd_GP_cNotPt_V4 :
2170  case Hexagon::STb_GP_cNotPt_V4 :
2171  case Hexagon::STh_GP_cNotPt_V4 :
2172  case Hexagon::STw_GP_cNotPt_V4 :
2173  case Hexagon::LDd_GP_cdnNotPt_V4 :
2174  case Hexagon::LDb_GP_cdnNotPt_V4 :
2175  case Hexagon::LDub_GP_cdnNotPt_V4 :
2176  case Hexagon::LDh_GP_cdnNotPt_V4 :
2177  case Hexagon::LDuh_GP_cdnNotPt_V4 :
2178  case Hexagon::LDw_GP_cdnNotPt_V4 :
2179  case Hexagon::STd_GP_cdnNotPt_V4 :
2180  case Hexagon::STb_GP_cdnNotPt_V4 :
2181  case Hexagon::STh_GP_cdnNotPt_V4 :
2182  case Hexagon::STw_GP_cdnNotPt_V4 :
2183    return false;
2184  }
2185  // return *some value* to avoid compiler warning
2186  return false;
2187}
2188
2189static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
2190                                               const HexagonInstrInfo *QII) {
2191  assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
2192#ifndef NDEBUG
2193  // Post Increment means duplicates. Use dense map to find duplicates in the
2194  // list. Caution: Densemap initializes with the minimum of 64 buckets,
2195  // whereas there are at most 5 operands in the post increment.
2196  DenseMap<unsigned,  unsigned> DefRegsSet;
2197  for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2198    if (MI->getOperand(opNum).isReg() &&
2199        MI->getOperand(opNum).isDef()) {
2200      DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
2201    }
2202
2203  for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2204    if (MI->getOperand(opNum).isReg() &&
2205        MI->getOperand(opNum).isUse()) {
2206      if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
2207        return MI->getOperand(opNum);
2208      }
2209    }
2210#else
2211  if (MI->getDesc().mayLoad()) {
2212    // The 2nd operand is always the post increment operand in load.
2213    assert(MI->getOperand(1).isReg() &&
2214                "Post increment operand has be to a register.");
2215    return (MI->getOperand(1));
2216  }
2217  if (MI->getDesc().mayStore()) {
2218    // The 1st operand is always the post increment operand in store.
2219    assert(MI->getOperand(0).isReg() &&
2220                "Post increment operand has be to a register.");
2221    return (MI->getOperand(0));
2222  }
2223#endif
2224  // we should never come here.
2225  llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
2226}
2227
2228// get the value being stored
2229static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
2230  // value being stored is always the last operand.
2231  return (MI->getOperand(MI->getNumOperands()-1));
2232}
2233
2234// can be new value store?
2235// Following restrictions are to be respected in convert a store into
2236// a new value store.
2237// 1. If an instruction uses auto-increment, its address register cannot
2238//    be a new-value register. Arch Spec 5.4.2.1
2239// 2. If an instruction uses absolute-set addressing mode,
2240//    its address register cannot be a new-value register.
2241//    Arch Spec 5.4.2.1.TODO: This is not enabled as
2242//    as absolute-set address mode patters are not implemented.
2243// 3. If an instruction produces a 64-bit result, its registers cannot be used
2244//    as new-value registers. Arch Spec 5.4.2.2.
2245// 4. If the instruction that sets a new-value register is conditional, then
2246//    the instruction that uses the new-value register must also be conditional,
2247//    and both must always have their predicates evaluate identically.
2248//    Arch Spec 5.4.2.3.
2249// 5. There is an implied restriction of a packet can not have another store,
2250//    if there is a  new value store in the packet. Corollary, if there is
2251//    already a store in a packet, there can not be a new value store.
2252//    Arch Spec: 3.4.4.2
2253bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
2254                MachineInstr *PacketMI, unsigned DepReg,
2255                std::map <MachineInstr*, SUnit*> MIToSUnit)
2256{
2257  // Make sure we are looking at the store
2258  if (!IsNewifyStore(MI))
2259    return false;
2260
2261  // Make sure there is dependency and can be new value'ed
2262  if (GetStoreValueOperand(MI).isReg() &&
2263      GetStoreValueOperand(MI).getReg() != DepReg)
2264    return false;
2265
2266  const HexagonRegisterInfo* QRI =
2267                            (const HexagonRegisterInfo *) TM.getRegisterInfo();
2268  const MCInstrDesc& MCID = PacketMI->getDesc();
2269  // first operand is always the result
2270
2271  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2272  const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
2273
2274  // if there is already an store in the packet, no can do new value store
2275  // Arch Spec 3.4.4.2.
2276  for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
2277         VE = CurrentPacketMIs.end();
2278       (VI != VE); ++VI) {
2279    SUnit* PacketSU = MIToSUnit[*VI];
2280    if (PacketSU->getInstr()->getDesc().mayStore() ||
2281        // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
2282        // then we don't need this
2283        PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2284        PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
2285      return false;
2286  }
2287
2288  if (PacketRC == &Hexagon::DoubleRegsRegClass) {
2289    // new value store constraint: double regs can not feed into new value store
2290    // arch spec section: 5.4.2.2
2291    return false;
2292  }
2293
2294  // Make sure it's NOT the post increment register that we are going to
2295  // new value.
2296  if (QII->isPostIncrement(MI) &&
2297      MI->getDesc().mayStore() &&
2298      GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
2299    return false;
2300  }
2301
2302  if (QII->isPostIncrement(PacketMI) &&
2303      PacketMI->getDesc().mayLoad() &&
2304      GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
2305    // if source is post_inc, or absolute-set addressing,
2306    // it can not feed into new value store
2307    //  r3 = memw(r2++#4)
2308    //  memw(r30 + #-1404) = r2.new -> can not be new value store
2309    // arch spec section: 5.4.2.1
2310    return false;
2311  }
2312
2313  // If the source that feeds the store is predicated, new value store must
2314  // also be also predicated.
2315  if (QII->isPredicated(PacketMI)) {
2316    if (!QII->isPredicated(MI))
2317      return false;
2318
2319    // Check to make sure that they both will have their predicates
2320    // evaluate identically
2321    unsigned predRegNumSrc = 0;
2322    unsigned predRegNumDst = 0;
2323    const TargetRegisterClass* predRegClass = NULL;
2324
2325    // Get predicate register used in the source instruction
2326    for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2327      if ( PacketMI->getOperand(opNum).isReg())
2328      predRegNumSrc = PacketMI->getOperand(opNum).getReg();
2329      predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
2330      if (predRegClass == &Hexagon::PredRegsRegClass) {
2331        break;
2332      }
2333    }
2334    assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2335        ("predicate register not found in a predicated PacketMI instruction"));
2336
2337    // Get predicate register used in new-value store instruction
2338    for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2339      if ( MI->getOperand(opNum).isReg())
2340      predRegNumDst = MI->getOperand(opNum).getReg();
2341      predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
2342      if (predRegClass == &Hexagon::PredRegsRegClass) {
2343        break;
2344      }
2345    }
2346    assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2347            ("predicate register not found in a predicated MI instruction"));
2348
2349    // New-value register producer and user (store) need to satisfy these
2350    // constraints:
2351    // 1) Both instructions should be predicated on the same register.
2352    // 2) If producer of the new-value register is .new predicated then store
2353    // should also be .new predicated and if producer is not .new predicated
2354    // then store should not be .new predicated.
2355    // 3) Both new-value register producer and user should have same predicate
2356    // sense, i.e, either both should be negated or both should be none negated.
2357
2358    if (( predRegNumDst != predRegNumSrc) ||
2359          QII->isDotNewInst(PacketMI) != QII->isDotNewInst(MI)  ||
2360          GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
2361      return false;
2362    }
2363  }
2364
2365  // Make sure that other than the new-value register no other store instruction
2366  // register has been modified in the same packet. Predicate registers can be
2367  // modified by they should not be modified between the producer and the store
2368  // instruction as it will make them both conditional on different values.
2369  // We already know this to be true for all the instructions before and
2370  // including PacketMI. Howerver, we need to perform the check for the
2371  // remaining instructions in the packet.
2372
2373  std::vector<MachineInstr*>::iterator VI;
2374  std::vector<MachineInstr*>::iterator VE;
2375  unsigned StartCheck = 0;
2376
2377  for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
2378      (VI != VE); ++VI) {
2379    SUnit* TempSU = MIToSUnit[*VI];
2380    MachineInstr* TempMI = TempSU->getInstr();
2381
2382    // Following condition is true for all the instructions until PacketMI is
2383    // reached (StartCheck is set to 0 before the for loop).
2384    // StartCheck flag is 1 for all the instructions after PacketMI.
2385    if (TempMI != PacketMI && !StartCheck) // start processing only after
2386      continue;                            // encountering PacketMI
2387
2388    StartCheck = 1;
2389    if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
2390      continue;
2391
2392    for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2393      if (MI->getOperand(opNum).isReg() &&
2394          TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
2395                                               QRI))
2396        return false;
2397    }
2398  }
2399
2400  // Make sure that for non POST_INC stores:
2401  // 1. The only use of reg is DepReg and no other registers.
2402  //    This handles V4 base+index registers.
2403  //    The following store can not be dot new.
2404  //    Eg.   r0 = add(r0, #3)a
2405  //          memw(r1+r0<<#2) = r0
2406  if (!QII->isPostIncrement(MI) &&
2407      GetStoreValueOperand(MI).isReg() &&
2408      GetStoreValueOperand(MI).getReg() == DepReg) {
2409    for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
2410      if (MI->getOperand(opNum).isReg() &&
2411          MI->getOperand(opNum).getReg() == DepReg) {
2412        return false;
2413      }
2414    }
2415    // 2. If data definition is because of implicit definition of the register,
2416    //    do not newify the store. Eg.
2417    //    %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
2418    //    STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
2419    for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2420      if (PacketMI->getOperand(opNum).isReg() &&
2421          PacketMI->getOperand(opNum).getReg() == DepReg &&
2422          PacketMI->getOperand(opNum).isDef() &&
2423          PacketMI->getOperand(opNum).isImplicit()) {
2424        return false;
2425      }
2426    }
2427  }
2428
2429  // Can be dot new store.
2430  return true;
2431}
2432
2433// can this MI to promoted to either
2434// new value store or new value jump
2435bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
2436                SUnit *PacketSU, unsigned DepReg,
2437                std::map <MachineInstr*, SUnit*> MIToSUnit,
2438                MachineBasicBlock::iterator &MII)
2439{
2440
2441  const HexagonRegisterInfo* QRI =
2442                            (const HexagonRegisterInfo *) TM.getRegisterInfo();
2443  if (!QRI->Subtarget.hasV4TOps() ||
2444      !IsNewifyStore(MI))
2445    return false;
2446
2447  MachineInstr *PacketMI = PacketSU->getInstr();
2448
2449  // Check to see the store can be new value'ed.
2450  if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
2451    return true;
2452
2453  // Check to see the compare/jump can be new value'ed.
2454  // This is done as a pass on its own. Don't need to check it here.
2455  return false;
2456}
2457
2458// Check to see if an instruction can be dot new
2459// There are three kinds.
2460// 1. dot new on predicate - V2/V3/V4
2461// 2. dot new on stores NV/ST - V4
2462// 3. dot new on jump NV/J - V4 -- This is generated in a pass.
2463bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
2464                              SUnit *PacketSU, unsigned DepReg,
2465                              std::map <MachineInstr*, SUnit*> MIToSUnit,
2466                              MachineBasicBlock::iterator &MII,
2467                              const TargetRegisterClass* RC )
2468{
2469  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2470  // Already a dot new instruction.
2471  if (QII->isDotNewInst(MI) && !IsNewifyStore(MI))
2472    return false;
2473
2474  if (!isNewifiable(MI))
2475    return false;
2476
2477  // predicate .new
2478  if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
2479      return true;
2480  else if (RC != &Hexagon::PredRegsRegClass &&
2481      !IsNewifyStore(MI)) // MI is not a new-value store
2482    return false;
2483  else {
2484    // Create a dot new machine instruction to see if resources can be
2485    // allocated. If not, bail out now.
2486    int NewOpcode = GetDotNewOp(MI->getOpcode());
2487    const MCInstrDesc &desc = QII->get(NewOpcode);
2488    DebugLoc dl;
2489    MachineInstr *NewMI =
2490                    MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
2491    bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
2492    MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
2493
2494    if (!ResourcesAvailable)
2495      return false;
2496
2497    // new value store only
2498    // new new value jump generated as a passes
2499    if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
2500      return false;
2501    }
2502  }
2503  return true;
2504}
2505
2506// Go through the packet instructions and search for anti dependency
2507// between them and DepReg from MI
2508// Consider this case:
2509// Trying to add
2510// a) %R1<def> = TFRI_cdNotPt %P3, 2
2511// to this packet:
2512// {
2513//   b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
2514//   c) %P3<def> = TFR_PdRs %R23
2515//   d) %R1<def> = TFRI_cdnPt %P3, 4
2516//  }
2517// The P3 from a) and d) will be complements after
2518// a)'s P3 is converted to .new form
2519// Anti Dep between c) and b) is irrelevant for this case
2520bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
2521      unsigned DepReg,
2522      std::map <MachineInstr*, SUnit*> MIToSUnit) {
2523
2524  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2525  SUnit* PacketSUDep = MIToSUnit[MI];
2526
2527  for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
2528       VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
2529
2530    // We only care for dependencies to predicated instructions
2531    if(!QII->isPredicated(*VIN)) continue;
2532
2533    // Scheduling Unit for current insn in the packet
2534    SUnit* PacketSU = MIToSUnit[*VIN];
2535
2536    // Look at dependencies between current members of the packet
2537    // and predicate defining instruction MI.
2538    // Make sure that dependency is on the exact register
2539    // we care about.
2540    if (PacketSU->isSucc(PacketSUDep)) {
2541      for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
2542        if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
2543            (PacketSU->Succs[i].getKind() == SDep::Anti) &&
2544            (PacketSU->Succs[i].getReg() == DepReg)) {
2545          return true;
2546        }
2547      }
2548    }
2549  }
2550
2551  return false;
2552}
2553
2554
2555// Given two predicated instructions, this function detects whether
2556// the predicates are complements
2557bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
2558     MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
2559
2560  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2561  // Currently can only reason about conditional transfers
2562  if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) {
2563    return false;
2564  }
2565
2566  // Scheduling unit for candidate
2567  SUnit* SU = MIToSUnit[MI1];
2568
2569  // One corner case deals with the following scenario:
2570  // Trying to add
2571  // a) %R24<def> = TFR_cPt %P0, %R25
2572  // to this packet:
2573  //
2574  // {
2575  //   b) %R25<def> = TFR_cNotPt %P0, %R24
2576  //   c) %P0<def> = CMPEQri %R26, 1
2577  // }
2578  //
2579  // On general check a) and b) are complements, but
2580  // presence of c) will convert a) to .new form, and
2581  // then it is not a complement
2582  // We attempt to detect it by analyzing  existing
2583  // dependencies in the packet
2584
2585  // Analyze relationships between all existing members of the packet.
2586  // Look for Anti dependecy on the same predicate reg
2587  // as used in the candidate
2588  for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
2589       VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
2590
2591    // Scheduling Unit for current insn in the packet
2592    SUnit* PacketSU = MIToSUnit[*VIN];
2593
2594    // If this instruction in the packet is succeeded by the candidate...
2595    if (PacketSU->isSucc(SU)) {
2596      for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
2597        // The corner case exist when there is true data
2598        // dependency between candidate and one of current
2599        // packet members, this dep is on predicate reg, and
2600        // there already exist anti dep on the same pred in
2601        // the packet.
2602        if (PacketSU->Succs[i].getSUnit() == SU &&
2603            Hexagon::PredRegsRegClass.contains(
2604              PacketSU->Succs[i].getReg()) &&
2605            PacketSU->Succs[i].getKind() == SDep::Data &&
2606            // Here I know that *VIN is predicate setting instruction
2607            // with true data dep to candidate on the register
2608            // we care about - c) in the above example.
2609            // Now I need to see if there is an anti dependency
2610            // from c) to any other instruction in the
2611            // same packet on the pred reg of interest
2612            RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
2613                                        MIToSUnit)) {
2614           return false;
2615        }
2616      }
2617    }
2618  }
2619
2620  // If the above case does not apply, check regular
2621  // complement condition.
2622  // Check that the predicate register is the same and
2623  // that the predicate sense is different
2624  // We also need to differentiate .old vs. .new:
2625  // !p0 is not complimentary to p0.new
2626  return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
2627          (GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
2628          (QII->isDotNewInst(MI1) == QII->isDotNewInst(MI2)));
2629}
2630
2631// initPacketizerState - Initialize packetizer flags
2632void HexagonPacketizerList::initPacketizerState() {
2633
2634  Dependence = false;
2635  PromotedToDotNew = false;
2636  GlueToNewValueJump = false;
2637  GlueAllocframeStore = false;
2638  FoundSequentialDependence = false;
2639
2640  return;
2641}
2642
2643// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
2644bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
2645                                                    MachineBasicBlock *MBB) {
2646  if (MI->isDebugValue())
2647    return true;
2648
2649  // We must print out inline assembly
2650  if (MI->isInlineAsm())
2651    return false;
2652
2653  // We check if MI has any functional units mapped to it.
2654  // If it doesn't, we ignore the instruction.
2655  const MCInstrDesc& TID = MI->getDesc();
2656  unsigned SchedClass = TID.getSchedClass();
2657  const InstrStage* IS =
2658                    ResourceTracker->getInstrItins()->beginStage(SchedClass);
2659  unsigned FuncUnits = IS->getUnits();
2660  return !FuncUnits;
2661}
2662
2663// isSoloInstruction: - Returns true for instructions that must be
2664// scheduled in their own packet.
2665bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
2666
2667  if (MI->isInlineAsm())
2668    return true;
2669
2670  if (MI->isEHLabel())
2671    return true;
2672
2673  // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
2674  // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
2675  // They must not be grouped with other instructions in a packet.
2676  if (IsSchedBarrier(MI))
2677    return true;
2678
2679  return false;
2680}
2681
2682// isLegalToPacketizeTogether:
2683// SUI is the current instruction that is out side of the current packet.
2684// SUJ is the current instruction inside the current packet against which that
2685// SUI will be packetized.
2686bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
2687  MachineInstr *I = SUI->getInstr();
2688  MachineInstr *J = SUJ->getInstr();
2689  assert(I && J && "Unable to packetize null instruction!");
2690
2691  const MCInstrDesc &MCIDI = I->getDesc();
2692  const MCInstrDesc &MCIDJ = J->getDesc();
2693
2694  MachineBasicBlock::iterator II = I;
2695
2696  const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
2697  const HexagonRegisterInfo* QRI =
2698                      (const HexagonRegisterInfo *) TM.getRegisterInfo();
2699  const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2700
2701  // Inline asm cannot go in the packet.
2702  if (I->getOpcode() == Hexagon::INLINEASM)
2703    llvm_unreachable("Should not meet inline asm here!");
2704
2705  if (isSoloInstruction(I))
2706    llvm_unreachable("Should not meet solo instr here!");
2707
2708  // A save callee-save register function call can only be in a packet
2709  // with instructions that don't write to the callee-save registers.
2710  if ((QII->isSaveCalleeSavedRegsCall(I) &&
2711       DoesModifyCalleeSavedReg(J, QRI)) ||
2712      (QII->isSaveCalleeSavedRegsCall(J) &&
2713       DoesModifyCalleeSavedReg(I, QRI))) {
2714    Dependence = true;
2715    return false;
2716  }
2717
2718  // Two control flow instructions cannot go in the same packet.
2719  if (IsControlFlow(I) && IsControlFlow(J)) {
2720    Dependence = true;
2721    return false;
2722  }
2723
2724  // A LoopN instruction cannot appear in the same packet as a jump or call.
2725  if (IsLoopN(I) && (   IsDirectJump(J)
2726                     || MCIDJ.isCall()
2727                     || QII->isDeallocRet(J))) {
2728    Dependence = true;
2729    return false;
2730  }
2731  if (IsLoopN(J) && (   IsDirectJump(I)
2732                     || MCIDI.isCall()
2733                     || QII->isDeallocRet(I))) {
2734    Dependence = true;
2735    return false;
2736  }
2737
2738  // dealloc_return cannot appear in the same packet as a conditional or
2739  // unconditional jump.
2740  if (QII->isDeallocRet(I) && (   MCIDJ.isBranch()
2741                               || MCIDJ.isCall()
2742                               || MCIDJ.isBarrier())) {
2743    Dependence = true;
2744    return false;
2745  }
2746
2747
2748  // V4 allows dual store. But does not allow second store, if the
2749  // first store is not in SLOT0. New value store, new value jump,
2750  // dealloc_return and memop always take SLOT0.
2751  // Arch spec 3.4.4.2
2752  if (QRI->Subtarget.hasV4TOps()) {
2753    if (MCIDI.mayStore() && MCIDJ.mayStore() &&
2754       (QII->isNewValueInst(J) || QII->isMemOp(J) || QII->isMemOp(I))) {
2755      Dependence = true;
2756      return false;
2757    }
2758
2759    if ((QII->isMemOp(J) && MCIDI.mayStore())
2760        || (MCIDJ.mayStore() && QII->isMemOp(I))
2761        || (QII->isMemOp(J) && QII->isMemOp(I))) {
2762      Dependence = true;
2763      return false;
2764    }
2765
2766    //if dealloc_return
2767    if (MCIDJ.mayStore() && QII->isDeallocRet(I)){
2768      Dependence = true;
2769      return false;
2770    }
2771
2772    // If an instruction feeds new value jump, glue it.
2773    MachineBasicBlock::iterator NextMII = I;
2774    ++NextMII;
2775    if (NextMII != I->getParent()->end() && QII->isNewValueJump(NextMII)) {
2776      MachineInstr *NextMI = NextMII;
2777
2778      bool secondRegMatch = false;
2779      bool maintainNewValueJump = false;
2780
2781      if (NextMI->getOperand(1).isReg() &&
2782          I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
2783        secondRegMatch = true;
2784        maintainNewValueJump = true;
2785      }
2786
2787      if (!secondRegMatch &&
2788           I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
2789        maintainNewValueJump = true;
2790      }
2791
2792      for (std::vector<MachineInstr*>::iterator
2793            VI = CurrentPacketMIs.begin(),
2794             VE = CurrentPacketMIs.end();
2795           (VI != VE && maintainNewValueJump); ++VI) {
2796        SUnit* PacketSU = MIToSUnit[*VI];
2797
2798        // NVJ can not be part of the dual jump - Arch Spec: section 7.8
2799        if (PacketSU->getInstr()->getDesc().isCall()) {
2800          Dependence = true;
2801          break;
2802        }
2803        // Validate
2804        // 1. Packet does not have a store in it.
2805        // 2. If the first operand of the nvj is newified, and the second
2806        //    operand is also a reg, it (second reg) is not defined in
2807        //    the same packet.
2808        // 3. If the second operand of the nvj is newified, (which means
2809        //    first operand is also a reg), first reg is not defined in
2810        //    the same packet.
2811        if (PacketSU->getInstr()->getDesc().mayStore()               ||
2812            PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2813            // Check #2.
2814            (!secondRegMatch && NextMI->getOperand(1).isReg() &&
2815             PacketSU->getInstr()->modifiesRegister(
2816                               NextMI->getOperand(1).getReg(), QRI)) ||
2817            // Check #3.
2818            (secondRegMatch &&
2819             PacketSU->getInstr()->modifiesRegister(
2820                               NextMI->getOperand(0).getReg(), QRI))) {
2821          Dependence = true;
2822          break;
2823        }
2824      }
2825      if (!Dependence)
2826        GlueToNewValueJump = true;
2827      else
2828        return false;
2829    }
2830  }
2831
2832  if (SUJ->isSucc(SUI)) {
2833    for (unsigned i = 0;
2834         (i < SUJ->Succs.size()) && !FoundSequentialDependence;
2835         ++i) {
2836
2837      if (SUJ->Succs[i].getSUnit() != SUI) {
2838        continue;
2839      }
2840
2841      SDep::Kind DepType = SUJ->Succs[i].getKind();
2842
2843      // For direct calls:
2844      // Ignore register dependences for call instructions for
2845      // packetization purposes except for those due to r31 and
2846      // predicate registers.
2847      //
2848      // For indirect calls:
2849      // Same as direct calls + check for true dependences to the register
2850      // used in the indirect call.
2851      //
2852      // We completely ignore Order dependences for call instructions
2853      //
2854      // For returns:
2855      // Ignore register dependences for return instructions like jumpr,
2856      // dealloc return unless we have dependencies on the explicit uses
2857      // of the registers used by jumpr (like r31) or dealloc return
2858      // (like r29 or r30).
2859      //
2860      // TODO: Currently, jumpr is handling only return of r31. So, the
2861      // following logic (specificaly IsCallDependent) is working fine.
2862      // We need to enable jumpr for register other than r31 and then,
2863      // we need to rework the last part, where it handles indirect call
2864      // of that (IsCallDependent) function. Bug 6216 is opened for this.
2865      //
2866      unsigned DepReg = 0;
2867      const TargetRegisterClass* RC = NULL;
2868      if (DepType == SDep::Data) {
2869        DepReg = SUJ->Succs[i].getReg();
2870        RC = QRI->getMinimalPhysRegClass(DepReg);
2871      }
2872      if ((MCIDI.isCall() || MCIDI.isReturn()) &&
2873          (!IsRegDependence(DepType) ||
2874            !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
2875        /* do nothing */
2876      }
2877
2878      // For instructions that can be promoted to dot-new, try to promote.
2879      else if ((DepType == SDep::Data) &&
2880               CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
2881               PromoteToDotNew(I, DepType, II, RC)) {
2882        PromotedToDotNew = true;
2883        /* do nothing */
2884      }
2885
2886      else if ((DepType == SDep::Data) &&
2887               (QII->isNewValueJump(I))) {
2888        /* do nothing */
2889      }
2890
2891      // For predicated instructions, if the predicates are complements
2892      // then there can be no dependence.
2893      else if (QII->isPredicated(I) &&
2894               QII->isPredicated(J) &&
2895          ArePredicatesComplements(I, J, MIToSUnit)) {
2896        /* do nothing */
2897
2898      }
2899      else if (IsDirectJump(I) &&
2900               !MCIDJ.isBranch() &&
2901               !MCIDJ.isCall() &&
2902               (DepType == SDep::Order)) {
2903        // Ignore Order dependences between unconditional direct branches
2904        // and non-control-flow instructions
2905        /* do nothing */
2906      }
2907      else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
2908               (DepType != SDep::Output)) {
2909        // Ignore all dependences for jumps except for true and output
2910        // dependences
2911        /* do nothing */
2912      }
2913
2914      // Ignore output dependences due to superregs. We can
2915      // write to two different subregisters of R1:0 for instance
2916      // in the same cycle
2917      //
2918
2919      //
2920      // Let the
2921      // If neither I nor J defines DepReg, then this is a
2922      // superfluous output dependence. The dependence must be of the
2923      // form:
2924      //  R0 = ...
2925      //  R1 = ...
2926      // and there is an output dependence between the two instructions
2927      // with
2928      // DepReg = D0
2929      // We want to ignore these dependences.
2930      // Ideally, the dependence constructor should annotate such
2931      // dependences. We can then avoid this relatively expensive check.
2932      //
2933      else if (DepType == SDep::Output) {
2934        // DepReg is the register that's responsible for the dependence.
2935        unsigned DepReg = SUJ->Succs[i].getReg();
2936
2937        // Check if I and J really defines DepReg.
2938        if (I->definesRegister(DepReg) ||
2939            J->definesRegister(DepReg)) {
2940          FoundSequentialDependence = true;
2941          break;
2942        }
2943      }
2944
2945      // We ignore Order dependences for
2946      // 1. Two loads unless they are volatile.
2947      // 2. Two stores in V4 unless they are volatile.
2948      else if ((DepType == SDep::Order) &&
2949               !I->hasOrderedMemoryRef() &&
2950               !J->hasOrderedMemoryRef()) {
2951        if (QRI->Subtarget.hasV4TOps() &&
2952            // hexagonv4 allows dual store.
2953            MCIDI.mayStore() && MCIDJ.mayStore()) {
2954          /* do nothing */
2955        }
2956        // store followed by store-- not OK on V2
2957        // store followed by load -- not OK on all (OK if addresses
2958        // are not aliased)
2959        // load followed by store -- OK on all
2960        // load followed by load  -- OK on all
2961        else if ( !MCIDJ.mayStore()) {
2962          /* do nothing */
2963        }
2964        else {
2965          FoundSequentialDependence = true;
2966          break;
2967        }
2968      }
2969
2970      // For V4, special case ALLOCFRAME. Even though there is dependency
2971      // between ALLOCAFRAME and subsequent store, allow it to be
2972      // packetized in a same packet. This implies that the store is using
2973      // caller's SP. Hense, offset needs to be updated accordingly.
2974      else if (DepType == SDep::Data
2975               && QRI->Subtarget.hasV4TOps()
2976               && J->getOpcode() == Hexagon::ALLOCFRAME
2977               && (I->getOpcode() == Hexagon::STrid
2978                   || I->getOpcode() == Hexagon::STriw
2979                   || I->getOpcode() == Hexagon::STrib)
2980               && I->getOperand(0).getReg() == QRI->getStackRegister()
2981               && QII->isValidOffset(I->getOpcode(),
2982                                     I->getOperand(1).getImm() -
2983                                     (FrameSize + HEXAGON_LRFP_SIZE)))
2984      {
2985        GlueAllocframeStore = true;
2986        // Since this store is to be glued with allocframe in the same
2987        // packet, it will use SP of the previous stack frame, i.e
2988        // caller's SP. Therefore, we need to recalculate offset according
2989        // to this change.
2990        I->getOperand(1).setImm(I->getOperand(1).getImm() -
2991                                        (FrameSize + HEXAGON_LRFP_SIZE));
2992      }
2993
2994      //
2995      // Skip over anti-dependences. Two instructions that are
2996      // anti-dependent can share a packet
2997      //
2998      else if (DepType != SDep::Anti) {
2999        FoundSequentialDependence = true;
3000        break;
3001      }
3002    }
3003
3004    if (FoundSequentialDependence) {
3005      Dependence = true;
3006      return false;
3007    }
3008  }
3009
3010  return true;
3011}
3012
3013// isLegalToPruneDependencies
3014bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
3015  MachineInstr *I = SUI->getInstr();
3016  assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
3017
3018  const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
3019
3020  if (Dependence) {
3021
3022    // Check if the instruction was promoted to a dot-new. If so, demote it
3023    // back into a dot-old.
3024    if (PromotedToDotNew) {
3025      DemoteToDotOld(I);
3026    }
3027
3028    // Check if the instruction (must be a store) was glued with an Allocframe
3029    // instruction. If so, restore its offset to its original value, i.e. use
3030    // curent SP instead of caller's SP.
3031    if (GlueAllocframeStore) {
3032      I->getOperand(1).setImm(I->getOperand(1).getImm() +
3033                                             FrameSize + HEXAGON_LRFP_SIZE);
3034    }
3035
3036    return false;
3037  }
3038  return true;
3039}
3040
3041MachineBasicBlock::iterator
3042HexagonPacketizerList::addToPacket(MachineInstr *MI) {
3043
3044    MachineBasicBlock::iterator MII = MI;
3045    MachineBasicBlock *MBB = MI->getParent();
3046
3047    const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3048
3049    if (GlueToNewValueJump) {
3050
3051      ++MII;
3052      MachineInstr *nvjMI = MII;
3053      assert(ResourceTracker->canReserveResources(MI));
3054      ResourceTracker->reserveResources(MI);
3055      if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
3056          !tryAllocateResourcesForConstExt(MI)) {
3057        endPacket(MBB, MI);
3058        ResourceTracker->reserveResources(MI);
3059        assert(canReserveResourcesForConstExt(MI) &&
3060               "Ensure that there is a slot");
3061        reserveResourcesForConstExt(MI);
3062        // Reserve resources for new value jump constant extender.
3063        assert(canReserveResourcesForConstExt(MI) &&
3064               "Ensure that there is a slot");
3065        reserveResourcesForConstExt(nvjMI);
3066        assert(ResourceTracker->canReserveResources(nvjMI) &&
3067               "Ensure that there is a slot");
3068
3069      } else if (   // Extended instruction takes two slots in the packet.
3070        // Try reserve and allocate 4-byte in the current packet first.
3071        (QII->isExtended(nvjMI)
3072            && (!tryAllocateResourcesForConstExt(nvjMI)
3073                || !ResourceTracker->canReserveResources(nvjMI)))
3074        || // For non-extended instruction, no need to allocate extra 4 bytes.
3075        (!QII->isExtended(nvjMI) &&
3076              !ResourceTracker->canReserveResources(nvjMI)))
3077      {
3078        endPacket(MBB, MI);
3079        // A new and empty packet starts.
3080        // We are sure that the resources requirements can be satisfied.
3081        // Therefore, do not need to call "canReserveResources" anymore.
3082        ResourceTracker->reserveResources(MI);
3083        if (QII->isExtended(nvjMI))
3084          reserveResourcesForConstExt(nvjMI);
3085      }
3086      // Here, we are sure that "reserveResources" would succeed.
3087      ResourceTracker->reserveResources(nvjMI);
3088      CurrentPacketMIs.push_back(MI);
3089      CurrentPacketMIs.push_back(nvjMI);
3090    } else {
3091      if (   (QII->isExtended(MI) || QII->isConstExtended(MI))
3092          && (   !tryAllocateResourcesForConstExt(MI)
3093              || !ResourceTracker->canReserveResources(MI)))
3094      {
3095        endPacket(MBB, MI);
3096        // Check if the instruction was promoted to a dot-new. If so, demote it
3097        // back into a dot-old
3098        if (PromotedToDotNew) {
3099          DemoteToDotOld(MI);
3100        }
3101        reserveResourcesForConstExt(MI);
3102      }
3103      // In case that "MI" is not an extended insn,
3104      // the resource availability has already been checked.
3105      ResourceTracker->reserveResources(MI);
3106      CurrentPacketMIs.push_back(MI);
3107    }
3108    return MII;
3109}
3110
3111//===----------------------------------------------------------------------===//
3112//                         Public Constructor Functions
3113//===----------------------------------------------------------------------===//
3114
3115FunctionPass *llvm::createHexagonPacketizer() {
3116  return new HexagonPacketizer();
3117}
3118
3119