1#- 2# Copyright (C) 2009-2012 Semihalf 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions 7# are met: 8# 1. Redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer. 10# 2. Redistributions in binary form must reproduce the above copyright 11# notice, this list of conditions and the following disclaimer in the 12# documentation and/or other materials provided with the distribution. 13# 14# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24# SUCH DAMAGE. 25# 26# $FreeBSD$ 27 28# 29# Sample NANDsim configuration file. 30# 31 32############################################################################# 33# 34# [sim] General (common) simulator configuration section. 35# 36[sim] 37# log_level=0..255 38log_level=11 39 40# log_output=[none, console, ram, file] 41# 42# When log_output=file is specified, each [ctrl] section must have a 43# corresponding 'log_filename' field provided, which specifies log file name 44# to be used. 45log_output=none 46 47############################################################################# 48# 49# [ctrl] Controller configuration section. 50# 51# There can be a number of controllers defined for simulation, each has a 52# dedicated [ctrl] section. With a given controller there are associated 53# subordinate NAND chips, which are tied to chip select lines. 54# 55[ctrl] 56# The number of this controller. 57# ctrl_num=0..3 58ctrl_num=0 59 60# The number of chip selects available at this controller. 61# num_cs=1..4 62num_cs=1 63 64# ECC enable flag. 65# ecc=[on|off] 66ecc=on 67 68# ECC layout. This is the list of byte offsets within OOB area, which comprise 69# the ECC contents set. 70# 71# ecc_layout=[byte1, byte2-byte3, ..byten] 72ecc_layout=[0-53] 73 74# Absolute path to the log file for this controller. 75#log_filename=/var/log/nandsim-ctl0.log 76 77 78############################################################################# 79# 80# [chip] Chip configuration section. 81# 82# There can be a number of individual NAND chip devices defined for 83# simulation, and each has a dedicated [chip] section. 84# 85# A particular chip needs to be associated with its parent NAND controller by 86# specifying the following fields: controller number (chip_ctrl) and the chip 87# select line it is connected to (chip_cs). The chip can be connected to only 88# a single (and unique) controller:cs pair. 89# 90[chip] 91# The number of parent controller. This has to fit one of the controller 92# instance number (ctrl_num from [ctrl] section). 93# chip_ctrl=0..3 94chip_ctrl=0 95 96# Chip select line. 97# chip_cs=0..3 98chip_cs=0 99 100# ONFI device identifier. 101# device_id=0x00..0xff 102device_id=0xd3 103 104# ONFI manufacturer identifier. 105# manufacturer_id=0x00..0xff 106manufacturer_id=0xec 107 108# Textual description of the chip. 109# model="model_name" 110model="k9xxg08uxM:1GiB 3,3V 8-bit" 111 112# Textual name of the chip manufacturer. 113# manufacturer="manufacturer name" 114manufacturer="SAMSUNG" 115 116# page_size=[must be power of 2 and >= 512] (in bytes) 117page_size=2048 118# oob_size=[>0] 119oob_size=64 120# pages_per_block=n*32 121pages_per_block=64 122# blocks_per_lun=[>0] 123blocks_per_lun=4096 124# luns=1..N 125luns=1 126# column_addr_cycle=[1,2] 127column_addr_cycle=2 128# row_addr_cycle=[1,2,3] 129row_addr_cycle=3 130 131# program_time= (in us) 132program_time=0 133# erase_time= (in us) 134erase_time=0 135# read_time= (in us) 136read_time=0 137# ccs_time= (in us) 138#ccs_time=200 139 140# Simulate write-protect on the chip. 141# write_protect=[yes|no] 142#write_protect=no 143 144# Blocks wear-out threshold. Each block has a counter of program-erase cycles; 145# when this counter reaches 'wear_out' value a given block is treated as a bad 146# block (access will report error). 147# 148# Setting wear_out to 0 means that blocks will never wear out. 149# 150# wear_out=0..100000 151wear_out=50000 152 153# Errors per million read/write bytes. This simulates an accidental read/write 154# block error, which can happen in real devices with certain probability. Note 155# this isn't a bad block condition i.e. the block at which the read/write 156# operation is simulated to fail here remains usable, only the operation has 157# not succeeded (this is where ECC comes into play and is supposed to correct 158# such problems). 159# 160# error_ratio=0..1000000 161#error_ratio=50 162 163# Chip data bus width. All chips connected to the same controller must have 164# the same bus width. 165# 166# width=[8|16] 167width=8 168 169# Bad block map. NANDsim emulates bad block behavior upon accessing a block 170# with number from the specified list. 171# 172# bad_block_map=[bad_block1, bad_block2-bad_block3, ..bad_blockn] 173bad_block_map=[100-200] 174 175