1/*- 2 * Copyright (c) 1996, Sujal M. Patel 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Sujal M. Patel 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 * from: pnp.h,v 1.7 1998/09/13 22:15:44 eivind Exp 34 */ 35 36#ifndef _ISA_PNPREG_H_ 37#define _ISA_PNPREG_H_ 38 39/* Maximum Number of PnP Devices. 8 should be plenty */ 40#define PNP_MAX_CARDS 8 41 42/* Static ports to access PnP state machine */ 43#ifdef PC98 44#define _PNP_ADDRESS 0x259 45#define _PNP_WRITE_DATA 0xa59 46#else 47#define _PNP_ADDRESS 0x279 48#define _PNP_WRITE_DATA 0xa79 49#endif 50 51/* PnP Registers. Write to ADDRESS and then use WRITE/READ_DATA */ 52#define PNP_SET_RD_DATA 0x00 53 /*** 54 Writing to this location modifies the address of the port used for 55 reading from the Plug and Play ISA cards. Bits[7:0] become I/O 56 read port address bits[9:2]. Reads from this register are ignored. 57 ***/ 58 59#define PNP_SERIAL_ISOLATION 0x01 60 /*** 61 A read to this register causes a Plug and Play cards in the Isolation 62 state to compare one bit of the boards ID. 63 This register is read only. 64 ***/ 65 66#define PNP_CONFIG_CONTROL 0x02 67#define PNP_CONFIG_CONTROL_RESET_CSN 0x04 68#define PNP_CONFIG_CONTROL_WAIT_FOR_KEY 0x02 69#define PNP_CONFIG_CONTROL_RESET 0x01 70 /*** 71 Bit[2] Reset CSN to 0 72 Bit[1] Return to the Wait for Key state 73 Bit[0] Reset all logical devices and restore configuration 74 registers to their power-up values. 75 76 A write to bit[0] of this register performs a reset function on 77 all logical devices. This resets the contents of configuration 78 registers to their default state. All card's logical devices 79 enter their default state and the CSN is preserved. 80 81 A write to bit[1] of this register causes all cards to enter the 82 Wait for Key state but all CSNs are preserved and logical devices 83 are not affected. 84 85 A write to bit[2] of this register causes all cards to reset their 86 CSN to zero . 87 88 This register is write-only. The values are not sticky, that is, 89 hardware will automatically clear them and there is no need for 90 software to clear the bits. 91 ***/ 92 93#define PNP_WAKE 0x03 94 /*** 95 A write to this port will cause all cards that have a CSN that 96 matches the write data[7:0] to go from the Sleep state to the either 97 the Isolation state if the write data for this command is zero or 98 the Config state if the write data is not zero. Additionally, the 99 pointer to the byte-serial device is reset. This register is 100 writeonly. 101 ***/ 102 103#define PNP_RESOURCE_DATA 0x04 104 /*** 105 A read from this address reads the next byte of resource information. 106 The Status register must be polled until bit[0] is set before this 107 register may be read. This register is read only. 108 ***/ 109 110#define PNP_STATUS 0x05 111 /*** 112 Bit[0] when set indicates it is okay to read the next data byte 113 from the Resource Data register. This register is readonly. 114 ***/ 115 116#define PNP_SET_CSN 0x06 117 /*** 118 A write to this port sets a card's CSN. The CSN is a value uniquely 119 assigned to each ISA card after the serial identification process 120 so that each card may be individually selected during a Wake[CSN] 121 command. This register is read/write. 122 ***/ 123 124#define PNP_SET_LDN 0x07 125 /*** 126 Selects the current logical device. All reads and writes of memory, 127 I/O, interrupt and DMA configuration information access the registers 128 of the logical device written here. In addition, the I/O Range 129 Check and Activate commands operate only on the selected logical 130 device. This register is read/write. If a card has only 1 logical 131 device, this location should be a read-only value of 0x00. 132 ***/ 133 134/*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/ 135/*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/ 136 137#define PNP_ACTIVATE 0x30 138 /*** 139 For each logical device there is one activate register that controls 140 whether or not the logical device is active on the ISA bus. Bit[0], 141 if set, activates the logical device. Bits[7:1] are reserved and 142 must return 0 on reads. This is a read/write register. Before a 143 logical device is activated, I/O range check must be disabled. 144 ***/ 145 146#define PNP_IO_RANGE_CHECK 0x31 147#define PNP_IO_RANGE_CHECK_ENABLE 0x02 148#define PNP_IO_RANGE_CHECK_READ_AS_55 0x01 149 /*** 150 This register is used to perform a conflict check on the I/O port 151 range programmed for use by a logical device. 152 153 Bit[7:2] Reserved and must return 0 on reads 154 Bit[1] Enable I/O Range check, if set then I/O Range Check 155 is enabled. I/O range check is only valid when the logical 156 device is inactive. 157 158 Bit[0], if set, forces the logical device to respond to I/O reads 159 of the logical device's assigned I/O range with a 0x55 when I/O 160 range check is in operation. If clear, the logical device drives 161 0xAA. This register is read/write. 162 ***/ 163 164/*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/ 165/*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/ 166 167#define PNP_MEM_BASE_HIGH(i) (0x40 + 8*(i)) 168#define PNP_MEM_BASE_LOW(i) (0x41 + 8*(i)) 169#define PNP_MEM_CONTROL(i) (0x42 * 8*(i)) 170#define PNP_MEM_CONTROL_16BIT 0x2 171#define PNP_MEM_CONTROL_LIMIT 0x1 172#define PNP_MEM_RANGE_HIGH(i) (0x43 + 8*(i)) 173#define PNP_MEM_RANGE_LOW(i) (0x44 + 8*(i)) 174 /*** 175 Four memory resource registers per range, four ranges. 176 Fill with 0 if no ranges are enabled. 177 178 Offset 0: RW Memory base address bits[23:16] 179 Offset 1: RW Memory base address bits[15:8] 180 Offset 2: Memory control 181 Bit[1] specifies 8/16-bit control. This bit is set to indicate 182 16-bit memory, and cleared to indicate 8-bit memory. 183 Bit[0], if cleared, indicates the next field can be used as a range 184 length for decode (implies range length and base alignment of memory 185 descriptor are equal). 186 Bit[0], if set, indicates the next field is the upper limit for 187 the address. - - Bit[0] is read-only. 188 Offset 3: RW upper limit or range len, bits[23:16] 189 Offset 4: RW upper limit or range len, bits[15:8] 190 Offset 5-Offset 7: filler, unused. 191 ***/ 192 193#define PNP_IO_BASE_HIGH(i) (0x60 + 2*(i)) 194#define PNP_IO_BASE_LOW(i) (0x61 + 2*(i)) 195 /*** 196 Eight ranges, two bytes per range. 197 Offset 0: I/O port base address bits[15:8] 198 Offset 1: I/O port base address bits[7:0] 199 ***/ 200 201#define PNP_IRQ_LEVEL(i) (0x70 + 2*(i)) 202#define PNP_IRQ_TYPE(i) (0x71 + 2*(i)) 203 /*** 204 Two entries, two bytes per entry. 205 Offset 0: RW interrupt level (1..15, 0=unused). 206 Offset 1: Bit[1]: level(1:hi, 0:low), 207 Bit[0]: type (1:level, 0:edge) 208 byte 1 can be readonly if 1 type of int is used. 209 ***/ 210 211#define PNP_DMA_CHANNEL(i) (0x74 + 1*(i)) 212 /*** 213 Two entries, one byte per entry. Bits[2:0] select 214 which DMA channel is in use for DMA 0. Zero selects DMA channel 215 0, seven selects DMA channel 7. DMA channel 4, the cascade channel 216 is used to indicate no DMA channel is active. 217 ***/ 218 219/*** 32-bit memory accesses are at 0x76 ***/ 220 221/* Macros to parse Resource IDs */ 222#define PNP_RES_TYPE(a) (a >> 7) 223#define PNP_SRES_NUM(a) (a >> 3) 224#define PNP_SRES_LEN(a) (a & 0x07) 225#define PNP_LRES_NUM(a) (a & 0x7f) 226 227/* Small Resource Item names */ 228#define PNP_TAG_VERSION 0x1 229#define PNP_TAG_LOGICAL_DEVICE 0x2 230#define PNP_TAG_COMPAT_DEVICE 0x3 231#define PNP_TAG_IRQ_FORMAT 0x4 232#define PNP_TAG_DMA_FORMAT 0x5 233#define PNP_TAG_START_DEPENDANT 0x6 234#define PNP_TAG_END_DEPENDANT 0x7 235#define PNP_TAG_IO_RANGE 0x8 236#define PNP_TAG_IO_FIXED 0x9 237#define PNP_TAG_RESERVED 0xa-0xd 238#define PNP_TAG_VENDOR 0xe 239#define PNP_TAG_END 0xf 240 241/* Large Resource Item names */ 242#define PNP_TAG_MEMORY_RANGE 0x1 243#define PNP_TAG_ID_ANSI 0x2 244#define PNP_TAG_ID_UNICODE 0x3 245#define PNP_TAG_LARGE_VENDOR 0x4 246#define PNP_TAG_MEMORY32_RANGE 0x5 247#define PNP_TAG_MEMORY32_FIXED 0x6 248#define PNP_TAG_LARGE_RESERVED 0x7-0x7f 249 250#endif /* !_ISA_PNPREG_H_ */ 251