1/*- 2 * Copyright(c) 2002-2011 Exar Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification are permitted provided the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Exar Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31/*$FreeBSD$*/ 32 33#ifndef VXGE_HAL_LL_H 34#define VXGE_HAL_LL_H 35 36#include <dev/vxge/include/vxgehal-version.h> 37#include <dev/vxge/include/vxge-defs.h> 38#include <dev/vxge/include/vxge-os-pal.h> 39#include "vxgehal-status.h" 40#include <dev/vxge/include/vxgehal-types.h> 41#include <dev/vxge/include/vxge-debug.h> 42#include <dev/vxge/include/vxge-list.h> 43#include <dev/vxge/include/vxge-queue.h> 44#include <dev/vxge/include/vxgehal-config.h> 45#include <dev/vxge/include/vxgehal-stats.h> 46#include <dev/vxge/include/vxgehal-mgmt.h> 47#include <dev/vxge/include/vxgehal-mgmtaux.h> 48 49__EXTERN_BEGIN_DECLS 50 51/* 52 * Driver 53 */ 54 55/* 56 * enum vxge_hal_xpak_alarm_type_e - XPAK Alarm types 57 * @VXGE_HAL_XPAK_ALARM_EXCESS_TEMP: Excess temparature alarm 58 * @VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT: Excess bias current alarm 59 * @VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT: Excess laser output alarm 60 * 61 * XPAK alarm types 62 */ 63typedef enum vxge_hal_xpak_alarm_type_e { 64 VXGE_HAL_XPAK_ALARM_EXCESS_TEMP = 1, 65 VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT = 2, 66 VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT = 3, 67} vxge_hal_xpak_alarm_type_e; 68 69/* 70 * function vxge_uld_sched_timer_cb_f - Per-device periodic timer 71 * callback. 72 * @devh: HAL device handle. 73 * @userdata: Per-device user data (a.k.a. context) specified via 74 * vxge_hal_device_initialize(). 75 * 76 * Periodic or one-shot timer callback. If specified (that is, not NULL) 77 * HAL invokes this callback periodically. The call is performed in the 78 * interrupt context, or more exactly, in the context of HAL's ISR 79 * vxge_hal_device_continue_irq(). 80 * 81 * See also: vxge_hal_device_initialize {} 82 */ 83typedef void (*vxge_uld_sched_timer_cb_f) ( 84 vxge_hal_device_h devh, 85 void *userdata); 86 87/* 88 * function vxge_uld_link_up_f - Link-Up callback provided by upper-layer 89 * driver. 90 * @devh: HAL device handle. 91 * @userdata: Opaque context set by the ULD via 92 * vxge_hal_device_private_set() 93 * (typically - at HAL device iinitialization time). 94 * 95 * Link-up notification callback provided by the ULD. 96 * This is one of the per-driver callbacks, see vxge_hal_uld_cbs_t {}. 97 * 98 * See also: vxge_hal_uld_cbs_t {}, vxge_uld_link_down_f {}, 99 * vxge_hal_driver_initialize(), vxge_hal_device_private_set(). 100 */ 101typedef void (*vxge_uld_link_up_f) ( 102 vxge_hal_device_h devh, 103 void *userdata); 104 105/* 106 * function vxge_uld_link_down_f - Link-Down callback provided by 107 * upper-layer driver. 108 * @devh: HAL device handle. 109 * @userdata: Opaque context set by the ULD via 110 * vxge_hal_device_private_set() 111 * (typically - at HAL device iinitialization time). 112 * 113 * Link-Down notification callback provided by the upper-layer driver. 114 * This is one of the per-driver callbacks, see vxge_hal_uld_cbs_t {}. 115 * 116 * See also: vxge_hal_uld_cbs_t {}, vxge_uld_link_up_f {}, 117 * vxge_hal_driver_initialize(), vxge_hal_device_private_set(). 118 */ 119typedef void (*vxge_uld_link_down_f) ( 120 vxge_hal_device_h devh, 121 void *userdata); 122 123/* 124 * function vxge_uld_crit_err_f - Critical Error notification callback. 125 * @devh: HAL device handle. 126 * @userdata: Opaque context set by the ULD via 127 * vxge_hal_device_private_set() 128 * (typically - at HAL device iinitialization time). 129 * @type: Enumerated hw error, e.g.: double ECC. 130 * @serr_data: X3100 status. 131 * @ext_data: Extended data. The contents depends on the @type. 132 * 133 * Critical error notification callback provided by the upper-layer driver. 134 * This is one of the per-driver callbacks, see vxge_hal_uld_cbs_t {}. 135 * 136 * See also: vxge_hal_uld_cbs_t {}, vxge_hal_event_e {}, 137 * vxge_hal_device_private_set(), vxge_hal_driver_initialize(). 138 */ 139typedef void (*vxge_uld_crit_err_f) ( 140 vxge_hal_device_h devh, 141 void *userdata, 142 vxge_hal_event_e type, 143 u64 ext_data); 144 145/* 146 * function vxge_uld_xpak_alarm_log_f - ULD "XPAK alarm log" callback. 147 * @devh: HAL device handle. 148 * @port: Port number 149 * @type: XPAK Alarm type 150 * 151 * Unless NULL is specified, HAL invokes the callback after checking XPAK 152 * counters 153 */ 154typedef void (*vxge_uld_xpak_alarm_log_f) ( 155 vxge_hal_device_h devh, 156 u32 port, 157 vxge_hal_xpak_alarm_type_e type); 158 159/* 160 * struct vxge_hal_uld_cbs_t - Upper-layer driver "slow-path" callbacks. 161 * @link_up: See vxge_uld_link_up_f {}. 162 * @link_down: See vxge_uld_link_down_f {}. 163 * @crit_err: See vxge_uld_crit_err_f {}. 164 * @sched_timer: See vxge_uld_sched_timer_cb_f {}. 165 * @xpak_alarm_log: 166 * 167 * Upper layer driver slow-path (per-driver) callbacks. 168 * Implemented by ULD and provided to HAL via 169 * vxge_hal_driver_initialize(). 170 * Note that these callbacks are not mandatory: HAL will not invoke 171 * a callback if NULL is specified. 172 * 173 * See also: vxge_hal_driver_initialize(). 174 */ 175typedef struct vxge_hal_uld_cbs_t { 176 vxge_uld_link_up_f link_up; 177 vxge_uld_link_down_f link_down; 178 vxge_uld_crit_err_f crit_err; 179 vxge_uld_sched_timer_cb_f sched_timer; 180 vxge_uld_xpak_alarm_log_f xpak_alarm_log; 181} vxge_hal_uld_cbs_t; 182 183/* 184 * vxge_hal_driver_initialize - Initialize HAL. 185 * @config: HAL configuration, see vxge_hal_driver_config_t {}. 186 * @uld_callbacks: Upper-layer driver callbacks, e.g. link-up. 187 * 188 * HAL initialization entry point. Not to confuse with device initialization 189 * (note that HAL "contains" zero or more X3100 devices). 190 * 191 * Returns: VXGE_HAL_OK - success; 192 * VXGE_HAL_ERR_BAD_DRIVER_CONFIG - Driver configuration params invalid. 193 * 194 */ 195vxge_hal_status_e 196vxge_hal_driver_initialize( 197 vxge_hal_driver_config_t *config, 198 vxge_hal_uld_cbs_t *uld_callbacks); 199 200/* 201 * vxge_hal_driver_debug_set - Set the debug module, level and timestamp 202 * @level: Debug level as defined in enum vxge_debug_level_e 203 * 204 * This routine is used to dynamically change the debug output 205 */ 206void 207vxge_hal_driver_debug_set( 208 vxge_debug_level_e level); 209 210/* 211 * vxge_hal_driver_debug_get - Get the debug level 212 * 213 * This routine returns the current debug level set 214 */ 215u32 216vxge_hal_driver_debug_get(void); 217 218/* 219 * vxge_hal_driver_terminate - Terminate HAL. 220 * 221 * HAL termination entry point. 222 */ 223void 224vxge_hal_driver_terminate(void); 225 226void * 227vxge_hal_device_get_legacy_reg(pci_dev_h pdev, pci_reg_h regh, u8 *bar0); 228 229/* 230 * RX Descriptor 231 */ 232/* 233 * enum vxge_hal_rxd_state_e - Descriptor (RXD) state. 234 * @VXGE_HAL_RXD_STATE_NONE: Invalid state. 235 * @VXGE_HAL_RXD_STATE_AVAIL: Descriptor is available for reservation. 236 * @VXGE_HAL_RXD_STATE_POSTED: Descriptor is posted for processing by the 237 * device. 238 * @VXGE_HAL_RXD_STATE_FREED: Descriptor is free and can be reused for 239 * filling-in and posting later. 240 * 241 * X3100/HAL descriptor states. 242 * 243 */ 244typedef enum vxge_hal_rxd_state_e { 245 VXGE_HAL_RXD_STATE_NONE = 0, 246 VXGE_HAL_RXD_STATE_AVAIL = 1, 247 VXGE_HAL_RXD_STATE_POSTED = 2, 248 VXGE_HAL_RXD_STATE_FREED = 3 249} vxge_hal_rxd_state_e; 250 251/* 252 * Ring 253 */ 254 255/* 256 * struct vxge_hal_ring_rxd_info_t - Extended information associated with a 257 * completed ring descriptor. 258 * @syn_flag: SYN flag 259 * @is_icmp: Is ICMP 260 * @fast_path_eligible: Fast Path Eligible flag 261 * @l3_cksum_valid: in L3 checksum is valid 262 * @l3_cksum: Result of IP checksum check (by X3100 hardware). 263 * This field containing VXGE_HAL_L3_CKSUM_OK would mean that 264 * the checksum is correct, otherwise - the datagram is 265 * corrupted. 266 * @l4_cksum_valid: in L4 checksum is valid 267 * @l4_cksum: Result of TCP/UDP checksum check (by X3100 hardware). 268 * This field containing VXGE_HAL_L4_CKSUM_OK would mean that 269 * the checksum is correct. Otherwise - the packet is 270 * corrupted. 271 * @frame: Zero or more of vxge_hal_frame_type_e flags. 272 * See vxge_hal_frame_type_e {}. 273 * @proto: zero or more of vxge_hal_frame_proto_e flags. Reporting bits for 274 * various higher-layer protocols, including (but note restricted to) 275 * TCP and UDP. See vxge_hal_frame_proto_e {}. 276 * @is_vlan: If vlan tag is valid 277 * @vlan: VLAN tag extracted from the received frame. 278 * @rth_bucket: RTH bucket 279 * @rth_it_hit: Set, If RTH hash value calculated by the X3100 hardware 280 * has a matching entry in the Indirection table. 281 * @rth_spdm_hit: Set, If RTH hash value calculated by the X3100 hardware 282 * has a matching entry in the Socket Pair Direct Match table. 283 * @rth_hash_type: RTH hash code of the function used to calculate the hash. 284 * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by X3100 285 * hardware if RTH is enabled. 286 */ 287typedef struct vxge_hal_ring_rxd_info_t { 288 u32 syn_flag; 289 u32 is_icmp; 290 u32 fast_path_eligible; 291 u32 l3_cksum_valid; 292 u32 l3_cksum; 293 u32 l4_cksum_valid; 294 u32 l4_cksum; 295 u32 frame; 296 u32 proto; 297 u32 is_vlan; 298#define VXGE_HAL_VLAN_VID_MASK 0xfff 299 u32 vlan; 300 u32 rth_bucket; 301 u32 rth_it_hit; 302 u32 rth_spdm_hit; 303 u32 rth_hash_type; 304 u32 rth_value; 305} vxge_hal_ring_rxd_info_t; 306 307/* 308 * enum vxge_hal_frame_type_e - Ethernet frame format. 309 * @VXGE_HAL_FRAME_TYPE_DIX: DIX (Ethernet II) format. 310 * @VXGE_HAL_FRAME_TYPE_LLC: LLC format. 311 * @VXGE_HAL_FRAME_TYPE_SNAP: SNAP format. 312 * @VXGE_HAL_FRAME_TYPE_IPX: IPX format. 313 * 314 * Ethernet frame format. 315 */ 316typedef enum vxge_hal_frame_type_e { 317 VXGE_HAL_FRAME_TYPE_DIX = 0x0, 318 VXGE_HAL_FRAME_TYPE_LLC = 0x1, 319 VXGE_HAL_FRAME_TYPE_SNAP = 0x2, 320 VXGE_HAL_FRAME_TYPE_IPX = 0x3, 321} vxge_hal_frame_type_e; 322 323typedef enum vxge_hal_tcp_option_e { 324 325 VXGE_HAL_TCPOPT_NOP = 1, /* Padding */ 326 VXGE_HAL_TCPOPT_EOL = 0, /* End of options */ 327 VXGE_HAL_TCPOPT_MSS = 2, /* Segment size negotiating */ 328 VXGE_HAL_TCPOPT_WINDOW = 3, /* Window scaling */ 329 VXGE_HAL_TCPOPT_SACK_PERM = 4, /* SACK Permitted */ 330 VXGE_HAL_TCPOPT_SACK = 5, /* SACK Block */ 331 VXGE_HAL_TCPOPT_TIMESTAMP = 8, /* Better RTT estimations/PAWS */ 332 VXGE_HAL_TCPOPT_MD5SIG = 19, /* MD5 Signature (RFC2385) */ 333 VXGE_HAL_TCPOLEN_TIMESTAMP = 10, 334 VXGE_HAL_TCPOLEN_TSTAMP_ALIGNED = 12 335 336} vxge_hal_tcp_option_e; 337 338/* 339 * enum vxge_hal_frame_proto_e - Higher-layer ethernet protocols. 340 * @VXGE_HAL_FRAME_PROTO_VLAN_TAGGED: VLAN. 341 * @VXGE_HAL_FRAME_PROTO_IPV4: IPv4. 342 * @VXGE_HAL_FRAME_PROTO_IPV6: IPv6. 343 * @VXGE_HAL_FRAME_PROTO_IP_FRAG: IP fragmented. 344 * @VXGE_HAL_FRAME_PROTO_TCP: TCP. 345 * @VXGE_HAL_FRAME_PROTO_UDP: UDP. 346 * @VXGE_HAL_FRAME_PROTO_TCP_OR_UDP: TCP or UDP. 347 * 348 * Higher layer ethernet protocols and options. 349 */ 350typedef enum vxge_hal_frame_proto_e { 351 VXGE_HAL_FRAME_PROTO_VLAN_TAGGED = 0x80, 352 VXGE_HAL_FRAME_PROTO_IPV4 = 0x10, 353 VXGE_HAL_FRAME_PROTO_IPV6 = 0x08, 354 VXGE_HAL_FRAME_PROTO_IP_FRAG = 0x04, 355 VXGE_HAL_FRAME_PROTO_TCP = 0x02, 356 VXGE_HAL_FRAME_PROTO_UDP = 0x01, 357 VXGE_HAL_FRAME_PROTO_TCP_OR_UDP = (VXGE_HAL_FRAME_PROTO_TCP | \ 358 VXGE_HAL_FRAME_PROTO_UDP) 359} vxge_hal_frame_proto_e; 360 361/* 362 * enum vxge_hal_ring_tcode_e - Transfer codes returned by adapter 363 * @VXGE_HAL_RING_T_CODE_OK: Transfer ok. 364 * @VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH: Layer 3 checksum presentation 365 * configuration mismatch. 366 * @VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH: Layer 4 checksum presentation 367 * configuration mismatch. 368 * @VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH: Layer 3 and Layer 4 checksum 369 * presentation configuration mismatch. 370 * @VXGE_HAL_RING_T_CODE_L3_PKT_ERR: Layer 3 error: unparseable packet, 371 * such as unknown IPv6 header. 372 * @VXGE_HAL_RING_T_CODE_L2_FRM_ERR: Layer 2 error: frame integrity 373 * error, such as FCS or ECC). 374 * @VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR: Buffer size error: the RxD buffer(s) 375 * were not appropriately sized and data loss occurred. 376 * @VXGE_HAL_RING_T_CODE_INT_ECC_ERR: Internal ECC error: RxD corrupted. 377 * @VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW: Benign overflow: the contents of 378 * Segment1 exceeded the capacity of Buffer1 and the remainder 379 * was placed in Buffer2. Segment2 now starts in Buffer3. 380 * No data loss or errors occurred. 381 * @VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF: Buffer size 0: one of the RxDs 382 * assigned buffers has a size of 0 bytes. 383 * @VXGE_HAL_RING_T_CODE_FRM_DROP: Frame dropped: either due to 384 * VPath Reset or because of a VPIN mismatch. 385 * @VXGE_HAL_RING_T_CODE_UNUSED: Unused 386 * @VXGE_HAL_RING_T_CODE_MULTI_ERR: Multiple errors: more than one 387 * transfer code condition occurred. 388 * 389 * Transfer codes returned by adapter. 390 */ 391typedef enum vxge_hal_ring_tcode_e { 392 VXGE_HAL_RING_T_CODE_OK = 0x0, 393 VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH = 0x1, 394 VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH = 0x2, 395 VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH = 0x3, 396 VXGE_HAL_RING_T_CODE_L3_PKT_ERR = 0x5, 397 VXGE_HAL_RING_T_CODE_L2_FRM_ERR = 0x6, 398 VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR = 0x7, 399 VXGE_HAL_RING_T_CODE_INT_ECC_ERR = 0x8, 400 VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW = 0x9, 401 VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF = 0xA, 402 VXGE_HAL_RING_T_CODE_FRM_DROP = 0xC, 403 VXGE_HAL_RING_T_CODE_UNUSED = 0xE, 404 VXGE_HAL_RING_T_CODE_MULTI_ERR = 0xF 405} vxge_hal_ring_tcode_e; 406 407/* 408 * enum vxge_hal_ring_hash_type_e - RTH hash types 409 * @VXGE_HAL_RING_HASH_TYPE_NONE: No Hash 410 * @VXGE_HAL_RING_HASH_TYPE_TCP_IPV4: TCP IPv4 411 * @VXGE_HAL_RING_HASH_TYPE_UDP_IPV4: UDP IPv4 412 * @VXGE_HAL_RING_HASH_TYPE_IPV4: IPv4 413 * @VXGE_HAL_RING_HASH_TYPE_TCP_IPV6: TCP IPv6 414 * @VXGE_HAL_RING_HASH_TYPE_UDP_IPV6: UDP IPv6 415 * @VXGE_HAL_RING_HASH_TYPE_IPV6: IPv6 416 * @VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX: TCP IPv6 extension 417 * @VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX: UDP IPv6 extension 418 * @VXGE_HAL_RING_HASH_TYPE_IPV6_EX: IPv6 extension 419 * 420 * RTH hash types 421 */ 422typedef enum vxge_hal_ring_hash_type_e { 423 VXGE_HAL_RING_HASH_TYPE_NONE = 0x0, 424 VXGE_HAL_RING_HASH_TYPE_TCP_IPV4 = 0x1, 425 VXGE_HAL_RING_HASH_TYPE_UDP_IPV4 = 0x2, 426 VXGE_HAL_RING_HASH_TYPE_IPV4 = 0x3, 427 VXGE_HAL_RING_HASH_TYPE_TCP_IPV6 = 0x4, 428 VXGE_HAL_RING_HASH_TYPE_UDP_IPV6 = 0x5, 429 VXGE_HAL_RING_HASH_TYPE_IPV6 = 0x6, 430 VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX = 0x7, 431 VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX = 0x8, 432 VXGE_HAL_RING_HASH_TYPE_IPV6_EX = 0x9 433} vxge_hal_ring_hash_type_e; 434 435/* 436 * struct vxge_hal_ring_rxd_1_t - One buffer mode RxD for ring 437 * @host_control: This field is exclusively for host use and is "readonly" 438 * from the adapter's perspective. 439 * @control_0:Bits 0 to 6 - RTH_Bucket get 440 * Bit 7 - Own Descriptor ownership bit. This bit is set to 1 by the 441 * host, and is set to 0 by the adapter. 442 * 0 - Host owns RxD and buffer. 443 * 1 - The adapter owns RxD and buffer. 444 * Bit 8 - Fast_Path_Eligible When set, indicates that the received 445 * frame meets all of the criteria for fast path processing. 446 * The required criteria are as follows: 447 * !SYN & 448 * (Transfer_Code == "Transfer OK") & 449 * (!Is_IP_Fragment) & 450 * ((Is_IPv4 & computed_L3_checksum == 0xFFFF) | 451 * (Is_IPv6)) & 452 * ((Is_TCP & computed_L4_checksum == 0xFFFF) | 453 * (Is_UDP & (computed_L4_checksum == 0xFFFF | 454 * computed _L4_checksum == 0x0000))) 455 * (same meaning for all RxD buffer modes) 456 * Bit 9 - L3 Checksum Correct 457 * Bit 10 - L4 Checksum Correct 458 * Bit 11 - Reserved 459 * Bit 12 to 15 - This field is written by the adapter. It is used 460 * to report the status of the frame transfer to the host. 461 * 0x0 - Transfer OK 462 * 0x4 - RDA Failure During Transfer 463 * 0x5 - Unparseable Packet, such as unknown IPv6 header. 464 * 0x6 - Frame integrity error (FCS or ECC). 465 * 0x7 - Buffer Size Error. The provided buffer(s) were not 466 * appropriately sized and data loss occurred. 467 * 0x8 - Internal ECC Error. RxD corrupted. 468 * 0x9 - IPv4 Checksum error 469 * 0xA - TCP/UDP Checksum error 470 * 0xF - Unknown Error or Multiple Error. Indicates an unknown 471 * problem or that more than one of transfer codes is set. 472 * Bit 16 - SYN The adapter sets this field to indicate that the 473 * incoming frame contained a TCP segment with its SYN bit set 474 * and its ACK bit NOT set. (same meaning for all RxD buffer modes) 475 * Bit 17 - Is ICMP 476 * Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the 477 * Socket 478 * Pair Direct Match Table and the frame was steered based on SPDM. 479 * Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the 480 * Indirection Table and the frame was steered based on hash 481 * indirection. 482 * Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash type) 483 * that was used to calculate the hash. 484 * Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN tagged. 485 * Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation 486 * of the received frame. 487 * 0x0 - Ethernet DIX 488 * 0x1 - LLC 489 * 0x2 - SNAP (includes Jumbo-SNAP) 490 * 0x3 - IPX 491 * Bit 27 - IS_IPV4 Set to '1' if the frame contains IPv4 packet. 492 * Bit 28 - IS_IPV6 Set to '1' if the frame contains IPv6 packet. 493 * Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a 494 * fragmented IP packet. 495 * Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment. 496 * Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message. 497 * Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that 498 * arrived with the frame. If the resulting computed IPv4 header 499 * checksum for the frame did not produce the expected 0xFFFF value, 500 * then the transfer code would be set to 0x9. 501 * Bit 48 to 63 - L4_Checksum[0:15] TCP/UDP checksum value that 502 * arrived with the frame. If the resulting computed TCP/UDP checksum 503 * for the frame did not produce the expected 0xFFFF value, then the 504 * transfer code would be set to 0xA. 505 * @control_1:Bits 0 to 1 - Reserved 506 * Bits 2 to 15 - Buffer0_Size.This field is set by the host and 507 * eventually overwritten by the adapter. The host writes the 508 * available buffer size in bytes when it passes the descriptor to 509 * the adapter. When a frame is delivered the host, the adapter 510 * populates this field with the number of bytes written into the 511 * buffer. The largest supported buffer is 16, 383 bytes. 512 * Bit 16 to 47 - RTH Hash Value 32-bit RTH hash value. Only valid 513 * if RTH_HASH_TYPE (Control_0, bits 20:23) is nonzero. 514 * Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable 515 * portion of the VLAN tag, if one was detected by the adapter. 516 * This field is populated even if VLAN-tag stripping is enabled. 517 * @buffer0_ptr: Pointer to buffer. This field is populated by the driver. 518 * 519 * One buffer mode RxD for ring structure 520 */ 521typedef struct vxge_hal_ring_rxd_1_t { 522 u64 host_control; 523 u64 control_0; 524#define VXGE_HAL_RING_RXD_RTH_BUCKET_GET(ctrl0) bVAL7(ctrl0, 0) 525#define VXGE_HAL_RING_RXD_RTH_BUCKET_ADAPTER vBIT(val, 0, 7) 526 527#define VXGE_HAL_RING_RXD_LIST_OWN_GET(ctrl0) bVAL1(ctrl0, 7) 528#define VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER mBIT(7) 529 530#define VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0) bVAL1(ctrl0, 8) 531#define VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE mBIT(8) 532 533#define VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) bVAL1(ctrl0, 9) 534#define VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT mBIT(9) 535 536#define VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) bVAL1(ctrl0, 10) 537#define VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT mBIT(10) 538 539#define VXGE_HAL_RING_RXD_T_CODE_GET(ctrl0) bVAL4(ctrl0, 12) 540#define VXGE_HAL_RING_RXD_T_CODE(val) vBIT(val, 12, 4) 541#define VXGE_HAL_RING_RXD_T_CODE_OK VXGE_HAL_RING_T_CODE_OK 542#define VXGE_HAL_RING_RXD_T_CODE_L3_CKSUM_MISMATCH \ 543 VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH 544#define VXGE_HAL_RING_RXD_T_CODE_L4_CKSUM_MISMATCH \ 545 VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH 546#define VXGE_HAL_RING_RXD_T_CODE_L3_L4_CKSUM_MISMATCH \ 547 VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH 548#define VXGE_HAL_RING_RXD_T_CODE_L3_PKT_ERR VXGE_HAL_RING_T_CODE_L3_PKT_ERR 549#define VXGE_HAL_RING_RXD_T_CODE_L2_FRM_ERR VXGE_HAL_RING_T_CODE_L2_FRM_ERR 550#define VXGE_HAL_RING_RXD_T_CODE_BUF_SIZE_ERR \ 551 VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR 552#define VXGE_HAL_RING_RXD_T_CODE_INT_ECC_ERR VXGE_HAL_RING_T_CODE_INT_ECC_ERR 553#define VXGE_HAL_RING_RXD_T_CODE_BENIGN_OVFLOW \ 554 VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW 555#define VXGE_HAL_RING_RXD_T_CODE_ZERO_LEN_BUFF \ 556 VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF 557#define VXGE_HAL_RING_RXD_T_CODE_FRM_DROP VXGE_HAL_RING_T_CODE_FRM_DROP 558#define VXGE_HAL_RING_RXD_T_CODE_UNUSED VXGE_HAL_RING_T_CODE_UNUSED 559#define VXGE_HAL_RING_RXD_T_CODE_MULTI_ERR VXGE_HAL_RING_T_CODE_MULTI_ERR 560 561#define VXGE_HAL_RING_RXD_SYN_GET(ctrl0) bVAL1(ctrl0, 16) 562#define VXGE_HAL_RING_RXD_SYN mBIT(16) 563 564#define VXGE_HAL_RING_RXD_IS_ICMP_GET(ctrl0) bVAL1(ctrl0, 17) 565#define VXGE_HAL_RING_RXD_IS_ICMP mBIT(17) 566 567#define VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(ctrl0) bVAL1(ctrl0, 18) 568#define VXGE_HAL_RING_RXD_RTH_SPDM_HIT mBIT(18) 569 570#define VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(ctrl0) bVAL1(ctrl0, 19) 571#define VXGE_HAL_RING_RXD_RTH_IT_HIT mBIT(19) 572 573#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(ctrl0) bVAL4(ctrl0, 20) 574#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE(val) vBIT(val, 20, 4) 575#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_NONE VXGE_HAL_RING_HASH_TYPE_NONE 576#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV4 \ 577 VXGE_HAL_RING_HASH_TYPE_TCP_IPV4 578#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV4 \ 579 VXGE_HAL_RING_HASH_TYPE_UDP_IPV4 580#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV4 VXGE_HAL_RING_HASH_TYPE_IPV4 581#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6 \ 582 VXGE_HAL_RING_HASH_TYPE_TCP_IPV6 583#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6 \ 584 VXGE_HAL_RING_HASH_TYPE_UDP_IPV6 585#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6 VXGE_HAL_RING_HASH_TYPE_IPV6 586#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6_EX \ 587 VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX 588#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6_EX \ 589 VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX 590#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6_EX VXGE_HAL_RING_HASH_TYPE_IPV6_EX 591 592#define VXGE_HAL_RING_RXD_IS_VLAN_GET(ctrl0) bVAL1(ctrl0, 24) 593#define VXGE_HAL_RING_RXD_IS_VLAN mBIT(24) 594 595#define VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(ctrl0) bVAL2(ctrl0, 25) 596#define VXGE_HAL_RING_RXD_ETHER_ENCAP(val) vBIT(val, 25, 2) 597#define VXGE_HAL_RING_RXD_ETHER_ENCAP_DIX VXGE_HAL_FRAME_TYPE_DIX 598#define VXGE_HAL_RING_RXD_ETHER_ENCAP_LLC VXGE_HAL_FRAME_TYPE_LLC 599#define VXGE_HAL_RING_RXD_ETHER_ENCAP_SNAP VXGE_HAL_FRAME_TYPE_SNAP 600#define VXGE_HAL_RING_RXD_ETHER_ENCAP_IPX VXGE_HAL_FRAME_TYPE_IPX 601 602#define VXGE_HAL_RING_RXD_IS_IPV4_GET(ctrl0) bVAL1(ctrl0, 27) 603#define VXGE_HAL_RING_RXD_IS_IPV4 mBIT(27) 604 605#define VXGE_HAL_RING_RXD_IS_IPV6_GET(ctrl0) bVAL1(ctrl0, 28) 606#define VXGE_HAL_RING_RXD_IS_IPV6 mBIT(28) 607 608#define VXGE_HAL_RING_RXD_IS_IPV_FRAG_GET(ctrl0) bVAL1(ctrl0, 29) 609#define VXGE_HAL_RING_RXD_IS_IPV_FRAG mBIT(29) 610 611#define VXGE_HAL_RING_RXD_IS_TCP_GET(ctrl0) bVAL1(ctrl0, 30) 612#define VXGE_HAL_RING_RXD_IS_TCP mBIT(30) 613 614#define VXGE_HAL_RING_RXD_IS_UDP_GET(ctrl0) bVAL1(ctrl0, 31) 615#define VXGE_HAL_RING_RXD_IS_UDP mBIT(31) 616 617#define VXGE_HAL_RING_RXD_FRAME_PROTO_GET(ctrl0) bVAL5(ctrl0, 27) 618#define VXGE_HAL_RING_RXD_FRAME_PROTO(val) vBIT(val, 27, 5) 619#define VXGE_HAL_RING_RXD_FRAME_PROTO_IPV4 VXGE_HAL_FRAME_PROTO_IPV4 620#define VXGE_HAL_RING_RXD_FRAME_PROTO_IPV6 VXGE_HAL_FRAME_PROTO_IPV6 621#define VXGE_HAL_RING_RXD_FRAME_PROTO_IP_FRAG VXGE_HAL_FRAME_PROTO_IP_FRAG 622#define VXGE_HAL_RING_RXD_FRAME_PROTO_TCP VXGE_HAL_FRAME_PROTO_TCP 623#define VXGE_HAL_RING_RXD_FRAME_PROTO_UDP VXGE_HAL_FRAME_PROTO_UDP 624#define VXGE_HAL_RING_RXD_FRAME_PROTO_TCP_OR_UDP (VXGE_HAL_FRAME_PROTO_TCP |\ 625 VXGE_HAL_FRAME_PROTO_UDP) 626 627#define VXGE_HAL_RING_RXD_L3_CKSUM_GET(ctrl0) bVAL16(ctrl0, 32) 628#define VXGE_HAL_RING_RXD_L3_CKSUM(val) vBIT(val, 32, 16) 629 630#define VXGE_HAL_RING_RXD_L4_CKSUM_GET(ctrl0) bVAL16(ctrl0, 48) 631#define VXGE_HAL_RING_RXD_L4_CKSUM(val) vBIT(val, 48, 16) 632 633 u64 control_1; 634#define VXGE_HAL_RING_RXD_LIST_TAIL_OWN_ADAPTER mBIT(0) 635 636#define VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_GET(ctrl1) bVAL14(ctrl1, 2) 637#define VXGE_HAL_RING_RXD_1_BUFFER0_SIZE(val) vBIT(val, 2, 14) 638#define VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_MASK vBIT(0x3FFF, 2, 14) 639 640#define VXGE_HAL_RING_RXD_1_RTH_HASH_VAL_GET(ctrl1) bVAL32(ctrl1, 16) 641#define VXGE_HAL_RING_RXD_1_RTH_HASH_VAL(val) vBIT(val, 16, 32) 642 643#define VXGE_HAL_RING_RXD_VLAN_TAG_GET(ctrl1) bVAL16(ctrl1, 48) 644#define VXGE_HAL_RING_RXD_VLAN_TAG(val) vBIT(val, 48, 16) 645 646 u64 buffer0_ptr; 647 648} vxge_hal_ring_rxd_1_t; 649 650/* 651 * struct vxge_hal_ring_rxd_3_t - Three buffer mode RxD for ring 652 * @host_control: This field is exclusively for host use and is "readonly" 653 * from the adapter's perspective. 654 * @control_0:Bits 0 to 6 - RTH_Bucket get 655 * Bit 7 - Own Descriptor ownership bit. This bit is set to 1 656 * by the host, and is set to 0 by the adapter. 657 * 0 - Host owns RxD and buffer. 658 * 1 - The adapter owns RxD and buffer. 659 * Bit 8 - Fast_Path_Eligible When set, indicates that the 660 * received frame meets all of the criteria for fast path processing. 661 * The required criteria are as follows: 662 * !SYN & 663 * (Transfer_Code == "Transfer OK") & 664 * (!Is_IP_Fragment) & 665 * ((Is_IPv4 & computed_L3_checksum == 0xFFFF) | 666 * (Is_IPv6)) & 667 * ((Is_TCP & computed_L4_checksum == 0xFFFF) | 668 * (Is_UDP & (computed_L4_checksum == 0xFFFF | 669 * computed _L4_checksum == 0x0000))) 670 * (same meaning for all RxD buffer modes) 671 * Bit 9 - L3 Checksum Correct 672 * Bit 10 - L4 Checksum Correct 673 * Bit 11 - Reserved 674 * Bit 12 to 15 - This field is written by the adapter. It is used 675 * to report the status of the frame transfer to the host. 676 * 0x0 - Transfer OK 677 * 0x4 - RDA Failure During Transfer 678 * 0x5 - Unparseable Packet, such as unknown IPv6 header. 679 * 0x6 - Frame integrity error (FCS or ECC). 680 * 0x7 - Buffer Size Error. The provided buffer(s) were not 681 * appropriately sized and data loss occurred. 682 * 0x8 - Internal ECC Error. RxD corrupted. 683 * 0x9 - IPv4 Checksum error 684 * 0xA - TCP/UDP Checksum error 685 * 0xF - Unknown Error or Multiple Error. Indicates an unknown 686 * problem or that more than one of transfer codes is set. 687 * Bit 16 - SYN The adapter sets this field to indicate that the 688 * incoming frame contained a TCP segment with its SYN bit set 689 * and its ACK bit NOT set. (same meaning for all RxD buffer modes) 690 * Bit 17 - Is ICMP 691 * Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the 692 * Socket 693 * Pair Direct Match Table and the frame was steered based on SPDM. 694 * Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the 695 * Indirection Table and the frame was steered based on hash 696 * indirection. 697 * Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash type) 698 * that was used to calculate the hash. 699 * Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN tagged. 700 * Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation 701 * of the received frame. 702 * 0x0 - Ethernet DIX 703 * 0x1 - LLC 704 * 0x2 - SNAP (includes Jumbo-SNAP) 705 * 0x3 - IPX 706 * Bit 27 - IS_IPV4 Set to '1' if the frame contains IPv4 packet. 707 * Bit 28 - IS_IPV6 Set to '1' if the frame contains IPv6 packet. 708 * Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a 709 * fragmented IP packet. 710 * Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment. 711 * Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message. 712 * Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that 713 * arrived with the frame. If the resulting computed IPv4 header 714 * checksum for the frame did not produce the expected 0xFFFF value, 715 * then the transfer code would be set to 0x9. 716 * Bit 48 to 63 - L4_Checksum[0:15] TCP/UDP checksum value that 717 * arrived with the frame. If the resulting computed TCP/UDP checksum 718 * for the frame did not produce the expected 0xFFFF value, then the 719 * transfer code would be set to 0xA. 720 * @control_1:Bit 0 - This field must be used in conjunction with the Ownership 721 * field (above). 722 * 1 - Set by the host to indicate that the RxD points to fresh 723 * buffers. 724 * 0 - Cleared by the adapter to indicate that frame data has been 725 * placed into the assigned buffers, and that the host once again 726 * owns the descriptor. 727 * (Note: Please observe the usage guidelines outlined in the 728 * Ownership field (above)). 729 * Bit 1 - Unused. Ignored by Adapter on RxD read. Set to 0 730 * by Adapter on RxD write. 731 * Bits 2 to 15 - This field is written by the host and by X3100. 732 * The host writes the available buffer 0 size in bytes when it 733 * passes the descriptor to the X3100. The X3100 writes the number 734 * of bytes written to the buffer when it passes the descriptor back 735 * to the host. 736 * Bits 16 to 17 - Reserved 737 * Bits 18 to 31 - This field is set by the host and eventually 738 * overwritten by the adapter. The host writes the available 739 * buffer 1size in bytes when it passes the descriptor to the adapter. 740 * When a frame is delivered the host, the adapter populates this field 741 * with the number of bytes written into the buffer 1. The largest 742 * supported buffer is 16, 383 bytes. 743 * Bits 32 to 33 - Reserved 744 * Bits 34 to 47 - This field is set by the host and eventually 745 * overwritten by the adapter. The host writes the available 746 * buffer 2 size in bytes when it passes the descriptor to the adapter. 747 * When a frame is delivered the host, the adapter populates this field 748 * with the number of bytes written into the buffer 2. The largest 749 * supported buffer is 16, 383 bytes. 750 * Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable 751 * portion of the VLAN tag, if one was detected by the adapter. This 752 * field is populated even if VLAN-tag stripping is enabled. 753 * @buffer0_ptr: Pointer to buffer 0. This field is populated by the driver. 754 * In 3-buffer mode, when the RxD is returned to the host, 755 * buffer0_ptr field will be overwritten if the following conditions 756 * are met: 757 * 1 - RTH_Disable in the PRC_CTRL register is not set. 758 * 2 - RTH is enabled and a valid hash value was calculated for the 759 * frame. This will be indicated by a non-zero value in the 760 * RTH_HASH_TYPE field (Control_0, bits 20:23). In the event that the 761 * pointer is overwritten on return to the host, bits 0:31 will be 762 * all zeroes while bits 32:63 will contain the calculated hash value. 763 * @buffer1_ptr: Pointer to buffer 1. This field is populated by the driver. 764 * @buffer2_ptr: Pointer to buffer 2. This field is populated by the driver. 765 * 766 * Three buffer mode RxD for ring structure 767 */ 768typedef struct vxge_hal_ring_rxd_3_t { 769 u64 host_control; 770 u64 control_0; 771/* 772 * The following bit fields are common in all the three buffer modes and are 773 * defined in vxge_hal_ring_rxd_1_t 774 * #define VXGE_HAL_RING_RXD_RTH_BUCKET_GET(ctrl0) bVAL7(ctrl0, 0) 775 * #define VXGE_HAL_RING_RXD_RTH_BUCKET_ADAPTER vBIT(val, 0, 7) 776 * 777 * #define VXGE_HAL_RING_RXD_LIST_OWN_GET(ctrl0) bVAL1(ctrl0, 7) 778 * #define VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER mBIT(7) 779 * 780 * #define VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0) \ 781 * bVAL1(ctrl0, 8) 782 * #define VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE mBIT(8) 783 * 784 * #define VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) \ 785 * bVAL1(ctrl0, 9) 786 * #define VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT mBIT(9) 787 * 788 * #define VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) \ 789 * bVAL1(ctrl0, 10) 790 * #define VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT mBIT(10) 791 * 792 * #define VXGE_HAL_RING_RXD_T_CODE_GET(ctrl0) bVAL4(ctrl0, 12) 793 * #define VXGE_HAL_RING_RXD_T_CODE(val) vBIT(val, 12, 4) 794 * #define VXGE_HAL_RING_RXD_T_CODE_OK VXGE_HAL_RING_T_CODE_OK 795 * #define VXGE_HAL_RING_RXD_T_CODE_L3_CKSUM_MISMATCH \ 796 * VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH 797 * #define VXGE_HAL_RING_RXD_T_CODE_L4_CKSUM_MISMATCH \ 798 * VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH 799 * #define VXGE_HAL_RING_RXD_T_CODE_L3_L4_CKSUM_MISMATCH \ 800 * VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH 801 * #define VXGE_HAL_RING_RXD_T_CODE_L3_PKT_ERR \ 802 * VXGE_HAL_RING_T_CODE_L3_PKT_ERR 803 * #define VXGE_HAL_RING_RXD_T_CODE_L2_FRM_ERR \ 804 * VXGE_HAL_RING_T_CODE_L2_FRM_ERR 805 * #define VXGE_HAL_RING_RXD_T_CODE_BUF_SIZE_ERR \ 806 * VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR 807 * #define VXGE_HAL_RING_RXD_T_CODE_INT_ECC_ERR \ 808 * VXGE_HAL_RING_T_CODE_INT_ECC_ERR 809 * #define VXGE_HAL_RING_RXD_T_CODE_BENIGN_OVFLOW \ 810 * VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW 811 * #define VXGE_HAL_RING_RXD_T_CODE_ZERO_LEN_BUFF \ 812 * VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF 813 * #define VXGE_HAL_RING_RXD_T_CODE_FRM_DROP VXGE_HAL_RING_T_CODE_FRM_DROP 814 * #define VXGE_HAL_RING_RXD_T_CODE_UNUSED VXGE_HAL_RING_T_CODE_UNUSED 815 * #define VXGE_HAL_RING_RXD_T_CODE_MULTI_ERR \ 816 * VXGE_HAL_RING_T_CODE_MULTI_ERR 817 * 818 * #define VXGE_HAL_RING_RXD_SYN_GET(ctrl0) bVAL1(ctrl0, 16) 819 * #define VXGE_HAL_RING_RXD_SYN mBIT(16) 820 * 821 * #define VXGE_HAL_RING_RXD_IS_ICMP_GET(ctrl0) bVAL1(ctrl0, 17) 822 * #define VXGE_HAL_RING_RXD_IS_ICMP mBIT(17) 823 * 824 * #define VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(ctrl0) bVAL1(ctrl0, 18) 825 * #define VXGE_HAL_RING_RXD_RTH_SPDM_HIT mBIT(18) 826 * 827 * #define VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(ctrl0) bVAL1(ctrl0, 19) 828 * #define VXGE_HAL_RING_RXD_RTH_IT_HIT mBIT(19) 829 * 830 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(ctrl0) bVAL4(ctrl0, 20) 831 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE(val) vBIT(val, 20, 4) 832 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_NONE \ 833 * VXGE_HAL_RING_HASH_TYPE_NONE 834 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV4 \ 835 * VXGE_HAL_RING_HASH_TYPE_TCP_IPV4 836 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV4 \ 837 * VXGE_HAL_RING_HASH_TYPE_UDP_IPV4 838 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV4 \ 839 * VXGE_HAL_RING_HASH_TYPE_IPV4 840 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6 \ 841 * VXGE_HAL_RING_HASH_TYPE_TCP_IPV6 842 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6 \ 843 * VXGE_HAL_RING_HASH_TYPE_UDP_IPV6 844 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6 \ 845 * VXGE_HAL_RING_HASH_TYPE_IPV6 846 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6_EX \ 847 * VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX 848 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6_EX \ 849 * VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX 850 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6_EX \ 851 * VXGE_HAL_RING_HASH_TYPE_IPV6_EX 852 * 853 * #define VXGE_HAL_RING_RXD_IS_VLAN_GET(ctrl0) bVAL1(ctrl0, 24) 854 * #define VXGE_HAL_RING_RXD_IS_VLAN mBIT(24) 855 * 856 * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(ctrl0) bVAL2(ctrl0, 25) 857 * #define VXGE_HAL_RING_RXD_ETHER_ENCAP(val) vBIT(val, 25, 2) 858 * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_DIX VXGE_HAL_FRAME_TYPE_DIX 859 * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_LLC VXGE_HAL_FRAME_TYPE_LLC 860 * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_SNAP VXGE_HAL_FRAME_TYPE_SNAP 861 * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_IPX VXGE_HAL_FRAME_TYPE_IPX 862 * 863 * #define VXGE_HAL_RING_RXD_IS_IPV4_GET(ctrl0) bVAL1(ctrl0, 27) 864 * #define VXGE_HAL_RING_RXD_IS_IPV4 mBIT(27) 865 * 866 * #define VXGE_HAL_RING_RXD_IS_IPV6_GET(ctrl0) bVAL1(ctrl0, 28) 867 * #define VXGE_HAL_RING_RXD_IS_IPV6 mBIT(28) 868 * 869 * #define VXGE_HAL_RING_RXD_IS_IPV_FRAG_GET(ctrl0) bVAL1(ctrl0, 29) 870 * #define VXGE_HAL_RING_RXD_IS_IPV_FRAG mBIT(29) 871 * 872 * #define VXGE_HAL_RING_RXD_IS_TCP_GET(ctrl0) bVAL1(ctrl0, 30) 873 * #define VXGE_HAL_RING_RXD_IS_TCP mBIT(30) 874 * 875 * #define VXGE_HAL_RING_RXD_IS_UDP_GET(ctrl0) bVAL1(ctrl0, 31) 876 * #define VXGE_HAL_RING_RXD_IS_UDP mBIT(31) 877 * 878 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_GET(ctrl0) bVAL5(ctrl0, 27) 879 * #define VXGE_HAL_RING_RXD_FRAME_PROTO(val) vBIT(val, 27, 5) 880 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_IPV4 \ 881 * VXGE_HAL_FRAME_PROTO_IPV4 882 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_IPV6 \ 883 * VXGE_HAL_FRAME_PROTO_IPV6 884 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_IP_FRAG \ 885 * VXGE_HAL_FRAME_PROTO_IP_FRAG 886 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_TCP \ 887 * VXGE_HAL_FRAME_PROTO_TCP 888 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_UDP \ 889 * VXGE_HAL_FRAME_PROTO_UDP 890 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_TCP_OR_UDP \ 891 * (VXGE_HAL_FRAME_PROTO_TCP | VXGE_HAL_FRAME_PROTO_UDP) 892 * 893 * #define VXGE_HAL_RING_RXD_L3_CKSUM_GET(ctrl0) bVAL16(ctrl0, 32) 894 * #define VXGE_HAL_RING_RXD_L3_CKSUM(val) vBIT(val, 32, 16) 895 * 896 * #define VXGE_HAL_RING_RXD_L4_CKSUM_GET(ctrl0) bVAL16(ctrl0, 48) 897 * #define VXGE_HAL_RING_RXD_L4_CKSUM(val) vBIT(val, 48, 16) 898 */ 899 900 u64 control_1; 901#define VXGE_HAL_RING_RXD_3_BUFFER_EMPTY_GET(ctrl1) bVAL1(ctrl1, 0) 902#define VXGE_HAL_RING_RXD_3_BUFFER_EMPTY mBIT(0) 903 904#define VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_GET(ctrl1) bVAL14(ctrl1, 2) 905#define VXGE_HAL_RING_RXD_3_BUFFER0_SIZE(val) vBIT(val, 2, 14) 906#define VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_MASK vBIT(0x3FFc, 2, 14) 907 908#define VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_GET(ctrl1) bVAL14(ctrl1, 18) 909#define VXGE_HAL_RING_RXD_3_BUFFER1_SIZE(val) vBIT(val, 18, 14) 910#define VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_MASK vBIT(0x3FFc, 18, 14) 911 912#define VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_GET(ctrl1) bVAL14(ctrl1, 34) 913#define VXGE_HAL_RING_RXD_3_BUFFER2_SIZE(val) vBIT(val, 34, 14) 914#define VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_MASK vBIT(0x3FFc, 34, 14) 915 916/* 917 * The following bit fields are common in all the three buffer modes and are 918 * defined in vxge_hal_ring_rxd_1_t 919 * #define VXGE_HAL_RING_RXD_VLAN_TAG_GET(ctrl1) bVAL16(ctrl1, 48) 920 * #define VXGE_HAL_RING_RXD_VLAN_TAG(val) vBIT(val, 48, 16) 921 */ 922 u64 buffer0_ptr; 923#define VXGE_HAL_RING_RXD_3_RTH_HASH_VALUE_GET(b0_ptr) bVAL32(b0_ptr, 32) 924#define VXGE_HAL_RING_RXD_3_RTH_HASH_VALUE(val) vBIT(val, 32, 32) 925 926 u64 buffer1_ptr; 927 928 u64 buffer2_ptr; 929 930} vxge_hal_ring_rxd_3_t; 931 932/* 933 * struct vxge_hal_ring_rxd_5_t - Five buffer mode RxD for ring 934 * @host_control: This 32 bitfield is exclusively for host use and is "readonly" 935 * from the adapter's perspective. 936 * @control_2: Bits 0 to 1 - Reserved 937 * Bits 2 to 15 - This field is set by the host and eventually 938 * overwritten by the adapter. The host writes the available buffer 939 * 3 size in bytes when it pas ses the descriptor to the adapter. 940 * When a frame is delivered the host, the adapter populates this 941 * field with the number of bytes written into the buffer. The 942 * largest supported buffer is 16, 383 bytes. 943 * Bits 16 to 17 - Reserved 944 * Bits 18 to 31 - This field is set by the host and eventually 945 * overwritten by the adapter. The host writes the available buffer 946 * 4 size in bytes when it passes the descriptor to the adapter. 947 * When a frame is delivered the host, the adapter populates this 948 * field with the number of bytes written into the buffer. 949 * The largest supported buffer is 16, 383 bytes. 950 * @control_0: Bits 0 to 6 - RTH_Bucket get 951 * Bit 7 - Own Descriptor ownership bit. This bit is set to 1 by 952 * the host, and is set to 0 by the adapter. 953 * 0 - Host owns RxD and buffer. 954 * 1 - The adapter owns RxD and buffer. 955 * Bit 8 - Fast_Path_Eligible When set,indicates that the received 956 * frame meets all of the criteria for fast path processing. 957 * The required criteria are as follows: 958 * !SYN & 959 * (Transfer_Code == "Transfer OK") & 960 * (!Is_IP_Fragment) & 961 * ((Is_IPv4 & computed_L3_checksum == 0xFFFF) | 962 * (Is_IPv6)) & 963 * ((Is_TCP & computed_L4_checksum == 0xFFFF) | 964 * (Is_UDP & (computed_L4_checksum == 0xFFFF | 965 * computed _L4_checksum == 0x0000))) 966 * (same meaning for all RxD buffer modes) 967 * Bit 9 - L3 Checksum Correct 968 * Bit 10 - L4 Checksum Correct 969 * Bit 11 - Reserved 970 * Bit 12 to 15 - This field is written by the adapter. It is used 971 * to report the status of the frame transfer to the host. 972 * 0x0 - Transfer OK 973 * 0x4 - RDA Failure During Transfer 974 * 0x5 - Unparseable Packet, such as unknown IPv6 header. 975 * 0x6 - Frame integrity error (FCS or ECC). 976 * 0x7 - Buffer Size Error. The provided buffer(s) were not 977 * appropriately sized and data loss occurred. 978 * 0x8 - Internal ECC Error. RxD corrupted. 979 * 0x9 - IPv4 Checksum error 980 * 0xA - TCP/UDP Checksum error 981 * 0xF - Unknown Error or Multiple Error. Indicates an unknown 982 * problem or that more than one of transfer codes is set. 983 * Bit 16 - SYN The adapter sets this field to indicate that the 984 * incoming frame contained a TCP segment with its SYN bit set 985 * and its ACK bit NOT set. (same meaning for all RxD buffer modes) 986 * Bit 17 - Is ICMP 987 * Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the 988 * Socket Pair Direct Match Table and the frame was steered based on 989 * SPDM. 990 * Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the 991 * Indirection Table and the frame was steered based on hash 992 * indirection. 993 * Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash type) 994 * that was used to calculate the hash. 995 * Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN tagged. 996 * Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation 997 * of the received frame. 998 * 0x0 - Ethernet DIX 999 * 0x1 - LLC 1000 * 0x2 - SNAP (includes Jumbo-SNAP) 1001 * 0x3 - IPX 1002 * Bit 27 - IS_IPV4 Set to '1' if the frame contains IPv4 packet. 1003 * Bit 28 - IS_IPV6 Set to '1' if the frame contains IPv6 packet. 1004 * Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a 1005 * fragmented IP packet. 1006 * Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment. 1007 * Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message. 1008 * Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that 1009 * arrived with the frame. If the resulting computed IPv4 header 1010 * checksum for the frame did not produce the expected 0xFFFF value, 1011 * then the transfer code would be set to 0x9. 1012 * Bit 48 to 63 - L4_Checksum[0:15] TCP/UDP checksum value that 1013 * arrived with the frame. If the resulting computed TCP/UDP checksum 1014 * for the frame did not produce the expected 0xFFFF value, then the 1015 * transfer code would be set to 0xA. 1016 * @control_1: Bits 0 to 1 - Reserved. 1017 * Bits 2 to 15 - This field is written by the host and by X3100. 1018 * The host writes the available buffer 0 size in bytes when it 1019 * passes the descriptor to the X3100. The X3100 writes the number 1020 * of bytes written to the buffer when it passes the descriptor back 1021 * to the host. 1022 * Bits 16 to 17 - Reserved 1023 * Bits 18 to 31 - This field is set by the host and eventually 1024 * overwritten by the adapter. The host writes the available 1025 * buffer 1 size in bytes when it passes the descriptor to the adapter. 1026 * When a frame is delivered the host, the adapter populates this field 1027 * with the number of bytes written into the buffer 1. The largest 1028 * supported buffer is 16, 383 bytes. 1029 * Bits 32 to 33 - Reserved 1030 * Bits 34 to 47 - This field is set by the host and eventually 1031 * overwritten by the adapter. The host writes the available 1032 * buffer 2 size in bytes when it passes the descriptor to the adapter. 1033 * When a frame is delivered the host, the adapter populates this field 1034 * with the number of bytes written into the buffer 2. The largest 1035 * supported buffer is 16, 383 bytes. 1036 * Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable 1037 * portion of the VLAN tag, if one was detected by the adapter. This 1038 * field is populated even if VLAN-tag stripping is enabled. 1039 * @buffer0_ptr: Pointer to buffer 0. This field is populated by the driver. 1040 * In 5-buffer mode, when the RxD is returned to the host, 1041 * buffer0_ptr field will be overwritten if the following conditions 1042 * are met: 1043 * 1 - RTH_Disable in the PRC_CTRL register is not set. 1044 * 2 - RTH is enabled and a valid hash value was calculated for the 1045 * frame. This will be indicated by a non-zero value in the 1046 * RTH_HASH_TYPE field (Control_0, bits 20:23). In the event that the 1047 * pointer is overwritten on return to the host, bits 0:31 will be 1048 * all zeroes while bits 32:63 will contain the calculated hash value. 1049 * @buffer1_ptr: Pointer to buffer 1. This field is populated by the driver. 1050 * @buffer2_ptr: Pointer to buffer 2. This field is populated by the driver. 1051 * @buffer3_ptr: Pointer to buffer 3. This field is populated by the driver. 1052 * @buffer4_ptr: Pointer to buffer 4. This field is populated by the driver. 1053 * @pad: Pad to align at cache line boundary 1054 * 1055 * Three buffer mode RxD for ring structure 1056 */ 1057typedef struct vxge_hal_ring_rxd_5_t { 1058#if defined(VXGE_OS_HOST_BIG_ENDIAN) 1059 u32 host_control; 1060 u32 control_2; 1061#else 1062 u32 control_2; 1063 u32 host_control; 1064#endif 1065 1066#define VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_GET(ctrl2) bVAL14(ctrl2, 34) 1067#define VXGE_HAL_RING_RXD_5_BUFFER3_SIZE(val) vBIT(val, 34, 14) 1068#define VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_MASK vBIT(0x3FFF, 34, 14) 1069 1070#define VXGE_HAL_RING_RXD_5_BUFFER4_SIZE_GET(ctrl2) bVAL14(ctrl2, 50) 1071#define VXGE_HAL_RING_RXD_5_BUFFER4_SIZE(val) vBIT(val, 50, 14) 1072#define VXGE_HAL_RING_RXD_5_BUFFER4_SIZE_MASK vBIT(0x3FFF, 50, 14) 1073 1074 1075 u64 control_0; 1076/* 1077 * The following bit fields are common in all the three buffer modes and are 1078 * defined in vxge_hal_ring_rxd_1_t 1079 * #define VXGE_HAL_RING_RXD_RTH_BUCKET_GET(ctrl0) bVAL7(ctrl0, 0) 1080 * #define VXGE_HAL_RING_RXD_RTH_BUCKET_ADAPTER vBIT(val, 0, 7) 1081 * 1082 * #define VXGE_HAL_RING_RXD_LIST_OWN_GET(ctrl0) bVAL1(ctrl0, 7) 1083 * #define VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER mBIT(7) 1084 * 1085 * #define VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0 \ 1086 * bVAL1(ctrl0, 8) 1087 * #define VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE mBIT(8) 1088 * 1089 * #define VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) \ 1090 * bVAL1(ctrl0, 9) 1091 * #define VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT mBIT(9) 1092 * 1093 * #define VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) \ 1094 * bVAL1(ctrl0, 10) 1095 * #define VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT mBIT(10) 1096 * 1097 * #define VXGE_HAL_RING_RXD_T_CODE_GET(ctrl0) bVAL4(ctrl0, 12) 1098 * #define VXGE_HAL_RING_RXD_T_CODE(val) vBIT(val, 12, 4) 1099 * #define VXGE_HAL_RING_RXD_T_CODE_OK \ 1100 * VXGE_HAL_RING_T_CODE_OK 1101 * #define VXGE_HAL_RING_RXD_T_CODE_L3_CKSUM_MISMATCH \ 1102 * VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH 1103 * #define VXGE_HAL_RING_RXD_T_CODE_L4_CKSUM_MISMATCH \ 1104 * VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH 1105 * #define VXGE_HAL_RING_RXD_T_CODE_L3_L4_CKSUM_MISMATCH \ 1106 * VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH 1107 * #define VXGE_HAL_RING_RXD_T_CODE_L3_PKT_ERR \ 1108 * VXGE_HAL_RING_T_CODE_L3_PKT_ERR 1109 * #define VXGE_HAL_RING_RXD_T_CODE_L2_FRM_ERR \ 1110 * VXGE_HAL_RING_T_CODE_L2_FRM_ERR 1111 * #define VXGE_HAL_RING_RXD_T_CODE_BUF_SIZE_ERR \ 1112 * VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR 1113 * #define VXGE_HAL_RING_RXD_T_CODE_INT_ECC_ERR \ 1114 * VXGE_HAL_RING_T_CODE_INT_ECC_ERR 1115 * #define VXGE_HAL_RING_RXD_T_CODE_BENIGN_OVFLOW \ 1116 * VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW 1117 * #define VXGE_HAL_RING_RXD_T_CODE_ZERO_LEN_BUFF \ 1118 * VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF 1119 * #define VXGE_HAL_RING_RXD_T_CODE_FRM_DROP \ 1120 * VXGE_HAL_RING_T_CODE_FRM_DROP 1121 * #define VXGE_HAL_RING_RXD_T_CODE_UNUSED \ 1122 * VXGE_HAL_RING_T_CODE_UNUSED 1123 * #define VXGE_HAL_RING_RXD_T_CODE_MULTI_ERR \ 1124 * VXGE_HAL_RING_T_CODE_MULTI_ERR 1125 * 1126 * #define VXGE_HAL_RING_RXD_SYN_GET(ctrl0) bVAL1(ctrl0, 16) 1127 * #define VXGE_HAL_RING_RXD_SYN mBIT(16) 1128 * 1129 * #define VXGE_HAL_RING_RXD_IS_ICMP_GET(ctrl0) bVAL1(ctrl0, 17) 1130 * #define VXGE_HAL_RING_RXD_IS_ICMP mBIT(17) 1131 * 1132 * #define VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(ctrl0) bVAL1(ctrl0, 18) 1133 * #define VXGE_HAL_RING_RXD_RTH_SPDM_HIT mBIT(18) 1134 * 1135 * #define VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(ctrl0) bVAL1(ctrl0, 19) 1136 * #define VXGE_HAL_RING_RXD_RTH_IT_HIT mBIT(19) 1137 * 1138 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(ctrl0) bVAL4(ctrl0, 20) 1139 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE(val) vBIT(val, 20, 4) 1140 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_NONE \ 1141 * VXGE_HAL_RING_HASH_TYPE_NONE 1142 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV4 \ 1143 * VXGE_HAL_RING_HASH_TYPE_TCP_IPV4 1144 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV4 \ 1145 * VXGE_HAL_RING_HASH_TYPE_UDP_IPV4 1146 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV4 \ 1147 * VXGE_HAL_RING_HASH_TYPE_IPV4 1148 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6 \ 1149 * VXGE_HAL_RING_HASH_TYPE_TCP_IPV6 1150 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6 \ 1151 * VXGE_HAL_RING_HASH_TYPE_UDP_IPV6 1152 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6 \ 1153 * VXGE_HAL_RING_HASH_TYPE_IPV6 1154 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6_EX \ 1155 * VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX 1156 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6_EX \ 1157 * VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX 1158 * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6_EX \ 1159 * VXGE_HAL_RING_HASH_TYPE_IPV6_EX 1160 * 1161 * #define VXGE_HAL_RING_RXD_IS_VLAN_GET(ctrl0) bVAL1(ctrl0, 24) 1162 * #define VXGE_HAL_RING_RXD_IS_VLAN mBIT(24) 1163 * 1164 * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(ctrl0) bVAL2(ctrl0, 25) 1165 * #define VXGE_HAL_RING_RXD_ETHER_ENCAP(val) vBIT(val, 25, 2) 1166 * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_DIX VXGE_HAL_FRAME_TYPE_DIX 1167 * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_LLC VXGE_HAL_FRAME_TYPE_LLC 1168 * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_SNAP VXGE_HAL_FRAME_TYPE_SNAP 1169 * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_IPX VXGE_HAL_FRAME_TYPE_IPX 1170 * 1171 * #define VXGE_HAL_RING_RXD_IS_IPV4_GET(ctrl0) bVAL1(ctrl0, 27) 1172 * #define VXGE_HAL_RING_RXD_IS_IPV4 mBIT(27) 1173 * 1174 * #define VXGE_HAL_RING_RXD_IS_IPV6_GET(ctrl0) bVAL1(ctrl0, 28) 1175 * #define VXGE_HAL_RING_RXD_IS_IPV6 mBIT(28) 1176 * 1177 * #define VXGE_HAL_RING_RXD_IS_IPV_FRAG_GET(ctrl0) bVAL1(ctrl0, 29) 1178 * #define VXGE_HAL_RING_RXD_IS_IPV_FRAG mBIT(29) 1179 * 1180 * #define VXGE_HAL_RING_RXD_IS_TCP_GET(ctrl0) bVAL1(ctrl0, 30) 1181 * #define VXGE_HAL_RING_RXD_IS_TCP mBIT(30) 1182 * 1183 * #define VXGE_HAL_RING_RXD_IS_UDP_GET(ctrl0) bVAL1(ctrl0, 31) 1184 * #define VXGE_HAL_RING_RXD_IS_UDP mBIT(31) 1185 * 1186 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_GET(ctrl0) bVAL5(ctrl0, 27) 1187 * #define VXGE_HAL_RING_RXD_FRAME_PROTO(val) vBIT(val, 27, 5) 1188 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_IPV4 VXGE_HAL_FRAME_PROTO_IPV4 1189 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_IPV6 VXGE_HAL_FRAME_PROTO_IPV6 1190 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_IP_FRAG \ 1191 * VXGE_HAL_FRAME_PROTO_IP_FRAG 1192 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_TCP VXGE_HAL_FRAME_PROTO_TCP 1193 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_UDP VXGE_HAL_FRAME_PROTO_UDP 1194 * #define VXGE_HAL_RING_RXD_FRAME_PROTO_TCP_OR_UDP \ 1195 * (VXGE_HAL_FRAME_PROTO_TCP | VXGE_HAL_FRAME_PROTO_UDP) 1196 * 1197 * #define VXGE_HAL_RING_RXD_L3_CKSUM_GET(ctrl0) bVAL16(ctrl0, 32) 1198 * #define VXGE_HAL_RING_RXD_L3_CKSUM(val) vBIT(val, 32, 16) 1199 * 1200 * #define VXGE_HAL_RING_RXD_L4_CKSUM_GET(ctrl0) bVAL16(ctrl0, 48) 1201 * #define VXGE_HAL_RING_RXD_L4_CKSUM(val) vBIT(val, 48, 16) 1202 */ 1203 1204 u64 control_1; 1205 1206#define VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_GET(ctrl1) bVAL14(ctrl1, 2) 1207#define VXGE_HAL_RING_RXD_5_BUFFER0_SIZE(val) vBIT(val, 2, 14) 1208#define VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_MASK vBIT(0x3FFF, 2, 14) 1209 1210#define VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_GET(ctrl1) bVAL14(ctrl1, 18) 1211#define VXGE_HAL_RING_RXD_5_BUFFER1_SIZE(val) vBIT(val, 18, 14) 1212#define VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_MASK vBIT(0x3FFF, 18, 14) 1213 1214#define VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_GET(ctrl1) bVAL14(ctrl1, 34) 1215#define VXGE_HAL_RING_RXD_5_BUFFER2_SIZE(val) vBIT(val, 34, 14) 1216#define VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_MASK vBIT(0xFFFF, 34, 14) 1217 1218/* 1219 * The following bit fields are common in all the three buffer modes and are 1220 * defined in vxge_hal_ring_rxd_1_t 1221 * #define VXGE_HAL_RING_RXD_VLAN_TAG_GET(ctrl1) bVAL16(ctrl1, 48) 1222 * #define VXGE_HAL_RING_RXD_VLAN_TAG(val) vBIT(val, 48, 16) 1223 */ 1224 1225 u64 buffer0_ptr; 1226#define VXGE_HAL_RING_RXD_5_RTH_HASH_VALUE_GET(b0_ptr) bVAL32(b0_ptr, 32) 1227#define VXGE_HAL_RING_RXD_5_RTH_HASH_VALUE(val) vBIT(val, 32, 32) 1228 1229 u64 buffer1_ptr; 1230 u64 buffer2_ptr; 1231 u64 buffer3_ptr; 1232 u64 buffer4_ptr; 1233} vxge_hal_ring_rxd_5_t; 1234 1235/* 1236 * function vxge_hal_ring_callback_f - Ring callback. 1237 * @vpath_handle: Virtual Path whose Ring "containing" 1 or more completed 1238 * descriptors. 1239 * @rxdh: First completed descriptor. 1240 * @rxd_priv: Pointer to per rxd space allocated 1241 * @t_code: Transfer code, as per X3100 User Guide. 1242 * Returned by HAL. 1243 * @userdata: Opaque per-ring data specified at ring open 1244 * time, via vxge_hal_vpath_open(). 1245 * 1246 * ring completion callback (type declaration). A single per-ring 1247 * callback is specified at virtual path open time, via 1248 * vxge_hal_vpath_open(). 1249 * Typically gets called as part of the processing of the Interrupt 1250 * Service Routine. 1251 * 1252 * ring callback gets called by HAL if, and only if, there is at least 1253 * one new completion on a given ring . Upon processing the first @rxdh 1254 * ULD is _supposed_ to continue consuming completions 1255 * using - vxge_hal_ring_rxd_next_completed(). 1256 * 1257 * Note that failure to process new completions in a timely fashion 1258 * leads to VXGE_HAL_INF_OUT_OF_DESCRIPTORS condition. 1259 * 1260 * Non-zero @t_code means failure to process receive descriptor. 1261 * 1262 * In the "transmit" case the failure could happen, for instance, when the 1263 * link is down, in which case X3100 completes the descriptor because it 1264 * is not able to send the data out. 1265 * 1266 * For details please refer to X3100 User Guide. 1267 * 1268 * See also: vxge_hal_ring_rxd_next_completed(), vxge_hal_ring_rxd_term_f {}. 1269 */ 1270typedef vxge_hal_status_e(*vxge_hal_ring_callback_f) ( 1271 vxge_hal_vpath_h vpath_handle, 1272 vxge_hal_rxd_h rxdh, 1273 void *rxd_priv, 1274 u8 t_code, 1275 void *userdata); 1276 1277/* 1278 * function vxge_hal_ring_rxd_init_f - Initialize descriptor callback. 1279 * @vpath_handle: Virtual path whose ring "containing" the @rxdh descriptor. 1280 * @rxdh: Descriptor. 1281 * @rxd_priv: Pointer to per rxd space allocated 1282 * @index: Index of the descriptor in the ring's set of descriptors. 1283 * @userdata: Per-ring user data (a.k.a. context) specified at 1284 * ring open time, via vxge_hal_vpath_open(). 1285 * @reopen: See vxge_hal_reopen_e {}. 1286 * 1287 * Initialize descriptor callback. Unless NULL is specified in the 1288 * vxge_hal_ring_attr_t {} structure passed to vxge_hal_vpath_open()), 1289 * HAL invokes the callback as part of the ring create in vxge_hal_vpath_open() 1290 * implementation. 1291 * The ULD is expected to fill in this descriptor with buffer(s) 1292 * and control information. 1293 * 1294 * See also: vxge_hal_ring_attr_t {}, vxge_hal_ring_rxd_term_f {}. 1295 */ 1296typedef vxge_hal_status_e(*vxge_hal_ring_rxd_init_f) ( 1297 vxge_hal_vpath_h vpath_handle, 1298 vxge_hal_rxd_h rxdh, 1299 void *rxd_priv, 1300 u32 index, 1301 void *userdata, 1302 vxge_hal_reopen_e reopen); 1303 1304/* 1305 * function vxge_hal_ring_rxd_term_f - Terminate descriptor callback. 1306 * @vpath_handle: Virtual path whose ring "containing" the @rxdh descriptor. 1307 * @rxdh: First completed descriptor. 1308 * @rxd_priv: Pointer to per rxd space allocated 1309 * @state: One of the vxge_hal_rxd_state_e {} enumerated states. 1310 * @userdata: Per-ring user data (a.k.a. context) specified at 1311 * ring open time, via vxge_hal_vpath_open(). 1312 * @reopen: See vxge_hal_reopen_e {}. 1313 * 1314 * Terminate descriptor callback. Unless NULL is specified in the 1315 * vxge_hal_ring_attr_t {} structure passed to vxge_hal_vpath_open()), 1316 * HAL invokes the callback as part of closing the corresponding 1317 * ring, prior to de-allocating the ring and associated data 1318 * structures (including descriptors). 1319 * ULD should utilize the callback to (for instance) unmap 1320 * and free DMA data buffers associated with the posted (state = 1321 * VXGE_HAL_RXD_STATE_POSTED) descriptors, 1322 * as well as other relevant cleanup functions. 1323 * 1324 * See also: vxge_hal_ring_attr_t {}, vxge_hal_ring_rxd_init_f {}. 1325 */ 1326typedef void (*vxge_hal_ring_rxd_term_f) ( 1327 vxge_hal_vpath_h vpath_handle, 1328 vxge_hal_rxd_h rxdh, 1329 void *rxd_priv, 1330 vxge_hal_rxd_state_e state, 1331 void *userdata, 1332 vxge_hal_reopen_e reopen); 1333 1334/* 1335 * struct vxge_hal_ring_attr_t - Ring open "template". 1336 * @callback: Ring completion callback. HAL invokes the callback when there 1337 * are new completions on that ring. In many implementations 1338 * the @callback executes in the hw interrupt context. 1339 * @rxd_init: Ring's descriptor-initialize callback. 1340 * See vxge_hal_ring_rxd_init_f {}. 1341 * If not NULL, HAL invokes the callback when opening 1342 * the ring. 1343 * @rxd_term: Ring's descriptor-terminate callback. If not NULL, 1344 * HAL invokes the callback when closing the corresponding ring. 1345 * See also vxge_hal_ring_rxd_term_f {}. 1346 * @userdata: User-defined "context" of _that_ ring. Passed back to the 1347 * user as one of the @callback, @rxd_init, and @rxd_term arguments. 1348 * @per_rxd_space: If specified (i.e., greater than zero): extra space 1349 * reserved by HAL per each receive descriptor. Can be used to store, 1350 * and retrieve on completion, information specific 1351 * to the upper-layer. 1352 * 1353 * Ring open "template". User fills the structure with ring 1354 * attributes and passes it to vxge_hal_vpath_open(). 1355 */ 1356typedef struct vxge_hal_ring_attr_t { 1357 vxge_hal_ring_callback_f callback; 1358 vxge_hal_ring_rxd_init_f rxd_init; 1359 vxge_hal_ring_rxd_term_f rxd_term; 1360 void *userdata; 1361 u32 per_rxd_space; 1362} vxge_hal_ring_attr_t; 1363 1364 1365/* 1366 * vxge_hal_ring_rxd_size_get - Get the size of ring descriptor. 1367 * @buf_mode: Buffer mode (1, 3 or 5) 1368 * 1369 * This function returns the size of RxD for given buffer mode 1370 */ 1371static inline u32 1372/* LINTED */ 1373vxge_hal_ring_rxd_size_get( 1374 u32 buf_mode) 1375{ 1376 return ((u32) (buf_mode == 1 ? sizeof(vxge_hal_ring_rxd_1_t) : \ 1377 (buf_mode == 3 ? sizeof(vxge_hal_ring_rxd_3_t) : \ 1378 sizeof(vxge_hal_ring_rxd_5_t)))); 1379 1380} 1381 1382/* 1383 * vxge_hal_ring_rxds_per_block_get - Get the number of rxds per block. 1384 * @buf_mode: Buffer mode (1, 3 or 5) 1385 * 1386 * This function returns the number of RxD for RxD block for given buffer mode 1387 */ 1388static inline u32 1389/* LINTED */ 1390vxge_hal_ring_rxds_per_block_get( 1391 u32 buf_mode) 1392{ 1393 return ((u32) ((VXGE_OS_HOST_PAGE_SIZE - 16) / 1394 ((buf_mode == 1) ? sizeof(vxge_hal_ring_rxd_1_t) : 1395 ((buf_mode == 3) ? sizeof(vxge_hal_ring_rxd_3_t) : 1396 sizeof(vxge_hal_ring_rxd_5_t))))); 1397} 1398 1399/* 1400 * vxge_hal_ring_rxd_reserve - Reserve ring descriptor. 1401 * @vpath_handle: virtual Path handle. 1402 * @rxdh: Reserved descriptor. On success HAL fills this "out" parameter 1403 * with a valid handle. 1404 * @rxd_priv: Buffer to return the pointer to per rxd space allocated 1405 * 1406 * Reserve Rx descriptor for the subsequent filling-in (by upper layer 1407 * driver (ULD)) and posting on the corresponding ring 1408 * via vxge_hal_ring_rxd_post(). 1409 * 1410 * Returns: VXGE_HAL_OK - success. 1411 * VXGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available. 1412 * 1413 */ 1414vxge_hal_status_e 1415vxge_hal_ring_rxd_reserve( 1416 vxge_hal_vpath_h vpath_handle, 1417 vxge_hal_rxd_h *rxdh, 1418 void **rxd_priv); 1419 1420/* 1421 * vxge_hal_ring_rxd_1b_set - Prepare 1-buffer-mode descriptor. 1422 * @rxdh: Descriptor handle. 1423 * @dma_pointer: DMA address of a single receive buffer this descriptor 1424 * should carry. Note that by the time 1425 * vxge_hal_ring_rxd_1b_set is called, the 1426 * receive buffer should be already mapped 1427 * to the corresponding X3100 device. 1428 * @size: Size of the receive @dma_pointer buffer. 1429 * 1430 * Prepare 1-buffer-mode Rx descriptor for posting 1431 * (via vxge_hal_ring_rxd_post()). 1432 * 1433 * This inline helper-function does not return any parameters and always 1434 * succeeds. 1435 * 1436 */ 1437static inline 1438/* LINTED */ 1439void vxge_hal_ring_rxd_1b_set( 1440 vxge_hal_rxd_h rxdh, 1441 dma_addr_t dma_pointer, 1442 int size) 1443{ 1444 vxge_hal_ring_rxd_1_t *rxdp = (vxge_hal_ring_rxd_1_t *) rxdh; 1445 rxdp->buffer0_ptr = dma_pointer; 1446 rxdp->control_1 &= ~VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_MASK; 1447 rxdp->control_1 |= VXGE_HAL_RING_RXD_1_BUFFER0_SIZE(size); 1448} 1449 1450/* 1451 * vxge_hal_ring_rxd_3b_set - Prepare 3-buffer-mode descriptor. 1452 * @rxdh: Descriptor handle. 1453 * @dma_pointers: Array of DMA addresses. Contains exactly 3 receive buffers 1454 * _this_ descriptor should carry. Note that by the time 1455 * vxge_hal_ring_rxd_3b_set is called, the receive buffers should 1456 * be mapped to the corresponding X3100 device. 1457 * @sizes: Array of receive buffer sizes. Contains 3 sizes: one size per 1458 * buffer from @dma_pointers. 1459 * 1460 * Prepare 3-buffer-mode Rx descriptor for posting (via 1461 * vxge_hal_ring_rxd_post()). 1462 * This inline helper-function does not return any parameters and always 1463 * succeeds. 1464 * 1465 */ 1466static inline 1467/* LINTED */ 1468void vxge_hal_ring_rxd_3b_set( 1469 vxge_hal_rxd_h rxdh, 1470 dma_addr_t dma_pointers[], 1471 u32 sizes[]) 1472{ 1473 vxge_hal_ring_rxd_3_t *rxdp = (vxge_hal_ring_rxd_3_t *) rxdh; 1474 rxdp->buffer0_ptr = dma_pointers[0]; 1475 rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_MASK); 1476 rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER0_SIZE(sizes[0]); 1477 rxdp->buffer1_ptr = dma_pointers[1]; 1478 rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_MASK); 1479 rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER1_SIZE(sizes[1]); 1480 rxdp->buffer2_ptr = dma_pointers[2]; 1481 rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_MASK); 1482 rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER2_SIZE(sizes[2]); 1483} 1484 1485/* 1486 * vxge_hal_ring_rxd_5b_set - Prepare 5-buffer-mode descriptor. 1487 * @rxdh: Descriptor handle. 1488 * @dma_pointers: Array of DMA addresses. Contains exactly 5 receive buffers 1489 * _this_ descriptor should carry. Note that by the time 1490 * vxge_hal_ring_rxd_5b_set is called, the receive buffers should 1491 * be mapped to the corresponding X3100 device. 1492 * @sizes: Array of receive buffer sizes. Contains 5 sizes: one size per buffer 1493 * from @dma_pointers. 1494 * 1495 * Prepare 5-buffer-mode Rx descriptor for posting 1496 * (via vxge_hal_ring_rxd_post()). 1497 * This inline helper-function does not return any 1498 * values and always succeeds. 1499 * 1500 * See also: vxge_hal_ring_rxd_1b_set(), vxge_hal_ring_rxd_3b_set(). 1501 */ 1502static inline 1503/* LINTED */ 1504void vxge_hal_ring_rxd_5b_set( 1505 vxge_hal_rxd_h rxdh, 1506 dma_addr_t dma_pointers[], 1507 u32 sizes[]) 1508{ 1509 vxge_hal_ring_rxd_5_t *rxdp = (vxge_hal_ring_rxd_5_t *) rxdh; 1510 1511 rxdp->buffer0_ptr = dma_pointers[0]; 1512 rxdp->control_1 &= (~VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_MASK); 1513 rxdp->control_1 |= VXGE_HAL_RING_RXD_5_BUFFER0_SIZE(sizes[0]); 1514 rxdp->buffer1_ptr = dma_pointers[1]; 1515 rxdp->control_1 &= (~VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_MASK); 1516 rxdp->control_1 |= VXGE_HAL_RING_RXD_5_BUFFER1_SIZE(sizes[1]); 1517 rxdp->buffer2_ptr = dma_pointers[2]; 1518 rxdp->control_1 &= (~VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_MASK); 1519 rxdp->control_1 |= VXGE_HAL_RING_RXD_5_BUFFER2_SIZE(sizes[2]); 1520 rxdp->buffer3_ptr = dma_pointers[3]; 1521 rxdp->control_2 &= (~VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_MASK); 1522 rxdp->control_2 |= VXGE_HAL_RING_RXD_5_BUFFER3_SIZE(sizes[3]); 1523 rxdp->buffer4_ptr = dma_pointers[4]; 1524 rxdp->control_2 &= (~VXGE_HAL_RING_RXD_5_BUFFER4_SIZE_MASK); 1525 rxdp->control_2 |= VXGE_HAL_RING_RXD_5_BUFFER4_SIZE(sizes[4]); 1526} 1527 1528/* 1529 * vxge_hal_ring_rxd_pre_post - Prepare rxd and post 1530 * @vpath_handle: virtual Path handle. 1531 * @rxdh: Descriptor handle. 1532 * 1533 * This routine prepares a rxd and posts 1534 */ 1535void 1536vxge_hal_ring_rxd_pre_post( 1537 vxge_hal_vpath_h vpath_handle, 1538 vxge_hal_rxd_h rxdh); 1539 1540/* 1541 * vxge_hal_ring_rxd_post_post - Process rxd after post. 1542 * @vpath_handle: virtual Path handle. 1543 * @rxdh: Descriptor handle. 1544 * 1545 * Processes rxd after post 1546 */ 1547void 1548vxge_hal_ring_rxd_post_post( 1549 vxge_hal_vpath_h vpath_handle, 1550 vxge_hal_rxd_h rxdh); 1551 1552/* 1553 * vxge_hal_ring_rxd_post_post_db - Post Doorbell after posting the rxd(s). 1554 * @vpath_handle: virtual Path handle. 1555 * 1556 * Post Doorbell after posting the rxd(s). 1557 */ 1558void 1559vxge_hal_ring_rxd_post_post_db( 1560 vxge_hal_vpath_h vpath_handle); 1561 1562/* 1563 * vxge_hal_ring_rxd_post_post_wmb - Process rxd after post with memory barrier 1564 * @vpath_handle: virtual Path handle. 1565 * @rxdh: Descriptor handle. 1566 * 1567 * Processes rxd after post with memory barrier. 1568 */ 1569void 1570vxge_hal_ring_rxd_post_post_wmb( 1571 vxge_hal_vpath_h vpath_handle, 1572 vxge_hal_rxd_h rxdh); 1573 1574/* 1575 * vxge_hal_ring_rxd_post - Post descriptor on the ring. 1576 * @vpath_handle: virtual Path handle. 1577 * @rxdh: Descriptor obtained via vxge_hal_ring_rxd_reserve(). 1578 * 1579 * Post descriptor on the ring. 1580 * Prior to posting the descriptor should be filled in accordance with 1581 * Host/X3100 interface specification for a given service (LL, etc.). 1582 * 1583 */ 1584void 1585vxge_hal_ring_rxd_post( 1586 vxge_hal_vpath_h vpath_handle, 1587 vxge_hal_rxd_h rxdh); 1588 1589/* 1590 * vxge_hal_ring_is_next_rxd_completed - Check if the next rxd is completed 1591 * @vpath_handle: Virtual Path handle. 1592 * 1593 * Checks if the _next_ completed descriptor is in host memory 1594 * 1595 * Returns: VXGE_HAL_OK - success. 1596 * VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors 1597 * are currently available for processing. 1598 */ 1599vxge_hal_status_e 1600vxge_hal_ring_is_next_rxd_completed( 1601 vxge_hal_vpath_h vpath_handle); 1602 1603/* 1604 * vxge_hal_ring_rxd_next_completed - Get the _next_ completed descriptor. 1605 * @vpath_handle: Virtual path handle. 1606 * @rxdh: Descriptor handle. Returned by HAL. 1607 * @rxd_priv: Buffer to return a pointer to the per rxd space allocated 1608 * @t_code: Transfer code, as per X3100 User Guide, 1609 * Receive Descriptor Format. Returned by HAL. 1610 * 1611 * Retrieve the _next_ completed descriptor. 1612 * HAL uses ring callback (*vxge_hal_ring_callback_f) to notifiy 1613 * upper-layer driver (ULD) of new completed descriptors. After that 1614 * the ULD can use vxge_hal_ring_rxd_next_completed to retrieve the rest 1615 * completions (the very first completion is passed by HAL via 1616 * vxge_hal_ring_callback_f). 1617 * 1618 * Implementation-wise, the upper-layer driver is free to call 1619 * vxge_hal_ring_rxd_next_completed either immediately from inside the 1620 * ring callback, or in a deferred fashion and separate (from HAL) 1621 * context. 1622 * 1623 * Non-zero @t_code means failure to fill-in receive buffer(s) 1624 * of the descriptor. 1625 * For instance, parity error detected during the data transfer. 1626 * In this case X3100 will complete the descriptor and indicate 1627 * for the host that the received data is not to be used. 1628 * For details please refer to X3100 User Guide. 1629 * 1630 * Returns: VXGE_HAL_OK - success. 1631 * VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors 1632 * are currently available for processing. 1633 * 1634 * See also: vxge_hal_ring_callback_f {}, 1635 * vxge_hal_fifo_txdl_next_completed(), vxge_hal_status_e {}. 1636 */ 1637vxge_hal_status_e 1638vxge_hal_ring_rxd_next_completed( 1639 vxge_hal_vpath_h vpath_handle, 1640 vxge_hal_rxd_h *rxdh, 1641 void **rxd_priv, 1642 u8 *t_code); 1643 1644/* 1645 * vxge_hal_ring_handle_tcode - Handle transfer code. 1646 * @vpath_handle: Virtual Path handle. 1647 * @rxdh: Descriptor handle. 1648 * @t_code: One of the enumerated (and documented in the X3100 user guide) 1649 * "transfer codes". 1650 * 1651 * Handle descriptor's transfer code. The latter comes with each completed 1652 * descriptor. 1653 * 1654 * Returns: one of the vxge_hal_status_e {} enumerated types. 1655 * VXGE_HAL_OK - for success. 1656 * VXGE_HAL_ERR_CRITICAL - when encounters critical error. 1657 */ 1658vxge_hal_status_e 1659vxge_hal_ring_handle_tcode( 1660 vxge_hal_vpath_h vpath_handle, 1661 vxge_hal_rxd_h rxdh, 1662 u8 t_code); 1663 1664/* 1665 * vxge_hal_ring_rxd_1b_get - Get data from the completed 1-buf 1666 * descriptor. 1667 * @vpath_handle: Virtual Path handle. 1668 * @rxdh: Descriptor handle. 1669 * @dma_pointer: DMA address of a single receive buffer _this_ descriptor 1670 * carries. Returned by HAL. 1671 * @pkt_length: Length (in bytes) of the data in the buffer pointed by 1672 * @dma_pointer. Returned by HAL. 1673 * 1674 * Retrieve protocol data from the completed 1-buffer-mode Rx descriptor. 1675 * This inline helper-function uses completed descriptor to populate receive 1676 * buffer pointer and other "out" parameters. The function always succeeds. 1677 * 1678 */ 1679static inline 1680/* LINTED */ 1681void vxge_hal_ring_rxd_1b_get( 1682 vxge_hal_vpath_h vpath_handle, 1683 vxge_hal_rxd_h rxdh, 1684 dma_addr_t *dma_pointer, 1685 u32 *pkt_length) 1686{ 1687 vxge_hal_ring_rxd_1_t *rxdp = (vxge_hal_ring_rxd_1_t *) rxdh; 1688 1689 *pkt_length = 1690 (u32) VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_GET(rxdp->control_1); 1691 *dma_pointer = rxdp->buffer0_ptr; 1692} 1693 1694/* 1695 * vxge_hal_ring_rxd_3b_get - Get data from the completed 3-buf 1696 * descriptor. 1697 * @vpath_handle: Virtual Path handle. 1698 * @rxdh: Descriptor handle. 1699 * @dma_pointers: DMA addresses of the 3 receive buffers _this_ descriptor 1700 * carries. The first two buffers contain ethernet and 1701 * (IP + transport) headers. The 3rd buffer contains packet 1702 * data. 1703 * @sizes: Array of receive buffer sizes. Contains 3 sizes: one size per 1704 * buffer from @dma_pointers. Returned by HAL. 1705 * 1706 * Retrieve protocol data from the completed 3-buffer-mode Rx descriptor. 1707 * This inline helper-function uses completed descriptor to populate receive 1708 * buffer pointer and other "out" parameters. The function always succeeds. 1709 * 1710 */ 1711static inline 1712/* LINTED */ 1713void vxge_hal_ring_rxd_3b_get( 1714 vxge_hal_vpath_h vpath_handle, 1715 vxge_hal_rxd_h rxdh, 1716 dma_addr_t dma_pointers[], 1717 u32 sizes[]) 1718{ 1719 vxge_hal_ring_rxd_3_t *rxdp = (vxge_hal_ring_rxd_3_t *) rxdh; 1720 1721 dma_pointers[0] = rxdp->buffer0_ptr; 1722 sizes[0] = (u32) VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_GET(rxdp->control_1); 1723 1724 dma_pointers[1] = rxdp->buffer1_ptr; 1725 sizes[1] = (u32) VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_GET(rxdp->control_1); 1726 1727 dma_pointers[2] = rxdp->buffer2_ptr; 1728 sizes[2] = (u32) VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_GET(rxdp->control_1); 1729} 1730 1731/* 1732 * vxge_hal_ring_rxd_5b_get - Get data from the completed 5-buf descriptor. 1733 * @vpath_handle: Virtual Path handle. 1734 * @rxdh: Descriptor handle. 1735 * @dma_pointers: DMA addresses of the 5 receive buffers _this_ descriptor 1736 * carries. The first 4 buffers contains L2 (ethernet) through 1737 * L5 headers. The 5th buffer contain received (applicaion) 1738 * data. Returned by HAL. 1739 * @sizes: Array of receive buffer sizes. Contains 5 sizes: one size per 1740 * buffer from @dma_pointers. Returned by HAL. 1741 * 1742 * Retrieve protocol data from the completed 5-buffer-mode Rx descriptor. 1743 * This inline helper-function uses completed descriptor to populate receive 1744 * buffer pointer and other "out" parameters. The function always succeeds. 1745 * 1746 * See also: vxge_hal_ring_rxd_3b_get(), vxge_hal_ring_rxd_5b_get(). 1747 */ 1748static inline 1749/* LINTED */ 1750void vxge_hal_ring_rxd_5b_get( 1751 vxge_hal_vpath_h vpath_handle, 1752 vxge_hal_rxd_h rxdh, 1753 dma_addr_t dma_pointers[], 1754 int sizes[]) 1755{ 1756 vxge_hal_ring_rxd_5_t *rxdp = (vxge_hal_ring_rxd_5_t *) rxdh; 1757 1758 dma_pointers[0] = rxdp->buffer0_ptr; 1759 sizes[0] = (u32) VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_GET(rxdp->control_1); 1760 1761 dma_pointers[1] = rxdp->buffer1_ptr; 1762 sizes[1] = (u32) VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_GET(rxdp->control_1); 1763 1764 dma_pointers[2] = rxdp->buffer2_ptr; 1765 sizes[2] = (u32) VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_GET(rxdp->control_1); 1766 1767 dma_pointers[3] = rxdp->buffer3_ptr; 1768 sizes[3] = (u32) VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_GET(rxdp->control_2); 1769 1770 dma_pointers[4] = rxdp->buffer4_ptr; 1771 sizes[4] = (u32) VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_GET(rxdp->control_2); 1772} 1773 1774/* 1775 * vxge_hal_ring_rxd_1b_info_get - Get extended information associated with 1776 * a completed receive descriptor for 1b mode. 1777 * @vpath_handle: Virtual Path handle. 1778 * @rxdh: Descriptor handle. 1779 * @rxd_info: Descriptor information 1780 * 1781 * Retrieve extended information associated with a completed receive descriptor. 1782 * 1783 */ 1784static inline 1785/* LINTED */ 1786void vxge_hal_ring_rxd_1b_info_get( 1787 vxge_hal_vpath_h vpath_handle, 1788 vxge_hal_rxd_h rxdh, 1789 vxge_hal_ring_rxd_info_t *rxd_info) 1790{ 1791 vxge_hal_ring_rxd_1_t *rxdp = (vxge_hal_ring_rxd_1_t *) rxdh; 1792 1793 rxd_info->syn_flag = 1794 (u32) VXGE_HAL_RING_RXD_SYN_GET(rxdp->control_0); 1795 rxd_info->is_icmp = 1796 (u32) VXGE_HAL_RING_RXD_IS_ICMP_GET(rxdp->control_0); 1797 rxd_info->fast_path_eligible = 1798 (u32) VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(rxdp->control_0); 1799 rxd_info->l3_cksum_valid = 1800 (u32) VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(rxdp->control_0); 1801 rxd_info->l3_cksum = 1802 (u32) VXGE_HAL_RING_RXD_L3_CKSUM_GET(rxdp->control_0); 1803 rxd_info->l4_cksum_valid = 1804 (u32) VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(rxdp->control_0); 1805 rxd_info->l4_cksum = 1806 (u32) VXGE_HAL_RING_RXD_L4_CKSUM_GET(rxdp->control_0); 1807 rxd_info->frame = 1808 (u32) VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(rxdp->control_0); 1809 rxd_info->proto = 1810 (u32) VXGE_HAL_RING_RXD_FRAME_PROTO_GET(rxdp->control_0); 1811 rxd_info->is_vlan = 1812 (u32) VXGE_HAL_RING_RXD_IS_VLAN_GET(rxdp->control_0); 1813 rxd_info->vlan = 1814 (u32) VXGE_HAL_RING_RXD_VLAN_TAG_GET(rxdp->control_1); 1815 rxd_info->rth_bucket = 1816 (u32) VXGE_HAL_RING_RXD_RTH_BUCKET_GET(rxdp->control_0); 1817 rxd_info->rth_it_hit = 1818 (u32) VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(rxdp->control_0); 1819 rxd_info->rth_spdm_hit = 1820 (u32) VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(rxdp->control_0); 1821 rxd_info->rth_hash_type = 1822 (u32) VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(rxdp->control_0); 1823 rxd_info->rth_value = 1824 (u32) VXGE_HAL_RING_RXD_1_RTH_HASH_VAL_GET(rxdp->control_1); 1825} 1826 1827/* 1828 * vxge_hal_ring_rxd_3b_5b_info_get - Get extended information associated with 1829 * a completed receive descriptor for 3b & 5b mode. 1830 * @vpath_handle: Virtual Path handle. 1831 * @rxdh: Descriptor handle. 1832 * @rxd_info: Descriptor information 1833 * 1834 * Retrieve extended information associated with a completed receive descriptor. 1835 * 1836 */ 1837static inline 1838/* LINTED */ 1839void vxge_hal_ring_rxd_3b_5b_info_get( 1840 vxge_hal_vpath_h vpath_handle, 1841 vxge_hal_rxd_h rxdh, 1842 vxge_hal_ring_rxd_info_t *rxd_info) 1843{ 1844 vxge_hal_ring_rxd_3_t *rxdp = (vxge_hal_ring_rxd_3_t *) rxdh; 1845 1846 rxd_info->syn_flag = 1847 (u32) VXGE_HAL_RING_RXD_SYN_GET(rxdp->control_0); 1848 rxd_info->is_icmp = 1849 (u32) VXGE_HAL_RING_RXD_IS_ICMP_GET(rxdp->control_0); 1850 rxd_info->fast_path_eligible = 1851 (u32) VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(rxdp->control_0); 1852 rxd_info->l3_cksum_valid = 1853 (u32) VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(rxdp->control_0); 1854 rxd_info->l3_cksum = 1855 (u32) VXGE_HAL_RING_RXD_L3_CKSUM_GET(rxdp->control_0); 1856 rxd_info->l4_cksum_valid = 1857 (u32) VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(rxdp->control_0); 1858 rxd_info->l4_cksum = 1859 (u32) VXGE_HAL_RING_RXD_L4_CKSUM_GET(rxdp->control_0); 1860 rxd_info->frame = 1861 (u32) VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(rxdp->control_0); 1862 rxd_info->proto = 1863 (u32) VXGE_HAL_RING_RXD_FRAME_PROTO_GET(rxdp->control_0); 1864 rxd_info->is_vlan = 1865 (u32) VXGE_HAL_RING_RXD_IS_VLAN_GET(rxdp->control_0); 1866 rxd_info->vlan = 1867 (u32) VXGE_HAL_RING_RXD_VLAN_TAG_GET(rxdp->control_1); 1868 rxd_info->rth_bucket = 1869 (u32) VXGE_HAL_RING_RXD_RTH_BUCKET_GET(rxdp->control_0); 1870 rxd_info->rth_it_hit = 1871 (u32) VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(rxdp->control_0); 1872 rxd_info->rth_spdm_hit = 1873 (u32) VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(rxdp->control_0); 1874 rxd_info->rth_hash_type = 1875 (u32) VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(rxdp->control_0); 1876 rxd_info->rth_value = (u32) VXGE_HAL_RING_RXD_3_RTH_HASH_VALUE_GET( 1877 rxdp->buffer0_ptr); 1878} 1879 1880/* 1881 * vxge_hal_device_is_privileged 1882 * @host_type: host type. 1883 * @func_id: function id. 1884 * 1885 */ 1886vxge_hal_status_e 1887vxge_hal_device_is_privileged( 1888 u32 host_type, 1889 u32 func_id); 1890 1891/* 1892 * vxge_hal_ring_rxd_private_get - Get ULD private per-descriptor data 1893 * @vpath_handle: Virtual Path handle. 1894 * @rxdh: Descriptor handle. 1895 * 1896 * Returns: private ULD info associated with the descriptor. 1897 * ULD requests per-descriptor space via vxge_hal_ring_attr. 1898 * 1899 */ 1900void * 1901vxge_hal_ring_rxd_private_get( 1902 vxge_hal_vpath_h vpath_handle, 1903 vxge_hal_rxd_h rxdh); 1904 1905/* 1906 * vxge_hal_ring_rxd_free - Free descriptor. 1907 * @vpath_handle: Virtual Path handle. 1908 * @rxdh: Descriptor handle. 1909 * 1910 * Free the reserved descriptor. This operation is "symmetrical" to 1911 * vxge_hal_ring_rxd_reserve. The "free-ing" completes the descriptor's 1912 * lifecycle. 1913 * 1914 * After free-ing (see vxge_hal_ring_rxd_free()) the descriptor again can 1915 * be: 1916 * 1917 * - reserved (vxge_hal_ring_rxd_reserve); 1918 * 1919 * - posted (vxge_hal_ring_rxd_post); 1920 * 1921 * - completed (vxge_hal_ring_rxd_next_completed); 1922 * 1923 * - and recycled again (vxge_hal_ring_rxd_free). 1924 * 1925 * For alternative state transitions and more details please refer to 1926 * the design doc. 1927 * 1928 */ 1929void 1930vxge_hal_ring_rxd_free( 1931 vxge_hal_vpath_h vpath_handle, 1932 vxge_hal_rxd_h rxdh); 1933 1934 1935/* 1936 * Fifo 1937 */ 1938/* 1939 * TX Descriptor 1940 */ 1941/* 1942 * enum vxge_hal_txdl_state_e - Descriptor (TXDL) state. 1943 * @VXGE_HAL_TXDL_STATE_NONE: Invalid state. 1944 * @VXGE_HAL_TXDL_STATE_AVAIL: Descriptor is available for reservation. 1945 * @VXGE_HAL_TXDL_STATE_POSTED: Descriptor is posted for processing by the 1946 * device. 1947 * @VXGE_HAL_TXDL_STATE_FREED: Descriptor is free and can be reused for 1948 * filling-in and posting later. 1949 * 1950 * X3100/HAL descriptor states. 1951 * 1952 */ 1953typedef enum vxge_hal_txdl_state_e { 1954 VXGE_HAL_TXDL_STATE_NONE = 0, 1955 VXGE_HAL_TXDL_STATE_AVAIL = 1, 1956 VXGE_HAL_TXDL_STATE_POSTED = 2, 1957 VXGE_HAL_TXDL_STATE_FREED = 3 1958} vxge_hal_txdl_state_e; 1959 1960/* 1961 * enum vxge_hal_fifo_tcode_e - tcodes used in fifo 1962 * @VXGE_HAL_FIFO_T_CODE_OK: Transfer OK 1963 * @VXGE_HAL_FIFO_T_CODE_PCI_READ_CORRUPT: PCI read transaction (either TxD or 1964 * frame data) returned with corrupt data. 1965 * @VXGE_HAL_FIFO_T_CODE_PCI_READ_FAIL:PCI read transaction was returned 1966 * with no data. 1967 * @VXGE_HAL_FIFO_T_CODE_INVALID_MSS: The host attempted to send either a 1968 * frame or LSO MSS that was too long (>9800B). 1969 * @VXGE_HAL_FIFO_T_CODE_LSO_ERROR: Error detected during TCP/UDP Large Send 1970 * Offload operation, due to improper header template, 1971 * unsupported protocol, etc. 1972 * @VXGE_HAL_FIFO_T_CODE_UNUSED: Unused 1973 * @VXGE_HAL_FIFO_T_CODE_MULTI_ERROR: Set to 1 by the adapter if multiple 1974 * data buffer transfer errors are encountered (see below). 1975 * Otherwise it is set to 0. 1976 * 1977 * These tcodes are returned in various API for TxD status 1978 */ 1979typedef enum vxge_hal_fifo_tcode_e { 1980 VXGE_HAL_FIFO_T_CODE_OK = 0x0, 1981 VXGE_HAL_FIFO_T_CODE_PCI_READ_CORRUPT = 0x1, 1982 VXGE_HAL_FIFO_T_CODE_PCI_READ_FAIL = 0x2, 1983 VXGE_HAL_FIFO_T_CODE_INVALID_MSS = 0x3, 1984 VXGE_HAL_FIFO_T_CODE_LSO_ERROR = 0x4, 1985 VXGE_HAL_FIFO_T_CODE_UNUSED = 0x7, 1986 VXGE_HAL_FIFO_T_CODE_MULTI_ERROR = 0x8 1987} vxge_hal_fifo_tcode_e; 1988 1989/* 1990 * enum vxge_hal_fifo_host_steer_e - Host steer type 1991 * @VXGE_HAL_FIFO_HOST_STEER_NORMAL: Normal. Use Destination/MAC Address 1992 * lookup to determine the transmit porte 1993 * @VXGE_HAL_FIFO_HOST_STEER_PORT1: Send on physical Port1 1994 * @VXGE_HAL_FIFO_HOST_STEER_PORT0: Send on physical Port0 1995 * @VXGE_HAL_FIFO_HOST_STEER_BOTH: Send on both ports. 1996 * 1997 * Host steer type 1998 */ 1999typedef enum vxge_hal_fifo_host_steer_e { 2000 VXGE_HAL_FIFO_HOST_STEER_NORMAL = 0x0, 2001 VXGE_HAL_FIFO_HOST_STEER_PORT1 = 0x1, 2002 VXGE_HAL_FIFO_HOST_STEER_PORT0 = 0x2, 2003 VXGE_HAL_FIFO_HOST_STEER_BOTH = 0x3 2004} vxge_hal_fifo_host_steer_e; 2005 2006/* 2007 * enum vxge_hal_fifo_gather_code_e - Gather codes used in fifo TxD 2008 * @VXGE_HAL_FIFO_GATHER_CODE_FIRST: First TxDL 2009 * @VXGE_HAL_FIFO_GATHER_CODE_MIDDLE: Middle TxDL 2010 * @VXGE_HAL_FIFO_GATHER_CODE_LAST: Last TxDL 2011 * @VXGE_HAL_FIFO_GATHER_CODE_FIRST_LAST: First and Last TxDL. 2012 * 2013 * These gather codes are used to indicate the position of a TxD in a TxD list 2014 */ 2015typedef enum vxge_hal_fifo_gather_code_e { 2016 VXGE_HAL_FIFO_GATHER_CODE_FIRST = 0x2, 2017 VXGE_HAL_FIFO_GATHER_CODE_MIDDLE = 0x0, 2018 VXGE_HAL_FIFO_GATHER_CODE_LAST = 0x1, 2019 VXGE_HAL_FIFO_GATHER_CODE_FIRST_LAST = 0x3 2020} vxge_hal_fifo_gather_code_e; 2021 2022/* 2023 * enum vxge_hal_fifo_lso_frm_encap_e - LSO Frame Encapsulation 2024 * @VXGE_HAL_FIFO_LSO_FRM_ENCAP_AUTO: auto mode (best guess) 2025 * @VXGE_HAL_FIFO_LSO_FRM_ENCAP_LLC: LLC 2026 * @VXGE_HAL_FIFO_LSO_FRM_ENCAP_SNAP: SNAP 2027 * @VXGE_HAL_FIFO_LSO_FRM_ENCAP_DIX: DIX 2028 * 2029 * LSO Frame Encapsulation type 2030 */ 2031typedef enum vxge_hal_fifo_lso_frm_encap_e { 2032 VXGE_HAL_FIFO_LSO_FRM_ENCAP_AUTO = 0x0, 2033 VXGE_HAL_FIFO_LSO_FRM_ENCAP_LLC = 0x1, 2034 VXGE_HAL_FIFO_LSO_FRM_ENCAP_SNAP = 0x2, 2035 VXGE_HAL_FIFO_LSO_FRM_ENCAP_DIX = 0x3 2036} vxge_hal_fifo_lso_frm_encap_e; 2037 2038/* 2039 * struct vxge_hal_fifo_txd_t - Transmit Descriptor 2040 * @control_0: Bits 0 to 6 - Reserved. 2041 * Bit 7 - List Ownership. This field should be initialized 2042 * to '1' by the driver before the transmit list pointer is 2043 * written to the adapter. This field will be set to '0' by the 2044 * adapter once it has completed transmitting the frame or frames 2045 * in the list. Note - This field is only valid in TxD0. 2046 * Additionally, for multi-list sequences, the driver should not 2047 * release any buffers until the ownership of the last list in the 2048 * multi-list sequence has been returned to the host. 2049 * Bits 8 to 11 - Reserved 2050 * Bits 12 to 15 - Transfer_Code. This field is only valid in 2051 * TxD0. It is used to describe the status of the transmit data 2052 * buffer transfer. This field is always overwritten by the 2053 * adapter, so this field may be initialized to any value. 2054 * Bits 16 to 17 - Host steering. This field allows the host to 2055 * override the selection of the physical transmit port. 2056 * Attention: 2057 * Normal sounds as if learned from the switch rather than from 2058 * the aggregation algorythms. 2059 * 00: Normal. Use Destination/MAC Address 2060 * lookup to determine the transmit port. 2061 * 01: Send on physical Port1. 2062 * 10: Send on physical Port0. 2063 * 11: Send on both ports. 2064 * Bits 18 to 21 - Reserved 2065 * Bits 22 to 23 - Gather_Code. This field is set by the host and 2066 * is used to describe how individual buffers comprise a frame. 2067 * 10: First descriptor of a frame. 2068 * 00: Middle of a multi-descriptor frame. 2069 * 01: Last descriptor of a frame. 2070 * 11: First and last descriptor of a frame (the entire frame 2071 * resides in a single buffer). 2072 * For multi-descriptor frames, the only valid gather code sequence 2073 * is {10, [00], 01}. In other words,the descriptors must be placed 2074 * in the list in the correct order. 2075 * Bits 24 to 27 - Reserved 2076 * Bits 28 to 29 - LSO_Frm_Encap. LSO Frame Encapsulation 2077 * definition. Only valid in TxD0. This field allows the host to 2078 * indicate the Ethernet encapsulation of an outbound LSO packet. 2079 * 00 - classic mode (best guess) 2080 * 01 - LLC 2081 * 10 - SNAP 2082 * 11 - DIX 2083 * If "classic mode" is selected, the adapter will attempt to 2084 * decode the frame's Ethernet encapsulation by examining the L/T 2085 * field as follows: 2086 * <= 0x05DC LLC/SNAP encoding; must examine DSAP/SSAP to determine 2087 * if packet is IPv4 or IPv6. 2088 * 0x8870 Jumbo-SNAP encoding. 2089 * 0x0800 IPv4 DIX encoding 2090 * 0x86DD IPv6 DIX encoding 2091 * others illegal encapsulation 2092 * Bits 30 - LSO_ Flag. Large Send Offload (LSO) flag. 2093 * Set to 1 to perform segmentation offload for TCP/UDP. 2094 * This field is valid only in TxD0. 2095 * Bits 31 to 33 - Reserved. 2096 * Bits 34 to 47 - LSO_MSS. TCP/UDP LSO Maximum Segment Size 2097 * This field is meaningful only when LSO_Control is non-zero. 2098 * When LSO_Control is set to TCP_LSO, the single (possibly large) 2099 * TCP segment described by this TxDL will be sent as a series of 2100 * TCP segments each of which contains no more than LSO_MSS 2101 * payload bytes. 2102 * When LSO_Control is set to UDP_LSO, the single (possibly large) 2103 * UDP datagram described by this TxDL will be sent as a series of 2104 * UDP datagrams each of which contains no more than LSO_MSS 2105 * payload bytes. 2106 * All outgoing frames from this TxDL will have LSO_MSS bytes of 2107 * UDP or TCP payload, with the exception of the last, which will 2108 * have <= LSO_MSS bytes of payload. 2109 * Bits 48 to 63 - Buffer_Size. Number of valid bytes in the 2110 * buffer to be read by the adapter. This field is written by the 2111 * host. A value of 0 is illegal. 2112 * Bits 32 to 63 - This value is written by the adapter upon 2113 * completion of a UDP or TCP LSO operation and indicates the 2114 * number of UDP or TCP payload bytes that were transmitted. 2115 * 0x0000 will bereturned for any non-LSO operation. 2116 * @control_1: Bits 0 to 4 - Reserved. 2117 * Bit 5 - Tx_CKO_IPv4 Set to a '1' to enable IPv4 header checksum 2118 * offload. This field is only valid in the first TxD of a frame. 2119 * Bit 6 - Tx_CKO_TCP Set to a '1' to enable TCP checksum offload. 2120 * This field is only valid in the first TxD of a frame (the TxD's 2121 * gather code must be 10 or 11). The driver should only set this 2122 * Bit if it can guarantee that TCP is present. 2123 * Bit 7 - Tx_CKO_UDP Set to a '1' to enable UDP checksum offload. 2124 * This field is only valid in the first TxD of a frame (the TxD's 2125 * gather code must be 10 or 11). The driver should only set this 2126 * Bit if it can guarantee that UDP is present. 2127 * Bits 8 to 14 - Reserved. 2128 * Bit 15 - Tx_VLAN_Enable VLAN tag insertion flag. Set to a '1' to 2129 * instruct the adapter to insert the VLAN tag specified by the 2130 * Tx_VLAN_Tag field. This field is only valid in the first TxD of 2131 * a frame. 2132 * Bits 16 to 31 - Tx_VLAN_Tag. Variable portion of the VLAN tag 2133 * to be inserted into the frame by the adapter(the first two bytes 2134 * of a VLAN tag are always 0x8100).This field is only valid if the 2135 * Tx_VLAN_Enable field is set to '1'. 2136 * Bits 32 to 33 - Reserved. 2137 * Bits 34 to 39 - Tx_Int_Number. Indicates which Tx interrupt 2138 * number the frame associated with. This field is written by the 2139 * host. It is only valid in the first TxD of a frame. 2140 * Bits 40 to 42 - Reserved. 2141 * Bit 43 - Set to 1 to exclude the frame from bandwidth metering 2142 * functions. This field is valid only in the first TxD 2143 * of a frame. 2144 * Bits 44 to 45 - Reserved. 2145 * Bit 46 - Tx_Int_Per_List Set to a '1' to instruct the adapter to 2146 * generate an interrupt as soon as all of the frames in the list 2147 * have been transmitted. In order to have per-frame interrupts, 2148 * the driver should place a maximum of one frame per list. This 2149 * field is only valid in the first TxD of a frame. 2150 * Bit 47 - Tx_Int_Utilization Set to a '1' to instruct the adapter 2151 * to count the frame toward the utilization interrupt specified in 2152 * the Tx_Int_Number field. This field is only valid in the first 2153 * TxD of a frame. 2154 * Bits 48 to 63 - Reserved. 2155 * @buffer_pointer: Buffer start address. 2156 * @host_control: Host_Control.Opaque 64bit data stored by ULD inside the X3100 2157 * descriptor prior to posting the latter on the fifo 2158 * via vxge_hal_fifo_txdl_post().The %host_control is returned as is to 2159 * the ULD with each completed descriptor. 2160 * 2161 * Transmit descriptor (TxD).Fifo descriptor contains configured number 2162 * (list) of TxDs. * For more details please refer to X3100 User Guide, 2163 * Section 5.4.2 "Transmit Descriptor (TxD) Format". 2164 */ 2165typedef struct vxge_hal_fifo_txd_t { 2166 u64 control_0; 2167#define VXGE_HAL_FIFO_TXD_LIST_OWN_GET(ctrl0) bVAL1(ctrl0, 7) 2168#define VXGE_HAL_FIFO_TXD_LIST_OWN_ADAPTER mBIT(7) 2169 2170#define VXGE_HAL_FIFO_TXD_T_CODE_GET(ctrl0) bVAL4(ctrl0, 12) 2171#define VXGE_HAL_FIFO_TXD_T_CODE(val) vBIT(val, 12, 4) 2172#define VXGE_HAL_FIFO_TXD_T_CODE_OK VXGE_HAL_FIFO_T_CODE_OK 2173#define VXGE_HAL_FIFO_TXD_T_CODE_PCI_READ_CORRUPT \ 2174 VXGE_HAL_FIFO_T_CODE_PCI_READ_CORRUPT 2175#define VXGE_HAL_FIFO_TXD_T_CODE_PCI_READ_FAIL \ 2176 VXGE_HAL_FIFO_T_CODE_PCI_READ_FAIL 2177#define VXGE_HAL_FIFO_TXD_T_CODE_INVALID_MSS VXGE_HAL_FIFO_T_CODE_INVALID_MSS 2178#define VXGE_HAL_FIFO_TXD_T_CODE_LSO_ERROR VXGE_HAL_FIFO_T_CODE_LSO_ERROR 2179#define VXGE_HAL_FIFO_TXD_T_CODE_UNUSED VXGE_HAL_FIFO_T_CODE_UNUSED 2180#define VXGE_HAL_FIFO_TXD_T_CODE_MULTI_ERROR VXGE_HAL_FIFO_T_CODE_MULTI_ERROR 2181 2182#define VXGE_HAL_FIFO_TXD_HOST_STEER_GET(ctrl0) bVAL2(ctrl0, 16) 2183#define VXGE_HAL_FIFO_TXD_HOST_STEER(val) vBIT(val, 16, 2) 2184#define VXGE_HAL_FIFO_TXD_HOST_STEER_NORMAL VXGE_HAL_FIFO_HOST_STEER_NORMAL 2185#define VXGE_HAL_FIFO_TXD_HOST_STEER_PORT1 VXGE_HAL_FIFO_HOST_STEER_PORT1 2186#define VXGE_HAL_FIFO_TXD_HOST_STEER_PORT0 VXGE_HAL_FIFO_HOST_STEER_PORT0 2187#define VXGE_HAL_FIFO_TXD_HOST_STEER_BOTH VXGE_HAL_FIFO_HOST_STEER_BOTH 2188 2189#define VXGE_HAL_FIFO_TXD_GATHER_CODE_GET(ctrl0) bVAL2(ctrl0, 22) 2190#define VXGE_HAL_FIFO_TXD_GATHER_CODE(val) vBIT(val, 22, 2) 2191#define VXGE_HAL_FIFO_TXD_GATHER_CODE_FIRST VXGE_HAL_FIFO_GATHER_CODE_FIRST 2192#define VXGE_HAL_FIFO_TXD_GATHER_CODE_MIDDLE VXGE_HAL_FIFO_GATHER_CODE_MIDDLE 2193#define VXGE_HAL_FIFO_TXD_GATHER_CODE_LAST VXGE_HAL_FIFO_GATHER_CODE_LAST 2194#define VXGE_HAL_FIFO_TXD_GATHER_CODE_FIRST_LAST \ 2195 VXGE_HAL_FIFO_GATHER_CODE_FIRST_LAST 2196 2197#define VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_GET(ctrl0) bVAL2(ctrl0, 28) 2198#define VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP(val) vBIT(val, 28, 2) 2199#define VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_AUTO VXGE_HAL_FIFO_LSO_FRM_ENCAP_AUTO 2200#define VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_LLC VXGE_HAL_FIFO_LSO_FRM_ENCAP_LLC 2201#define VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_SNAP VXGE_HAL_FIFO_LSO_FRM_ENCAP_SNAP 2202#define VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_DIX VXGE_HAL_FIFO_LSO_FRM_ENCAP_DIX 2203 2204#define VXGE_HAL_FIFO_TXD_LSO_FLAG_GET(ctrl0) bVAL1(ctrl0, 30) 2205#define VXGE_HAL_FIFO_TXD_LSO_FLAG mBIT(30) 2206 2207#define VXGE_HAL_FIFO_TXD_LSO_MSS_GET(ctrl0) bVAL14(ctrl0, 34) 2208#define VXGE_HAL_FIFO_TXD_LSO_MSS(val) vBIT(val, 34, 14) 2209 2210#define VXGE_HAL_FIFO_TXD_BUFFER_SIZE_GET(ctrl0) bVAL16(ctrl0, 48) 2211#define VXGE_HAL_FIFO_TXD_BUFFER_SIZE(val) vBIT(val, 48, 16) 2212 2213#define VXGE_HAL_FIFO_TXD_LSO_BYTES_SENT_GET(ctrl0) bVAL32(ctrl0, 32) 2214#define VXGE_HAL_FIFO_TXD_LSO_BYTES_SENT(val) vBIT(val, 32, 32) 2215 2216 u64 control_1; 2217#define VXGE_HAL_FIFO_TXD_TX_CKO_IPV4_EN_GET(ctrl1) bVAL1(ctrl1, 5) 2218#define VXGE_HAL_FIFO_TXD_TX_CKO_IPV4_EN mBIT(5) 2219 2220#define VXGE_HAL_FIFO_TXD_TX_CKO_TCP_EN_GET(ctrl1) bVAL1(ctrl1, 6) 2221#define VXGE_HAL_FIFO_TXD_TX_CKO_TCP_EN mBIT(6) 2222 2223#define VXGE_HAL_FIFO_TXD_TX_CKO_UDP_EN_GET(ctrl1) bVAL1(ctrl1, 7) 2224#define VXGE_HAL_FIFO_TXD_TX_CKO_UDP_EN mBIT(7) 2225 2226#define VXGE_HAL_FIFO_TXD_TX_CKO_CONTROL (mBIT(5)|mBIT(6)|mBIT(7)) 2227 2228#define VXGE_HAL_FIFO_TXD_VLAN_ENABLE_GET(ctrl1) bVAL1(ctrl1, 15) 2229#define VXGE_HAL_FIFO_TXD_VLAN_ENABLE mBIT(15) 2230 2231#define VXGE_HAL_FIFO_TXD_VLAN_TAG_GET(ctrl1) bVAL16(ctrl1, 16) 2232#define VXGE_HAL_FIFO_TXD_VLAN_TAG(val) vBIT(val, 16, 16) 2233 2234#define VXGE_HAL_FIFO_TXD_INT_NUMBER_GET(ctrl1) bVAL6(ctrl1, 34) 2235#define VXGE_HAL_FIFO_TXD_INT_NUMBER(val) vBIT(val, 34, 6) 2236 2237#define VXGE_HAL_FIFO_TXD_NO_BW_LIMIT_GET(ctrl1) bVAL1(ctrl1, 43) 2238#define VXGE_HAL_FIFO_TXD_NO_BW_LIMIT mBIT(43) 2239 2240#define VXGE_HAL_FIFO_TXD_INT_TYPE_PER_LIST_GET(ctrl1) bVAL1(ctrl1, 46) 2241#define VXGE_HAL_FIFO_TXD_INT_TYPE_PER_LIST mBIT(46) 2242 2243#define VXGE_HAL_FIFO_TXD_INT_TYPE_UTILZ_GET(ctrl1) bVAL1(ctrl1, 47) 2244#define VXGE_HAL_FIFO_TXD_INT_TYPE_UTILZ mBIT(47) 2245 2246 u64 buffer_pointer; 2247 2248 u64 host_control; 2249 2250} vxge_hal_fifo_txd_t; 2251 2252typedef vxge_hal_fifo_txd_t *vxge_hal_fifo_txdl_t; 2253 2254/* 2255 * function vxge_hal_fifo_callback_f - FIFO callback. 2256 * @vpath_handle: Virtual path whose Fifo "containing" 1 or more completed 2257 * descriptors. 2258 * @txdlh: First completed descriptor. 2259 * @txdl_priv: Pointer to per txdl space allocated 2260 * @t_code: Transfer code, as per X3100 User Guide. 2261 * Returned by HAL. 2262 * @host_control: Opaque 64bit data stored by ULD inside the X3100 2263 * descriptor prior to posting the latter on the fifo 2264 * via vxge_hal_fifo_txdl_post(). The @host_control is returned 2265 * as is to the ULD with each completed descriptor. 2266 * @userdata: Opaque per-fifo data specified at fifo open 2267 * time, via vxge_hal_vpath_open(). 2268 * 2269 * Fifo completion callback (type declaration). A single per-fifo 2270 * callback is specified at fifo open time, via 2271 * vxge_hal_vpath_open(). Typically gets called as part of the processing 2272 * of the Interrupt Service Routine. 2273 * 2274 * Fifo callback gets called by HAL if, and only if, there is at least 2275 * one new completion on a given fifo. Upon processing the first @txdlh ULD 2276 * is _supposed_ to continue consuming completions using: 2277 * - vxge_hal_fifo_txdl_next_completed() 2278 * 2279 * Note that failure to process new completions in a timely fashion 2280 * leads to VXGE_HAL_INF_OUT_OF_DESCRIPTORS condition. 2281 * 2282 * Non-zero @t_code means failure to process transmit descriptor. 2283 * 2284 * In the "transmit" case the failure could happen, for instance, when the 2285 * link is down, in which case X3100 completes the descriptor because it 2286 * is not able to send the data out. 2287 * 2288 * For details please refer to X3100 User Guide. 2289 * 2290 * See also: vxge_hal_fifo_txdl_next_completed(), vxge_hal_fifo_txdl_term_f {}. 2291 */ 2292typedef vxge_hal_status_e(*vxge_hal_fifo_callback_f) ( 2293 vxge_hal_vpath_h vpath_handle, 2294 vxge_hal_txdl_h txdlh, 2295 void *txdl_priv, 2296 vxge_hal_fifo_tcode_e t_code, 2297 void *userdata); 2298 2299/* 2300 * function vxge_hal_fifo_txdl_init_f - Initialize descriptor callback. 2301 * @vpath_handle: Virtual path whose Fifo "containing" the @txdlh descriptor. 2302 * @txdlh: Descriptor. 2303 * @txdl_priv: Pointer to per txdl space allocated 2304 * @index: Index of the descriptor in the fifo's set of descriptors. 2305 * @userdata: Per-fifo user data (a.k.a. context) specified at 2306 * fifo open time, via vxge_hal_vpath_open(). 2307 * @reopen: See vxge_hal_reopen_e {}. 2308 * 2309 * Initialize descriptor callback. Unless NULL is specified in the 2310 * vxge_hal_fifo_attr_t {} structure passed to vxge_hal_vpath_open()), 2311 * HAL invokes the callback as part of the vxge_hal_vpath_open() 2312 * implementation. 2313 * The ULD could use the callback to pre-set DMA mappings and/or alignment 2314 * buffers. 2315 * 2316 * See also: vxge_hal_fifo_attr_t {}, vxge_hal_fifo_txdl_term_f {}. 2317 */ 2318typedef vxge_hal_status_e(*vxge_hal_fifo_txdl_init_f) ( 2319 vxge_hal_vpath_h vpath_handle, 2320 vxge_hal_txdl_h txdlh, 2321 void *txdl_priv, 2322 u32 index, 2323 void *userdata, 2324 vxge_hal_reopen_e reopen); 2325 2326/* 2327 * function vxge_hal_fifo_txdl_term_f - Terminate descriptor callback. 2328 * @vpath_handle: Virtual path whose Fifo "containing" the @txdlh descriptor. 2329 * @txdlh: First completed descriptor. 2330 * @txdl_priv: Pointer to per txdl space allocated 2331 * @state: One of the vxge_hal_txdl_state_e {} enumerated states. 2332 * @userdata: Per-fifo user data (a.k.a. context) specified at 2333 * fifo open time, via vxge_hal_vpath_open(). 2334 * @reopen: See vxge_hal_reopen_e {}. 2335 * 2336 * Terminate descriptor callback. Unless NULL is specified in the 2337 * vxge_hal_fifo_attr_t {} structure passed to vxge_hal_vpath_open()), 2338 * HAL invokes the callback as part of closing fifo, prior to 2339 * de-allocating the ring and associated data structures 2340 * (including descriptors). 2341 * ULD should utilize the callback to (for instance) unmap 2342 * and free DMA data buffers associated with the posted (state = 2343 * VXGE_HAL_TXDL_STATE_POSTED) descriptors, 2344 * as well as other relevant cleanup functions. 2345 * 2346 * See also: vxge_hal_fifo_attr_t {}, vxge_hal_fifo_txdl_init_f {}. 2347 */ 2348typedef void (*vxge_hal_fifo_txdl_term_f) ( 2349 vxge_hal_vpath_h vpath_handle, 2350 vxge_hal_txdl_h txdlh, 2351 void *txdl_priv, 2352 vxge_hal_txdl_state_e state, 2353 void *userdata, 2354 vxge_hal_reopen_e reopen); 2355 2356/* 2357 * struct vxge_hal_fifo_attr_t - Fifo open "template". 2358 * @callback: Fifo completion callback. HAL invokes the callback when there 2359 * are new completions on that fifo. In many implementations 2360 * the @callback executes in the hw interrupt context. 2361 * @txdl_init: Fifo's descriptor-initialize callback. 2362 * See vxge_hal_fifo_txdl_init_f {}. 2363 * If not NULL, HAL invokes the callback when opening 2364 * the fifo via vxge_hal_vpath_open(). 2365 * @txdl_term: Fifo's descriptor-terminate callback. If not NULL, 2366 * HAL invokes the callback when closing the corresponding fifo. 2367 * See also vxge_hal_fifo_txdl_term_f {}. 2368 * @userdata: User-defined "context" of _that_ fifo. Passed back to the 2369 * user as one of the @callback, @txdl_init, and @txdl_term arguments. 2370 * @per_txdl_space: If specified (i.e., greater than zero): extra space 2371 * reserved by HAL per each transmit descriptor. Can be used to 2372 * store, and retrieve on completion, information specific 2373 * to the upper-layer. 2374 * 2375 * Fifo open "template". User fills the structure with fifo 2376 * attributes and passes it to vxge_hal_vpath_open(). 2377 */ 2378typedef struct vxge_hal_fifo_attr_t { 2379 vxge_hal_fifo_callback_f callback; 2380 vxge_hal_fifo_txdl_init_f txdl_init; 2381 vxge_hal_fifo_txdl_term_f txdl_term; 2382 void *userdata; 2383 u32 per_txdl_space; 2384} vxge_hal_fifo_attr_t; 2385 2386/* 2387 * vxge_hal_fifo_doorbell_reset - Resets the doorbell fifo 2388 * @vpath_handle: Vpath Handle 2389 * 2390 * This function resets the doorbell fifo during if fifo error occurs 2391 */ 2392vxge_hal_status_e 2393vxge_hal_fifo_doorbell_reset( 2394 vxge_hal_vpath_h vpath_handle); 2395 2396/* 2397 * vxge_hal_fifo_txdl_reserve - Reserve fifo descriptor. 2398 * @vpath_handle: virtual path handle. 2399 * @txdlh: Reserved descriptor. On success HAL fills this "out" parameter 2400 * with a valid handle. 2401 * @txdl_priv: Buffer to return the pointer to per txdl space allocated 2402 * 2403 * Reserve a single TxDL (that is, fifo descriptor) 2404 * for the subsequent filling-in by upper layerdriver (ULD)) 2405 * and posting on the corresponding fifo 2406 * via vxge_hal_fifo_txdl_post(). 2407 * 2408 * Note: it is the responsibility of ULD to reserve multiple descriptors 2409 * for lengthy (e.g., LSO) transmit operation. A single fifo descriptor 2410 * carries up to configured number (fifo.max_frags) of contiguous buffers. 2411 * 2412 * Returns: VXGE_HAL_OK - success; 2413 * VXGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available 2414 * 2415 */ 2416vxge_hal_status_e 2417vxge_hal_fifo_txdl_reserve( 2418 vxge_hal_vpath_h vpath_handle, 2419 vxge_hal_txdl_h *txdlh, 2420 void **txdl_priv); 2421 2422 2423/* 2424 * vxge_hal_fifo_txdl_cksum_set_bits - Offload checksum. 2425 * @txdlh: Descriptor handle. 2426 * @cksum_bits: Specifies which checksums are to be offloaded: IPv4, 2427 * and/or TCP and/or UDP. 2428 * 2429 * Ask X3100 to calculate IPv4 & transport checksums for _this_ transmit 2430 * descriptor. 2431 * This API is part of the preparation of the transmit descriptor for posting 2432 * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include 2433 * vxge_hal_fifo_txdl_mss_set(), vxge_hal_fifo_txdl_buffer_set_aligned(), 2434 * and vxge_hal_fifo_txdl_buffer_set(). 2435 * All these APIs fill in the fields of the fifo descriptor, 2436 * in accordance with the X3100 specification. 2437 * 2438 */ 2439static inline 2440/* LINTED */ 2441void vxge_hal_fifo_txdl_cksum_set_bits( 2442 vxge_hal_txdl_h txdlh, 2443 u64 cksum_bits) 2444{ 2445 vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh; 2446 2447 txdp->control_1 |= cksum_bits; 2448 2449} 2450 2451/* 2452 * vxge_hal_fifo_txdl_interrupt_type_set - Set the interrupt type for the txdl 2453 * @txdlh: Descriptor handle. 2454 * @interrupt_type: utiliz based interupt or List interrupt 2455 * 2456 * vxge_hal_fifo_txdl_interrupt_type_set is used to set the interrupt type for 2457 * each xmit txdl dynamically 2458 */ 2459static inline 2460/* LINTED */ 2461void vxge_hal_fifo_txdl_interrupt_type_set( 2462 vxge_hal_txdl_h txdlh, 2463 u64 interrupt_type) 2464{ 2465 vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh; 2466 2467 txdp->control_1 |= interrupt_type; 2468} 2469 2470/* 2471 * vxge_hal_fifo_txdl_lso_set - Set LSO Parameters. 2472 * @txdlh: Descriptor handle. 2473 * @encap: LSO Encapsulation 2474 * @mss: MSS size for LSO. 2475 * 2476 * This API is part of the preparation of the transmit descriptor for posting 2477 * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include 2478 * vxge_hal_fifo_txdl_buffer_set(), vxge_hal_fifo_txdl_buffer_set_aligned(), 2479 * and vxge_hal_fifo_txdl_cksum_set_bits(). 2480 * All these APIs fill in the fields of the fifo descriptor, 2481 * in accordance with the X3100 specification. 2482 * 2483 */ 2484static inline 2485/* LINTED */ 2486void vxge_hal_fifo_txdl_lso_set( 2487 vxge_hal_txdl_h txdlh, 2488 u32 encap, 2489 u32 mss) 2490{ 2491 vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh; 2492 2493 txdp->control_0 |= VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP(encap) | 2494 VXGE_HAL_FIFO_TXD_LSO_FLAG | VXGE_HAL_FIFO_TXD_LSO_MSS(mss); 2495} 2496 2497/* 2498 * vxge_hal_fifo_txdl_lso_bytes_sent - Get the lso bytes sent. 2499 * @txdlh: Descriptor handle. 2500 * 2501 * Returns the lso bytes sent 2502 */ 2503static inline 2504/* LINTED */ 2505u32 vxge_hal_fifo_txdl_lso_bytes_sent( 2506 vxge_hal_txdl_h txdlh) 2507{ 2508 vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh; 2509 2510 return (u32) VXGE_HAL_FIFO_TXD_LSO_BYTES_SENT_GET(txdp->control_0); 2511} 2512 2513/* 2514 * vxge_hal_fifo_txdl_vlan_set - Set VLAN tag. 2515 * @txdlh: Descriptor handle. 2516 * @vlan_tag: 16bit VLAN tag. 2517 * 2518 * Insert VLAN tag into specified transmit descriptor. 2519 * The actual insertion of the tag into outgoing frame is done by the hardware. 2520 */ 2521static inline 2522/* LINTED */ 2523void vxge_hal_fifo_txdl_vlan_set( 2524 vxge_hal_txdl_h txdlh, 2525 u16 vlan_tag) 2526{ 2527 vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh; 2528 2529 txdp->control_1 |= VXGE_HAL_FIFO_TXD_VLAN_ENABLE; 2530 txdp->control_1 |= VXGE_HAL_FIFO_TXD_VLAN_TAG(vlan_tag); 2531} 2532 2533/* 2534 * vxge_hal_fifo_txdl_buffer_set - Set transmit buffer pointer in the 2535 * descriptor. 2536 * @vpath_handle: virtual path handle. 2537 * @txdlh: Descriptor handle. 2538 * @frag_idx: Index of the data buffer in the caller's scatter-gather list 2539 * (of buffers). 2540 * @dma_pointer: DMA address of the data buffer referenced by @frag_idx. 2541 * @size: Size of the data buffer (in bytes). 2542 * 2543 * This API is part of the preparation of the transmit descriptor for posting 2544 * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include 2545 * vxge_hal_fifo_txdl_mss_set() and vxge_hal_fifo_txdl_cksum_set_bits(). 2546 * All three APIs fill in the fields of the fifo descriptor, 2547 * in accordance with the X3100 specification. 2548 * 2549 */ 2550void 2551vxge_hal_fifo_txdl_buffer_set( 2552 vxge_hal_vpath_h vpath_handle, 2553 vxge_hal_txdl_h txdlh, 2554 u32 frag_idx, 2555 dma_addr_t dma_pointer, 2556 unsigned long size); 2557 2558/* 2559 * vxge_hal_fifo_txdl_buffer_set_aligned - Align transmit buffer and fill 2560 * in fifo descriptor. 2561 * @vpath_handle: Virtual path handle. 2562 * @txdlh: Descriptor handle. 2563 * @frag_idx: Index of the data buffer in the caller's scatter-gather list 2564 * (of buffers). 2565 * @vaddr: Virtual address of the data buffer. 2566 * @dma_pointer: DMA address of the data buffer referenced by @frag_idx. 2567 * @size: Size of the data buffer (in bytes). 2568 * @misaligned_size: Size (in bytes) of the misaligned portion of the 2569 * data buffer. Calculated by the caller, based on the platform/OS/other 2570 * specific criteria, which is outside of HAL's domain. See notes below. 2571 * 2572 * This API is part of the transmit descriptor preparation for posting 2573 * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include 2574 * vxge_hal_fifo_txdl_mss_set() and vxge_hal_fifo_txdl_cksum_set_bits(). 2575 * All three APIs fill in the fields of the fifo descriptor, 2576 * in accordance with the X3100 specification. 2577 * On the PCI-X based systems aligning transmit data typically provides better 2578 * transmit performance. The typical alignment granularity: L2 cacheline size. 2579 * However, HAL does not make assumptions in terms of the alignment granularity; 2580 * this is specified via additional @misaligned_size parameter described above. 2581 * Prior to calling vxge_hal_fifo_txdl_buffer_set_aligned(), 2582 * ULD is supposed to check alignment of a given fragment/buffer. For this HAL 2583 * provides a separate vxge_hal_check_alignment() API sufficient to cover 2584 * most (but not all) possible alignment criteria. 2585 * If the buffer appears to be aligned, the ULD calls 2586 * vxge_hal_fifo_txdl_buffer_set(). 2587 * Otherwise, ULD calls vxge_hal_fifo_txdl_buffer_set_aligned(). 2588 * 2589 * Note; This API is a "superset" of vxge_hal_fifo_txdl_buffer_set(). In 2590 * addition to filling in the specified descriptor it aligns transmit data on 2591 * the specified boundary. 2592 * Note: Decision on whether to align or not to align a given contiguous 2593 * transmit buffer is outside of HAL's domain. To this end ULD can use any 2594 * programmable criteria, which can help to 1) boost transmit performance, 2595 * and/or 2) provide a workaround for PCI bridge bugs, if any. 2596 * 2597 */ 2598vxge_hal_status_e 2599vxge_hal_fifo_txdl_buffer_set_aligned( 2600 vxge_hal_vpath_h vpath_handle, 2601 vxge_hal_txdl_h txdlh, 2602 u32 frag_idx, 2603 void *vaddr, 2604 dma_addr_t dma_pointer, 2605 u32 size, 2606 u32 misaligned_size); 2607 2608/* 2609 * vxge_hal_fifo_txdl_buffer_append - Append the contents of virtually 2610 * contiguous data buffer to a single physically contiguous buffer. 2611 * @vpath_handle: Virtual path handle. 2612 * @txdlh: Descriptor handle. 2613 * @vaddr: Virtual address of the data buffer. 2614 * @size: Size of the data buffer (in bytes). 2615 * 2616 * This API is part of the transmit descriptor preparation for posting 2617 * (via vxge_hal_fifo_txdl_post()). 2618 * The main difference of this API wrt to the APIs 2619 * vxge_hal_fifo_txdl_buffer_set_aligned() is that this API appends the 2620 * contents of virtually contiguous data buffers received from 2621 * upper layer into a single physically contiguous data buffer and the 2622 * device will do a DMA from this buffer. 2623 * 2624 * See Also: vxge_hal_fifo_txdl_buffer_finalize(), 2625 * vxge_hal_fifo_txdl_buffer_set(), 2626 * vxge_hal_fifo_txdl_buffer_set_aligned(). 2627 */ 2628vxge_hal_status_e 2629vxge_hal_fifo_txdl_buffer_append( 2630 vxge_hal_vpath_h vpath_handle, 2631 vxge_hal_txdl_h txdlh, 2632 void *vaddr, 2633 u32 size); 2634/* 2635 * vxge_hal_fifo_txdl_buffer_finalize - Prepares a descriptor that contains the 2636 * single physically contiguous buffer. 2637 * 2638 * @vpath_handle: Virtual path handle. 2639 * @txdlh: Descriptor handle. 2640 * @frag_idx: Index of the data buffer in the Txdl list. 2641 * 2642 * This API in conjuction with vxge_hal_fifo_txdl_buffer_append() prepares 2643 * a descriptor that consists of a single physically contiguous buffer 2644 * which inturn contains the contents of one or more virtually contiguous 2645 * buffers received from the upper layer. 2646 * 2647 * See Also: vxge_hal_fifo_txdl_buffer_append(). 2648 */ 2649void 2650vxge_hal_fifo_txdl_buffer_finalize( 2651 vxge_hal_vpath_h vpath_handle, 2652 vxge_hal_txdl_h txdlh, 2653 u32 frag_idx); 2654 2655/* 2656 * vxge_hal_fifo_txdl_new_frame_set - Start the new packet by setting TXDL flags 2657 * @vpath_handle: virtual path handle. 2658 * @txdlh: Descriptor handle. 2659 * 2660 * This API is part of the preparation of the transmit descriptor for posting 2661 * (via vxge_hal_fifo_txdl_post()). This api is used to mark the end of previous 2662 * frame and start of a new frame. 2663 * 2664 */ 2665void 2666vxge_hal_fifo_txdl_new_frame_set( 2667 vxge_hal_vpath_h vpath_handle, 2668 vxge_hal_txdl_h txdlh, 2669 u32 tagged); 2670 2671/* 2672 * vxge_hal_fifo_txdl_post - Post descriptor on the fifo. 2673 * @vpath_handle: Virtual path handle. 2674 * @txdlh: Descriptor obtained via vxge_hal_fifo_txdl_reserve() 2675 * 2676 * Post descriptor on the fifo for transmission. 2677 * Prior to posting the descriptor should be filled in accordance with 2678 * Host/X3100 interface specification for a given service (LL, etc.). 2679 * 2680 */ 2681void 2682vxge_hal_fifo_txdl_post( 2683 vxge_hal_vpath_h vpath_handle, 2684 vxge_hal_txdl_h txdlh, 2685 u32 tagged); 2686 2687/* 2688 * vxge_hal_fifo_is_next_txdl_completed - Checks if the next txdl is completed 2689 * @vpath_handle: Virtual path handle. 2690 */ 2691vxge_hal_status_e 2692vxge_hal_fifo_is_next_txdl_completed( 2693 vxge_hal_vpath_h vpath_handle); 2694 2695/* 2696 * vxge_hal_fifo_free_txdl_count_get - returns the number of txdls available 2697 * in the fifo 2698 * @vpath_handle: Virtual path handle. 2699 */ 2700u32 2701vxge_hal_fifo_free_txdl_count_get( 2702 vxge_hal_vpath_h vpath_handle); 2703 2704/* 2705 * vxge_hal_fifo_txdl_next_completed - Retrieve next completed descriptor. 2706 * @vpath_handle: Virtual path handle. 2707 * @txdlh: Descriptor handle. Returned by HAL. 2708 * @txdl_priv: Buffer to return the pointer to per txdl space allocated 2709 * @t_code: Transfer code, as per X3100 User Guide, 2710 * Transmit Descriptor Format. 2711 * Returned by HAL. 2712 * 2713 * Retrieve the _next_ completed descriptor. 2714 * HAL uses fifo callback (*vxge_hal_fifo_callback_f) to notifiy 2715 * upper-layer driver (ULD) of new completed descriptors. After that 2716 * the ULD can use vxge_hal_fifo_txdl_next_completed to retrieve the rest 2717 * completions (the very first completion is passed by HAL via 2718 * vxge_hal_fifo_callback_f). 2719 * 2720 * Implementation-wise, the upper-layer driver is free to call 2721 * vxge_hal_fifo_txdl_next_completed either immediately from inside the 2722 * fifo callback, or in a deferred fashion and separate (from HAL) 2723 * context. 2724 * 2725 * Non-zero @t_code means failure to process the descriptor. 2726 * The failure could happen, for instance, when the link is 2727 * down, in which case X3100 completes the descriptor because it 2728 * is not able to send the data out. 2729 * 2730 * For details please refer to X3100 User Guide. 2731 * 2732 * Returns: VXGE_HAL_OK - success. 2733 * VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors 2734 * are currently available for processing. 2735 * 2736 */ 2737vxge_hal_status_e 2738vxge_hal_fifo_txdl_next_completed( 2739 vxge_hal_vpath_h vpath_handle, 2740 vxge_hal_txdl_h *txdlh, 2741 void **txdl_priv, 2742 vxge_hal_fifo_tcode_e *t_code); 2743 2744/* 2745 * vxge_hal_fifo_handle_tcode - Handle transfer code. 2746 * @vpath_handle: Virtual Path handle. 2747 * @txdlh: Descriptor handle. 2748 * @t_code: One of the enumerated (and documented in the X3100 user guide) 2749 * "transfer codes". 2750 * 2751 * Handle descriptor's transfer code. The latter comes with each completed 2752 * descriptor. 2753 * 2754 * Returns: one of the vxge_hal_status_e {} enumerated types. 2755 * VXGE_HAL_OK - for success. 2756 * VXGE_HAL_ERR_CRITICAL - when encounters critical error. 2757 */ 2758vxge_hal_status_e 2759vxge_hal_fifo_handle_tcode( 2760 vxge_hal_vpath_h vpath_handle, 2761 vxge_hal_txdl_h txdlh, 2762 vxge_hal_fifo_tcode_e t_code); 2763 2764/* 2765 * vxge_hal_fifo_txdl_private_get - Retrieve per-descriptor private data. 2766 * @vpath_handle: Virtual path handle. 2767 * @txdlh: Descriptor handle. 2768 * 2769 * Retrieve per-descriptor private data. 2770 * Note that ULD requests per-descriptor space via 2771 * vxge_hal_fifo_attr_t passed to 2772 * vxge_hal_vpath_open(). 2773 * 2774 * Returns: private ULD data associated with the descriptor. 2775 */ 2776void * 2777vxge_hal_fifo_txdl_private_get( 2778 vxge_hal_vpath_h vpath_handle, 2779 vxge_hal_txdl_h txdlh); 2780 2781/* 2782 * vxge_hal_fifo_txdl_free - Free descriptor. 2783 * @vpath_handle: Virtual path handle. 2784 * @txdlh: Descriptor handle. 2785 * 2786 * Free the reserved descriptor. This operation is "symmetrical" to 2787 * vxge_hal_fifo_txdl_reserve. The "free-ing" completes the descriptor's 2788 * lifecycle. 2789 * 2790 * After free-ing (see vxge_hal_fifo_txdl_free()) the descriptor again can 2791 * be: 2792 * 2793 * - reserved (vxge_hal_fifo_txdl_reserve); 2794 * 2795 * - posted (vxge_hal_fifo_txdl_post); 2796 * 2797 * - completed (vxge_hal_fifo_txdl_next_completed); 2798 * 2799 * - and recycled again (vxge_hal_fifo_txdl_free). 2800 * 2801 * For alternative state transitions and more details please refer to 2802 * the design doc. 2803 * 2804 */ 2805void 2806vxge_hal_fifo_txdl_free( 2807 vxge_hal_vpath_h vpath_handle, 2808 vxge_hal_txdl_h txdlh); 2809 2810/* 2811 * Device 2812 */ 2813 2814/* 2815 * enum vxge_hal_card_e - X3100 adapter type. 2816 * @VXGE_HAL_CARD_UNKNOWN: Unknown device. 2817 * @VXGE_HAL_CARD_TITAN: X3100 device. 2818 * 2819 * Enumerates X3100 adapter types. 2820 * 2821 * See also: vxge_hal_device_check_id(). 2822 */ 2823typedef enum vxge_hal_card_e { 2824 VXGE_HAL_CARD_UNKNOWN = 0, 2825 VXGE_HAL_CARD_TITAN_1 = 1, 2826 VXGE_HAL_CARD_TITAN_1A = 2, 2827 VXGE_HAL_CARD_TITAN_2 = 3 2828} vxge_hal_card_e; 2829 2830/* 2831 * struct vxge_hal_device_attr_t - Device memory spaces. 2832 * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 2833 * (Linux and the rest.) 2834 * @regh1: BAR1 mapped memory handle. Same comment as above. 2835 * @regh2: BAR2 mapped memory handle. Same comment as above. 2836 * @bar0: BAR0 virtual address. 2837 * @bar1: BAR1 virtual address. 2838 * @bar2: BAR2 virtual address. 2839 * @irqh: IRQ handle (Solaris). 2840 * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux). 2841 * @pdev: PCI device object. 2842 * 2843 * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device 2844 * mapped memories. Also, includes a pointer to OS-specific PCI device object. 2845 */ 2846typedef struct vxge_hal_device_attr_t { 2847 pci_reg_h regh0; 2848 pci_reg_h regh1; 2849 pci_reg_h regh2; 2850 u8 *bar0; 2851 u8 *bar1; 2852 u8 *bar2; 2853 pci_irq_h irqh; 2854 pci_cfg_h cfgh; 2855 pci_dev_h pdev; 2856} vxge_hal_device_attr_t; 2857 2858/* 2859 * enum vxge_hal_device_link_state_e - Link state enumeration. 2860 * @VXGE_HAL_LINK_NONE: Invalid link state. 2861 * @VXGE_HAL_LINK_DOWN: Link is down. 2862 * @VXGE_HAL_LINK_UP: Link is up. 2863 * 2864 */ 2865typedef enum vxge_hal_device_link_state_e { 2866 VXGE_HAL_LINK_NONE, 2867 VXGE_HAL_LINK_DOWN, 2868 VXGE_HAL_LINK_UP 2869} vxge_hal_device_link_state_e; 2870 2871/* 2872 * enum vxge_hal_device_data_rate_e - Data rate enumeration. 2873 * @VXGE_HAL_DATA_RATE_UNKNOWN: Unknown . 2874 * @VXGE_HAL_DATA_RATE_1G: 1G. 2875 * @VXGE_HAL_DATA_RATE_10G: 10G. 2876 * 2877 */ 2878typedef enum vxge_hal_device_data_rate_e { 2879 VXGE_HAL_DATA_RATE_UNKNOWN, 2880 VXGE_HAL_DATA_RATE_1G, 2881 VXGE_HAL_DATA_RATE_10G 2882} vxge_hal_device_data_rate_e; 2883 2884/* 2885 * enum vxge_hal_device_lag_mode_e - X3100 adapter lag mode 2886 * @VXGE_HAL_DEVICE_LAG_MODE_UNKNOWN: Unknown mode. 2887 * @VXGE_HAL_DEVICE_LAG_MODE_HW_LACP: Hardware Link Aggregation. 2888 * @VXGE_HAL_DEVICE_LAG_MODE_ACTIVE_PASSIVE: Active Passive. 2889 * @VXGE_HAL_DEVICE_LAG_MODE_SINGLE_PORT: Single Port. 2890 * @VXGE_HAL_DEVICE_LAG_MODE_DUAL_PORT: Dual Port. 2891 * @VXGE_HAL_DEVICE_LAG_MODE_DISABLED: Disabled. 2892 * 2893 * Enumerates X3100 adapter lag modes. 2894 * 2895 */ 2896typedef enum vxge_hal_device_lag_mode_e { 2897 VXGE_HAL_DEVICE_LAG_MODE_UNKNOWN = 0, 2898 VXGE_HAL_DEVICE_LAG_MODE_HW_LACP, 2899 VXGE_HAL_DEVICE_LAG_MODE_ACTIVE_PASSIVE, 2900 VXGE_HAL_DEVICE_LAG_MODE_SINGLE_PORT, 2901 VXGE_HAL_DEVICE_LAG_MODE_DUAL_PORT, 2902 VXGE_HAL_DEVICE_LAG_MODE_DISABLED 2903} vxge_hal_device_lag_mode_e; 2904 2905/* 2906 * enum vxge_hal_pci_e_signalling_rate_e - PCI-E Lane signalling rate 2907 * @VXGE_HAL_PCI_E_SIGNALLING_RATE_2_5GB: PCI-E signalling rate 2.5 GB 2908 * @VXGE_HAL_PCI_E_SIGNALLING_RATE_5GB: PCI-E signalling rate 5 GB 2909 * @VXGE_HAL_PCI_E_SIGNALLING_RATE_UNKNOWN: Unrecognized PCI bus frequency 2910 * 2911 * PCI-E Lane signalling rate 2912 */ 2913typedef enum vxge_hal_pci_e_signalling_rate_e { 2914 VXGE_HAL_PCI_E_SIGNALLING_RATE_2_5GB = 1, 2915 VXGE_HAL_PCI_E_SIGNALLING_RATE_5GB = 2, 2916 VXGE_HAL_PCI_E_SIGNALLING_RATE_UNKNOWN = 0 2917} vxge_hal_pci_e_signalling_rate_e; 2918 2919/* 2920 * enum vxge_hal_pci_e_link_width_e - PCI-E Link width enumeration. 2921 * @VXGE_HAL_PCI_E_LINK_WIDTH_X1: 1 Lane. 2922 * @VXGE_HAL_PCI_E_LINK_WIDTH_X2: 2 Lane. 2923 * @VXGE_HAL_PCI_E_LINK_WIDTH_X4: 4 Lane. 2924 * @VXGE_HAL_PCI_E_LINK_WIDTH_X8: 8 Lane. 2925 * @VXGE_HAL_PCI_E_LINK_WIDTH_X12: 12 Lane. 2926 * @VXGE_HAL_PCI_E_LINK_WIDTH_X16: 16 Lane. 2927 * @VXGE_HAL_PCI_E_LINK_WIDTH_X32: 32 Lane. 2928 * @VXGE_HAL_PCI_E_LINK_WIDTH_UNKNOWN: Unknown 2929 * 2930 * PCI-E Link width enumeration. 2931 */ 2932typedef enum vxge_hal_pci_e_link_width_e { 2933 VXGE_HAL_PCI_E_LINK_WIDTH_X1 = 1, 2934 VXGE_HAL_PCI_E_LINK_WIDTH_X2 = 2, 2935 VXGE_HAL_PCI_E_LINK_WIDTH_X4 = 4, 2936 VXGE_HAL_PCI_E_LINK_WIDTH_X8 = 8, 2937 VXGE_HAL_PCI_E_LINK_WIDTH_X12 = 12, 2938 VXGE_HAL_PCI_E_LINK_WIDTH_X16 = 16, 2939 VXGE_HAL_PCI_E_LINK_WIDTH_X32 = 32, 2940 VXGE_HAL_PCI_E_LINK_WIDTH_UNKNOWN = 0 2941} vxge_hal_pci_e_link_width_e; 2942 2943#define VXGE_HAL_DEVICE_STATS_SW_INFO_NOT_TRAFFIC_INTR(hldev) \ 2944 ((vxge_hal_device_t *)hldev)->not_traffic_intr_cnt++ 2945 2946#define VXGE_HAL_DEVICE_STATS_SW_INFO_TRAFFIC_INTR(hldev) \ 2947 ((vxge_hal_device_t *)hldev)->traffic_intr_cnt++ 2948 2949/* 2950 * struct vxge_hal_device_t - Hal device object 2951 * @magic: Magic Number 2952 * @device_id: PCI Device Id of the adapter 2953 * @revision: PCI Device major revision 2954 * @upper_layer_data: Private data set by LL driver 2955 * @signalling_rate: PCI-E signalling rate 2956 * @link_width: see vxge_hal_pci_e_link_width_e {} 2957 * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 2958 * (Linux and the rest.) 2959 * @regh1: BAR1 mapped memory handle. Same comment as above. 2960 * @regh2: BAR2 mapped memory handle. Same comment as above. 2961 * @bar0: BAR0 virtual address. 2962 * @bar1: BAR1 virtual address. 2963 * @bar2: BAR2 virtual address. 2964 * @irqh: IRQ handle 2965 * @cfgh: Configuration space handle 2966 * @pdev: Physical device handle 2967 * @config: Confguration passed by the LL driver at initialization 2968 * @is_initialized: Flag to specify if device is initialized 2969 * @msix_enabled: Flag to indicate if msix is enabled 2970 * @terminating: Flag to specify if the device is terminating 2971 * @link_state: Link state 2972 * @data_rate: Data rate 2973 * @not_traffic_intr_cnt: Number of times the host was interrupted 2974 * without new completions. 2975 * "Non-traffic interrupt counter". 2976 * @traffic_intr_cnt: Number of traffic interrupts for the device. 2977 * @debug_module_mask: Debug module mask 2978 * @debug_level: Debug Level 2979 * 2980 * HAL device object. Represents Titan adapter 2981 */ 2982typedef struct vxge_hal_device_t { 2983 u32 magic; 2984#define VXGE_HAL_DEVICE_MAGIC 0x12345678 2985#define VXGE_HAL_DEVICE_DEAD 0xDEADDEAD 2986 u16 device_id; 2987 u16 revision; 2988 void *upper_layer_data; 2989 vxge_hal_pci_e_signalling_rate_e signalling_rate; 2990 vxge_hal_pci_e_link_width_e link_width; 2991 pci_reg_h regh0; 2992 pci_reg_h regh1; 2993 pci_reg_h regh2; 2994 u8 *bar0; 2995 u8 *bar1; 2996 u8 *bar2; 2997 pci_irq_h irqh; 2998 pci_cfg_h cfgh; 2999 pci_dev_h pdev; 3000 vxge_hal_device_config_t config; 3001 volatile u32 is_initialized; 3002 volatile u32 msix_enabled; 3003 volatile u32 terminating; 3004 volatile vxge_hal_device_link_state_e link_state; 3005 volatile vxge_hal_device_data_rate_e data_rate; 3006 volatile u32 not_traffic_intr_cnt; 3007 volatile u32 traffic_intr_cnt; 3008 u32 debug_module_mask; 3009 u32 debug_level; 3010} vxge_hal_device_t; 3011 3012/* 3013 * struct vxge_hal_device_date_t - Date Format 3014 * @day: Day 3015 * @month: Month 3016 * @year: Year 3017 * @date: Date in string format 3018 * 3019 * Structure for returning date 3020 */ 3021typedef struct vxge_hal_device_date_t { 3022 u32 day; 3023 u32 month; 3024 u32 year; 3025 char date[16]; 3026} vxge_hal_device_date_t; 3027 3028/* 3029 * struct vxge_hal_device_version_t - Version Format 3030 * @major: Major Version 3031 * @minor: Minor Version 3032 * @build: Build Number 3033 * @version: Version in string format 3034 * 3035 * Structure for returning version 3036 */ 3037typedef struct vxge_hal_device_version_t { 3038 u32 major; 3039 u32 minor; 3040 u32 build; 3041 char version[32]; 3042} vxge_hal_device_version_t; 3043 3044/* 3045 * struct vxge_hal_device_pmd_info_t - PMD Information 3046 * @type: PMD Type 3047 * @vendor: Vender name 3048 * @part_num: PMD Part Number 3049 * @ser_num: PMD Serial Number 3050 * 3051 * Structure for returning PMD info 3052 */ 3053typedef struct vxge_hal_device_pmd_info_t { 3054 u32 type; 3055#define VXGE_HAL_DEVICE_PMD_TYPE_UNKNOWN 0 3056#define VXGE_HAL_DEVICE_PMD_TYPE_10G_SR 1 3057#define VXGE_HAL_DEVICE_PMD_TYPE_10G_LR 2 3058#define VXGE_HAL_DEVICE_PMD_TYPE_10G_LRM 3 3059#define VXGE_HAL_DEVICE_PMD_TYPE_10G_DIRECT 4 3060#define VXGE_HAL_DEVICE_PMD_TYPE_10G_CX4 5 3061#define VXGE_HAL_DEVICE_PMD_TYPE_10G_BASE_T 6 3062#define VXGE_HAL_DEVICE_PMD_TYPE_10G_OTHER 7 3063#define VXGE_HAL_DEVICE_PMD_TYPE_1G_SX 8 3064#define VXGE_HAL_DEVICE_PMD_TYPE_1G_LX 9 3065#define VXGE_HAL_DEVICE_PMD_TYPE_1G_CX 10 3066#define VXGE_HAL_DEVICE_PMD_TYPE_1G_DIRECT 11 3067#define VXGE_HAL_DEVICE_PMD_TYPE_1G_CX4 12 3068#define VXGE_HAL_DEVICE_PMD_TYPE_1G_BASE_T 13 3069#define VXGE_HAL_DEVICE_PMD_TYPE_1G_OTHER 14 3070 u32 unused; 3071 char vendor[24]; 3072 char part_num[24]; 3073 char ser_num[24]; 3074} vxge_hal_device_pmd_info_t; 3075 3076 3077/* 3078 * struct vxge_hal_device_hw_info_t - Device information 3079 * @host_type: Host Type 3080 * @function_mode: PCI Function Mode 3081 * @func_id: Function Id 3082 * @vpath_mask: vpath bit mask 3083 * @fw_version: Firmware version 3084 * @fw_date: Firmware Date 3085 * @flash_version: Firmware version 3086 * @flash_date: Firmware Date 3087 * @serial_number: Card Serial Number 3088 * @part_number: Card Part Number 3089 * @product_description: Card Product Description 3090 * @unused: For Solaris alignment purpose 3091 * @ports: Number of ports present 3092 * @pmd_port0: Port 0 PMD Info 3093 * @pmd_port1: Port 1 PMD Info 3094 * @mac_addrs: Mac addresses for each vpath 3095 * @mac_addr_masks: Mac address masks for each vpath 3096 * 3097 * Returns the vpath mask that has the bits set for each vpath allocated 3098 * for the driver and the first mac addresse for each vpath 3099 */ 3100typedef struct vxge_hal_device_hw_info_t { 3101 u32 host_type; 3102#define VXGE_HAL_NO_MR_NO_SR_NORMAL_FUNCTION 0 3103#define VXGE_HAL_MR_NO_SR_VH0_BASE_FUNCTION 1 3104#define VXGE_HAL_NO_MR_SR_VH0_FUNCTION0 2 3105#define VXGE_HAL_NO_MR_SR_VH0_VIRTUAL_FUNCTION 3 3106#define VXGE_HAL_MR_SR_VH0_INVALID_CONFIG 4 3107#define VXGE_HAL_SR_VH_FUNCTION0 5 3108#define VXGE_HAL_SR_VH_VIRTUAL_FUNCTION 6 3109#define VXGE_HAL_VH_NORMAL_FUNCTION 7 3110 u64 function_mode; 3111 u32 func_id; 3112 u64 vpath_mask; 3113 vxge_hal_device_version_t fw_version; 3114 vxge_hal_device_date_t fw_date; 3115 vxge_hal_device_version_t flash_version; 3116 vxge_hal_device_date_t flash_date; 3117 u8 serial_number[24]; 3118 u8 part_number[24]; 3119 u8 product_description[72]; 3120 u32 unused; 3121 u32 ports; 3122 vxge_hal_device_pmd_info_t pmd_port0; 3123 vxge_hal_device_pmd_info_t pmd_port1; 3124 macaddr_t mac_addrs[VXGE_HAL_MAX_VIRTUAL_PATHS]; 3125 macaddr_t mac_addr_masks[VXGE_HAL_MAX_VIRTUAL_PATHS]; 3126} vxge_hal_device_hw_info_t; 3127 3128/* 3129 * vxge_hal_device_hw_info_get - Get the hw information 3130 * @pdev: PCI device object. 3131 * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 3132 * (Linux and the rest.) 3133 * @bar0: Address of BAR0 in PCI config 3134 * @hw_info: Buffer to return vxge_hal_device_hw_info_t {} structure 3135 * 3136 * Returns the vpath mask that has the bits set for each vpath allocated 3137 * for the driver, FW version information and the first mac addresse for 3138 * each vpath 3139 */ 3140vxge_hal_status_e 3141vxge_hal_device_hw_info_get( 3142 pci_dev_h pdev, 3143 pci_reg_h regh0, 3144 u8 *bar0, 3145 vxge_hal_device_hw_info_t *hw_info); 3146 3147/* 3148 * vxge_hal_device_config_default_get - Initialize device config with defaults. 3149 * @device_config: Configuration structure to be initialized, 3150 * For the X3100 configuration "knobs" please 3151 * refer to vxge_hal_device_config_t and X3100 3152 * User Guide. 3153 * 3154 * Initialize X3100 device config with default values. 3155 * 3156 * See also: vxge_hal_device_initialize(), vxge_hal_device_terminate(), 3157 * vxge_hal_status_e {} vxge_hal_device_attr_t {}. 3158 */ 3159vxge_hal_status_e 3160vxge_hal_device_config_default_get( 3161 vxge_hal_device_config_t *device_config); 3162 3163/* 3164 * vxge_hal_device_initialize - Initialize X3100 device. 3165 * @devh: Buffer to return HAL device handle. 3166 * @attr: pointer to vxge_hal_device_attr_t structure 3167 * @device_config: Configuration to be _applied_ to the device, 3168 * For the X3100 configuration "knobs" please refer to 3169 * vxge_hal_device_config_t and X3100 User Guide. 3170 * 3171 * Initialize X3100 device. Note that all the arguments of this public API 3172 * are 'IN', except @hldev. Upper-layer driver (ULD) cooperates with 3173 * OS to find new X3100 device, locate its PCI and memory spaces. 3174 * 3175 * When done, the ULD allocates sizeof(vxge_hal_device_t) bytes for HAL 3176 * to enable the latter to perform X3100 hardware initialization. 3177 * 3178 * Returns: VXGE_HAL_OK - success. 3179 * VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED - Driver is not initialized. 3180 * VXGE_HAL_ERR_BAD_DEVICE_CONFIG - Device configuration params are not 3181 * valid. 3182 * VXGE_HAL_ERR_OUT_OF_MEMORY - Memory allocation failed. 3183 * VXGE_HAL_ERR_BAD_SUBSYSTEM_ID - Device subsystem id is invalid. 3184 * VXGE_HAL_ERR_INVALID_MAC_ADDRESS - Device mac address in not valid. 3185 * VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to retrieve the mac 3186 * address within the time(timeout) or TTI/RTI initialization failed. 3187 * VXGE_HAL_ERR_SWAPPER_CTRL - Failed to configure swapper control. 3188 * 3189 * See also: vxge_hal_device_terminate(), vxge_hal_status_e {} 3190 * vxge_hal_device_attr_t {}. 3191 */ 3192vxge_hal_status_e 3193vxge_hal_device_initialize( 3194 vxge_hal_device_h *devh, 3195 vxge_hal_device_attr_t *attr, 3196 vxge_hal_device_config_t *device_config); 3197 3198/* 3199 * vxge_hal_device_check_id - Verify device ID. 3200 * @devh: HAL device handle. 3201 * 3202 * Verify device ID. 3203 * Returns: one of the vxge_hal_card_e {} enumerated types. 3204 * See also: vxge_hal_card_e {}. 3205 */ 3206static inline 3207/* LINTED */ 3208vxge_hal_card_e vxge_hal_device_check_id( 3209 vxge_hal_device_h devh) 3210{ 3211 vxge_hal_device_t *hldev = (vxge_hal_device_t *) devh; 3212 switch (hldev->device_id) { 3213 case VXGE_PCI_DEVICE_ID_TITAN_1: 3214 if (hldev->revision == VXGE_PCI_REVISION_TITAN_1) 3215 return (VXGE_HAL_CARD_TITAN_1); 3216 else if (hldev->revision == VXGE_PCI_REVISION_TITAN_1A) 3217 return (VXGE_HAL_CARD_TITAN_1A); 3218 else 3219 break; 3220 3221 case VXGE_PCI_DEVICE_ID_TITAN_2: 3222 if (hldev->revision == VXGE_PCI_REVISION_TITAN_2) 3223 return (VXGE_HAL_CARD_TITAN_2); 3224 else 3225 break; 3226 default: 3227 break; 3228 } 3229 3230 return (VXGE_HAL_CARD_UNKNOWN); 3231} 3232 3233/* 3234 * vxge_hal_device_revision_get - Get Device revision number. 3235 * @devh: HAL device handle. 3236 * 3237 * Returns: Device revision number 3238 */ 3239static inline 3240/* LINTED */ 3241u32 vxge_hal_device_revision_get( 3242 vxge_hal_device_h devh) 3243{ 3244 return (((vxge_hal_device_t *) devh)->revision); 3245} 3246 3247/* 3248 * vxge_hal_device_pciconfig_get - Read the content of given address 3249 * in pci config space. 3250 * @devh: Device handle. 3251 * @offset: Configuration address(offset)to read from 3252 * @length: Length of the data (1, 2 or 4 bytes) 3253 * @val: Pointer to a buffer to return the content of the address 3254 * 3255 * Read from the pci config space. 3256 * 3257 */ 3258vxge_hal_status_e 3259vxge_hal_device_pciconfig_get( 3260 vxge_hal_device_h devh, 3261 u32 offset, 3262 u32 length, 3263 void *val); 3264 3265/* 3266 * vxge_hal_device_bar0_get - Get BAR0 mapped address. 3267 * @devh: HAL device handle. 3268 * 3269 * Returns: BAR0 address of the specified device. 3270 */ 3271static inline 3272/* LINTED */ 3273u8 *vxge_hal_device_bar0_get( 3274 vxge_hal_device_h devh) 3275{ 3276 return (((vxge_hal_device_t *) devh)->bar0); 3277} 3278 3279/* 3280 * vxge_hal_device_bar1_get - Get BAR1 mapped address. 3281 * @devh: HAL device handle. 3282 * 3283 * Returns: BAR1 address of the specified device. 3284 */ 3285static inline 3286/* LINTED */ 3287u8 *vxge_hal_device_bar1_get( 3288 vxge_hal_device_h devh) 3289{ 3290 return (((vxge_hal_device_t *) devh)->bar1); 3291} 3292 3293/* 3294 * vxge_hal_device_bar2_get - Get BAR2 mapped address. 3295 * @devh: HAL device handle. 3296 * 3297 * Returns: BAR2 address of the specified device. 3298 */ 3299static inline 3300/* LINTED */ 3301u8 *vxge_hal_device_bar2_get( 3302 vxge_hal_device_h devh) 3303{ 3304 return (((vxge_hal_device_t *) devh)->bar2); 3305} 3306 3307/* 3308 * vxge_hal_device_bar0_set - Set BAR0 mapped address. 3309 * @devh: HAL device handle. 3310 * @bar0: BAR0 mapped address. 3311 * * Set BAR0 address in the HAL device object. 3312 */ 3313static inline 3314/* LINTED */ 3315void 3316vxge_hal_device_bar0_set( 3317 vxge_hal_device_h devh, 3318 u8 *bar0) 3319{ 3320 ((vxge_hal_device_t *) devh)->bar0 = bar0; 3321} 3322 3323/* 3324 * vxge_hal_device_bar1_set - Set BAR1 mapped address. 3325 * @devh: HAL device handle. 3326 * @bar1: BAR1 mapped address. 3327 * 3328 * Set BAR1 address in the HAL Device Object. 3329 */ 3330static inline 3331/* LINTED */ 3332void 3333vxge_hal_device_bar1_set( 3334 vxge_hal_device_h devh, 3335 u8 *bar1) 3336{ 3337 ((vxge_hal_device_t *) devh)->bar1 = bar1; 3338} 3339 3340/* 3341 * vxge_hal_device_bar2_set - Set BAR2 mapped address. 3342 * @devh: HAL device handle. 3343 * @bar2: BAR2 mapped address. 3344 * 3345 * Set BAR2 address in the HAL Device Object. 3346 */ 3347static inline 3348/* LINTED */ 3349void 3350vxge_hal_device_bar2_set( 3351 vxge_hal_device_h devh, 3352 u8 *bar2) 3353{ 3354 ((vxge_hal_device_t *) devh)->bar2 = bar2; 3355} 3356 3357/* 3358 * vxge_hal_device_enable - Enable device. 3359 * @devh: HAL device handle. 3360 * 3361 * Enable the specified device: bring up the link/interface. 3362 * 3363 */ 3364vxge_hal_status_e 3365vxge_hal_device_enable( 3366 vxge_hal_device_h devh); 3367 3368/* 3369 * vxge_hal_device_disable - Disable X3100 adapter. 3370 * @devh: HAL device handle. 3371 * 3372 * Disable this device. To gracefully reset the adapter, the host should: 3373 * 3374 * - call vxge_hal_device_disable(); 3375 * 3376 * - call vxge_hal_device_intr_disable(); 3377 * 3378 * - do some work (error recovery, change mtu, reset, etc); 3379 * 3380 * - call vxge_hal_device_enable(); 3381 * 3382 * - call vxge_hal_device_intr_enable(). 3383 * 3384 * Note: Disabling the device does _not_ include disabling of interrupts. 3385 * After disabling the device stops receiving new frames but those frames 3386 * that were already in the pipe will keep coming for some few milliseconds. 3387 * 3388 * 3389 */ 3390vxge_hal_status_e 3391vxge_hal_device_disable( 3392 vxge_hal_device_h devh); 3393 3394/* 3395 * vxge_hal_device_pci_info_get - Get PCI bus informations such as width, 3396 * frequency, and mode from previously stored values. 3397 * @devh: HAL device handle. 3398 * @signalling_rate: pointer to a variable of enumerated type 3399 * vxge_hal_pci_e_signalling_rate_e {}. 3400 * @link_width: pointer to a variable of enumerated type 3401 * vxge_hal_pci_e_link_width_e {}. 3402 * 3403 * Get pci-e signalling rate and link width. 3404 * 3405 * Returns: one of the vxge_hal_status_e {} enumerated types. 3406 * VXGE_HAL_OK - for success. 3407 * VXGE_HAL_ERR_INVALID_DEVICE - for invalid device handle. 3408 */ 3409static inline 3410/* LINTED */ 3411vxge_hal_status_e vxge_hal_device_pci_info_get( 3412 vxge_hal_device_h devh, 3413 vxge_hal_pci_e_signalling_rate_e *signalling_rate, 3414 vxge_hal_pci_e_link_width_e *link_width) 3415{ 3416 vxge_hal_device_t *hldev = (vxge_hal_device_t *) devh; 3417 3418 if (!hldev || !hldev->is_initialized || 3419 (hldev->magic != VXGE_HAL_DEVICE_MAGIC)) { 3420 return (VXGE_HAL_ERR_INVALID_DEVICE); 3421 } 3422 *signalling_rate = hldev->signalling_rate; 3423 *link_width = hldev->link_width; 3424 3425 return (VXGE_HAL_OK); 3426} 3427 3428/* 3429 * vxge_hal_device_link_state_test - Test the link state. 3430 * @devh: HAL device handle. 3431 * 3432 * Test link state. 3433 * Returns: link state. 3434 */ 3435vxge_hal_device_link_state_e 3436vxge_hal_device_link_state_test( 3437 vxge_hal_device_h devh); 3438 3439/* 3440 * vxge_hal_device_link_state_get - Get link state. 3441 * @devh: HAL device handle. 3442 * 3443 * Get link state. 3444 * Returns: link state. 3445 */ 3446static inline 3447/* LINTED */ 3448vxge_hal_device_link_state_e vxge_hal_device_link_state_get( 3449 vxge_hal_device_h devh) 3450{ 3451 return (((vxge_hal_device_t *) devh)->link_state); 3452} 3453 3454/* 3455 * vxge_hal_device_link_state_poll - Poll for the link state. 3456 * @devh: HAL device handle. 3457 * 3458 * Get link state. 3459 * Returns: link state. 3460 */ 3461vxge_hal_device_link_state_e 3462vxge_hal_device_link_state_poll( 3463 vxge_hal_device_h devh); 3464 3465/* 3466 * vxge_hal_device_data_rate_get - Get data rate. 3467 * @devh: HAL device handle. 3468 * 3469 * Get data rate. 3470 * Returns: data rate(1G or 10G). 3471 */ 3472static inline 3473/* LINTED */ 3474vxge_hal_device_data_rate_e vxge_hal_device_data_rate_get( 3475 vxge_hal_device_h devh) 3476{ 3477 return (((vxge_hal_device_t *) devh)->data_rate); 3478} 3479 3480/* 3481 * vxge_hal_device_data_rate_poll - Poll for the data rate. 3482 * @devh: HAL device handle. 3483 * 3484 * Get data rate. 3485 * Returns: data rate. 3486 */ 3487vxge_hal_device_data_rate_e 3488vxge_hal_device_data_rate_poll( 3489 vxge_hal_device_h devh); 3490 3491/* 3492 * vxge_hal_device_lag_mode_get - Get Current LAG Mode 3493 * @devh: HAL device handle. 3494 * 3495 * Get Current LAG Mode 3496 */ 3497vxge_hal_device_lag_mode_e 3498vxge_hal_device_lag_mode_get( 3499 vxge_hal_device_h devh); 3500 3501/* 3502 * vxge_hal_device_reset - Reset device. 3503 * @devh: HAL device handle. 3504 * 3505 * Soft-reset the device, reset the device stats except reset_cnt. 3506 * 3507 * After reset is done, will try to re-initialize HW. 3508 * 3509 * Returns: VXGE_HAL_PENDING - successfully sent reset to device. 3510 * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 3511 * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 3512 * 3513 */ 3514vxge_hal_status_e 3515vxge_hal_device_reset( 3516 vxge_hal_device_h devh); 3517 3518/* 3519 * vxge_hal_device_reset_poll - Poll the device for reset complete. 3520 * @devh: HAL device handle. 3521 * 3522 * Poll the device for reset complete 3523 * 3524 * Returns: VXGE_HAL_OK - success. 3525 * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 3526 * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 3527 * 3528 * See also: vxge_hal_status_e {}. 3529 */ 3530vxge_hal_status_e 3531vxge_hal_device_reset_poll(vxge_hal_device_h devh); 3532 3533/* 3534 * vxge_hal_device_mrpcim_reset_poll - Poll the device for mrpcim reset 3535 * complete. 3536 * @devh: HAL device handle. 3537 * 3538 * Poll the device for mrpcim reset complete 3539 * 3540 * Returns: VXGE_HAL_OK - success. 3541 * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 3542 * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 3543 * VXGE_HAL_ERR_MANAGER_NOT_FOUND - MRPCIM/SRPCIM manager not found 3544 * VXGE_HAL_ERR_TIME_OUT - Device Reset timed out 3545 * 3546 * See also: vxge_hal_status_e {}. 3547 */ 3548vxge_hal_status_e 3549vxge_hal_device_mrpcim_reset_poll(vxge_hal_device_h devh); 3550 3551/* 3552 * vxge_hal_device_terminating - Mark the device as 'terminating'. 3553 * @devh: HAL device handle. 3554 * 3555 * Mark the device as 'terminating', going to terminate. Can be used 3556 * to serialize termination with other running processes/contexts. 3557 * 3558 * See also: vxge_hal_device_terminate(). 3559 */ 3560static inline void 3561/* LINTED */ 3562vxge_hal_device_terminating(vxge_hal_device_h devh) 3563{ 3564 ((vxge_hal_device_t *) devh)->terminating = 1; 3565} 3566 3567/* 3568 * vxge_hal_device_terminate - Terminate X3100 device. 3569 * @devh: HAL device handle. 3570 * 3571 * Terminate HAL device. 3572 * 3573 * See also: vxge_hal_device_initialize(). 3574 */ 3575void 3576vxge_hal_device_terminate( 3577 vxge_hal_device_h devh); 3578 3579/* 3580 * vxge_hal_device_private_set - Set ULD context. 3581 * @devh: HAL device handle. 3582 * @data: pointer to ULD context 3583 * 3584 * Use HAL device to set upper-layer driver (ULD) context. 3585 * 3586 * See also: vxge_hal_device_private_get() 3587 */ 3588static inline 3589/* LINTED */ 3590void vxge_hal_device_private_set( 3591 vxge_hal_device_h devh, 3592 void *data) 3593{ 3594 ((vxge_hal_device_t *) devh)->upper_layer_data = data; 3595} 3596 3597/* 3598 * vxge_hal_device_private_get - Get ULD context. 3599 * @devh: HAL device handle. 3600 * 3601 * Use HAL device to set upper-layer driver (ULD) context. 3602 * 3603 * See also: vxge_hal_device_private_get() 3604 */ 3605static inline 3606/* LINTED */ 3607void *vxge_hal_device_private_get( 3608 vxge_hal_device_h devh) 3609{ 3610 return (((vxge_hal_device_t *) devh)->upper_layer_data); 3611} 3612 3613/* 3614 * vxge_hal_device_status - Check whether X3100 hardware is ready for 3615 * operation. 3616 * @devh: HAL device handle. 3617 * @hw_status: X3100 status register. Returned by HAL. 3618 * 3619 * Check whether X3100 hardware is ready for operation. 3620 * The checking includes TDMA, RDMA, PFC, PIC, MC_DRAM, and the rest 3621 * hardware functional blocks. 3622 * 3623 * Returns: VXGE_HAL_OK if the device is ready for operation. Otherwise 3624 * returns VXGE_HAL_FAIL. Also, fills in adapter status (in @hw_status). 3625 * 3626 * See also: vxge_hal_status_e {}. 3627 * Usage: See ex_open {}. 3628 */ 3629vxge_hal_status_e 3630vxge_hal_device_status(vxge_hal_device_h devh, u64 *hw_status); 3631 3632/* 3633 * vxge_hal_device_is_slot_freeze 3634 * @devh: the device 3635 * 3636 * Returns non-zero if the slot is freezed. 3637 * The determination is made based on the adapter_status 3638 * register which will never give all FFs, unless PCI read 3639 * cannot go through. 3640 */ 3641int 3642vxge_hal_device_is_slot_freeze(vxge_hal_device_h devh); 3643 3644/* 3645 * vxge_hal_device_is_traffic_interrupt 3646 * @reason: The reason returned by the vxge)hal_device_begin_irq 3647 * @vp_id: Id of vpath for which to check the interrupt 3648 * 3649 * Returns non-zero if traffic interrupt raised, 0 otherwise 3650 */ 3651static inline u64 3652/* LINTED */ 3653vxge_hal_device_is_traffic_interrupt(u64 reason, u32 vp_id) 3654{ 3655 return (reason & mBIT(vp_id + 3)); 3656} 3657 3658/* 3659 * vxge_hal_device_intr_enable - Enable X3100 interrupts. 3660 * @devh: HAL device handle. 3661 * @op: One of the vxge_hal_device_intr_e enumerated values specifying 3662 * the type(s) of interrupts to enable. 3663 * 3664 * Enable X3100 interrupts. The function is to be executed the last in 3665 * X3100 initialization sequence. 3666 * 3667 * See also: vxge_hal_device_intr_disable() 3668 */ 3669void 3670vxge_hal_device_intr_enable( 3671 vxge_hal_device_h devh); 3672 3673/* 3674 * vxge_hal_device_intr_disable - Disable X3100 interrupts. 3675 * @devh: HAL device handle. 3676 * @op: One of the vxge_hal_device_intr_e enumerated values specifying 3677 * the type(s) of interrupts to disable. 3678 * 3679 * Disable X3100 interrupts. 3680 * 3681 * See also: vxge_hal_device_intr_enable() 3682 */ 3683void 3684vxge_hal_device_intr_disable( 3685 vxge_hal_device_h devh); 3686 3687/* 3688 * vxge_hal_device_mask_all - Mask all device interrupts. 3689 * @devh: HAL device handle. 3690 * 3691 * Mask all device interrupts. 3692 * 3693 * See also: vxge_hal_device_unmask_all() 3694 */ 3695void 3696vxge_hal_device_mask_all( 3697 vxge_hal_device_h devh); 3698 3699/* 3700 * vxge_hal_device_unmask_all - Unmask all device interrupts. 3701 * @devh: HAL device handle. 3702 * 3703 * Unmask all device interrupts. 3704 * 3705 * See also: vxge_hal_device_mask_all() 3706 */ 3707void 3708vxge_hal_device_unmask_all( 3709 vxge_hal_device_h devh); 3710 3711/* 3712 * vxge_hal_device_begin_irq - Begin IRQ processing. 3713 * @devh: HAL device handle. 3714 * @skip_alarms: Do not clear the alarms 3715 * @reason: "Reason" for the interrupt, the value of X3100's 3716 * general_int_status register. 3717 * 3718 * The function performs two actions, It first checks whether (shared IRQ) the 3719 * interrupt was raised by the device. Next, it masks the device interrupts. 3720 * 3721 * Note: 3722 * vxge_hal_device_begin_irq() does not flush MMIO writes through the 3723 * bridge. Therefore, two back-to-back interrupts are potentially possible. 3724 * It is the responsibility of the ULD to make sure that only one 3725 * vxge_hal_device_continue_irq() runs at a time. 3726 * 3727 * Returns: 0, if the interrupt is not "ours" (note that in this case the 3728 * device remain enabled). 3729 * Otherwise, vxge_hal_device_begin_irq() returns 64bit general adapter 3730 * status. 3731 * See also: vxge_hal_device_handle_irq() 3732 */ 3733vxge_hal_status_e 3734vxge_hal_device_begin_irq( 3735 vxge_hal_device_h devh, 3736 u32 skip_alarms, 3737 u64 *reason); 3738 3739/* 3740 * vxge_hal_device_continue_irq - Continue handling IRQ: process all 3741 * completed descriptors. 3742 * @devh: HAL device handle. 3743 * 3744 * Process completed descriptors and unmask the device interrupts. 3745 * 3746 * The vxge_hal_device_continue_irq() walks all open virtual paths 3747 * and calls upper-layer driver (ULD) via supplied completion 3748 * callback. 3749 * 3750 * Note that the vxge_hal_device_continue_irq is part of the _fast_ path. 3751 * To optimize the processing, the function does _not_ check for 3752 * errors and alarms. 3753 * 3754 * Returns: VXGE_HAL_OK. 3755 * 3756 * See also: vxge_hal_device_handle_irq(), 3757 * vxge_hal_ring_rxd_next_completed(), 3758 * vxge_hal_fifo_txdl_next_completed(), vxge_hal_ring_callback_f {}, 3759 * vxge_hal_fifo_callback_f {}. 3760 */ 3761vxge_hal_status_e 3762vxge_hal_device_continue_irq( 3763 vxge_hal_device_h devh); 3764 3765/* 3766 * vxge_hal_device_handle_irq - Handle device IRQ. 3767 * @devh: HAL device handle. 3768 * @skip_alarms: Do not clear the alarms 3769 * 3770 * Perform the complete handling of the line interrupt. The function 3771 * performs two calls. 3772 * First it uses vxge_hal_device_begin_irq() to check the reason for 3773 * the interrupt and mask the device interrupts. 3774 * Second, it calls vxge_hal_device_continue_irq() to process all 3775 * completed descriptors and re-enable the interrupts. 3776 * 3777 * Returns: VXGE_HAL_OK - success; 3778 * VXGE_HAL_ERR_WRONG_IRQ - (shared) IRQ produced by other device. 3779 * 3780 * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(). 3781 */ 3782vxge_hal_status_e 3783vxge_hal_device_handle_irq( 3784 vxge_hal_device_h devh, 3785 u32 skip_alarms); 3786 3787/* 3788 * vxge_hal_device_mask_tx - Mask Tx interrupts. 3789 * @devh: HAL device. 3790 * 3791 * Mask Tx device interrupts. 3792 * 3793 * See also: vxge_hal_device_unmask_tx(), vxge_hal_device_mask_rx(), 3794 * vxge_hal_device_clear_tx(). 3795 */ 3796void 3797vxge_hal_device_mask_tx( 3798 vxge_hal_device_h devh); 3799 3800/* 3801 * vxge_hal_device_clear_tx - Acknowledge (that is, clear) the 3802 * condition that has caused the TX interrupt. 3803 * @devh: HAL device. 3804 * 3805 * Acknowledge (that is, clear) the condition that has caused 3806 * the Tx interrupt. 3807 * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(), 3808 * vxge_hal_device_clear_rx(), vxge_hal_device_mask_tx(). 3809 */ 3810void 3811vxge_hal_device_clear_tx( 3812 vxge_hal_device_h devh); 3813 3814 3815/* 3816 * vxge_hal_device_unmask_tx - Unmask Tx interrupts. 3817 * @devh: HAL device. 3818 * 3819 * Unmask Tx device interrupts. 3820 * 3821 * See also: vxge_hal_device_mask_tx(), vxge_hal_device_clear_tx(). 3822 */ 3823void 3824vxge_hal_device_unmask_tx( 3825 vxge_hal_device_h devh); 3826 3827/* 3828 * vxge_hal_device_mask_rx - Mask Rx interrupts. 3829 * @devh: HAL device. 3830 * 3831 * Mask Rx device interrupts. 3832 * 3833 * See also: vxge_hal_device_unmask_rx(), vxge_hal_device_mask_tx(), 3834 * vxge_hal_device_clear_rx(). 3835 */ 3836void 3837vxge_hal_device_mask_rx( 3838 vxge_hal_device_h devh); 3839 3840 3841/* 3842 * vxge_hal_device_clear_rx - Acknowledge (that is, clear) the 3843 * condition that has caused the RX interrupt. 3844 * @devh: HAL device. 3845 * 3846 * Acknowledge (that is, clear) the condition that has caused 3847 * the Rx interrupt. 3848 * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(), 3849 * vxge_hal_device_clear_tx(), vxge_hal_device_mask_rx(). 3850 */ 3851void 3852vxge_hal_device_clear_rx( 3853 vxge_hal_device_h devh); 3854 3855/* 3856 * vxge_hal_device_unmask_rx - Unmask Rx interrupts. 3857 * @devh: HAL device. 3858 * 3859 * Unmask Rx device interrupts. 3860 * 3861 * See also: vxge_hal_device_mask_rx(), vxge_hal_device_clear_rx(). 3862 */ 3863void 3864vxge_hal_device_unmask_rx( 3865 vxge_hal_device_h devh); 3866 3867/* 3868 * vxge_hal_device_mask_tx_rx - Mask Tx and Rx interrupts. 3869 * @devh: HAL device. 3870 * 3871 * Mask Tx and Rx device interrupts. 3872 * 3873 * See also: vxge_hal_device_unmask_tx_rx(), vxge_hal_device_clear_tx_rx(). 3874 */ 3875void 3876vxge_hal_device_mask_tx_rx( 3877 vxge_hal_device_h devh); 3878 3879/* 3880 * vxge_hal_device_clear_tx_rx - Acknowledge (that is, clear) the 3881 * condition that has caused the Tx and RX interrupt. 3882 * @devh: HAL device. 3883 * 3884 * Acknowledge (that is, clear) the condition that has caused 3885 * the Tx and Rx interrupt. 3886 * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(), 3887 * vxge_hal_device_mask_tx_rx(), vxge_hal_device_unmask_tx_rx(). 3888 */ 3889void 3890vxge_hal_device_clear_tx_rx( 3891 vxge_hal_device_h devh); 3892 3893/* 3894 * vxge_hal_device_unmask_tx_rx - Unmask Tx and Rx interrupts. 3895 * @devh: HAL device. 3896 * 3897 * Unmask Tx and Rx device interrupts. 3898 * 3899 * See also: vxge_hal_device_mask_tx_rx(), vxge_hal_device_clear_tx_rx(). 3900 */ 3901void 3902vxge_hal_device_unmask_tx_rx( 3903 vxge_hal_device_h devh); 3904 3905/* 3906 * vxge_hal_device_msix_mode - Is MSIX enabled? 3907 * @devh: HAL device handle. 3908 * 3909 * Returns 0 if MSIX is enabled for the specified device, 3910 * non-zero otherwise. 3911 */ 3912static inline int 3913/* LINTED */ 3914vxge_hal_device_msix_mode(vxge_hal_device_h devh) 3915{ 3916 return (((vxge_hal_device_t *) devh)->msix_enabled); 3917} 3918 3919#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR) 3920 3921/* 3922 * vxge_hal_device_trace_write - Write the trace from the given buffer into 3923 * circular trace buffer 3924 * @devh: HAL device handle. 3925 * @trace_buf: Buffer containing the trace. 3926 * @trace_len: Length of the trace in the buffer 3927 * 3928 * Writes the trace from the given buffer into the circular trace buffer 3929 * 3930 */ 3931void 3932vxge_hal_device_trace_write(vxge_hal_device_h devh, 3933 u8 *trace_buf, 3934 u32 trace_len); 3935 3936/* 3937 * vxge_hal_device_trace_dump - Dump the trace buffer. 3938 * @devh: HAL device handle. 3939 * 3940 * Dump the trace buffer contents. 3941 */ 3942void 3943 vxge_hal_device_trace_dump(vxge_hal_device_h devh); 3944 3945/* 3946 * vxge_hal_device_trace_read - Read trace buffer contents. 3947 * @devh: HAL device handle. 3948 * @buffer: Buffer to store the trace buffer contents. 3949 * @buf_size: Size of the buffer. 3950 * @read_length: Size of the valid data in the buffer. 3951 * 3952 * Read HAL trace buffer contents starting from the offset 3953 * upto the size of the buffer or till EOF is reached. 3954 * 3955 * Returns: VXGE_HAL_OK - success. 3956 * VXGE_HAL_EOF_TRACE_BUF - No more data in the trace buffer. 3957 * 3958 */ 3959vxge_hal_status_e 3960vxge_hal_device_trace_read(vxge_hal_device_h devh, 3961 char *buffer, 3962 unsigned buf_size, 3963 unsigned *read_length); 3964 3965#endif 3966 3967/* 3968 * vxge_hal_device_debug_set - Set the debug module, level and timestamp 3969 * @devh: Hal device object 3970 * @level: Debug level as defined in enum vxge_debug_level_e 3971 * @mask: An or value of component masks as defined in vxge_debug.h 3972 * 3973 * This routine is used to dynamically change the debug output 3974 */ 3975void 3976vxge_hal_device_debug_set( 3977 vxge_hal_device_h devh, 3978 vxge_debug_level_e level, 3979 u32 mask); 3980 3981/* 3982 * vxge_hal_device_debug_level_get - Get the debug level 3983 * @devh: Hal device object 3984 * 3985 * This routine returns the current debug level set 3986 */ 3987static inline u32 3988/* LINTED */ 3989vxge_hal_device_debug_level_get(vxge_hal_device_h devh) 3990{ 3991 return (((vxge_hal_device_t *) devh)->debug_level); 3992} 3993 3994/* 3995 * vxge_hal_device_debug_mask_get - Get the debug mask 3996 * @devh: Hal device object 3997 * 3998 * This routine returns the current debug mask set 3999 */ 4000static inline u32 4001/* LINTED */ 4002vxge_hal_device_debug_mask_get(vxge_hal_device_h devh) 4003{ 4004 return (((vxge_hal_device_t *) devh)->debug_module_mask); 4005} 4006 4007/* 4008 * vxge_hal_device_flick_link_led - Flick (blink) link LED. 4009 * @devh: HAL device handle. 4010 * @port : Port number 0, or 1 4011 * @on_off: TRUE if flickering to be on, FALSE to be off 4012 * 4013 * Flicker the link LED. 4014 */ 4015vxge_hal_status_e 4016vxge_hal_device_flick_link_led( 4017 vxge_hal_device_h devh, 4018 u32 port, 4019 u32 on_off); 4020 4021/* 4022 * vxge_hal_device_getpause_data -Pause frame frame generation and reception. 4023 * @devh: HAL device handle. 4024 * @port : Port number 0, 1, or 2 4025 * @tx : A field to return the pause generation capability of the NIC. 4026 * @rx : A field to return the pause reception capability of the NIC. 4027 * 4028 * Returns the Pause frame generation and reception capability of the NIC. 4029 * Return value: 4030 * status 4031 */ 4032vxge_hal_status_e 4033vxge_hal_device_getpause_data( 4034 vxge_hal_device_h devh, 4035 u32 port, 4036 u32 *tx, 4037 u32 *rx); 4038 4039/* 4040 * Privileged operations 4041 */ 4042 4043/* 4044 * enum vxge_hal_pcie_function_mode_e - PCIE Function modes 4045 * @VXGE_HAL_PCIE_FUNC_MODE_SF1_VP17: Single Function 4046 * - 1 function with 17 VPATHs 4047 * @VXGE_HAL_PCIE_FUNC_MODE_MF8_VP2: Multi Function 4048 * - 8 functions with 2 VPATHs per function 4049 * @VXGE_HAL_PCIE_FUNC_MODE_SR17_VP1: SRIOV 4050 * - 17 VFs with 1 VPATH per VF 4051 * @VXGE_HAL_PCIE_FUNC_MODE_MR17_VP1: MRIOV 4052 * - 17 Virtual Hierarchies, 1 Path/Function/Hierarchy 4053 * @VXGE_HAL_PCIE_FUNC_MODE_MR8_VP2: MRIOV 4054 * - 8 Virtual Hierarchies, 2 Path/Function/Hierarchy 4055 * @VXGE_HAL_PCIE_FUNC_MODE_MF17_VP1: Multi Function 4056 * - 17 functions, 1 Path/Function (PCIe ARI) 4057 * @VXGE_HAL_PCIE_FUNC_MODE_SR8_VP2: SRIOV 4058 * - 1 PF, 7 VF, 2 Paths/Function 4059 * @VXGE_HAL_PCIE_FUNC_MODE_SR4_VP4: SRIOV 4060 * - 1 PF, 3 VF, 4 Paths/Function 4061 * @VXGE_HAL_PCIE_FUNC_MODE_MF2_VP8: Multi Function 4062 * - 2 functions, 8 Paths/Function (funcs 2-7 have no resources) 4063 */ 4064typedef enum vxge_hal_pcie_function_mode_e { 4065 VXGE_HAL_PCIE_FUNC_MODE_SF1_VP17, 4066 VXGE_HAL_PCIE_FUNC_MODE_MF8_VP2, 4067 VXGE_HAL_PCIE_FUNC_MODE_SR17_VP1, 4068 VXGE_HAL_PCIE_FUNC_MODE_MR17_VP1, 4069 VXGE_HAL_PCIE_FUNC_MODE_MR8_VP2, 4070 VXGE_HAL_PCIE_FUNC_MODE_MF17_VP1, 4071 VXGE_HAL_PCIE_FUNC_MODE_SR8_VP2, 4072 VXGE_HAL_PCIE_FUNC_MODE_SR4_VP4, 4073 VXGE_HAL_PCIE_FUNC_MODE_MF2_VP8, 4074 VXGE_HAL_PCIE_FUNC_MODE_MF4_VP4, 4075 VXGE_HAL_PCIE_FUNC_MODE_MR4_VP4, 4076 VXGE_HAL_PCIE_FUNC_MODE_MF8P_VP2 4077 4078} vxge_hal_pcie_function_mode_e; 4079 4080/* Behavior on failure */ 4081typedef enum vxge_hal_xmac_nwif_behavior_on_failure { 4082 VXGE_HAL_XMAC_NWIF_OnFailure_NoMove, 4083 VXGE_HAL_XMAC_NWIF_OnFailure_OtherPort, 4084 VXGE_HAL_XMAC_NWIF_OnFailure_OtherPortBackOnRestore 4085} vxge_hal_xmac_nwif_behavior_on_failure; 4086 4087/* 4088 * Network Port configuration cmds 4089 */ 4090typedef enum vxge_hal_nwif_cmds { 4091 VXGE_HAL_XMAC_NWIF_Cmd_Version = 0x0, 4092 VXGE_HAL_XMAC_NWIF_Cmd_SetMode = 0x1, 4093 VXGE_HAL_XMAC_NWIF_Cmd_CfgSnglPort = 0x4, 4094 VXGE_HAL_XMAC_NWIF_Cmd_Avail = 0x6, 4095 VXGE_HAL_XMAC_NWIF_Cmd_CfgSetActPassPreferredPort = 0x7, 4096 VXGE_HAL_XMAC_NWIF_Cmd_CfgSetBehaviourOnFailure = 0x8, 4097 VXGE_HAL_XMAC_NWIF_Cmd_CfgDualPort_L2SwitchEnable = 0x9, 4098 VXGE_HAL_XMAC_NWIF_Cmd_CfgDualPort_VPathVector = 0xa, 4099 VXGE_HAL_XMAC_NWIF_Cmd_Get_Active_Config = 0xb 4100} vxge_hal_nwif_cmds; 4101 4102/* Network port get active config options */ 4103typedef enum vxge_hal_xmac_nwif_actconfig { 4104 VXGE_HAL_XMAC_NWIF_ActConfig_Avail = 0, 4105 VXGE_HAL_XMAC_NWIF_ActConfig_NWPortMode = 1, 4106 VXGE_HAL_XMAC_NWIF_ActConfig_PreferredPort = 2, 4107 VXGE_HAL_XMAC_NWIF_ActConfig_BehaviourOnFail = 3, 4108 VXGE_HAL_XMAC_NWIF_ActConfig_ActivePort = 4, 4109 VXGE_HAL_XMAC_NWIF_ActConfig_L2SwitchEnabled = 5, 4110 VXGE_HAL_XMAC_NWIF_ActConfig_DualPortPath = 6 4111} vxge_hal_xmac_nwif_actconfig; 4112 4113/* Dual port modes */ 4114typedef enum vxge_hal_xmac_nwif_dp_mode { 4115 VXGE_HAL_DP_NP_MODE_DEFAULT, 4116 VXGE_HAL_DP_NP_MODE_LINK_AGGR, 4117 VXGE_HAL_DP_NP_MODE_ACTIVE_PASSIVE, 4118 VXGE_HAL_DP_NP_MODE_SINGLE_PORT, 4119 VXGE_HAL_DP_NP_MODE_DUAL_PORT, 4120 VXGE_HAL_DP_NP_MODE_DISABLE_PORT_MGMT 4121} vxge_hal_xmac_nwif_dp_mode; 4122 4123/* L2 switch status */ 4124typedef enum vxge_hal_xmac_nwif_l2_switch_status { 4125 VXGE_HAL_XMAC_NWIF_L2_SWITCH_DISABLE, 4126 VXGE_HAL_XMAC_NWIF_L2_SWITCH_ENABLE 4127} vxge_hal_xmac_nwif_l2_switch_status; 4128 4129/* 4130 * vxge_hal_srpcim_alarm_process - Process srpcim Alarms. 4131 * @devh: Device Handle. 4132 * @skip_alarms: Flasg to indicate not to clear alarms 4133 * 4134 * Process srpcim alarms. 4135 * 4136 */ 4137vxge_hal_status_e 4138vxge_hal_srpcim_alarm_process(vxge_hal_device_h devh, u32 skip_alarms); 4139 4140/* 4141 * vxge_hal_srpcim_intr_enable - Enable srpcim interrupts. 4142 * @devh: Device Handle. 4143 * 4144 * Enable srpcim interrupts. 4145 * 4146 * See also: vxge_hal_srpcim_intr_disable() 4147 */ 4148vxge_hal_status_e 4149vxge_hal_srpcim_intr_enable(vxge_hal_device_h devh); 4150 4151/* 4152 * vxge_hal_srpcim_intr_disable - Disable srpcim interrupts. 4153 * @devh: Device Handle. 4154 * 4155 * Disable srpcim interrupts. 4156 * 4157 * See also: vxge_hal_srpcim_intr_enable() 4158 */ 4159vxge_hal_status_e 4160vxge_hal_srpcim_intr_disable(vxge_hal_device_h devh); 4161 4162/* 4163 * vxge_hal_srpcim_msix_set - Associate MSIX vector with srpcim alarm 4164 * @devh: Device Handle. 4165 * @alarm_msix_id: MSIX vector for alarm. 4166 * 4167 * This API will associate a given MSIX vector numbers with srpcim alarm 4168 */ 4169vxge_hal_status_e 4170vxge_hal_srpcim_msix_set(vxge_hal_device_h devh, int alarm_msix_id); 4171 4172/* 4173 * vxge_hal_srpcim_msix_mask - Mask MSIX Vector. 4174 * @devh: Device Handle. 4175 * 4176 * The function masks the srpcim msix interrupt 4177 * 4178 */ 4179void 4180vxge_hal_srpcim_msix_mask(vxge_hal_device_h devh); 4181 4182/* 4183 * vxge_hal_srpcim_msix_clear - Clear MSIX Vector. 4184 * @devh: Device Handle. 4185 * 4186 * The function clears the srpcim msix interrupt 4187 * 4188 */ 4189void 4190vxge_hal_srpcim_msix_clear(vxge_hal_device_h devh); 4191 4192 4193/* 4194 * vxge_hal_srpcim_msix_unmask - Unmask MSIX Vector. 4195 * @devh: Device Handle. 4196 * 4197 * The function unmasks the srpcim msix interrupt 4198 * 4199 */ 4200void 4201vxge_hal_srpcim_msix_unmask(vxge_hal_device_h devh); 4202 4203vxge_hal_status_e 4204vxge_hal_func_mode_count(vxge_hal_device_h devh, 4205 u32 func_mode, u32 *num_funcs); 4206 4207vxge_hal_status_e 4208vxge_hal_send_message(vxge_hal_device_h devh, u64 vp_id, u8 msg_type, 4209 u8 msg_dst, u32 msg_data, u64 *msg_sent_to_vpaths); 4210 4211/* 4212 * vxge_hal_func_mode_set - Set PCI-E function mode 4213 * @devh: Device Handle. 4214 * @func_mode: PCI-E func mode. Please see vxge_hal_pcie_function_mode_e{} 4215 * 4216 * Set PCI-E function mode. 4217 * 4218 */ 4219vxge_hal_status_e 4220vxge_hal_func_mode_get(vxge_hal_device_h devh, u32 *func_mode); 4221/* 4222 * vxge_hal_func_mode_set - Set PCI-E function mode 4223 * @devh: Device Handle. 4224 * @func_mode: PCI-E func mode. Please see vxge_hal_pcie_function_mode_e{} 4225 * 4226 * Set PCI-E function mode. 4227 * 4228 */ 4229vxge_hal_status_e 4230vxge_hal_mrpcim_pcie_func_mode_set(vxge_hal_device_h devh, 4231 vxge_hal_pcie_function_mode_e func_mode); 4232 4233/* 4234 * vxge_hal_get_active_config - Get active configuration 4235 * @devh: Device Handle. 4236 * 4237 */ 4238vxge_hal_status_e 4239vxge_hal_get_active_config(vxge_hal_device_h devh, 4240 vxge_hal_xmac_nwif_actconfig req_config, u64 *cur_config); 4241 4242/* 4243 * vxge_hw_set_port_mode - Set dual port mode 4244 * override the default dual port mode 4245 * @devh: Device Handle. 4246 * 4247 */ 4248 4249vxge_hal_status_e 4250vxge_hal_set_port_mode(vxge_hal_device_h devh, 4251 vxge_hal_xmac_nwif_dp_mode port_mode); 4252 4253/* 4254 * vxge_hal_set_behavior_on_failure - Set port behaviour 4255 * change port behavior on failure 4256 * @devh: Device Handle. 4257 */ 4258vxge_hal_status_e 4259vxge_hal_set_behavior_on_failure(vxge_hal_device_h devh, 4260 vxge_hal_xmac_nwif_behavior_on_failure behave_on_failure); 4261 4262 4263/* 4264 * vxge_hal_set_l2switch_mode - Set port behaviour 4265 * set l2switch mode 4266 * @devh: Device Handle. 4267 */ 4268vxge_hal_status_e 4269vxge_hal_set_l2switch_mode(vxge_hal_device_h devh, 4270 enum vxge_hal_xmac_nwif_l2_switch_status l2_switch); 4271/* 4272 * vxge_hal_set_fw_api - Setup FW api 4273 * @devh: Device Handle. 4274 * 4275 */ 4276vxge_hal_status_e 4277vxge_hal_set_fw_api(vxge_hal_device_h devh, u64 vp_id, u32 action, 4278 u32 offset, u64 data0, u64 data1); 4279 4280vxge_hal_status_e 4281vxge_hal_config_vpath_map(vxge_hal_device_h devh, u64 port_map); 4282 4283vxge_hal_status_e 4284vxge_hal_get_vpath_mask(vxge_hal_device_h devh, u32 vf_id, 4285 u32 *no_of_vpath, u64 *vpath_mask); 4286 4287vxge_hal_status_e 4288vxge_hal_get_vpath_list(vxge_hal_device_h devh, u32 vf_id, 4289 u64 *vpath_list, u32 *vpath_count); 4290 4291vxge_hal_status_e 4292vxge_hal_rx_bw_priority_set(vxge_hal_device_h devh, u64 vp_id); 4293 4294vxge_hal_status_e 4295vxge_hal_tx_bw_priority_set(vxge_hal_device_h devh, u64 vp_id); 4296 4297vxge_hal_status_e 4298vxge_hal_bw_priority_get(vxge_hal_device_h devh, u64 vp_id, 4299 u32 *bandwidth, u32 *priority); 4300 4301vxge_hal_status_e 4302vxge_hal_vf_rx_bw_get(vxge_hal_device_h devh, u64 func_id, 4303 u32 *bandwidth, u32 *priority); 4304/* 4305 * vxge_hal_mrpcim_serial_number_get - Returns the serial number 4306 * @devh: Device Handle. 4307 * 4308 * Return the serial number 4309 */ 4310const u8 * 4311vxge_hal_mrpcim_serial_number_get(vxge_hal_device_h devh); 4312 4313/* 4314 * vxge_hal_mrpcim_fw_upgrade - Upgrade firmware 4315 * @pdev: PCI device object. 4316 * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 4317 * (Linux and the rest.) 4318 * @bar0: Address of BAR0 in PCI config 4319 * @buffer: Buffer containing F/W image 4320 * @length: F/W image length 4321 * 4322 * Upgrade firmware 4323 */ 4324vxge_hal_status_e 4325vxge_hal_mrpcim_fw_upgrade( 4326 pci_dev_h pdev, 4327 pci_reg_h regh0, 4328 u8 *bar0, 4329 u8 *buffer, 4330 u32 length); 4331 4332/* 4333 * vxge_hal_mrpcim_vpath_map_get - Returns the assigned vpaths map 4334 * @pdev: PCI device object. 4335 * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 4336 * (Linux and the rest.) 4337 * @bar0: Address of BAR0 in PCI config 4338 * @func: Function Number 4339 * 4340 * Returns the assigned vpaths map 4341 */ 4342u64 4343vxge_hal_mrpcim_vpath_map_get( 4344 pci_dev_h pdev, 4345 pci_reg_h regh0, 4346 u8 *bar0, 4347 u32 func); 4348 4349/* 4350 * vxge_hal_mrpcim_vpath_qos_set - Set the priority, Guaranteed and maximum 4351 * bandwidth for a vpath. 4352 * @devh: HAL device handle. 4353 * @vp_id: Vpath Id. 4354 * @priority: Priority 4355 * @min_bandwidth: Minimum Bandwidth 4356 * @max_bandwidth: Maximum Bandwidth 4357 * 4358 * Set the Priority, Guaranteed and maximum bandwidth for a given vpath 4359 * 4360 */ 4361vxge_hal_status_e 4362vxge_hal_mrpcim_vpath_qos_set( 4363 vxge_hal_device_h devh, 4364 u32 vp_id, 4365 u32 priority, 4366 u32 min_bandwidth, 4367 u32 max_bandwidth); 4368 4369/* 4370 * vxge_hal_mrpcim_vpath_qos_get - Get the priority, Guaranteed and maximum 4371 * bandwidth for a vpath. 4372 * @devh: HAL device handle. 4373 * @vp_id: Vpath Id. 4374 * @priority: Buffer to return Priority 4375 * @min_bandwidth: Buffer to return Minimum Bandwidth 4376 * @max_bandwidth: Buffer to return Maximum Bandwidth 4377 * 4378 * Get the Priority, Guaranteed and maximum bandwidth for a given vpath 4379 * 4380 */ 4381vxge_hal_status_e 4382vxge_hal_mrpcim_vpath_qos_get( 4383 vxge_hal_device_h devh, 4384 u32 vp_id, 4385 u32 *priority, 4386 u32 *min_bandwidth, 4387 u32 *max_bandwidth); 4388 4389/* 4390 * vxge_hal_mrpcim_mac_addr_add - Add the mac address entry 4391 * into MAC address table. 4392 * @devh: Device handle. 4393 * @offset: Index into the DA table to add the mac address. 4394 * @macaddr: MAC address to be added for this vpath into the list 4395 * @macaddr_mask: MAC address mask for macaddr 4396 * @vpath_vector: Bit mask specifying the vpaths to which the mac address 4397 * applies 4398 * @duplicate_mode: Duplicate MAC address add mode. Please see 4399 * vxge_hal_vpath_mac_addr_add_mode_e {} 4400 * 4401 * Adds the given mac address, mac address mask and vpath vector into the list 4402 * 4403 * see also: vxge_hal_vpath_mac_addr_delete, vxge_hal_vpath_mac_addr_get and 4404 * vxge_hal_vpath_mac_addr_get_next 4405 * 4406 */ 4407vxge_hal_status_e 4408vxge_hal_mrpcim_mac_addr_add( 4409 vxge_hal_device_h devh, 4410 u32 offset, 4411 macaddr_t macaddr, 4412 macaddr_t macaddr_mask, 4413 u64 vpath_vector, 4414 u32 duplicate_mode); 4415 4416/* 4417 * vxge_hal_mrpcim_mac_addr_get - Read the mac address entry 4418 * into MAC address table. 4419 * @devh: Device handle. 4420 * @offset: Index into the DA table to execute the command on. 4421 * @macaddr: Buffer to return MAC address to be added for this vpath 4422 * @macaddr_mask: Buffer to return MAC address mask for macaddr 4423 * @vpath_vector: Buffer to return Bit mask specifying the vpaths to which 4424 * the mac address applies 4425 * 4426 * Reads the mac address,mac address mask and vpath vector from the given offset 4427 * 4428 * see also: vxge_hal_mrpcim_mac_addr_add 4429 * 4430 */ 4431vxge_hal_status_e 4432vxge_hal_mrpcim_mac_addr_get( 4433 vxge_hal_device_h devh, 4434 u32 offset, 4435 macaddr_t macaddr, 4436 macaddr_t macaddr_mask, 4437 u64 *vpath_vector); 4438 4439/* 4440 * vxge_hal_mrpcim_reset - Reset the entire device. 4441 * @devh: HAL device handle. 4442 * 4443 * Soft-reset the device, reset the device stats except reset_cnt. 4444 * 4445 * 4446 * Returns: VXGE_HAL_OK - success. 4447 * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 4448 * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 4449 * 4450 * See also: vxge_hal_status_e {}. 4451 */ 4452vxge_hal_status_e 4453vxge_hal_mrpcim_reset(vxge_hal_device_h devh); 4454 4455/* 4456 * vxge_hal_mrpcim_reset_poll - Poll the device for reset complete. 4457 * @devh: HAL device handle. 4458 * 4459 * Soft-reset the device, reset the device stats except reset_cnt. 4460 * 4461 * After reset is done, will try to re-initialize HW. 4462 * 4463 * Returns: VXGE_HAL_OK - success. 4464 * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 4465 * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 4466 * 4467 * See also: vxge_hal_status_e {}. 4468 */ 4469vxge_hal_status_e 4470vxge_hal_mrpcim_reset_poll(vxge_hal_device_h devh); 4471 4472/* 4473 * vxge_hal_mrpcim_strip_repl_vlan_tag_enable - Enable strip Repl vlan tag. 4474 * @devh: Device handle. 4475 * 4476 * Enable X3100 strip Repl vlan tag. 4477 * Returns: VXGE_HAL_OK on success. 4478 * 4479 */ 4480vxge_hal_status_e 4481vxge_hal_mrpcim_strip_repl_vlan_tag_enable( 4482 vxge_hal_device_h devh); 4483 4484/* 4485 * vxge_hal_mrpcim_strip_repl_vlan_tag_disable - Disable strip Repl vlan tag. 4486 * @devh: Device handle. 4487 * 4488 * Disable X3100 strip Repl vlan tag. 4489 * Returns: VXGE_HAL_OK on success. 4490 * 4491 */ 4492vxge_hal_status_e 4493vxge_hal_mrpcim_strip_repl_vlan_tag_disable( 4494 vxge_hal_device_h devh); 4495 4496/* 4497 * vxge_hal_mrpcim_intr_enable - Enable the interrupts on mrpcim. 4498 * @devh: HAL device handle. 4499 * 4500 * Enable mrpcim interrupts 4501 * 4502 * See also: vxge_hal_mrpcim_intr_disable(). 4503 */ 4504vxge_hal_status_e 4505vxge_hal_mrpcim_intr_enable(vxge_hal_device_h devh); 4506 4507/* 4508 * vxge_hal_mrpcim_intr_disable - Disable the interrupts on mrpcim. 4509 * @devh: HAL device handle. 4510 * 4511 * Disable mrpcim interrupts 4512 * 4513 * See also: vxge_hal_mrpcim_intr_enable(). 4514 */ 4515vxge_hal_status_e 4516vxge_hal_mrpcim_intr_disable(vxge_hal_device_h devh); 4517 4518/* 4519 * vxge_hal_mrpcim_lag_config_get - Get the LAG config. 4520 * @devh: Device handle. 4521 * @lconfig: LAG Configuration 4522 * 4523 * Returns the current LAG configuration. 4524 * Returns: VXGE_HAL_OK on success. 4525 * 4526 */ 4527vxge_hal_status_e 4528vxge_hal_mrpcim_lag_config_get( 4529 vxge_hal_device_h devh, 4530 vxge_hal_lag_config_t *lconfig); 4531 4532/* 4533 * vxge_hal_mrpcim_lag_config_set - Set the LAG config. 4534 * @devh: Device handle. 4535 * @lconfig: LAG Configuration 4536 * 4537 * Sets the LAG configuration. 4538 * Returns: VXGE_HAL_OK on success. 4539 * 4540 */ 4541vxge_hal_status_e 4542vxge_hal_mrpcim_lag_config_set( 4543 vxge_hal_device_h devh, 4544 vxge_hal_lag_config_t *lconfig); 4545 4546/* 4547 * vxge_hal_mrpcim_getpause_data -Pause frame frame generation and reception. 4548 * @devh: HAL device handle. 4549 * @port : Port number 0, 1, or 2 4550 * @tx : A field to return the pause generation capability of the NIC. 4551 * @rx : A field to return the pause reception capability of the NIC. 4552 * 4553 * Returns the Pause frame generation and reception capability of the NIC. 4554 * Return value: 4555 * status 4556 */ 4557vxge_hal_status_e 4558vxge_hal_mrpcim_getpause_data(vxge_hal_device_h devh, 4559 u32 port, 4560 u32 *tx, 4561 u32 *rx); 4562 4563/* 4564 * vxge_hal_mrpcim_setpause_data - set/reset pause frame generation. 4565 * @devh: HAL device handle. 4566 * @port : Port number 0, 1, or 2 4567 * @tx: A field that indicates the pause generation capability to be 4568 * set on the NIC. 4569 * @rx: A field that indicates the pause reception capability to be 4570 * set on the NIC. 4571 * 4572 * It can be used to set or reset Pause frame generation or reception 4573 * support of the NIC. 4574 * Return value: 4575 * int, returns 0 on Success 4576 */ 4577 4578vxge_hal_status_e 4579vxge_hal_mrpcim_setpause_data( 4580 vxge_hal_device_h devh, 4581 u32 port, 4582 u32 tx, 4583 u32 rx); 4584 4585/* 4586 * vxge_hal_mrpcim_bist_test - invokes the MemBist test of the card . 4587 * @devh: HAL device handle. 4588 * @data:variable that returns the result of each of the test conducted by 4589 * the driver. 4590 * 4591 * This invokes the MemBist test of the card. We give around 4592 * 2 secs time for the Test to complete. If it's still not complete 4593 * within this peiod, we consider that the test failed. 4594 * Return value: 4595 * 0 on success and -1 on failure. 4596 */ 4597vxge_hal_status_e 4598vxge_hal_mrpcim_bist_test(vxge_hal_device_h devh, u64 *data); 4599 4600/* 4601 * vxge_hal_mrpcim_udp_rth_enable - Enable UDP/RTH. 4602 * @devh: HAL device handle. 4603 * 4604 * enable udp rth 4605 * 4606 */ 4607vxge_hal_status_e 4608vxge_hal_mrpcim_udp_rth_enable( 4609 vxge_hal_device_h devh); 4610 4611/* 4612 * Virtual Paths 4613 */ 4614 4615/* 4616 * struct vxge_hal_vpath_attr_t - Attributes of virtual path 4617 * @vp_id: Identifier of Virtual Path 4618 * @ring_attr: Attributes of ring for non-offload receive 4619 * @fifo_attr: Attributes of fifo for non-offload transmit 4620 * 4621 * Attributes of virtual path. This structure is passed as parameter 4622 * to the vxge_hal_vpath_open() routine to set the attributes of DMQ, UMQ, 4623 * ring and fifo. After virtual path is open, iWARP/RDMA module can attach 4624 * to virtual path. 4625 */ 4626typedef struct vxge_hal_vpath_attr_t { 4627 u32 vp_id; 4628 vxge_hal_ring_attr_t ring_attr; 4629 vxge_hal_fifo_attr_t fifo_attr; 4630} vxge_hal_vpath_attr_t; 4631 4632/* 4633 * vxge_hal_vpath_open - Open a virtual path on a given adapter 4634 * @devh: handle to device object 4635 * @attr: Virtual path attributes 4636 * @cb_fn: Call back to be called to complete an asynchronous function call 4637 * @client_handle: handle to be returned in the callback 4638 * @vpath_handle: Buffer to return a handle to the vpath 4639 * 4640 * This function is used to open access to virtual path of an 4641 * adapter for offload, LRO and SPDM operations. This function returns 4642 * synchronously. 4643 */ 4644vxge_hal_status_e 4645vxge_hal_vpath_open( 4646 vxge_hal_device_h devh, 4647 vxge_hal_vpath_attr_t *attr, 4648 vxge_hal_vpath_callback_f cb_fn, 4649 vxge_hal_client_h client_handle, 4650 vxge_hal_vpath_h *vpath_handle); 4651 4652/* 4653 * vxge_hal_vpath_enable 4654 * @vpath_handle: Handle to the vpath object 4655 * 4656 * This routine clears the vpath reset and puts vpath in service 4657 */ 4658vxge_hal_status_e 4659vxge_hal_vpath_enable( 4660 vxge_hal_vpath_h vpath_handle); 4661 4662/* 4663 * vxge_hal_vpath_id - Get virtual path ID 4664 * @vpath_handle: Handle got from previous vpath open 4665 * 4666 * This function returns virtual path id 4667 */ 4668u32 4669vxge_hal_vpath_id(vxge_hal_vpath_h vpath_handle); 4670 4671/* 4672 * vxge_hal_vpath_close - Close the handle got from previous vpath (vpath) open 4673 * @vpath_handle: Handle got from previous vpath open 4674 * 4675 * This function is used to close access to virtual path opened 4676 * earlier. This function returns synchronously. 4677 */ 4678vxge_hal_status_e 4679vxge_hal_vpath_close(vxge_hal_vpath_h vpath_handle); 4680 4681/* 4682 * vxge_hal_vpath_reset - Resets vpath 4683 * @vpath_handle: Handle got from previous vpath open 4684 * 4685 * This function is used to request a reset of vpath 4686 */ 4687vxge_hal_status_e 4688vxge_hal_vpath_reset(vxge_hal_vpath_h vpath_handle); 4689 4690/* 4691 * vxge_hal_vpath_reset_poll - Poll for reset complete 4692 * @vpath_handle: Handle got from previous vpath open 4693 * 4694 * This function is used to poll for the vpath reset completion 4695 */ 4696vxge_hal_status_e 4697vxge_hal_vpath_reset_poll(vxge_hal_vpath_h vpath_handle); 4698 4699/* 4700 * vxge_hal_vpath_obj_count_get - Get the Object usage count for a given 4701 * virtual path 4702 * @vpath_handle: Virtal path handle 4703 * @obj_counts: Buffer to return object counts 4704 * 4705 * This function returns the object counts for virtual path. This function 4706 * returns synchronously. 4707 */ 4708vxge_hal_status_e 4709vxge_hal_vpath_obj_count_get(vxge_hal_vpath_h vpath_handle, 4710 vxge_hal_vpath_sw_obj_count_t *obj_counts); 4711 4712/* 4713 * vxge_hal_vpath_mtu_check - check MTU value for ranges 4714 * @vpath_handle: Virtal path handle 4715 * @new_mtu: new MTU value to check 4716 * 4717 * Will do sanity check for new MTU value. 4718 * 4719 * Returns: VXGE_HAL_OK - success. 4720 * VXGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid. 4721 * 4722 * See also: vxge_hal_vpath_mtu_set() 4723 */ 4724vxge_hal_status_e 4725vxge_hal_device_mtu_check(vxge_hal_vpath_h vpath_handle, 4726 unsigned long new_mtu); 4727 4728/* 4729 * vxge_hal_vpath_mtu_set - Set MTU. 4730 * @vpath_handle: Virtal path handle 4731 * @new_mtu: New MTU size to configure. 4732 * 4733 * Set new MTU value. Example, to use jumbo frames: 4734 * vxge_hal_vpath_mtu_set(my_device, 9600); 4735 * 4736 */ 4737vxge_hal_status_e 4738vxge_hal_vpath_mtu_set(vxge_hal_vpath_h vpath_handle, 4739 unsigned long new_mtu); 4740 4741typedef enum vxge_hal_vpath_mac_addr_add_mode_e { 4742 VXGE_HAL_VPATH_MAC_ADDR_ADD_DUPLICATE = 0, 4743 VXGE_HAL_VPATH_MAC_ADDR_DISCARD_DUPLICATE = 1, 4744 VXGE_HAL_VPATH_MAC_ADDR_REPLACE_DUPLICATE = 2 4745} vxge_hal_vpath_mac_addr_add_mode_e; 4746 4747/* 4748 * vxge_hal_vpath_mac_addr_add - Add the mac address entry for this vpath 4749 * to MAC address table. 4750 * @vpath_handle: Vpath handle. 4751 * @macaddr: MAC address to be added for this vpath into the list 4752 * @macaddr_mask: MAC address mask for mac_addr 4753 * @duplicate_mode: Duplicate MAC address add mode. Please see 4754 * vxge_hal_vpath_mac_addr_add_mode_e {} 4755 * 4756 * Adds the given mac address and mac address mask into the list for this 4757 * vpath. 4758 * see also: vxge_hal_vpath_mac_addr_delete, vxge_hal_vpath_mac_addr_get and 4759 * vxge_hal_vpath_mac_addr_get_next 4760 * 4761 */ 4762vxge_hal_status_e 4763vxge_hal_vpath_mac_addr_add( 4764 vxge_hal_vpath_h vpath_handle, 4765 macaddr_t macaddr, 4766 macaddr_t macaddr_mask, 4767 vxge_hal_vpath_mac_addr_add_mode_e duplicate_mode); 4768 4769/* 4770 * vxge_hal_vpath_mac_addr_get - Get the first mac address entry for this vpath 4771 * from MAC address table. 4772 * @vpath_handle: Vpath handle. 4773 * @macaddr: First MAC address entry for this vpath in the list 4774 * @macaddr_mask: MAC address mask for mac_addr 4775 * 4776 * Returns the first mac address and mac address mask in the list for this 4777 * vpath. 4778 * see also: vxge_hal_vpath_mac_addr_get_next 4779 * 4780 */ 4781vxge_hal_status_e 4782vxge_hal_vpath_mac_addr_get( 4783 vxge_hal_vpath_h vpath_handle, 4784 macaddr_t macaddr, 4785 macaddr_t macaddr_mask); 4786 4787/* 4788 * vxge_hal_vpath_mac_addr_get_next - Get the next mac address entry for this 4789 * vpath from MAC address table. 4790 * @vpath_handle: Vpath handle. 4791 * @macaddr: Next MAC address entry for this vpath in the list 4792 * @macaddr_mask: MAC address mask for mac_addr 4793 * 4794 * Returns the next mac address and mac address mask in the list for this 4795 * vpath. 4796 * see also: vxge_hal_vpath_mac_addr_get 4797 * 4798 */ 4799vxge_hal_status_e 4800vxge_hal_vpath_mac_addr_get_next( 4801 vxge_hal_vpath_h vpath_handle, 4802 macaddr_t macaddr, 4803 macaddr_t macaddr_mask); 4804 4805/* 4806 * vxge_hal_vpath_mac_addr_delete - Delete the mac address entry for this vpath 4807 * to MAC address table. 4808 * @vpath_handle: Vpath handle. 4809 * @macaddr: MAC address to be added for this vpath into the list 4810 * @macaddr_mask: MAC address mask for macaddr 4811 * 4812 * Delete the given mac address and mac address mask into the list for this 4813 * vpath. 4814 * see also: vxge_hal_vpath_mac_addr_add, vxge_hal_vpath_mac_addr_get and 4815 * vxge_hal_vpath_mac_addr_get_next 4816 * 4817 */ 4818vxge_hal_status_e 4819vxge_hal_vpath_mac_addr_delete( 4820 vxge_hal_vpath_h vpath_handle, 4821 macaddr_t macaddr, 4822 macaddr_t macaddr_mask); 4823 4824/* 4825 * vxge_hal_vpath_vid_add - Add the vlan id entry for this vpath 4826 * to vlan id table. 4827 * @vpath_handle: Vpath handle. 4828 * @vid: vlan id to be added for this vpath into the list 4829 * 4830 * Adds the given vlan id into the list for this vpath. 4831 * see also: vxge_hal_vpath_vid_delete, vxge_hal_vpath_vid_get and 4832 * vxge_hal_vpath_vid_get_next 4833 * 4834 */ 4835vxge_hal_status_e 4836vxge_hal_vpath_vid_add( 4837 vxge_hal_vpath_h vpath_handle, 4838 u64 vid); 4839 4840/* 4841 * vxge_hal_vpath_vid_get - Get the first vid entry for this vpath 4842 * from vlan id table. 4843 * @vpath_handle: Vpath handle. 4844 * @vid: Buffer to return vlan id 4845 * 4846 * Returns the first vlan id in the list for this vpath. 4847 * see also: vxge_hal_vpath_vid_get_next 4848 * 4849 */ 4850vxge_hal_status_e 4851vxge_hal_vpath_vid_get( 4852 vxge_hal_vpath_h vpath_handle, 4853 u64 *vid); 4854 4855/* 4856 * vxge_hal_vpath_vid_get_next - Get the next vid entry for this vpath 4857 * from vlan id table. 4858 * @vpath_handle: Vpath handle. 4859 * @vid: Buffer to return vlan id 4860 * 4861 * Returns the next vlan id in the list for this vpath. 4862 * see also: vxge_hal_vpath_vid_get 4863 * 4864 */ 4865vxge_hal_status_e 4866vxge_hal_vpath_vid_get_next( 4867 vxge_hal_vpath_h vpath_handle, 4868 u64 *vid); 4869 4870/* 4871 * vxge_hal_vpath_vid_delete - Delete the vlan id entry for this vpath 4872 * to vlan id table. 4873 * @vpath_handle: Vpath handle. 4874 * @vid: vlan id to be added for this vpath into the list 4875 * 4876 * Adds the given vlan id into the list for this vpath. 4877 * see also: vxge_hal_vpath_vid_add, vxge_hal_vpath_vid_get and 4878 * vxge_hal_vpath_vid_get_next 4879 * 4880 */ 4881vxge_hal_status_e 4882vxge_hal_vpath_vid_delete( 4883 vxge_hal_vpath_h vpath_handle, 4884 u64 vid); 4885 4886/* 4887 * vxge_hal_vpath_etype_add - Add the Ethertype entry for this vpath 4888 * to Ethertype table. 4889 * @vpath_handle: Vpath handle. 4890 * @etype: ethertype to be added for this vpath into the list 4891 * 4892 * Adds the given Ethertype into the list for this vpath. 4893 * see also: vxge_hal_vpath_etype_delete, vxge_hal_vpath_etype_get and 4894 * vxge_hal_vpath_etype_get_next 4895 * 4896 */ 4897vxge_hal_status_e 4898vxge_hal_vpath_etype_add( 4899 vxge_hal_vpath_h vpath_handle, 4900 u64 etype); 4901 4902/* 4903 * vxge_hal_vpath_etype_get - Get the first ethertype entry for this vpath 4904 * from Ethertype table. 4905 * @vpath_handle: Vpath handle. 4906 * @etype: Buffer to return Ethertype 4907 * 4908 * Returns the first ethype entry in the list for this vpath. 4909 * see also: vxge_hal_vpath_etype_get_next 4910 * 4911 */ 4912vxge_hal_status_e 4913vxge_hal_vpath_etype_get( 4914 vxge_hal_vpath_h vpath_handle, 4915 u64 *etype); 4916 4917/* 4918 * vxge_hal_vpath_etype_get_next - Get the next Ethertype entry for this vpath 4919 * from Ethertype table. 4920 * @vpath_handle: Vpath handle. 4921 * @etype: Buffer to return Ethwrtype 4922 * 4923 * Returns the next Ethwrtype in the list for this vpath. 4924 * see also: vxge_hal_vpath_etype_get 4925 * 4926 */ 4927vxge_hal_status_e 4928vxge_hal_vpath_etype_get_next( 4929 vxge_hal_vpath_h vpath_handle, 4930 u64 *etype); 4931 4932/* 4933 * vxge_hal_vpath_etype_delete - Delete the Ethertype entry for this vpath 4934 * to Ethertype table. 4935 * @vpath_handle: Vpath handle. 4936 * @etype: ethertype to be added for this vpath into the list 4937 * 4938 * Adds the given Ethertype into the list for this vpath. 4939 * see also: vxge_hal_vpath_etype_add, vxge_hal_vpath_etype_get and 4940 * vxge_hal_vpath_etype_get_next 4941 * 4942 */ 4943vxge_hal_status_e 4944vxge_hal_vpath_etype_delete( 4945 vxge_hal_vpath_h vpath_handle, 4946 u64 etype); 4947 4948/* 4949 * vxge_hal_vpath_port_add - Add the port entry for this vpath 4950 * to port number table. 4951 * @vpath_handle: Vpath handle. 4952 * @port_type: if 0 - Src port or 1 - Dest port 4953 * @protocol: if 0 - TCP or 1 - UDP 4954 * @port: port to be added for this vpath into the list 4955 * 4956 * Adds the given port into the list for this vpath. 4957 * see also: vxge_hal_vpath_port_delete, vxge_hal_vpath_port_get and 4958 * vxge_hal_vpath_port_get_next 4959 * 4960 */ 4961vxge_hal_status_e 4962vxge_hal_vpath_port_add( 4963 vxge_hal_vpath_h vpath_handle, 4964 u32 port_type, 4965 u32 protocol, 4966 u32 port); 4967 4968/* 4969 * vxge_hal_vpath_port_get - Get the first port number entry for this vpath 4970 * from port number table. 4971 * @vpath_handle: Vpath handle. 4972 * @port_type: Buffer to return if 0 - Src port or 1 - Dest port 4973 * @protocol: Buffer to return if 0 - TCP or 1 - UDP 4974 * @port: Buffer to return port number 4975 * 4976 * Returns the first port number entry in the list for this vpath. 4977 * see also: vxge_hal_vpath_port_get_next 4978 * 4979 */ 4980vxge_hal_status_e 4981vxge_hal_vpath_port_get( 4982 vxge_hal_vpath_h vpath_handle, 4983 u32 *port_type, 4984 u32 *protocol, 4985 u32 *port); 4986 4987/* 4988 * vxge_hal_vpath_port_get_next - Get the next port number entry for this vpath 4989 * from port number table. 4990 * @vpath_handle: Vpath handle. 4991 * @port_type: Buffer to return if 0 - Src port or 1 - Dest port 4992 * @protocol: Buffer to return if 0 - TCP or 1 - UDP 4993 * @port: Buffer to return port number 4994 * 4995 * Returns the next port number entry in the list for this vpath. 4996 * see also: vxge_hal_vpath_port_get 4997 * 4998 */ 4999vxge_hal_status_e 5000vxge_hal_vpath_port_get_next( 5001 vxge_hal_vpath_h vpath_handle, 5002 u32 *port_type, 5003 u32 *protocol, 5004 u32 *port); 5005 5006/* 5007 * vxge_hal_vpath_port_delete - Delete the port entry for this vpath 5008 * to port number table. 5009 * @vpath_handle: Vpath handle. 5010 * @port_type: if 0 - Src port or 1 - Dest port 5011 * @protocol: if 0 - TCP or 1 - UDP 5012 * @port: port to be added for this vpath into the list 5013 * 5014 * Adds the given port into the list for this vpath. 5015 * see also: vxge_hal_vpath_port_add, vxge_hal_vpath_port_get and 5016 * vxge_hal_vpath_port_get_next 5017 * 5018 */ 5019vxge_hal_status_e 5020vxge_hal_vpath_port_delete( 5021 vxge_hal_vpath_h vpath_handle, 5022 u32 port_type, 5023 u32 protocol, 5024 u32 port); 5025 5026typedef enum vxge_hal_rth_algoritms_t { 5027 RTH_ALG_NONE = -1, 5028 RTH_ALG_JENKINS = 0, 5029 RTH_ALG_MS_RSS = 1, 5030 RTH_ALG_CRC32C = 2 5031} vxge_hal_rth_algoritms_t; 5032 5033/* 5034 * struct vxge_hal_rth_hash_types_t - RTH hash types. 5035 * @hash_type_tcpipv4_en: Enables RTH field type HashTypeTcpIPv4 5036 * @hash_type_ipv4_en: Enables RTH field type HashTypeIPv4 5037 * @hash_type_tcpipv6_en: Enables RTH field type HashTypeTcpIPv6 5038 * @hash_type_ipv6_en: Enables RTH field type HashTypeIPv6 5039 * @hash_type_tcpipv6ex_en: Enables RTH field type HashTypeTcpIPv6Ex 5040 * @hash_type_ipv6ex_en: Enables RTH field type HashTypeIPv6Ex 5041 * 5042 * Used to pass RTH hash types to rts_rts_set. 5043 * 5044 * See also: vxge_hal_vpath_rts_rth_set(), vxge_hal_vpath_rts_rth_get(). 5045 */ 5046typedef struct vxge_hal_rth_hash_types_t { 5047 u8 hash_type_tcpipv4_en; 5048 u8 hash_type_ipv4_en; 5049 u8 hash_type_tcpipv6_en; 5050 u8 hash_type_ipv6_en; 5051 u8 hash_type_tcpipv6ex_en; 5052 u8 hash_type_ipv6ex_en; 5053} vxge_hal_rth_hash_types_t; 5054 5055/* 5056 * vxge_hal_vpath_udp_rth_disable - Disable UDP/RTH. 5057 * @vpath_handle: Vpath handle. 5058 * 5059 * Disable udp rth 5060 * 5061 */ 5062vxge_hal_status_e 5063vxge_hal_vpath_udp_rth_disable( 5064 vxge_hal_vpath_h vpath_handle); 5065 5066/* 5067 * vxge_hal_vpath_rts_rth_set - Set/configure RTS hashing. 5068 * @vpath_handle: Virtual Path handle. 5069 * @algorithm: Algorithm Select 5070 * @hash_type: Hash Type 5071 * @bucket_size: no of least significant bits to be used for hashing. 5072 * @it_switch: Itable switch required 5073 * 5074 * Used to set/configure all RTS hashing related stuff. 5075 * 5076 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_itable_set(). 5077 */ 5078vxge_hal_status_e 5079vxge_hal_vpath_rts_rth_set( 5080 vxge_hal_vpath_h vpath_handle, 5081 vxge_hal_rth_algoritms_t algorithm, 5082 vxge_hal_rth_hash_types_t *hash_type, 5083 u16 bucket_size, 5084 u16 it_switch); 5085 5086/* 5087 * vxge_hal_vpath_rts_rth_get - Read RTS hashing. 5088 * @vpath_handle: Virtual Path handle. 5089 * @algorithm: Buffer to return Algorithm Select 5090 * @hash_type: Buffer to return Hash Type 5091 * @table_select: Buffer to return active Table 5092 * @bucket_size: Buffer to return no of least significant bits used for hashing. 5093 * 5094 * Used to read all RTS hashing related stuff. 5095 * 5096 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_itable_set(), 5097 * vxge_hal_vpath_rts_rth_set(). 5098 */ 5099vxge_hal_status_e 5100vxge_hal_vpath_rts_rth_get( 5101 vxge_hal_vpath_h vpath_handle, 5102 vxge_hal_rth_algoritms_t *algorithm, 5103 vxge_hal_rth_hash_types_t *hash_type, 5104 u8 *table_select, 5105 u16 *bucket_size); 5106 5107/* 5108 * vxge_hal_vpath_rts_rth_key_set - Configure 40byte secret for hash calc. 5109 * 5110 * @vpath_handle: Virtual Path ahandle. 5111 * @KeySize: Number of 64-bit words 5112 * @Key: upto 40-byte array of 64-bit values 5113 * This function configures the 40-byte secret which is used for hash 5114 * calculation. 5115 * 5116 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(). 5117 */ 5118vxge_hal_status_e 5119vxge_hal_vpath_rts_rth_key_set( 5120 vxge_hal_vpath_h vpath_handle, 5121 u8 KeySize, 5122 u64 *Key); 5123 5124/* 5125 * vxge_hal_vpath_rts_rth_key_get - Read 40byte secret for hash calc. 5126 * 5127 * @vpath_handle: Virtual Path ahandle. 5128 * @KeySize: Number of 64-bit words 5129 * @Key: Buffer to return the key 5130 * This function reads the 40-byte secret which is used for hash 5131 * calculation. 5132 * 5133 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(), 5134 * vxge_hal_vpath_rts_rth_key_set(). 5135 */ 5136vxge_hal_status_e 5137vxge_hal_vpath_rts_rth_key_get( 5138 vxge_hal_vpath_h vpath_handle, 5139 u8 KeySize, 5140 u64 *Key); 5141 5142/* 5143 * vxge_hal_vpath_rts_rth_jhash_cfg_set - Configure JHASH algorithm 5144 * 5145 * @vpath_handle: Virtual Path ahandle. 5146 * @golden_ratio: Golden ratio 5147 * @init_value: Initial value 5148 * This function configures JENKIN's HASH algorithm 5149 * 5150 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(). 5151 */ 5152vxge_hal_status_e 5153vxge_hal_vpath_rts_rth_jhash_cfg_set( 5154 vxge_hal_vpath_h vpath_handle, 5155 u32 golden_ratio, 5156 u32 init_value); 5157 5158/* 5159 * vxge_hal_vpath_rts_rth_jhash_cfg_get - Read JHASH algorithm 5160 * 5161 * @vpath_handle: Virtual Path ahandle. 5162 * @golden_ratio: Buffer to return Golden ratio 5163 * @init_value: Buffer to return Initial value 5164 * This function reads JENKIN's HASH algorithm 5165 * 5166 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(), 5167 * vxge_hal_vpath_rts_rth_jhash_cfg_set(). 5168 */ 5169vxge_hal_status_e 5170vxge_hal_vpath_rts_rth_jhash_cfg_get( 5171 vxge_hal_vpath_h vpath_handle, 5172 u32 *golden_ratio, 5173 u32 *init_value); 5174 5175/* 5176 * vxge_hal_vpath_rts_rth_mask_set - Set/configure JHASH mask. 5177 * @vpath_handle: Virtual Path ahandle. 5178 * @table_size: Size of the mask table 5179 * @hash_mask_ipv6sa: IPv6SA Hash Mask 5180 * @hash_mask_ipv6da: IPv6DA Hash Mask 5181 * @hash_mask_ipv4sa: IPv4SA Hash Mask 5182 * @hash_mask_ipv4da: IPv4DA Hash Mask 5183 * @hash_mask_l4sp: L4SP Hash Mask 5184 * @hash_mask_l4dp: L4DP Hash Mask 5185 * 5186 * Used to set/configure indirection table masks. 5187 * 5188 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(). 5189 */ 5190vxge_hal_status_e 5191vxge_hal_vpath_rts_rth_mask_set( 5192 vxge_hal_vpath_h vpath_handle, 5193 u32 table_size, 5194 u32 *hash_mask_ipv6sa, 5195 u32 *hash_mask_ipv6da, 5196 u32 *hash_mask_ipv4sa, 5197 u32 *hash_mask_ipv4da, 5198 u32 *hash_mask_l4sp, 5199 u32 *hash_mask_l4dp); 5200 5201/* 5202 * vxge_hal_vpath_rts_rth_mask_get - Read JHASH mask. 5203 * @vpath_handle: Virtual Path ahandle. 5204 * @table_size: Size of the mask table 5205 * @hash_mask_ipv6sa: Buffer to return IPv6SA Hash Mask 5206 * @hash_mask_ipv6da: Buffer to return IPv6DA Hash Mask 5207 * @hash_mask_ipv4sa: Buffer to return IPv4SA Hash Mask 5208 * @hash_mask_ipv4da: Buffer to return IPv4DA Hash Mask 5209 * @hash_mask_l4sp: Buffer to return L4SP Hash Mask 5210 * @hash_mask_l4dp: Buffer to return L4DP Hash Mask 5211 * 5212 * Used to read rth mask. 5213 * 5214 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(), 5215 * vxge_hal_vpath_rts_rth_mask_set(). 5216 */ 5217vxge_hal_status_e 5218vxge_hal_vpath_rts_rth_mask_get( 5219 vxge_hal_vpath_h vpath_handle, 5220 u32 table_size, 5221 u32 *hash_mask_ipv6sa, 5222 u32 *hash_mask_ipv6da, 5223 u32 *hash_mask_ipv4sa, 5224 u32 *hash_mask_ipv4da, 5225 u32 *hash_mask_l4sp, 5226 u32 *hash_mask_l4dp); 5227 5228/* 5229 * vxge_hal_vpath_rts_rth_itable_set - Set/configure indirection table (IT). 5230 * @vpath_handles: Virtual Path handles. 5231 * @vpath_count: Number of vpath handles passed in vpath_handles 5232 * @itable: Pointer to indirection table 5233 * @itable_size: Number of entries in itable 5234 * 5235 * Used to set/configure indirection table. 5236 * It enables the required no of entries in the IT. 5237 * It adds entries to the IT. 5238 * 5239 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(). 5240 */ 5241vxge_hal_status_e 5242vxge_hal_vpath_rts_rth_itable_set( 5243 vxge_hal_vpath_h *vpath_handles, 5244 u32 vpath_count, 5245 u8 *itable, 5246 u32 itable_size); 5247 5248/* 5249 * vxge_hal_vpath_rts_rth_itable_get - Read indirection table (IT). 5250 * @vpath_handles: Virtual Path handles. 5251 * @vpath_count: Number of vpath handles passed in vpath_handles 5252 * @itable: Pointer to the buffer to return indirection table 5253 * @itable_size: pointer to buffer to return Number of entries in itable 5254 * 5255 * Used to read indirection table. 5256 * 5257 * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(), 5258 * vxge_hal_vpath_rts_rth_itable_set(). 5259 */ 5260vxge_hal_status_e 5261vxge_hal_vpath_rts_rth_itable_get( 5262 vxge_hal_vpath_h *vpath_handles, 5263 u32 vpath_count, 5264 u8 *itable, 5265 u32 itable_size); 5266 5267/* 5268 * vxge_hal_vpath_rts_rth_clr - Clear RTS hashing. 5269 * @vpath_handles: Virtual Path handles. 5270 * @vpath_count: Number of vpath handles passed in vpath_handles 5271 * 5272 * This function is used to clear all RTS hashing related stuff. 5273 * 5274 * See also: vxge_hal_vpath_rts_rth_set(), vxge_hal_vpath_rts_rth_itable_set(). 5275 */ 5276vxge_hal_status_e 5277vxge_hal_vpath_rts_rth_clr( 5278 vxge_hal_vpath_h *vpath_handles, 5279 u32 vpath_count); 5280 5281/* 5282 * vxge_hal_vpath_promisc_enable - Enable promiscuous mode. 5283 * @vpath_handle: Vpath handle. 5284 * 5285 * Enable promiscuous mode of X3100 operation. 5286 * 5287 * See also: vxge_hal_vpath_promisc_disable(). 5288 */ 5289vxge_hal_status_e 5290vxge_hal_vpath_promisc_enable( 5291 vxge_hal_vpath_h vpath_handle); 5292 5293/* 5294 * vxge_hal_vpath_promisc_disable - Disable promiscuous mode. 5295 * @vpath_handle: Vpath handle. 5296 * 5297 * Disable promiscuous mode of X3100 operation. 5298 * 5299 * See also: vxge_hal_vpath_promisc_enable(). 5300 */ 5301vxge_hal_status_e 5302vxge_hal_vpath_promisc_disable( 5303 vxge_hal_vpath_h vpath_handle); 5304 5305/* 5306 * vxge_hal_vpath_bcast_enable - Enable broadcast 5307 * @vpath_handle: Vpath handle. 5308 * 5309 * Enable receiving broadcasts. 5310 */ 5311vxge_hal_status_e 5312vxge_hal_vpath_bcast_enable( 5313 vxge_hal_vpath_h vpath_handle); 5314 5315/* 5316 * vxge_hal_vpath_bcast_disable - Disable broadcast 5317 * @vpath_handle: Vpath handle. 5318 * 5319 * Disable receiving broadcasts. 5320 */ 5321vxge_hal_status_e 5322vxge_hal_vpath_bcast_disable( 5323 vxge_hal_vpath_h vpath_handle); 5324 5325/* 5326 * vxge_hal_vpath_mcast_enable - Enable multicast addresses. 5327 * @vpath_handle: Vpath handle. 5328 * 5329 * Enable X3100 multicast addresses. 5330 * Returns: VXGE_HAL_OK on success. 5331 * 5332 */ 5333vxge_hal_status_e 5334vxge_hal_vpath_mcast_enable( 5335 vxge_hal_vpath_h vpath_handle); 5336 5337/* 5338 * vxge_hal_vpath_mcast_disable - Disable multicast addresses. 5339 * @vpath_handle: Vpath handle. 5340 * 5341 * Disable X3100 multicast addresses. 5342 * Returns: VXGE_HAL_OK - success. 5343 * 5344 */ 5345vxge_hal_status_e 5346vxge_hal_vpath_mcast_disable( 5347 vxge_hal_vpath_h vpath_handle); 5348 5349/* 5350 * vxge_hal_vpath_ucast_enable - Enable unicast addresses. 5351 * @vpath_handle: Vpath handle. 5352 * 5353 * Enable X3100 unicast addresses. 5354 * Returns: VXGE_HAL_OK on success. 5355 * 5356 */ 5357vxge_hal_status_e 5358vxge_hal_vpath_ucast_enable( 5359 vxge_hal_vpath_h vpath_handle); 5360 5361/* 5362 * vxge_hal_vpath_ucast_disable - Disable unicast addresses. 5363 * @vpath_handle: Vpath handle. 5364 * 5365 * Disable X3100 unicast addresses. 5366 * Returns: VXGE_HAL_OK - success. 5367 * 5368 */ 5369vxge_hal_status_e 5370vxge_hal_vpath_ucast_disable( 5371 vxge_hal_vpath_h vpath_handle); 5372 5373/* 5374 * vxge_hal_vpath_all_vid_enable - Enable all Vlan Ids. 5375 * @vpath_handle: Vpath handle. 5376 * 5377 * Enable X3100 vlan ids. 5378 * Returns: VXGE_HAL_OK on success. 5379 * 5380 */ 5381vxge_hal_status_e 5382vxge_hal_vpath_all_vid_enable( 5383 vxge_hal_vpath_h vpath_handle); 5384 5385/* 5386 * vxge_hal_vpath_all_vid_disable - Disable all Vlan Ids. 5387 * @vpath_handle: Vpath handle. 5388 * 5389 * Disable X3100 vlan ids. 5390 * Returns: VXGE_HAL_OK - success. 5391 * 5392 */ 5393vxge_hal_status_e 5394vxge_hal_vpath_all_vid_disable( 5395 vxge_hal_vpath_h vpath_handle); 5396 5397/* 5398 * vxge_hal_vpath_strip_vlan_tag_enable - Enable strip vlan tag. 5399 * @vpath_handle: Vpath handle. 5400 * 5401 * Enable X3100 strip vlan tag. 5402 * Returns: VXGE_HAL_OK on success. 5403 * 5404 */ 5405vxge_hal_status_e 5406vxge_hal_vpath_strip_vlan_tag_enable( 5407 vxge_hal_vpath_h vpath_handle); 5408 5409/* 5410 * vxge_hal_vpath_strip_vlan_tag_disable - Disable strip vlan tag. 5411 * @vpath_handle: Vpath handle. 5412 * 5413 * Disable X3100 strip vlan tag. 5414 * Returns: VXGE_HAL_OK on success. 5415 * 5416 */ 5417vxge_hal_status_e 5418vxge_hal_vpath_strip_vlan_tag_disable( 5419 vxge_hal_vpath_h vpath_handle); 5420 5421void 5422vxge_hal_vpath_dynamic_tti_rtimer_set(vxge_hal_vpath_h vpath_handle, 5423 u32 timer_val); 5424 5425void 5426vxge_hal_vpath_dynamic_rti_rtimer_set(vxge_hal_vpath_h vpath_handle, 5427 u32 timer_val); 5428 5429void 5430vxge_hal_vpath_tti_ci_set(vxge_hal_vpath_h vpath_handle); 5431 5432void 5433vxge_hal_vpath_tti_ci_reset(vxge_hal_vpath_h vpath_handle); 5434 5435void 5436vxge_hal_vpath_rti_ci_set(vxge_hal_vpath_h vpath_handle); 5437 5438void 5439vxge_hal_vpath_rti_ci_reset(vxge_hal_vpath_h vpath_handle); 5440 5441/* 5442 * struct vxge_hal_vpath_tpa_params - Vpath TPA Parameters. 5443 * @tpa_lsov2_en: LSOv2 Behaviour for IP ID roll-over 5444 * 1 - enable, 0 - disable, 5445 * VXGE_HAL_DEFAULT_32 - don't change current setting 5446 * @tpa_ignore_frame_error: Ignore Frame Error. TPA may detect frame integrity 5447 * errors as it processes each frame. If this bit is set to '0', 5448 * the TPA will tag such frames as invalid and they will be dropped 5449 * by the transmit MAC. If the bit is set to '1',the frame will not 5450 * be tagged as "errored". Detectable errors include: 5451 * 1) early end-of-frame error, which occurs when the frame ends 5452 * before the number of bytes predicted by the IP "total length" 5453 * field have been received; 5454 * 2) IP version mismatches; 5455 * 3) IPv6 packets that include routing headers that are not type 0 5456 * 4) Frames which contain IP packets but have an illegal SNAP-OUI 5457 * or LLC-CTRL fields, unless IGNORE_SNAP_OUI or IGNORE_LLC_CTRL 5458 * are set (see below). 5459 * setting the value of this field to VXGE_HAL_DEFAULT_32 - don't 5460 * change current setting 5461 * @tpa_ipv6_keep_searching: If unknown IPv6 header is found, 5462 * 0 - stop searching for TCP 5463 * 1 - keep searching for TCP 5464 * VXGE_HAL_DEFAULT_32 - don't change current setting 5465 * @tpa_l4_pshdr_present: If asserted true, indicates the host has provided a 5466 * valid pseudo header for TCP or UDP running over IPv4 or IPv6 5467 * if set to VXGE_HAL_DEFAULT_32 - don't change current setting 5468 * @tpa_support_mobile_ipv6_hdrs: This register is somewhat equivalent to 5469 * asserting both Hercules register fields LSO_RT2_EN and 5470 * LSO_IPV6_HAO_EN. Enable/disable support for Type 2 Routing 5471 * Headers, and for Mobile-IPv6 Home Address Option (HAO), as 5472 * defined by mobile-ipv6. if set to VXGE_HAL_DEFAULT_32 - 5473 * don't change current setting 5474 * 5475 * See also: vxge_hal_vpath_tpa_set() 5476 */ 5477typedef struct vxge_hal_vpath_tpa_params { 5478 u32 tpa_lsov2_en; 5479 u32 tpa_ignore_frame_error; 5480 u32 tpa_ipv6_keep_searching; 5481 u32 tpa_l4_pshdr_present; 5482 u32 tpa_support_mobile_ipv6_hdrs; 5483} vxge_hal_vpath_tpa_params; 5484 5485/* 5486 * vxge_hal_vpath_tpa_set - Set tpa parameters. 5487 * @vpath_handle: Virtual Path ahandle. 5488 * @params: vxge_hal_vpath_tpa_params {} structure with parameters 5489 * 5490 * The function sets the tpa parametrs for the vpath. 5491 * 5492 * See also: vxge_hal_vpath_tpa_params {} 5493 */ 5494vxge_hal_status_e 5495vxge_hal_vpath_tpa_set( 5496 vxge_hal_vpath_h vpath_handle, 5497 vxge_hal_vpath_tpa_params *params); 5498 5499/* 5500 * struct vxge_hal_vpath_rpa_params - Vpath RPA Parameters. 5501 * 5502 * @rpa_ipv4_tcp_incl_ph: Determines if the pseudo-header is included in the 5503 * calculation of the L4 checksum that is passed to the host. This 5504 * field applies to TCP/IPv4 packets only. This field affects both 5505 * non-offload and LRO traffic. Note that the RPA always includes 5506 * the pseudo-header in the "Checksum Ok" L4 checksum calculation 5507 * i.e. the checksum that decides whether a frame is a candidate to 5508 * be offloaded. 5509 * 0 - Do not include the pseudo-header in L4 checksum calculation. 5510 * This setting should be used if the adapter is incorrectly 5511 * calculating the pseudo-header. 5512 * 1 - Include the pseudo-header in L4 checksum calculation 5513 * VXGE_HAL_DEFAULT_32 - don't change current setting 5514 * @rpa_ipv6_tcp_incl_ph: Determines whether the pseudo-header is included in 5515 * the calculation of the L4 checksum that is passed to the host. 5516 * This field applies to TCP/IPv6 packets only. This field affects 5517 * both non-offload and LRO traffic. Note that the RPA always 5518 * includes the pseudo-header in the "Checksum Ok" L4 checksum 5519 * calculation. i.e. the checksum that decides whether a frame 5520 * is a candidate to be offloaded. 5521 * 0 - Do not include the pseudo-header in L4 checksum calculation. 5522 * This setting should be used if the adapter is incorrectly 5523 * calculating the pseudo-header. 5524 * 1 - Include the pseudo-header in L4 checksum calculation 5525 * VXGE_HAL_DEFAULT_32 - don't change current setting 5526 * @rpa_ipv4_udp_incl_ph: Determines whether the pseudo-header is included in 5527 * the calculation of the L4 checksum that is passed to the host. 5528 * This field applies to UDP/IPv4 packets only. It only affects 5529 * non-offload traffic(since UDP frames are not candidates for LRO) 5530 * 0 - Do not include the pseudo-header in L4 checksum calculation. 5531 * This setting should be used if the adapter is incorrectly 5532 * calculating the pseudo-header. 5533 * 1 - Include the pseudo-header in L4 checksum calculation 5534 * VXGE_HAL_DEFAULT_32 - don't change current setting 5535 * @rpa_ipv6_udp_incl_ph: Determines if the pseudo-header is included in the 5536 * calculation of the L4 checksum that is passed to the host. This 5537 * field applies to UDP/IPv6 packets only. It only affects 5538 * non-offload traffic(since UDP frames are not candidates for LRO) 5539 * 0 - Do not include the pseudo-header in L4 checksum calculation. 5540 * This setting should be used if the adapter is incorrectly 5541 * calculating the pseudo-header. 5542 * 1 - Include the pseudo-header in L4 checksum calculation 5543 * VXGE_HAL_DEFAULT_32 - don't change current setting 5544 * @rpa_l4_incl_cf: Determines whether the checksum field (CF) of the received 5545 * frame is included in the calculation of the L4 checksum that is 5546 * passed to the host. This field affects both non-offload and LRO 5547 * traffic. Note that the RPA always includes the checksum field in 5548 * the "Checksum Ok" L4 checksum calculation -- i.e. the checksum 5549 * that decides whether a frame is a candidate to be offloaded. 5550 * 0 - Do not include the checksum field in L4 checksum calculation 5551 * 1 - Include the checksum field in L4 checksum calculation 5552 * VXGE_HAL_DEFAULT_32 - don't change current setting 5553 * @rpa_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device to 5554 * remove the VLAN tag from all received tagged frames that are not 5555 * replicated at the internal L2 switch. 5556 * 0 - Do not strip the VLAN tag. 5557 * 1 - Strip the VLAN tag. Regardless of this setting,VLAN tags are 5558 * always placed into the RxDMA descriptor. 5559 * VXGE_HAL_DEFAULT_32 - don't change current setting 5560 * @rpa_l4_comp_csum: Determines whether the calculated L4 checksum should be 5561 * complemented before it is passed to the host This field affects 5562 * both non-offload and LRO traffic. 5563 * 0 - Do not complement the calculated L4 checksum. 5564 * 1 - Complement the calculated L4 checksum 5565 * VXGE_HAL_DEFAULT_32 - don't change current setting 5566 * @rpa_l3_incl_cf: Determines whether the checksum field (CF) of the received 5567 * frame is included in the calculation of the L3 checksum that is 5568 * passed to the host. This field affects both non-offload and LRO 5569 * traffic. Note that the RPA always includes the checksum field in 5570 * the "Checksum Ok" L3 checksum calculation -- i.e. the checksum 5571 * that decides whether a frame is a candidate to be offloaded. 5572 * 0 - Do not include the checksum field in L3 checksum calculation 5573 * 1 - Include the checksum field in L3 checksum calculation 5574 * VXGE_HAL_DEFAULT_32 - don't change current setting 5575 * @rpa_l3_comp_csum: Determines whether the calculated L3 checksum should be 5576 * complemented before it is passed to the host This field affects 5577 * both non-offload and LRO traffic. 5578 * 0 - Do not complement the calculated L3 checksum. 5579 * 1 - Complement the calculated L3 checksum 5580 * VXGE_HAL_DEFAULT_32 - don't change current setting 5581 * @rpa_ucast_all_addr_en: Enables frames with any unicast address (as its 5582 * destination address) to be passed to the host. 5583 * Setting this field to VXGE_HAL_DEFAULT_32 - don't change current 5584 * setting 5585 * @rpa_mcast_all_addr_en: Enables frames with any multicast address (as its 5586 * destination address) to be passed to the host. 5587 * Setting this field to VXGE_HAL_DEFAULT_32 - don't change current 5588 * setting 5589 * @rpa_bcast_en: Enables frames with any broadicast address (as its 5590 * destination address) to be passed to the host. 5591 * Setting this field to VXGE_HAL_DEFAULT_32 - don't change current 5592 * setting 5593 * @rpa_all_vid_en: romiscuous mode, it overrides the value held in this field. 5594 * 0 - Disable; 5595 * 1 - Enable 5596 * VXGE_HAL_DEFAULT_32 - don't change current setting 5597 * Note: RXMAC_GLOBAL_CFG.AUTHORIZE_VP_ALL_VID must be set to 5598 * allow this. 5599 * 5600 * See also: vxge_hal_vpath_rpa_set() 5601 */ 5602typedef struct vxge_hal_vpath_rpa_params { 5603 u32 rpa_ipv4_tcp_incl_ph; 5604 u32 rpa_ipv6_tcp_incl_ph; 5605 u32 rpa_ipv4_udp_incl_ph; 5606 u32 rpa_ipv6_udp_incl_ph; 5607 u32 rpa_l4_incl_cf; 5608 u32 rpa_strip_vlan_tag; 5609 u32 rpa_l4_comp_csum; 5610 u32 rpa_l3_incl_cf; 5611 u32 rpa_l3_comp_csum; 5612 u32 rpa_ucast_all_addr_en; 5613 u32 rpa_mcast_all_addr_en; 5614 u32 rpa_bcast_en; 5615 u32 rpa_all_vid_en; 5616} vxge_hal_vpath_rpa_params; 5617 5618/* 5619 * vxge_hal_vpath_rpa_set - Set rpa parameters. 5620 * @vpath_handle: Virtual Path ahandle. 5621 * @params: vxge_hal_vpath_rpa_params {} structure with parameters 5622 * 5623 * The function sets the rpa parametrs for the vpath. 5624 * 5625 * See also: vxge_hal_vpath_rpa_params {} 5626 */ 5627vxge_hal_status_e 5628vxge_hal_vpath_rpa_set( 5629 vxge_hal_vpath_h vpath_handle, 5630 vxge_hal_vpath_rpa_params *params); 5631 5632/* 5633 * vxge_hal_vpath_poll_rx - Poll Rx od Virtual Path for completed 5634 * descriptors and process the same. 5635 * @vpath_handle: Virtual Path ahandle. 5636 * @got_rx: Buffer to return the flag set if receive interrupt is occured 5637 * 5638 * The function polls the Rx for the completed descriptors and calls 5639 * the upper-layer driver (ULD) via supplied completion callback. 5640 * 5641 * Returns: VXGE_HAL_OK, if the polling is completed successful. 5642 * VXGE_HAL_COMPLETIONS_REMAIN: There are still more completed 5643 * descriptors available which are yet to be processed. 5644 * 5645 * See also: vxge_hal_vpath_poll_tx() 5646 */ 5647vxge_hal_status_e 5648vxge_hal_vpath_poll_rx( 5649 vxge_hal_vpath_h vpath_handle, 5650 u32 *got_rx); 5651 5652/* 5653 * vxge_hal_vpath_poll_tx - Poll Tx for completed descriptors and process 5654 * the same. 5655 * @vpath_handle: Virtual Path ahandle. 5656 * @got_tx: Buffer to return the flag set if transmit interrupt is occured 5657 * 5658 * The function polls the Tx for the completed descriptors and calls 5659 * the upper-layer driver (ULD) via supplied completion callback. 5660 * 5661 * Returns: VXGE_HAL_OK, if the polling is completed successful. 5662 * VXGE_HAL_COMPLETIONS_REMAIN: There are still more completed 5663 * descriptors available which are yet to be processed. 5664 * 5665 * See also: vxge_hal_vpath_poll_rx(). 5666 */ 5667vxge_hal_status_e 5668vxge_hal_vpath_poll_tx( 5669 vxge_hal_vpath_h vpath_handle, 5670 u32 *got_tx); 5671 5672 5673/* 5674 * vxge_hal_vpath_intr_enable - Enable vpath interrupts. 5675 * @vpath_handle: Virtual Path handle. 5676 * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying 5677 * the type(s) of interrupts to enable. 5678 * 5679 * Enable vpath interrupts. The function is to be executed the last in 5680 * vpath initialization sequence. 5681 * 5682 * See also: vxge_hal_vpath_intr_disable() 5683 */ 5684vxge_hal_status_e 5685vxge_hal_vpath_intr_enable( 5686 vxge_hal_vpath_h vpath_handle); 5687 5688/* 5689 * vxge_hal_vpath_intr_disable - Disable vpath interrupts. 5690 * @vpath_handle: Virtual Path handle. 5691 * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying 5692 * the type(s) of interrupts to disable. 5693 * 5694 * Disable vpath interrupts. 5695 * 5696 * See also: vxge_hal_vpath_intr_enable() 5697 */ 5698vxge_hal_status_e 5699vxge_hal_vpath_intr_disable( 5700 vxge_hal_vpath_h vpath_handle); 5701 5702/* 5703 * vxge_hal_vpath_mask_all - Mask all vpath interrupts. 5704 * @vpath_handle: Virtual Path handle. 5705 * 5706 * Mask all vpath interrupts. 5707 * 5708 * See also: vxge_hal_vpath_unmask_all() 5709 */ 5710void 5711vxge_hal_vpath_mask_all( 5712 vxge_hal_vpath_h vpath_handle); 5713 5714/* 5715 * vxge_hal_vpath_unmask_all - Unmask all vpath interrupts. 5716 * @vpath_handle: Virtual Path handle. 5717 * 5718 * Unmask all vpath interrupts. 5719 * 5720 * See also: vxge_hal_vpath_mask_all() 5721 */ 5722void 5723vxge_hal_vpath_unmask_all( 5724 vxge_hal_vpath_h vpath_handle); 5725 5726/* 5727 * vxge_hal_vpath_begin_irq - Begin IRQ processing. 5728 * @vpath_handle: Virtual Path handle. 5729 * @skip_alarms: Do not clear the alarms 5730 * @reason: "Reason" for the interrupt, the value of vpath's 5731 * general_int_status register. 5732 * 5733 * The function performs two actions, It first checks whether (shared IRQ) the 5734 * interrupt was raised by the device. Next, it masks the device interrupts. 5735 * 5736 * Note: 5737 * vxge_hal_vpath_begin_irq() does not flush MMIO writes through the 5738 * bridge. Therefore, two back-to-back interrupts are potentially possible. 5739 * It is the responsibility of the ULD to make sure that only one 5740 * vxge_hal_vpath_continue_irq() runs at a time. 5741 * 5742 * Returns: 0, if the interrupt is not "ours" (note that in this case the 5743 * vpath remain enabled). 5744 * Otherwise, vxge_hal_vpath_begin_irq() returns 64bit general adapter 5745 * status. 5746 * See also: vxge_hal_vpath_handle_irq() 5747 */ 5748vxge_hal_status_e 5749vxge_hal_vpath_begin_irq( 5750 vxge_hal_vpath_h vpath_handle, 5751 u32 skip_alarms, 5752 u64 *reason); 5753 5754/* 5755 * vxge_hal_vpath_continue_irq - Continue handling IRQ: process all 5756 * completed descriptors. 5757 * @vpath_handle: Virtual Path handle. 5758 * 5759 * Process completed descriptors and unmask the vpath interrupts. 5760 * 5761 * The vxge_hal_vpath_continue_irq() calls upper-layer driver (ULD) 5762 * via supplied completion callback. 5763 * 5764 * Note that the vxge_hal_vpath_continue_irq is part of the _fast_ path. 5765 * To optimize the processing, the function does _not_ check for 5766 * errors and alarms. 5767 * 5768 * Returns: VXGE_HAL_OK. 5769 * 5770 * See also: vxge_hal_vpath_handle_irq(), 5771 * vxge_hal_ring_rxd_next_completed(), 5772 * vxge_hal_fifo_txdl_next_completed(), vxge_hal_ring_callback_f {}, 5773 * vxge_hal_fifo_callback_f {}. 5774 */ 5775vxge_hal_status_e 5776vxge_hal_vpath_continue_irq( 5777 vxge_hal_vpath_h vpath_handle); 5778 5779/* 5780 * vxge_hal_vpathe_handle_irq - Handle vpath IRQ. 5781 * @vpath_handle: Virtual Path handle. 5782 * @skip_alarms: Do not clear the alarms 5783 * 5784 * Perform the complete handling of the line interrupt. The function 5785 * performs two calls. 5786 * First it uses vxge_hal_vpath_begin_irq() to check the reason for 5787 * the interrupt and mask the vpath interrupts. 5788 * Second, it calls vxge_hal_vpath_continue_irq() to process all 5789 * completed descriptors and re-enable the interrupts. 5790 * 5791 * Returns: VXGE_HAL_OK - success; 5792 * VXGE_HAL_ERR_WRONG_IRQ - (shared) IRQ produced by other device. 5793 * 5794 * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(). 5795 */ 5796vxge_hal_status_e 5797vxge_hal_vpath_handle_irq( 5798 vxge_hal_vpath_h vpath_handle, 5799 u32 skip_alarms); 5800 5801/* 5802 * vxge_hal_vpath_mask_tx - Mask Tx interrupts. 5803 * @vpath_handle: Virtual Path handle. 5804 * 5805 * Mask Tx device interrupts. 5806 * 5807 * See also: vxge_hal_vpath_unmask_tx(), vxge_hal_vpath_mask_rx(), 5808 * vxge_hal_vpath_clear_tx(). 5809 */ 5810void 5811vxge_hal_vpath_mask_tx( 5812 vxge_hal_vpath_h vpath_handle); 5813 5814/* 5815 * vxge_hal_vpath_clear_tx - Acknowledge (that is, clear) the 5816 * condition that has caused the TX interrupt. 5817 * @vpath_handle: Virtual Path handle. 5818 * 5819 * Acknowledge (that is, clear) the condition that has caused 5820 * the Tx interrupt. 5821 * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(), 5822 * vxge_hal_vpath_clear_rx(), vxge_hal_vpath_mask_tx(). 5823 */ 5824void 5825vxge_hal_vpath_clear_tx( 5826 vxge_hal_vpath_h vpath_handle); 5827 5828 5829/* 5830 * vxge_hal_vpath_unmask_tx - Unmask Tx interrupts. 5831 * @vpath_handle: Virtual Path handle. 5832 * 5833 * Unmask Tx vpath interrupts. 5834 * 5835 * See also: vxge_hal_vpath_mask_tx(), vxge_hal_vpath_clear_tx(). 5836 */ 5837void 5838vxge_hal_vpath_unmask_tx( 5839 vxge_hal_vpath_h vpath_handle); 5840 5841/* 5842 * vxge_hal_vpath_mask_rx - Mask Rx interrupts. 5843 * @vpath_handle: Virtual Path handle. 5844 * 5845 * Mask Rx vpath interrupts. 5846 * 5847 * See also: vxge_hal_vpath_unmask_rx(), vxge_hal_vpath_mask_tx(), 5848 * vxge_hal_vpath_clear_rx(). 5849 */ 5850void 5851vxge_hal_vpath_mask_rx( 5852 vxge_hal_vpath_h vpath_handle); 5853 5854 5855/* 5856 * vxge_hal_vpath_clear_rx - Acknowledge (that is, clear) the 5857 * condition that has caused the RX interrupt. 5858 * @vpath_handle: Virtual Path handle. 5859 * 5860 * Acknowledge (that is, clear) the condition that has caused 5861 * the Rx interrupt. 5862 * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(), 5863 * vxge_hal_vpath_clear_tx(), vxge_hal_vpath_mask_rx(). 5864 */ 5865void 5866vxge_hal_vpath_clear_rx( 5867 vxge_hal_vpath_h vpath_handle); 5868 5869/* 5870 * vxge_hal_vpath_unmask_rx - Unmask Rx interrupts. 5871 * @vpath_handle: Virtual Path handle. 5872 * 5873 * Unmask Rx vpath interrupts. 5874 * 5875 * See also: vxge_hal_vpath_mask_rx(), vxge_hal_vpath_clear_rx(). 5876 */ 5877void 5878vxge_hal_vpath_unmask_rx( 5879 vxge_hal_vpath_h vpath_handle); 5880 5881/* 5882 * vxge_hal_vpath_mask_tx_rx - Mask Tx and Rx interrupts. 5883 * @vpath_handle: Virtual Path handle. 5884 * 5885 * Mask Tx and Rx vpath interrupts. 5886 * 5887 * See also: vxge_hal_vpath_unmask_tx_rx(), vxge_hal_vpath_clear_tx_rx(). 5888 */ 5889void 5890vxge_hal_vpath_mask_tx_rx( 5891 vxge_hal_vpath_h vpath_handle); 5892 5893/* 5894 * vxge_hal_vpath_clear_tx_rx - Acknowledge (that is, clear) the 5895 * condition that has caused the Tx and RX interrupt. 5896 * @vpath_handle: Virtual Path handle. 5897 * 5898 * Acknowledge (that is, clear) the condition that has caused 5899 * the Tx and Rx interrupt. 5900 * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(), 5901 * vxge_hal_vpath_clear_tx_rx(), vxge_hal_vpath_mask_tx_rx(). 5902 */ 5903void 5904vxge_hal_vpath_clear_tx_rx( 5905 vxge_hal_vpath_h vpath_handle); 5906 5907/* 5908 * vxge_hal_vpath_unmask_tx_rx - Unmask Tx and Rx interrupts. 5909 * @vpath_handle: Virtual Path handle. 5910 * 5911 * Unmask Tx and Rx vpath interrupts. 5912 * 5913 * See also: vxge_hal_vpath_mask_tx_rx(), vxge_hal_vpath_clear_tx_rx(). 5914 */ 5915void 5916vxge_hal_vpath_unmask_tx_rx( 5917 vxge_hal_vpath_h vpath_handle); 5918 5919/* 5920 * vxge_hal_vpath_alarm_process - Process Alarms. 5921 * @vpath: Virtual Path. 5922 * @skip_alarms: Do not clear the alarms 5923 * 5924 * Process vpath alarms. 5925 * 5926 */ 5927vxge_hal_status_e 5928vxge_hal_vpath_alarm_process( 5929 vxge_hal_vpath_h vpath_handle, 5930 u32 skip_alarms); 5931 5932/* NEWCODE */ 5933 5934vxge_hal_status_e 5935vxge_hal_vpath_mf_msix_set(vxge_hal_vpath_h vpath_handle, 5936 int *tim_msix_id, int alarm_msix_id); 5937void 5938vxge_hal_vpath_mf_msix_clear(vxge_hal_vpath_h vpath_handle, int msix_id); 5939void 5940vxge_hal_vpath_mf_msix_mask(vxge_hal_vpath_h vpath_handle, int msix_id); 5941void 5942vxge_hal_vpath_mf_msix_unmask(vxge_hal_vpath_h vpath_handle, int msix_id); 5943 5944/* NEWCODE */ 5945 5946/* 5947 * vxge_hal_vpath_msix_mode - Is MSIX enabled? 5948 * @vpath_handle: Virtual Path handle. 5949 * 5950 * Returns 0 if MSI is enabled for the specified device, 5951 * non-zero otherwise. 5952 */ 5953u32 5954vxge_hal_vpath_msix_mode(vxge_hal_vpath_h vpath_handle); 5955 5956/* 5957 * vxge_hal_vpath_msix_set - Associate MSIX vectors with TIM interrupts and 5958 * alrms 5959 * @vpath_handle: Virtual Path handle. 5960 * @tim_msix_id: MSIX vectors associated with VXGE_HAL_VPATH_MSIX_MAX number of 5961 * interrupts(Valid numbers 0 to 3). 5962 * @alarm_msix_id: MSIX vector for alarm (Valid numbers 0 to 3). 5963 * 5964 * This API will associate a given MSIX vector numbers with the four TIM 5965 * interrupts and alarm interrupt. 5966 */ 5967vxge_hal_status_e 5968vxge_hal_vpath_msix_set(vxge_hal_vpath_h vpath_handle, 5969 int *tim_msix_id, 5970 int alarm_msix_id); 5971 5972/* 5973 * vxge_hal_vpath_msix_mask - Mask MSIX Vector. 5974 * @vpath_handle: Virtual Path handle. 5975 * @msix_id: MSIX ID 5976 * 5977 * The function masks the msix interrupt for the given msix_id 5978 * 5979 * Note: 5980 * 5981 * Returns: 0, 5982 * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range 5983 * status. 5984 * See also: 5985 */ 5986void 5987vxge_hal_vpath_msix_mask(vxge_hal_vpath_h vpath_handle, int msix_id); 5988 5989/* 5990 * vxge_hal_vpath_msix_clear - Clear MSIX Vector. 5991 * @vpath_handle: Virtual Path handle. 5992 * @msix_id: MSI ID 5993 * 5994 * The function clears the msix interrupt for the given msix_id 5995 * 5996 * Note: 5997 * 5998 * Returns: 0, 5999 * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range 6000 * status. 6001 * See also: 6002 */ 6003void 6004vxge_hal_vpath_msix_clear(vxge_hal_vpath_h vpath_handle, int msix_id); 6005 6006/* 6007 * vxge_hal_vpath_msix_unmask - Unmask MSIX Vector. 6008 * @vpath_handle: Virtual Path handle. 6009 * @msix_id: MSI ID 6010 * 6011 * The function unmasks the msix interrupt for the given msix_id 6012 * 6013 * Note: 6014 * 6015 * Returns: 0, 6016 * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range 6017 * status. 6018 * See also: 6019 */ 6020void 6021vxge_hal_vpath_msix_unmask(vxge_hal_vpath_h vpath_handle, int msix_id); 6022 6023/* 6024 * vxge_hal_vpath_msix_mask_all - Mask all MSIX vectors for the vpath. 6025 * @vpath_handle: Virtual Path handle. 6026 * 6027 * The function masks the msix interrupt for the given vpath 6028 * 6029 */ 6030void 6031vxge_hal_vpath_msix_mask_all(vxge_hal_vpath_h vpath_handle); 6032 6033/* 6034 * vxge_hal_vpath_msix_unmask_all - Unmask all MSIX vectors for the vpath. 6035 * @vpath_handle: Virtual Path handle. 6036 * 6037 * The function unmasks the msix interrupt for the given vpath 6038 * 6039 */ 6040void 6041vxge_hal_vpath_msix_unmask_all(vxge_hal_vpath_h vpath_handle); 6042 6043/* 6044 * vxge_hal_vpath_is_rxdmem_leak - Check for the rxd memory leak. 6045 * @vpath_handle: Virtual Path handle. 6046 * 6047 * The function checks for the rxd memory leak. 6048 * 6049 */ 6050u32 6051vxge_hal_vpath_is_rxdmem_leak(vxge_hal_vpath_h vpath_handle); 6052 6053/* 6054 * vxge_hal_rldram_test - offline test for access to the RldRam chip on 6055 * the NIC 6056 * @devh: HAL device handle. 6057 * @data: variable that returns the result of each of the test 6058 * conducted by the driver. 6059 * 6060 * This is one of the offline test that tests the read and write 6061 * access to the RldRam chip on the NIC. 6062 * Return value: 6063 * 0 on success. 6064 */ 6065vxge_hal_status_e 6066vxge_hal_rldram_test( 6067 vxge_hal_device_h devh, 6068 u64 *data); 6069 6070/* 6071 * vxge_hal_check_alignment - Check buffer alignment and calculate the 6072 * "misaligned" portion. 6073 * @dma_pointer: DMA address of the buffer. 6074 * @size: Buffer size, in bytes. 6075 * @alignment: Alignment "granularity" (see below), in bytes. 6076 * @copy_size: Maximum number of bytes to "extract" from the buffer 6077 * (in order to spost it as a separate scatter-gather entry). See below. 6078 * 6079 * Check buffer alignment and calculate "misaligned" portion, if exists. 6080 * The buffer is considered aligned if its address is multiple of 6081 * the specified @alignment. If this is the case, 6082 * vxge_hal_check_alignment() returns zero. 6083 * Otherwise, vxge_hal_check_alignment() uses the last argument, 6084 * @copy_size, 6085 * to calculate the size to "extract" from the buffer. The @copy_size 6086 * may or may not be equal @alignment. The difference between these two 6087 * arguments is that the @alignment is used to make the decision: aligned 6088 * or not aligned. While the @copy_size is used to calculate the portion 6089 * of the buffer to "extract", i.e. to post as a separate entry in the 6090 * transmit descriptor. For example, the combination 6091 * @alignment=8 and @copy_size=64 will work okay on AMD Opteron boxes. 6092 * 6093 * Note: @copy_size should be a multiple of @alignment. In many practical 6094 * cases @copy_size and @alignment will probably be equal. 6095 * 6096 * See also: vxge_hal_fifo_txdl_buffer_set_aligned(). 6097 */ 6098u32 6099vxge_hal_check_alignment( 6100 dma_addr_t dma_pointer, 6101 u32 size, 6102 u32 alignment, 6103 u32 copy_size); 6104 6105 6106void 6107vxge_hw_vpath_set_zero_rx_frm_len(vxge_hal_device_h devh, u32 vp_id); 6108 6109void 6110vxge_hw_vpath_wait_receive_idle(vxge_hal_device_h devh, u32 vp_id, 6111 u32 *count, u32 *total_count); 6112 6113#define VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT 5 6114#define VXGE_HW_MAX_POLLING_COUNT 160 6115 6116 6117__EXTERN_END_DECLS 6118 6119#include <dev/vxge/include/vxge-os-debug.h> 6120 6121#endif /* VXGE_HAL_LL_H */ 6122