1/*- 2 * Copyright (c) 1997, 1998, 1999, 2000-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD$"); 35 36/* 37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 38 * Used in the LinkSys USB200M and various other adapters. 39 * 40 * Manuals available from: 41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 43 * controller) to find the definitions for the RX control register. 44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 45 * 46 * Written by Bill Paul <wpaul@windriver.com> 47 * Senior Engineer 48 * Wind River Systems 49 */ 50 51/* 52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 53 * It uses an external PHY (reference designs use a RealTek chip), 54 * and has a 64-bit multicast hash filter. There is some information 55 * missing from the manual which one needs to know in order to make 56 * the chip function: 57 * 58 * - You must set bit 7 in the RX control register, otherwise the 59 * chip won't receive any packets. 60 * - You must initialize all 3 IPG registers, or you won't be able 61 * to send any packets. 62 * 63 * Note that this device appears to only support loading the station 64 * address via autload from the EEPROM (i.e. there's no way to manaully 65 * set it). 66 * 67 * (Adam Weinberger wanted me to name this driver if_gir.c.) 68 */ 69 70/* 71 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 73 * 74 * Manual here: 75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 77 */ 78 79#include <sys/param.h> 80#include <sys/systm.h> 81#include <sys/bus.h> 82#include <sys/condvar.h> 83#include <sys/endian.h> 84#include <sys/kernel.h> 85#include <sys/lock.h> 86#include <sys/malloc.h> 87#include <sys/mbuf.h> 88#include <sys/module.h> 89#include <sys/mutex.h> 90#include <sys/socket.h> 91#include <sys/sockio.h> 92#include <sys/sysctl.h> 93#include <sys/sx.h> 94 95#include <net/if.h> 96#include <net/ethernet.h> 97#include <net/if_types.h> 98#include <net/if_media.h> 99#include <net/if_vlan_var.h> 100 101#include <dev/mii/mii.h> 102#include <dev/mii/miivar.h> 103 104#include <dev/usb/usb.h> 105#include <dev/usb/usbdi.h> 106#include <dev/usb/usbdi_util.h> 107#include "usbdevs.h" 108 109#define USB_DEBUG_VAR axe_debug 110#include <dev/usb/usb_debug.h> 111#include <dev/usb/usb_process.h> 112 113#include <dev/usb/net/usb_ethernet.h> 114#include <dev/usb/net/if_axereg.h> 115 116/* 117 * AXE_178_MAX_FRAME_BURST 118 * max frame burst size for Ax88178 and Ax88772 119 * 0 2048 bytes 120 * 1 4096 bytes 121 * 2 8192 bytes 122 * 3 16384 bytes 123 * use the largest your system can handle without USB stalling. 124 * 125 * NB: 88772 parts appear to generate lots of input errors with 126 * a 2K rx buffer and 8K is only slightly faster than 4K on an 127 * EHCI port on a T42 so change at your own risk. 128 */ 129#define AXE_178_MAX_FRAME_BURST 1 130 131#define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 132 133#ifdef USB_DEBUG 134static int axe_debug = 0; 135 136static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe"); 137SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0, 138 "Debug level"); 139#endif 140 141/* 142 * Various supported device vendors/products. 143 */ 144static const STRUCT_USB_HOST_ID axe_devs[] = { 145#define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 146 AXE_DEV(ABOCOM, UF200, 0), 147 AXE_DEV(ACERCM, EP1427X2, 0), 148 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), 149 AXE_DEV(ASIX, AX88172, 0), 150 AXE_DEV(ASIX, AX88178, AXE_FLAG_178), 151 AXE_DEV(ASIX, AX88772, AXE_FLAG_772), 152 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), 153 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B), 154 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B), 155 AXE_DEV(ATEN, UC210T, 0), 156 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), 157 AXE_DEV(BILLIONTON, USB2AR, 0), 158 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), 159 AXE_DEV(COREGA, FETHER_USB2_TX, 0), 160 AXE_DEV(DLINK, DUBE100, 0), 161 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), 162 AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B), 163 AXE_DEV(GOODWAY, GWUSB2E, 0), 164 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), 165 AXE_DEV(JVC, MP_PRX1, 0), 166 AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B), 167 AXE_DEV(LINKSYS2, USB200M, 0), 168 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), 169 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), 170 AXE_DEV(MELCO, LUAU2KTX, 0), 171 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), 172 AXE_DEV(NETGEAR, FA120, 0), 173 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), 174 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), 175 AXE_DEV(SITECOM, LN029, 0), 176 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), 177 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), 178#undef AXE_DEV 179}; 180 181static device_probe_t axe_probe; 182static device_attach_t axe_attach; 183static device_detach_t axe_detach; 184 185static usb_callback_t axe_bulk_read_callback; 186static usb_callback_t axe_bulk_write_callback; 187 188static miibus_readreg_t axe_miibus_readreg; 189static miibus_writereg_t axe_miibus_writereg; 190static miibus_statchg_t axe_miibus_statchg; 191 192static uether_fn_t axe_attach_post; 193static uether_fn_t axe_init; 194static uether_fn_t axe_stop; 195static uether_fn_t axe_start; 196static uether_fn_t axe_tick; 197static uether_fn_t axe_setmulti; 198static uether_fn_t axe_setpromisc; 199 200static int axe_attach_post_sub(struct usb_ether *); 201static int axe_ifmedia_upd(struct ifnet *); 202static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 203static int axe_cmd(struct axe_softc *, int, int, int, void *); 204static void axe_ax88178_init(struct axe_softc *); 205static void axe_ax88772_init(struct axe_softc *); 206static void axe_ax88772_phywake(struct axe_softc *); 207static void axe_ax88772a_init(struct axe_softc *); 208static void axe_ax88772b_init(struct axe_softc *); 209static int axe_get_phyno(struct axe_softc *, int); 210static int axe_ioctl(struct ifnet *, u_long, caddr_t); 211static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 212static int axe_rxeof(struct usb_ether *, struct usb_page_cache *, 213 unsigned int offset, unsigned int, struct axe_csum_hdr *); 214static void axe_csum_cfg(struct usb_ether *); 215 216static const struct usb_config axe_config[AXE_N_TRANSFER] = { 217 218 [AXE_BULK_DT_WR] = { 219 .type = UE_BULK, 220 .endpoint = UE_ADDR_ANY, 221 .direction = UE_DIR_OUT, 222 .frames = 16, 223 .bufsize = 16 * MCLBYTES, 224 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 225 .callback = axe_bulk_write_callback, 226 .timeout = 10000, /* 10 seconds */ 227 }, 228 229 [AXE_BULK_DT_RD] = { 230 .type = UE_BULK, 231 .endpoint = UE_ADDR_ANY, 232 .direction = UE_DIR_IN, 233 .bufsize = 16384, /* bytes */ 234 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 235 .callback = axe_bulk_read_callback, 236 .timeout = 0, /* no timeout */ 237 }, 238}; 239 240static const struct ax88772b_mfb ax88772b_mfb_table[] = { 241 { 0x8000, 0x8001, 2048 }, 242 { 0x8100, 0x8147, 4096}, 243 { 0x8200, 0x81EB, 6144}, 244 { 0x8300, 0x83D7, 8192}, 245 { 0x8400, 0x851E, 16384}, 246 { 0x8500, 0x8666, 20480}, 247 { 0x8600, 0x87AE, 24576}, 248 { 0x8700, 0x8A3D, 32768} 249}; 250 251static device_method_t axe_methods[] = { 252 /* Device interface */ 253 DEVMETHOD(device_probe, axe_probe), 254 DEVMETHOD(device_attach, axe_attach), 255 DEVMETHOD(device_detach, axe_detach), 256 257 /* MII interface */ 258 DEVMETHOD(miibus_readreg, axe_miibus_readreg), 259 DEVMETHOD(miibus_writereg, axe_miibus_writereg), 260 DEVMETHOD(miibus_statchg, axe_miibus_statchg), 261 262 DEVMETHOD_END 263}; 264 265static driver_t axe_driver = { 266 .name = "axe", 267 .methods = axe_methods, 268 .size = sizeof(struct axe_softc), 269}; 270 271static devclass_t axe_devclass; 272 273DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0); 274DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0); 275MODULE_DEPEND(axe, uether, 1, 1, 1); 276MODULE_DEPEND(axe, usb, 1, 1, 1); 277MODULE_DEPEND(axe, ether, 1, 1, 1); 278MODULE_DEPEND(axe, miibus, 1, 1, 1); 279MODULE_VERSION(axe, 1); 280 281static const struct usb_ether_methods axe_ue_methods = { 282 .ue_attach_post = axe_attach_post, 283 .ue_attach_post_sub = axe_attach_post_sub, 284 .ue_start = axe_start, 285 .ue_init = axe_init, 286 .ue_stop = axe_stop, 287 .ue_tick = axe_tick, 288 .ue_setmulti = axe_setmulti, 289 .ue_setpromisc = axe_setpromisc, 290 .ue_mii_upd = axe_ifmedia_upd, 291 .ue_mii_sts = axe_ifmedia_sts, 292}; 293 294static int 295axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 296{ 297 struct usb_device_request req; 298 usb_error_t err; 299 300 AXE_LOCK_ASSERT(sc, MA_OWNED); 301 302 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 303 UT_WRITE_VENDOR_DEVICE : 304 UT_READ_VENDOR_DEVICE); 305 req.bRequest = AXE_CMD_CMD(cmd); 306 USETW(req.wValue, val); 307 USETW(req.wIndex, index); 308 USETW(req.wLength, AXE_CMD_LEN(cmd)); 309 310 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); 311 312 return (err); 313} 314 315static int 316axe_miibus_readreg(device_t dev, int phy, int reg) 317{ 318 struct axe_softc *sc = device_get_softc(dev); 319 uint16_t val; 320 int locked; 321 322 locked = mtx_owned(&sc->sc_mtx); 323 if (!locked) 324 AXE_LOCK(sc); 325 326 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 327 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 328 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 329 330 val = le16toh(val); 331 if (AXE_IS_772(sc) && reg == MII_BMSR) { 332 /* 333 * BMSR of AX88772 indicates that it supports extended 334 * capability but the extended status register is 335 * revered for embedded ethernet PHY. So clear the 336 * extended capability bit of BMSR. 337 */ 338 val &= ~BMSR_EXTCAP; 339 } 340 341 if (!locked) 342 AXE_UNLOCK(sc); 343 return (val); 344} 345 346static int 347axe_miibus_writereg(device_t dev, int phy, int reg, int val) 348{ 349 struct axe_softc *sc = device_get_softc(dev); 350 int locked; 351 352 val = htole32(val); 353 locked = mtx_owned(&sc->sc_mtx); 354 if (!locked) 355 AXE_LOCK(sc); 356 357 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 358 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 359 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 360 361 if (!locked) 362 AXE_UNLOCK(sc); 363 return (0); 364} 365 366static void 367axe_miibus_statchg(device_t dev) 368{ 369 struct axe_softc *sc = device_get_softc(dev); 370 struct mii_data *mii = GET_MII(sc); 371 struct ifnet *ifp; 372 uint16_t val; 373 int err, locked; 374 375 locked = mtx_owned(&sc->sc_mtx); 376 if (!locked) 377 AXE_LOCK(sc); 378 379 ifp = uether_getifp(&sc->sc_ue); 380 if (mii == NULL || ifp == NULL || 381 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 382 goto done; 383 384 sc->sc_flags &= ~AXE_FLAG_LINK; 385 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 386 (IFM_ACTIVE | IFM_AVALID)) { 387 switch (IFM_SUBTYPE(mii->mii_media_active)) { 388 case IFM_10_T: 389 case IFM_100_TX: 390 sc->sc_flags |= AXE_FLAG_LINK; 391 break; 392 case IFM_1000_T: 393 if ((sc->sc_flags & AXE_FLAG_178) == 0) 394 break; 395 sc->sc_flags |= AXE_FLAG_LINK; 396 break; 397 default: 398 break; 399 } 400 } 401 402 /* Lost link, do nothing. */ 403 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) 404 goto done; 405 406 val = 0; 407 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 408 val |= AXE_MEDIA_FULL_DUPLEX; 409 if (AXE_IS_178_FAMILY(sc)) { 410 if ((IFM_OPTIONS(mii->mii_media_active) & 411 IFM_ETH_TXPAUSE) != 0) 412 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 413 if ((IFM_OPTIONS(mii->mii_media_active) & 414 IFM_ETH_RXPAUSE) != 0) 415 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 416 } 417 } 418 if (AXE_IS_178_FAMILY(sc)) { 419 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 420 if ((sc->sc_flags & AXE_FLAG_178) != 0) 421 val |= AXE_178_MEDIA_ENCK; 422 switch (IFM_SUBTYPE(mii->mii_media_active)) { 423 case IFM_1000_T: 424 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 425 break; 426 case IFM_100_TX: 427 val |= AXE_178_MEDIA_100TX; 428 break; 429 case IFM_10_T: 430 /* doesn't need to be handled */ 431 break; 432 } 433 } 434 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 435 if (err) 436 device_printf(dev, "media change failed, error %d\n", err); 437done: 438 if (!locked) 439 AXE_UNLOCK(sc); 440} 441 442/* 443 * Set media options. 444 */ 445static int 446axe_ifmedia_upd(struct ifnet *ifp) 447{ 448 struct axe_softc *sc = ifp->if_softc; 449 struct mii_data *mii = GET_MII(sc); 450 struct mii_softc *miisc; 451 int error; 452 453 AXE_LOCK_ASSERT(sc, MA_OWNED); 454 455 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 456 PHY_RESET(miisc); 457 error = mii_mediachg(mii); 458 return (error); 459} 460 461/* 462 * Report current media status. 463 */ 464static void 465axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 466{ 467 struct axe_softc *sc = ifp->if_softc; 468 struct mii_data *mii = GET_MII(sc); 469 470 AXE_LOCK(sc); 471 mii_pollstat(mii); 472 ifmr->ifm_active = mii->mii_media_active; 473 ifmr->ifm_status = mii->mii_media_status; 474 AXE_UNLOCK(sc); 475} 476 477static void 478axe_setmulti(struct usb_ether *ue) 479{ 480 struct axe_softc *sc = uether_getsc(ue); 481 struct ifnet *ifp = uether_getifp(ue); 482 struct ifmultiaddr *ifma; 483 uint32_t h = 0; 484 uint16_t rxmode; 485 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 486 487 AXE_LOCK_ASSERT(sc, MA_OWNED); 488 489 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 490 rxmode = le16toh(rxmode); 491 492 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 493 rxmode |= AXE_RXCMD_ALLMULTI; 494 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 495 return; 496 } 497 rxmode &= ~AXE_RXCMD_ALLMULTI; 498 499 if_maddr_rlock(ifp); 500 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 501 { 502 if (ifma->ifma_addr->sa_family != AF_LINK) 503 continue; 504 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 505 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 506 hashtbl[h / 8] |= 1 << (h % 8); 507 } 508 if_maddr_runlock(ifp); 509 510 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 511 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 512} 513 514static int 515axe_get_phyno(struct axe_softc *sc, int sel) 516{ 517 int phyno; 518 519 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 520 case PHY_TYPE_100_HOME: 521 case PHY_TYPE_GIG: 522 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 523 break; 524 case PHY_TYPE_SPECIAL: 525 /* FALLTHROUGH */ 526 case PHY_TYPE_RSVD: 527 /* FALLTHROUGH */ 528 case PHY_TYPE_NON_SUP: 529 /* FALLTHROUGH */ 530 default: 531 phyno = -1; 532 break; 533 } 534 535 return (phyno); 536} 537 538#define AXE_GPIO_WRITE(x, y) do { \ 539 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 540 uether_pause(ue, (y)); \ 541} while (0) 542 543static void 544axe_ax88178_init(struct axe_softc *sc) 545{ 546 struct usb_ether *ue; 547 int gpio0, ledmode, phymode; 548 uint16_t eeprom, val; 549 550 ue = &sc->sc_ue; 551 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 552 /* XXX magic */ 553 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 554 eeprom = le16toh(eeprom); 555 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 556 557 /* if EEPROM is invalid we have to use to GPIO0 */ 558 if (eeprom == 0xffff) { 559 phymode = AXE_PHY_MODE_MARVELL; 560 gpio0 = 1; 561 ledmode = 0; 562 } else { 563 phymode = eeprom & 0x7f; 564 gpio0 = (eeprom & 0x80) ? 0 : 1; 565 ledmode = eeprom >> 8; 566 } 567 568 if (bootverbose) 569 device_printf(sc->sc_ue.ue_dev, 570 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, 571 phymode); 572 /* Program GPIOs depending on PHY hardware. */ 573 switch (phymode) { 574 case AXE_PHY_MODE_MARVELL: 575 if (gpio0 == 1) { 576 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 577 hz / 32); 578 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 579 hz / 32); 580 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 581 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 582 hz / 32); 583 } else { 584 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 585 AXE_GPIO1_EN, hz / 3); 586 if (ledmode == 1) { 587 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 588 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 589 hz / 3); 590 } else { 591 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 592 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 593 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 594 AXE_GPIO2_EN, hz / 4); 595 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 596 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 597 } 598 } 599 break; 600 case AXE_PHY_MODE_CICADA: 601 case AXE_PHY_MODE_CICADA_V2: 602 case AXE_PHY_MODE_CICADA_V2_ASIX: 603 if (gpio0 == 1) 604 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 605 AXE_GPIO0_EN, hz / 32); 606 else 607 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 608 AXE_GPIO1_EN, hz / 32); 609 break; 610 case AXE_PHY_MODE_AGERE: 611 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 612 AXE_GPIO1_EN, hz / 32); 613 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 614 AXE_GPIO2_EN, hz / 32); 615 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 616 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 617 AXE_GPIO2_EN, hz / 32); 618 break; 619 case AXE_PHY_MODE_REALTEK_8211CL: 620 case AXE_PHY_MODE_REALTEK_8211BN: 621 case AXE_PHY_MODE_REALTEK_8251CL: 622 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 623 AXE_GPIO1 | AXE_GPIO1_EN; 624 AXE_GPIO_WRITE(val, hz / 32); 625 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 626 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 627 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 628 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 629 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 630 0x1F, 0x0005); 631 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 632 0x0C, 0x0000); 633 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 634 0x0001); 635 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 636 0x01, val | 0x0080); 637 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 638 0x1F, 0x0000); 639 } 640 break; 641 default: 642 /* Unknown PHY model or no need to program GPIOs. */ 643 break; 644 } 645 646 /* soft reset */ 647 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 648 uether_pause(ue, hz / 4); 649 650 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 651 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 652 uether_pause(ue, hz / 4); 653 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 654 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 655 uether_pause(ue, hz / 4); 656 657 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 658} 659 660static void 661axe_ax88772_init(struct axe_softc *sc) 662{ 663 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 664 uether_pause(&sc->sc_ue, hz / 16); 665 666 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 667 /* ask for the embedded PHY */ 668 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 669 uether_pause(&sc->sc_ue, hz / 64); 670 671 /* power down and reset state, pin reset state */ 672 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 673 AXE_SW_RESET_CLEAR, NULL); 674 uether_pause(&sc->sc_ue, hz / 16); 675 676 /* power down/reset state, pin operating state */ 677 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 678 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 679 uether_pause(&sc->sc_ue, hz / 4); 680 681 /* power up, reset */ 682 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 683 684 /* power up, operating */ 685 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 686 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 687 } else { 688 /* ask for external PHY */ 689 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 690 uether_pause(&sc->sc_ue, hz / 64); 691 692 /* power down internal PHY */ 693 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 694 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 695 } 696 697 uether_pause(&sc->sc_ue, hz / 4); 698 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 699} 700 701static void 702axe_ax88772_phywake(struct axe_softc *sc) 703{ 704 struct usb_ether *ue; 705 706 ue = &sc->sc_ue; 707 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 708 /* Manually select internal(embedded) PHY - MAC mode. */ 709 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 710 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, 711 NULL); 712 uether_pause(&sc->sc_ue, hz / 32); 713 } else { 714 /* 715 * Manually select external PHY - MAC mode. 716 * Reverse MII/RMII is for AX88772A PHY mode. 717 */ 718 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 719 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 720 uether_pause(&sc->sc_ue, hz / 32); 721 } 722 /* Take PHY out of power down. */ 723 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 724 AXE_SW_RESET_IPRL, NULL); 725 uether_pause(&sc->sc_ue, hz / 4); 726 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 727 uether_pause(&sc->sc_ue, hz); 728 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 729 uether_pause(&sc->sc_ue, hz / 32); 730 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 731 uether_pause(&sc->sc_ue, hz / 32); 732} 733 734static void 735axe_ax88772a_init(struct axe_softc *sc) 736{ 737 struct usb_ether *ue; 738 739 ue = &sc->sc_ue; 740 /* Reload EEPROM. */ 741 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 742 axe_ax88772_phywake(sc); 743 /* Stop MAC. */ 744 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 745} 746 747static void 748axe_ax88772b_init(struct axe_softc *sc) 749{ 750 struct usb_ether *ue; 751 uint16_t eeprom; 752 uint8_t *eaddr; 753 int i; 754 755 ue = &sc->sc_ue; 756 /* Reload EEPROM. */ 757 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 758 /* 759 * Save PHY power saving configuration(high byte) and 760 * clear EEPROM checksum value(low byte). 761 */ 762 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); 763 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 764 765 /* 766 * Auto-loaded default station address from internal ROM is 767 * 00:00:00:00:00:00 such that an explicit access to EEPROM 768 * is required to get real station address. 769 */ 770 eaddr = ue->ue_eaddr; 771 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 772 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, 773 &eeprom); 774 eeprom = le16toh(eeprom); 775 *eaddr++ = (uint8_t)(eeprom & 0xFF); 776 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 777 } 778 /* Wakeup PHY. */ 779 axe_ax88772_phywake(sc); 780 /* Stop MAC. */ 781 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 782} 783 784#undef AXE_GPIO_WRITE 785 786static void 787axe_reset(struct axe_softc *sc) 788{ 789 struct usb_config_descriptor *cd; 790 usb_error_t err; 791 792 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 793 794 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 795 cd->bConfigurationValue); 796 if (err) 797 DPRINTF("reset failed (ignored)\n"); 798 799 /* Wait a little while for the chip to get its brains in order. */ 800 uether_pause(&sc->sc_ue, hz / 100); 801 802 /* Reinitialize controller to achieve full reset. */ 803 if (sc->sc_flags & AXE_FLAG_178) 804 axe_ax88178_init(sc); 805 else if (sc->sc_flags & AXE_FLAG_772) 806 axe_ax88772_init(sc); 807 else if (sc->sc_flags & AXE_FLAG_772A) 808 axe_ax88772a_init(sc); 809 else if (sc->sc_flags & AXE_FLAG_772B) 810 axe_ax88772b_init(sc); 811} 812 813static void 814axe_attach_post(struct usb_ether *ue) 815{ 816 struct axe_softc *sc = uether_getsc(ue); 817 818 /* 819 * Load PHY indexes first. Needed by axe_xxx_init(). 820 */ 821 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 822 if (bootverbose) 823 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", 824 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); 825 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 826 if (sc->sc_phyno == -1) 827 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 828 if (sc->sc_phyno == -1) { 829 device_printf(sc->sc_ue.ue_dev, 830 "no valid PHY address found, assuming PHY address 0\n"); 831 sc->sc_phyno = 0; 832 } 833 834 /* Initialize controller and get station address. */ 835 if (sc->sc_flags & AXE_FLAG_178) { 836 axe_ax88178_init(sc); 837 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 838 } else if (sc->sc_flags & AXE_FLAG_772) { 839 axe_ax88772_init(sc); 840 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 841 } else if (sc->sc_flags & AXE_FLAG_772A) { 842 axe_ax88772a_init(sc); 843 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 844 } else if (sc->sc_flags & AXE_FLAG_772B) { 845 axe_ax88772b_init(sc); 846 } else 847 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 848 849 /* 850 * Fetch IPG values. 851 */ 852 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) { 853 /* Set IPG values. */ 854 sc->sc_ipgs[0] = 0x15; 855 sc->sc_ipgs[1] = 0x16; 856 sc->sc_ipgs[2] = 0x1A; 857 } else 858 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 859} 860 861static int 862axe_attach_post_sub(struct usb_ether *ue) 863{ 864 struct axe_softc *sc; 865 struct ifnet *ifp; 866 u_int adv_pause; 867 int error; 868 869 sc = uether_getsc(ue); 870 ifp = ue->ue_ifp; 871 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 872 ifp->if_start = uether_start; 873 ifp->if_ioctl = axe_ioctl; 874 ifp->if_init = uether_init; 875 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 876 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 877 IFQ_SET_READY(&ifp->if_snd); 878 879 if (AXE_IS_178_FAMILY(sc)) 880 ifp->if_capabilities |= IFCAP_VLAN_MTU; 881 if (sc->sc_flags & AXE_FLAG_772B) { 882 ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM; 883 ifp->if_hwassist = AXE_CSUM_FEATURES; 884 /* 885 * Checksum offloading of AX88772B also works with VLAN 886 * tagged frames but there is no way to take advantage 887 * of the feature because vlan(4) assumes 888 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 889 * support checksum offloading with VLAN. VLAN hardware 890 * tagging support of AX88772B is very limited so it's 891 * not possible to announce IFCAP_VLAN_HWTAGGING. 892 */ 893 } 894 ifp->if_capenable = ifp->if_capabilities; 895 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178)) 896 adv_pause = MIIF_DOPAUSE; 897 else 898 adv_pause = 0; 899 mtx_lock(&Giant); 900 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 901 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 902 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause); 903 mtx_unlock(&Giant); 904 905 return (error); 906} 907 908/* 909 * Probe for a AX88172 chip. 910 */ 911static int 912axe_probe(device_t dev) 913{ 914 struct usb_attach_arg *uaa = device_get_ivars(dev); 915 916 if (uaa->usb_mode != USB_MODE_HOST) 917 return (ENXIO); 918 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 919 return (ENXIO); 920 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 921 return (ENXIO); 922 923 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 924} 925 926/* 927 * Attach the interface. Allocate softc structures, do ifmedia 928 * setup and ethernet/BPF attach. 929 */ 930static int 931axe_attach(device_t dev) 932{ 933 struct usb_attach_arg *uaa = device_get_ivars(dev); 934 struct axe_softc *sc = device_get_softc(dev); 935 struct usb_ether *ue = &sc->sc_ue; 936 uint8_t iface_index; 937 int error; 938 939 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 940 941 device_set_usb_desc(dev); 942 943 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 944 945 iface_index = AXE_IFACE_IDX; 946 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 947 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 948 if (error) { 949 device_printf(dev, "allocating USB transfers failed\n"); 950 goto detach; 951 } 952 953 ue->ue_sc = sc; 954 ue->ue_dev = dev; 955 ue->ue_udev = uaa->device; 956 ue->ue_mtx = &sc->sc_mtx; 957 ue->ue_methods = &axe_ue_methods; 958 959 error = uether_ifattach(ue); 960 if (error) { 961 device_printf(dev, "could not attach interface\n"); 962 goto detach; 963 } 964 return (0); /* success */ 965 966detach: 967 axe_detach(dev); 968 return (ENXIO); /* failure */ 969} 970 971static int 972axe_detach(device_t dev) 973{ 974 struct axe_softc *sc = device_get_softc(dev); 975 struct usb_ether *ue = &sc->sc_ue; 976 977 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 978 uether_ifdetach(ue); 979 mtx_destroy(&sc->sc_mtx); 980 981 return (0); 982} 983 984#if (AXE_BULK_BUF_SIZE >= 0x10000) 985#error "Please update axe_bulk_read_callback()!" 986#endif 987 988static void 989axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 990{ 991 struct axe_softc *sc = usbd_xfer_softc(xfer); 992 struct usb_ether *ue = &sc->sc_ue; 993 struct usb_page_cache *pc; 994 int actlen; 995 996 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 997 998 switch (USB_GET_STATE(xfer)) { 999 case USB_ST_TRANSFERRED: 1000 pc = usbd_xfer_get_frame(xfer, 0); 1001 axe_rx_frame(ue, pc, actlen); 1002 1003 /* FALLTHROUGH */ 1004 case USB_ST_SETUP: 1005tr_setup: 1006 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 1007 usbd_transfer_submit(xfer); 1008 uether_rxflush(ue); 1009 return; 1010 1011 default: /* Error */ 1012 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 1013 1014 if (error != USB_ERR_CANCELLED) { 1015 /* try to clear stall first */ 1016 usbd_xfer_set_stall(xfer); 1017 goto tr_setup; 1018 } 1019 return; 1020 1021 } 1022} 1023 1024static int 1025axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 1026{ 1027 struct axe_softc *sc; 1028 struct axe_sframe_hdr hdr; 1029 struct axe_csum_hdr csum_hdr; 1030 int error, len, pos; 1031 1032 sc = uether_getsc(ue); 1033 pos = 0; 1034 len = 0; 1035 error = 0; 1036 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) { 1037 while (pos < actlen) { 1038 if ((int)(pos + sizeof(hdr)) > actlen) { 1039 /* too little data */ 1040 error = EINVAL; 1041 break; 1042 } 1043 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 1044 1045 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) { 1046 /* we lost sync */ 1047 error = EINVAL; 1048 break; 1049 } 1050 pos += sizeof(hdr); 1051 len = le16toh(hdr.len); 1052 if (pos + len > actlen) { 1053 /* invalid length */ 1054 error = EINVAL; 1055 break; 1056 } 1057 axe_rxeof(ue, pc, pos, len, NULL); 1058 pos += len + (len % 2); 1059 } 1060 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) { 1061 while (pos < actlen) { 1062 if ((int)(pos + sizeof(csum_hdr)) > actlen) { 1063 /* too little data */ 1064 error = EINVAL; 1065 break; 1066 } 1067 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr)); 1068 1069 csum_hdr.len = le16toh(csum_hdr.len); 1070 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1071 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1072 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1073 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1074 sc->sc_lenmask) { 1075 /* we lost sync */ 1076 error = EINVAL; 1077 break; 1078 } 1079 /* 1080 * Get total transferred frame length including 1081 * checksum header. The length should be multiple 1082 * of 4. 1083 */ 1084 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len); 1085 len = (len + 3) & ~3; 1086 if (pos + len > actlen) { 1087 /* invalid length */ 1088 error = EINVAL; 1089 break; 1090 } 1091 axe_rxeof(ue, pc, pos + sizeof(csum_hdr), 1092 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr); 1093 pos += len; 1094 } 1095 } else 1096 axe_rxeof(ue, pc, 0, actlen, NULL); 1097 1098 if (error != 0) 1099 ue->ue_ifp->if_ierrors++; 1100 return (error); 1101} 1102 1103static int 1104axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, 1105 unsigned int len, struct axe_csum_hdr *csum_hdr) 1106{ 1107 struct ifnet *ifp = ue->ue_ifp; 1108 struct mbuf *m; 1109 1110 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 1111 ifp->if_ierrors++; 1112 return (EINVAL); 1113 } 1114 1115 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1116 if (m == NULL) { 1117 ifp->if_iqdrops++; 1118 return (ENOMEM); 1119 } 1120 m->m_len = m->m_pkthdr.len = MCLBYTES; 1121 m_adj(m, ETHER_ALIGN); 1122 1123 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 1124 1125 ifp->if_ipackets++; 1126 m->m_pkthdr.rcvif = ifp; 1127 m->m_pkthdr.len = m->m_len = len; 1128 1129 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1130 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR | 1131 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) { 1132 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1133 CSUM_IP_VALID; 1134 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1135 AXE_CSUM_HDR_L4_TYPE_TCP || 1136 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1137 AXE_CSUM_HDR_L4_TYPE_UDP) { 1138 m->m_pkthdr.csum_flags |= 1139 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1140 m->m_pkthdr.csum_data = 0xffff; 1141 } 1142 } 1143 } 1144 1145 _IF_ENQUEUE(&ue->ue_rxq, m); 1146 return (0); 1147} 1148 1149#if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 1150#error "Please update axe_bulk_write_callback()!" 1151#endif 1152 1153static void 1154axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 1155{ 1156 struct axe_softc *sc = usbd_xfer_softc(xfer); 1157 struct axe_sframe_hdr hdr; 1158 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 1159 struct usb_page_cache *pc; 1160 struct mbuf *m; 1161 int nframes, pos; 1162 1163 switch (USB_GET_STATE(xfer)) { 1164 case USB_ST_TRANSFERRED: 1165 DPRINTFN(11, "transfer complete\n"); 1166 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1167 /* FALLTHROUGH */ 1168 case USB_ST_SETUP: 1169tr_setup: 1170 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || 1171 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 1172 /* 1173 * Don't send anything if there is no link or 1174 * controller is busy. 1175 */ 1176 return; 1177 } 1178 1179 for (nframes = 0; nframes < 16 && 1180 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 1181 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1182 if (m == NULL) 1183 break; 1184 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 1185 nframes); 1186 pos = 0; 1187 pc = usbd_xfer_get_frame(xfer, nframes); 1188 if (AXE_IS_178_FAMILY(sc)) { 1189 hdr.len = htole16(m->m_pkthdr.len); 1190 hdr.ilen = ~hdr.len; 1191 /* 1192 * If upper stack computed checksum, driver 1193 * should tell controller not to insert 1194 * computed checksum for checksum offloading 1195 * enabled controller. 1196 */ 1197 if (ifp->if_capabilities & IFCAP_TXCSUM) { 1198 if ((m->m_pkthdr.csum_flags & 1199 AXE_CSUM_FEATURES) != 0) 1200 hdr.len |= htole16( 1201 AXE_TX_CSUM_PSEUDO_HDR); 1202 else 1203 hdr.len |= htole16( 1204 AXE_TX_CSUM_DIS); 1205 } 1206 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 1207 pos += sizeof(hdr); 1208 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1209 pos += m->m_pkthdr.len; 1210 if ((pos % 512) == 0) { 1211 hdr.len = 0; 1212 hdr.ilen = 0xffff; 1213 usbd_copy_in(pc, pos, &hdr, 1214 sizeof(hdr)); 1215 pos += sizeof(hdr); 1216 } 1217 } else { 1218 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1219 pos += m->m_pkthdr.len; 1220 } 1221 1222 /* 1223 * XXX 1224 * Update TX packet counter here. This is not 1225 * correct way but it seems that there is no way 1226 * to know how many packets are sent at the end 1227 * of transfer because controller combines 1228 * multiple writes into single one if there is 1229 * room in TX buffer of controller. 1230 */ 1231 ifp->if_opackets++; 1232 1233 /* 1234 * if there's a BPF listener, bounce a copy 1235 * of this frame to him: 1236 */ 1237 BPF_MTAP(ifp, m); 1238 1239 m_freem(m); 1240 1241 /* Set frame length. */ 1242 usbd_xfer_set_frame_len(xfer, nframes, pos); 1243 } 1244 if (nframes != 0) { 1245 usbd_xfer_set_frames(xfer, nframes); 1246 usbd_transfer_submit(xfer); 1247 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1248 } 1249 return; 1250 /* NOTREACHED */ 1251 default: /* Error */ 1252 DPRINTFN(11, "transfer error, %s\n", 1253 usbd_errstr(error)); 1254 1255 ifp->if_oerrors++; 1256 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1257 1258 if (error != USB_ERR_CANCELLED) { 1259 /* try to clear stall first */ 1260 usbd_xfer_set_stall(xfer); 1261 goto tr_setup; 1262 } 1263 return; 1264 1265 } 1266} 1267 1268static void 1269axe_tick(struct usb_ether *ue) 1270{ 1271 struct axe_softc *sc = uether_getsc(ue); 1272 struct mii_data *mii = GET_MII(sc); 1273 1274 AXE_LOCK_ASSERT(sc, MA_OWNED); 1275 1276 mii_tick(mii); 1277 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 1278 axe_miibus_statchg(ue->ue_dev); 1279 if ((sc->sc_flags & AXE_FLAG_LINK) != 0) 1280 axe_start(ue); 1281 } 1282} 1283 1284static void 1285axe_start(struct usb_ether *ue) 1286{ 1287 struct axe_softc *sc = uether_getsc(ue); 1288 1289 /* 1290 * start the USB transfers, if not already started: 1291 */ 1292 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 1293 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 1294} 1295 1296static void 1297axe_csum_cfg(struct usb_ether *ue) 1298{ 1299 struct axe_softc *sc; 1300 struct ifnet *ifp; 1301 uint16_t csum1, csum2; 1302 1303 sc = uether_getsc(ue); 1304 AXE_LOCK_ASSERT(sc, MA_OWNED); 1305 1306 if ((sc->sc_flags & AXE_FLAG_772B) != 0) { 1307 ifp = uether_getifp(ue); 1308 csum1 = 0; 1309 csum2 = 0; 1310 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1311 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP | 1312 AXE_TXCSUM_UDP; 1313 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1314 csum1 = 0; 1315 csum2 = 0; 1316 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1317 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE | 1318 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP | 1319 AXE_RXCSUM_IGMP; 1320 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1321 } 1322} 1323 1324static void 1325axe_init(struct usb_ether *ue) 1326{ 1327 struct axe_softc *sc = uether_getsc(ue); 1328 struct ifnet *ifp = uether_getifp(ue); 1329 uint16_t rxmode; 1330 1331 AXE_LOCK_ASSERT(sc, MA_OWNED); 1332 1333 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1334 return; 1335 1336 /* Cancel pending I/O */ 1337 axe_stop(ue); 1338 1339 axe_reset(sc); 1340 1341 /* Set MAC address and transmitter IPG values. */ 1342 if (AXE_IS_178_FAMILY(sc)) { 1343 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1344 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1345 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1346 } else { 1347 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1348 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1349 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1350 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1351 } 1352 1353 if (AXE_IS_178_FAMILY(sc)) { 1354 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME); 1355 if ((sc->sc_flags & AXE_FLAG_772B) != 0 && 1356 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1357 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1358 sc->sc_flags |= AXE_FLAG_CSUM_FRAME; 1359 } else { 1360 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1361 sc->sc_flags |= AXE_FLAG_STD_FRAME; 1362 } 1363 } 1364 1365 /* Configure TX/RX checksum offloading. */ 1366 axe_csum_cfg(ue); 1367 1368 if (sc->sc_flags & AXE_FLAG_772B) { 1369 /* AX88772B uses different maximum frame burst configuration. */ 1370 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1371 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1372 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1373 } 1374 1375 /* Enable receiver, set RX mode. */ 1376 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1377 if (AXE_IS_178_FAMILY(sc)) { 1378 if (sc->sc_flags & AXE_FLAG_772B) { 1379 /* 1380 * Select RX header format type 1. Aligning IP 1381 * header on 4 byte boundary is not needed when 1382 * checksum offloading feature is not used 1383 * because we always copy the received frame in 1384 * RX handler. When RX checksum offloading is 1385 * active, aligning IP header is required to 1386 * reflect actual frame length including RX 1387 * header size. 1388 */ 1389 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1390 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1391 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1392 } else { 1393 /* 1394 * Default Rx buffer size is too small to get 1395 * maximum performance. 1396 */ 1397 rxmode |= AXE_178_RXCMD_MFB_16384; 1398 } 1399 } else { 1400 rxmode |= AXE_172_RXCMD_UNICAST; 1401 } 1402 1403 /* If we want promiscuous mode, set the allframes bit. */ 1404 if (ifp->if_flags & IFF_PROMISC) 1405 rxmode |= AXE_RXCMD_PROMISC; 1406 1407 if (ifp->if_flags & IFF_BROADCAST) 1408 rxmode |= AXE_RXCMD_BROADCAST; 1409 1410 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1411 1412 /* Load the multicast filter. */ 1413 axe_setmulti(ue); 1414 1415 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1416 1417 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1418 /* Switch to selected media. */ 1419 axe_ifmedia_upd(ifp); 1420} 1421 1422static void 1423axe_setpromisc(struct usb_ether *ue) 1424{ 1425 struct axe_softc *sc = uether_getsc(ue); 1426 struct ifnet *ifp = uether_getifp(ue); 1427 uint16_t rxmode; 1428 1429 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1430 1431 rxmode = le16toh(rxmode); 1432 1433 if (ifp->if_flags & IFF_PROMISC) { 1434 rxmode |= AXE_RXCMD_PROMISC; 1435 } else { 1436 rxmode &= ~AXE_RXCMD_PROMISC; 1437 } 1438 1439 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1440 1441 axe_setmulti(ue); 1442} 1443 1444static void 1445axe_stop(struct usb_ether *ue) 1446{ 1447 struct axe_softc *sc = uether_getsc(ue); 1448 struct ifnet *ifp = uether_getifp(ue); 1449 1450 AXE_LOCK_ASSERT(sc, MA_OWNED); 1451 1452 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1453 sc->sc_flags &= ~AXE_FLAG_LINK; 1454 1455 /* 1456 * stop all the transfers, if not already stopped: 1457 */ 1458 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1459 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1460} 1461 1462static int 1463axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1464{ 1465 struct usb_ether *ue = ifp->if_softc; 1466 struct axe_softc *sc; 1467 struct ifreq *ifr; 1468 int error, mask, reinit; 1469 1470 sc = uether_getsc(ue); 1471 ifr = (struct ifreq *)data; 1472 error = 0; 1473 reinit = 0; 1474 if (cmd == SIOCSIFCAP) { 1475 AXE_LOCK(sc); 1476 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1477 if ((mask & IFCAP_TXCSUM) != 0 && 1478 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1479 ifp->if_capenable ^= IFCAP_TXCSUM; 1480 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1481 ifp->if_hwassist |= AXE_CSUM_FEATURES; 1482 else 1483 ifp->if_hwassist &= ~AXE_CSUM_FEATURES; 1484 reinit++; 1485 } 1486 if ((mask & IFCAP_RXCSUM) != 0 && 1487 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1488 ifp->if_capenable ^= IFCAP_RXCSUM; 1489 reinit++; 1490 } 1491 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 1492 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1493 else 1494 reinit = 0; 1495 AXE_UNLOCK(sc); 1496 if (reinit > 0) 1497 uether_init(ue); 1498 } else 1499 error = uether_ioctl(ifp, cmd, data); 1500 1501 return (error); 1502} 1503