1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187611Ssam * $FreeBSD$ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25185377Ssam#include "ar5212/ar5212.h" 26185377Ssam#include "ar5212/ar5212reg.h" 27185377Ssam#include "ar5212/ar5212phy.h" 28185377Ssam 29185377Ssam#include "ah_eeprom_v3.h" 30185377Ssam 31185377Ssam/* Additional Time delay to wait after activiting the Base band */ 32185377Ssam#define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 33185377Ssam#define PLL_SETTLE_DELAY 300 /* 300 usec */ 34185377Ssam 35185377Ssamstatic HAL_BOOL ar5212SetResetReg(struct ath_hal *, uint32_t resetMask); 36185377Ssam/* NB: public for 5312 use */ 37187831SsamHAL_BOOL ar5212IsSpurChannel(struct ath_hal *, 38187831Ssam const struct ieee80211_channel *); 39187831SsamHAL_BOOL ar5212ChannelChange(struct ath_hal *, 40187831Ssam const struct ieee80211_channel *); 41187831Ssamint16_t ar5212GetNf(struct ath_hal *, struct ieee80211_channel *); 42187831SsamHAL_BOOL ar5212SetBoardValues(struct ath_hal *, 43187831Ssam const struct ieee80211_channel *); 44187831Ssamvoid ar5212SetDeltaSlope(struct ath_hal *, 45187831Ssam const struct ieee80211_channel *); 46185377SsamHAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah, 47187831Ssam const struct ieee80211_channel *chan, uint16_t *rfXpdGain); 48185377Ssamstatic HAL_BOOL ar5212SetRateTable(struct ath_hal *, 49187831Ssam const struct ieee80211_channel *, int16_t tpcScaleReduction, 50187831Ssam int16_t powerLimit, 51185380Ssam HAL_BOOL commit, int16_t *minPower, int16_t *maxPower); 52185377Ssamstatic void ar5212CorrectGainDelta(struct ath_hal *, int twiceOfdmCckDelta); 53187831Ssamstatic void ar5212GetTargetPowers(struct ath_hal *, 54187831Ssam const struct ieee80211_channel *, 55185380Ssam const TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels, 56185380Ssam TRGT_POWER_INFO *pNewPower); 57185377Ssamstatic uint16_t ar5212GetMaxEdgePower(uint16_t channel, 58185380Ssam const RD_EDGES_POWER *pRdEdgesPower); 59187831Ssamvoid ar5212SetRateDurationTable(struct ath_hal *, 60187831Ssam const struct ieee80211_channel *); 61187831Ssamvoid ar5212SetIFSTiming(struct ath_hal *, 62187831Ssam const struct ieee80211_channel *); 63185377Ssam 64185377Ssam/* NB: public for RF backend use */ 65185380Ssamvoid ar5212GetLowerUpperValues(uint16_t value, 66185380Ssam uint16_t *pList, uint16_t listSize, 67185380Ssam uint16_t *pLowerValue, uint16_t *pUpperValue); 68185380Ssamvoid ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, 69185380Ssam uint32_t numBits, uint32_t firstBit, uint32_t column); 70185377Ssam 71185377Ssamstatic int 72185377Ssamwrite_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 73185377Ssam HAL_BOOL bChannelChange, int writes) 74185377Ssam{ 75185377Ssam#define IS_NO_RESET_TIMER_ADDR(x) \ 76185377Ssam ( (((x) >= AR_BEACON) && ((x) <= AR_CFP_DUR)) || \ 77185377Ssam (((x) >= AR_SLEEP1) && ((x) <= AR_SLEEP3))) 78185377Ssam#define V(r, c) (ia)->data[((r)*(ia)->cols) + (c)] 79185377Ssam int r; 80185377Ssam 81185377Ssam /* Write Common Array Parameters */ 82185377Ssam for (r = 0; r < ia->rows; r++) { 83185377Ssam uint32_t reg = V(r, 0); 84185377Ssam /* XXX timer/beacon setup registers? */ 85185377Ssam /* On channel change, don't reset the PCU registers */ 86185377Ssam if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) { 87185377Ssam OS_REG_WRITE(ah, reg, V(r, 1)); 88185377Ssam DMA_YIELD(writes); 89185377Ssam } 90185377Ssam } 91185377Ssam return writes; 92185377Ssam#undef IS_NO_RESET_TIMER_ADDR 93185377Ssam#undef V 94185377Ssam} 95185377Ssam 96185377Ssam#define IS_DISABLE_FAST_ADC_CHAN(x) (((x) == 2462) || ((x) == 2467)) 97185377Ssam 98185377Ssam/* 99226489Sadrian * XXX NDIS 5.x code had MAX_RESET_WAIT set to 2000 for AP code 100226489Sadrian * and 10 for Client code 101226489Sadrian */ 102226489Sadrian#define MAX_RESET_WAIT 10 103226489Sadrian 104226489Sadrian#define TX_QUEUEPEND_CHECK 1 105226489Sadrian#define TX_ENABLE_CHECK 2 106226489Sadrian#define RX_ENABLE_CHECK 4 107226489Sadrian 108226489Sadrian/* 109185377Ssam * Places the device in and out of reset and then places sane 110185377Ssam * values in the registers based on EEPROM config, initialization 111185377Ssam * vectors (as determined by the mode), and station configuration 112185377Ssam * 113185377Ssam * bChannelChange is used to preserve DMA/PCU registers across 114185377Ssam * a HW Reset during channel change. 115185377Ssam */ 116185377SsamHAL_BOOL 117185377Ssamar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 118187831Ssam struct ieee80211_channel *chan, 119187831Ssam HAL_BOOL bChannelChange, HAL_STATUS *status) 120185377Ssam{ 121185377Ssam#define N(a) (sizeof (a) / sizeof (a[0])) 122185377Ssam#define FAIL(_code) do { ecode = _code; goto bad; } while (0) 123185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 124185377Ssam HAL_CHANNEL_INTERNAL *ichan = AH_NULL; 125185377Ssam const HAL_EEPROM *ee; 126185377Ssam uint32_t softLedCfg, softLedState; 127185377Ssam uint32_t saveFrameSeqCount, saveDefAntenna, saveLedState; 128185377Ssam uint32_t macStaId1, synthDelay, txFrm2TxDStart; 129185377Ssam uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 130185377Ssam int16_t cckOfdmPwrDelta = 0; 131185377Ssam u_int modesIndex, freqIndex; 132185377Ssam HAL_STATUS ecode; 133185377Ssam int i, regWrites; 134185377Ssam uint32_t testReg, powerVal; 135185377Ssam int8_t twiceAntennaGain, twiceAntennaReduction; 136185377Ssam uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow; 137185377Ssam HAL_BOOL isBmode = AH_FALSE; 138185377Ssam 139185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 140185377Ssam ee = AH_PRIVATE(ah)->ah_eeprom; 141185377Ssam 142185377Ssam OS_MARK(ah, AH_MARK_RESET, bChannelChange); 143185377Ssam 144185377Ssam /* Bring out of sleep mode */ 145185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 146185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n", 147185377Ssam __func__); 148185377Ssam FAIL(HAL_EIO); 149185377Ssam } 150185377Ssam 151185377Ssam /* 152185377Ssam * Map public channel to private. 153185377Ssam */ 154185377Ssam ichan = ath_hal_checkchannel(ah, chan); 155187831Ssam if (ichan == AH_NULL) 156185377Ssam FAIL(HAL_EINVAL); 157185377Ssam switch (opmode) { 158185377Ssam case HAL_M_STA: 159185377Ssam case HAL_M_IBSS: 160185377Ssam case HAL_M_HOSTAP: 161185377Ssam case HAL_M_MONITOR: 162185377Ssam break; 163185377Ssam default: 164185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", 165185377Ssam __func__, opmode); 166185377Ssam FAIL(HAL_EINVAL); 167185377Ssam break; 168185377Ssam } 169185377Ssam HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3); 170185377Ssam 171185377Ssam SAVE_CCK(ah, chan, isBmode); 172185377Ssam 173185377Ssam /* Preserve certain DMA hardware registers on a channel change */ 174185377Ssam if (bChannelChange) { 175185377Ssam /* 176185377Ssam * On Venice, the TSF is almost preserved across a reset; 177185377Ssam * it requires doubling writes to the RESET_TSF 178185377Ssam * bit in the AR_BEACON register; it also has the quirk 179185377Ssam * of the TSF going back in time on the station (station 180185377Ssam * latches onto the last beacon's tsf during a reset 50% 181185377Ssam * of the times); the latter is not a problem for adhoc 182185377Ssam * stations since as long as the TSF is behind, it will 183185377Ssam * get resynchronized on receiving the next beacon; the 184185377Ssam * TSF going backwards in time could be a problem for the 185185377Ssam * sleep operation (supported on infrastructure stations 186185377Ssam * only) - the best and most general fix for this situation 187185377Ssam * is to resynchronize the various sleep/beacon timers on 188185377Ssam * the receipt of the next beacon i.e. when the TSF itself 189185377Ssam * gets resynchronized to the AP's TSF - power save is 190185377Ssam * needed to be temporarily disabled until that time 191185377Ssam * 192185377Ssam * Need to save the sequence number to restore it after 193185377Ssam * the reset! 194185377Ssam */ 195185377Ssam saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM); 196185377Ssam } else 197185377Ssam saveFrameSeqCount = 0; /* NB: silence compiler */ 198234774Sadrian 199234774Sadrian /* Blank the channel survey statistics */ 200234774Sadrian OS_MEMZERO(&ahp->ah_chansurvey, sizeof(ahp->ah_chansurvey)); 201185377Ssam#if 0 202185377Ssam /* 203185377Ssam * XXX disable for now; this appears to sometimes cause OFDM 204185377Ssam * XXX timing error floods when ani is enabled and bg scanning 205185377Ssam * XXX kicks in 206185377Ssam */ 207185377Ssam /* If the channel change is across the same mode - perform a fast channel change */ 208185377Ssam if (IS_2413(ah) || IS_5413(ah)) { 209185377Ssam /* 210185377Ssam * Fast channel change can only be used when: 211185377Ssam * -channel change requested - so it's not the initial reset. 212185377Ssam * -it's not a change to the current channel - 213185377Ssam * often called when switching modes on a channel 214185377Ssam * -the modes of the previous and requested channel are the 215185377Ssam * same 216185377Ssam * XXX opmode shouldn't change either? 217185377Ssam */ 218185377Ssam if (bChannelChange && 219185377Ssam (AH_PRIVATE(ah)->ah_curchan != AH_NULL) && 220187831Ssam (chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) && 221187831Ssam ((chan->ic_flags & IEEE80211_CHAN_ALLTURBO) == 222187831Ssam (AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) { 223185377Ssam if (ar5212ChannelChange(ah, chan)) { 224185377Ssam /* If ChannelChange completed - skip the rest of reset */ 225185377Ssam /* XXX ani? */ 226187831Ssam goto done; 227185377Ssam } 228185377Ssam } 229185377Ssam } 230185377Ssam#endif 231185377Ssam /* 232185377Ssam * Preserve the antenna on a channel change 233185377Ssam */ 234185377Ssam saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); 235185377Ssam if (saveDefAntenna == 0) /* XXX magic constants */ 236185377Ssam saveDefAntenna = 1; 237185377Ssam 238185377Ssam /* Save hardware flag before chip reset clears the register */ 239185377Ssam macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 240185377Ssam (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT); 241185377Ssam 242185377Ssam /* Save led state from pci config register */ 243185377Ssam saveLedState = OS_REG_READ(ah, AR_PCICFG) & 244185377Ssam (AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK | 245185377Ssam AR_PCICFG_LEDSLOW); 246185377Ssam softLedCfg = OS_REG_READ(ah, AR_GPIOCR); 247185377Ssam softLedState = OS_REG_READ(ah, AR_GPIODO); 248185377Ssam 249185377Ssam ar5212RestoreClock(ah, opmode); /* move to refclk operation */ 250185377Ssam 251185377Ssam /* 252185377Ssam * Adjust gain parameters before reset if 253185377Ssam * there's an outstanding gain updated. 254185377Ssam */ 255185377Ssam (void) ar5212GetRfgain(ah); 256185377Ssam 257185377Ssam if (!ar5212ChipReset(ah, chan)) { 258185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 259185377Ssam FAIL(HAL_EIO); 260185377Ssam } 261185377Ssam 262185377Ssam /* Setup the indices for the next set of register array writes */ 263187831Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 264187831Ssam freqIndex = 2; 265187831Ssam if (IEEE80211_IS_CHAN_108G(chan)) 266187831Ssam modesIndex = 5; 267187831Ssam else if (IEEE80211_IS_CHAN_G(chan)) 268187831Ssam modesIndex = 4; 269187831Ssam else if (IEEE80211_IS_CHAN_B(chan)) 270187831Ssam modesIndex = 3; 271187831Ssam else { 272187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 273187831Ssam "%s: invalid channel %u/0x%x\n", 274187831Ssam __func__, chan->ic_freq, chan->ic_flags); 275187831Ssam FAIL(HAL_EINVAL); 276187831Ssam } 277187831Ssam } else { 278185377Ssam freqIndex = 1; 279187831Ssam if (IEEE80211_IS_CHAN_TURBO(chan)) 280187831Ssam modesIndex = 2; 281187831Ssam else if (IEEE80211_IS_CHAN_A(chan)) 282187831Ssam modesIndex = 1; 283187831Ssam else { 284187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 285187831Ssam "%s: invalid channel %u/0x%x\n", 286187831Ssam __func__, chan->ic_freq, chan->ic_flags); 287187831Ssam FAIL(HAL_EINVAL); 288187831Ssam } 289185377Ssam } 290185377Ssam 291185377Ssam OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 292185377Ssam 293185377Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 294185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 295185377Ssam 296185377Ssam regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0); 297185377Ssam regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange, 298185377Ssam regWrites); 299207472Simp#ifdef AH_RXCFG_SDMAMW_4BYTES 300207472Simp /* 301207472Simp * Nala doesn't work with 128 byte bursts on pb42(hydra) (ar71xx), 302207472Simp * use 4 instead. Enabling it on all platforms would hurt performance, 303207472Simp * so we only enable it on the ones that are affected by it. 304207472Simp */ 305207472Simp OS_REG_WRITE(ah, AR_RXCFG, 0); 306207472Simp#endif 307185377Ssam ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 308185377Ssam 309185377Ssam OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 310185377Ssam 311187831Ssam if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan)) { 312185377Ssam ar5212SetIFSTiming(ah, chan); 313185377Ssam if (IS_5413(ah)) { 314185377Ssam /* 315185377Ssam * Force window_length for 1/2 and 1/4 rate channels, 316185377Ssam * the ini file sets this to zero otherwise. 317185377Ssam */ 318185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 319185377Ssam AR_PHY_FRAME_CTL_WINLEN, 3); 320185377Ssam } 321185377Ssam } 322185377Ssam 323185377Ssam /* Overwrite INI values for revised chipsets */ 324185377Ssam if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) { 325185377Ssam /* ADC_CTL */ 326185377Ssam OS_REG_WRITE(ah, AR_PHY_ADC_CTL, 327185377Ssam SM(2, AR_PHY_ADC_CTL_OFF_INBUFGAIN) | 328185377Ssam SM(2, AR_PHY_ADC_CTL_ON_INBUFGAIN) | 329185377Ssam AR_PHY_ADC_CTL_OFF_PWDDAC | 330185377Ssam AR_PHY_ADC_CTL_OFF_PWDADC); 331185377Ssam 332185377Ssam /* TX_PWR_ADJ */ 333187831Ssam if (ichan->channel == 2484) { 334185377Ssam cckOfdmPwrDelta = SCALE_OC_DELTA( 335185377Ssam ee->ee_cckOfdmPwrDelta - 336185377Ssam ee->ee_scaledCh14FilterCckDelta); 337185377Ssam } else { 338185377Ssam cckOfdmPwrDelta = SCALE_OC_DELTA( 339185377Ssam ee->ee_cckOfdmPwrDelta); 340185377Ssam } 341185377Ssam 342187831Ssam if (IEEE80211_IS_CHAN_G(chan)) { 343185377Ssam OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 344185377Ssam SM((ee->ee_cckOfdmPwrDelta*-1), 345185377Ssam AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) | 346185377Ssam SM((cckOfdmPwrDelta*-1), 347185377Ssam AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX)); 348185377Ssam } else { 349185377Ssam OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0); 350185377Ssam } 351185377Ssam 352185377Ssam /* Add barker RSSI thresh enable as disabled */ 353185377Ssam OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK, 354185377Ssam AR_PHY_DAG_CTRLCCK_EN_RSSI_THR); 355185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK, 356185377Ssam AR_PHY_DAG_CTRLCCK_RSSI_THR, 2); 357185377Ssam 358185377Ssam /* Set the mute mask to the correct default */ 359185377Ssam OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); 360185377Ssam } 361185377Ssam 362185377Ssam if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) { 363185377Ssam /* Clear reg to alllow RX_CLEAR line debug */ 364185377Ssam OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); 365185377Ssam } 366185377Ssam if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) { 367185377Ssam#ifdef notyet 368185377Ssam /* Enable burst prefetch for the data queues */ 369185377Ssam OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... ); 370185377Ssam /* Enable double-buffering */ 371185377Ssam OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS); 372185377Ssam#endif 373185377Ssam } 374185377Ssam 375185377Ssam /* Set ADC/DAC select values */ 376185377Ssam OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); 377185377Ssam 378185377Ssam if (IS_5413(ah) || IS_2417(ah)) { 379187831Ssam uint32_t newReg = 1; 380187831Ssam if (IS_DISABLE_FAST_ADC_CHAN(ichan->channel)) 381185377Ssam newReg = 0; 382185377Ssam /* As it's a clock changing register, only write when the value needs to be changed */ 383185377Ssam if (OS_REG_READ(ah, AR_PHY_FAST_ADC) != newReg) 384185377Ssam OS_REG_WRITE(ah, AR_PHY_FAST_ADC, newReg); 385185377Ssam } 386185377Ssam 387185377Ssam /* Setup the transmit power values. */ 388187831Ssam if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) { 389185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 390185377Ssam "%s: error init'ing transmit power\n", __func__); 391185377Ssam FAIL(HAL_EIO); 392185377Ssam } 393185377Ssam 394185377Ssam /* Write the analog registers */ 395187831Ssam if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) { 396185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n", 397185377Ssam __func__); 398185377Ssam FAIL(HAL_EIO); 399185377Ssam } 400185377Ssam 401185377Ssam /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 402187831Ssam if (IEEE80211_IS_CHAN_OFDM(chan)) { 403187831Ssam if (IS_5413(ah) || 404187831Ssam AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3) 405187831Ssam ar5212SetSpurMitigation(ah, chan); 406185377Ssam ar5212SetDeltaSlope(ah, chan); 407185377Ssam } 408185377Ssam 409185377Ssam /* Setup board specific options for EEPROM version 3 */ 410187831Ssam if (!ar5212SetBoardValues(ah, chan)) { 411185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 412185377Ssam "%s: error setting board options\n", __func__); 413185377Ssam FAIL(HAL_EIO); 414185377Ssam } 415185377Ssam 416185377Ssam /* Restore certain DMA hardware registers on a channel change */ 417185377Ssam if (bChannelChange) 418185377Ssam OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount); 419185377Ssam 420185377Ssam OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 421185377Ssam 422185377Ssam OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 423185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) 424185377Ssam | macStaId1 425185377Ssam | AR_STA_ID1_RTS_USE_DEF 426185377Ssam | ahp->ah_staId1Defaults 427185377Ssam ); 428185377Ssam ar5212SetOperatingMode(ah, opmode); 429185377Ssam 430185377Ssam /* Set Venice BSSID mask according to current state */ 431185377Ssam OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); 432185377Ssam OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); 433185377Ssam 434185377Ssam /* Restore previous led state */ 435185377Ssam OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState); 436185377Ssam 437185377Ssam /* Restore soft Led state to GPIO */ 438185377Ssam OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg); 439185377Ssam OS_REG_WRITE(ah, AR_GPIODO, softLedState); 440185377Ssam 441185377Ssam /* Restore previous antenna */ 442185377Ssam OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 443185377Ssam 444226760Sadrian /* then our BSSID and associate id */ 445185377Ssam OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 446226760Sadrian OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 447226760Sadrian (ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S); 448185377Ssam 449185377Ssam /* Restore bmiss rssi & count thresholds */ 450185377Ssam OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 451185377Ssam 452185377Ssam OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ 453185377Ssam 454187831Ssam if (!ar5212SetChannel(ah, chan)) 455185377Ssam FAIL(HAL_EIO); 456185377Ssam 457185377Ssam OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 458185377Ssam 459185377Ssam ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); 460185377Ssam 461185377Ssam ar5212SetRateDurationTable(ah, chan); 462185377Ssam 463185377Ssam /* Set Tx frame start to tx data start delay */ 464185380Ssam if (IS_RAD5112_ANY(ah) && 465187831Ssam (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))) { 466185377Ssam txFrm2TxDStart = 467187831Ssam IEEE80211_IS_CHAN_HALF(chan) ? 468185377Ssam TX_FRAME_D_START_HALF_RATE: 469185377Ssam TX_FRAME_D_START_QUARTER_RATE; 470185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL, 471185377Ssam AR_PHY_TX_FRAME_TO_TX_DATA_START, txFrm2TxDStart); 472185377Ssam } 473185377Ssam 474185377Ssam /* 475185377Ssam * Setup fast diversity. 476185377Ssam * Fast diversity can be enabled or disabled via regadd.txt. 477185377Ssam * Default is enabled. 478185377Ssam * For reference, 479185377Ssam * Disable: reg val 480185377Ssam * 0x00009860 0x00009d18 (if 11a / 11g, else no change) 481185377Ssam * 0x00009970 0x192bb514 482185377Ssam * 0x0000a208 0xd03e4648 483185377Ssam * 484185377Ssam * Enable: 0x00009860 0x00009d10 (if 11a / 11g, else no change) 485185377Ssam * 0x00009970 0x192fb514 486185377Ssam * 0x0000a208 0xd03e6788 487185377Ssam */ 488185377Ssam 489185377Ssam /* XXX Setup pre PHY ENABLE EAR additions */ 490185377Ssam /* 491185377Ssam * Wait for the frequency synth to settle (synth goes on 492185377Ssam * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 493185377Ssam * Value is in 100ns increments. 494185377Ssam */ 495185377Ssam synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 496187831Ssam if (IEEE80211_IS_CHAN_B(chan)) { 497185377Ssam synthDelay = (4 * synthDelay) / 22; 498185377Ssam } else { 499185377Ssam synthDelay /= 10; 500185377Ssam } 501185377Ssam 502185377Ssam /* Activate the PHY (includes baseband activate and synthesizer on) */ 503185377Ssam OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 504185377Ssam 505185377Ssam /* 506185377Ssam * There is an issue if the AP starts the calibration before 507185377Ssam * the base band timeout completes. This could result in the 508185377Ssam * rx_clear false triggering. As a workaround we add delay an 509185377Ssam * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 510185377Ssam * does not happen. 511185377Ssam */ 512187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) { 513185377Ssam OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY); 514187831Ssam } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 515185377Ssam OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY); 516185377Ssam } else { 517185377Ssam OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 518185377Ssam } 519185377Ssam 520185377Ssam /* 521185377Ssam * The udelay method is not reliable with notebooks. 522185377Ssam * Need to check to see if the baseband is ready 523185377Ssam */ 524185377Ssam testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL); 525185377Ssam /* Selects the Tx hold */ 526185377Ssam OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD); 527185377Ssam i = 0; 528185377Ssam while ((i++ < 20) && 529185377Ssam (OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */ OS_DELAY(200); 530185377Ssam OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg); 531185377Ssam 532185377Ssam /* Calibrate the AGC and start a NF calculation */ 533185377Ssam OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, 534185377Ssam OS_REG_READ(ah, AR_PHY_AGC_CONTROL) 535185377Ssam | AR_PHY_AGC_CONTROL_CAL 536185377Ssam | AR_PHY_AGC_CONTROL_NF); 537185377Ssam 538187831Ssam if (!IEEE80211_IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) { 539185377Ssam /* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */ 540185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 541185377Ssam AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 542185377Ssam INIT_IQCAL_LOG_COUNT_MAX); 543185377Ssam OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 544185377Ssam AR_PHY_TIMING_CTRL4_DO_IQCAL); 545185377Ssam ahp->ah_bIQCalibration = IQ_CAL_RUNNING; 546185377Ssam } else 547185377Ssam ahp->ah_bIQCalibration = IQ_CAL_INACTIVE; 548185377Ssam 549185377Ssam /* Setup compression registers */ 550185377Ssam ar5212SetCompRegs(ah); 551185377Ssam 552185377Ssam /* Set 1:1 QCU to DCU mapping for all queues */ 553185377Ssam for (i = 0; i < AR_NUM_DCU; i++) 554185377Ssam OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 555185377Ssam 556185377Ssam ahp->ah_intrTxqs = 0; 557185377Ssam for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) 558185377Ssam ar5212ResetTxQueue(ah, i); 559185377Ssam 560185377Ssam /* 561185377Ssam * Setup interrupt handling. Note that ar5212ResetTxQueue 562185377Ssam * manipulates the secondary IMR's as queues are enabled 563185377Ssam * and disabled. This is done with RMW ops to insure the 564185377Ssam * settings we make here are preserved. 565185377Ssam */ 566185377Ssam ahp->ah_maskReg = AR_IMR_TXOK | AR_IMR_TXERR | AR_IMR_TXURN 567185377Ssam | AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXORN 568185377Ssam | AR_IMR_HIUERR 569185377Ssam ; 570185377Ssam if (opmode == HAL_M_HOSTAP) 571185377Ssam ahp->ah_maskReg |= AR_IMR_MIB; 572185377Ssam OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 573185377Ssam /* Enable bus errors that are OR'd to set the HIUERR bit */ 574185377Ssam OS_REG_WRITE(ah, AR_IMR_S2, 575185377Ssam OS_REG_READ(ah, AR_IMR_S2) 576185377Ssam | AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR); 577185377Ssam 578185377Ssam if (AH_PRIVATE(ah)->ah_rfkillEnabled) 579185377Ssam ar5212EnableRfKill(ah); 580185377Ssam 581185377Ssam if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { 582185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 583185377Ssam "%s: offset calibration failed to complete in 1ms;" 584185377Ssam " noisy environment?\n", __func__); 585185377Ssam } 586185377Ssam 587185377Ssam /* 588185377Ssam * Set clocks back to 32kHz if they had been using refClk, then 589185377Ssam * use an external 32kHz crystal when sleeping, if one exists. 590185377Ssam */ 591185377Ssam ar5212SetupClock(ah, opmode); 592185377Ssam 593185377Ssam /* 594185377Ssam * Writing to AR_BEACON will start timers. Hence it should 595185377Ssam * be the last register to be written. Do not reset tsf, do 596185377Ssam * not enable beacons at this point, but preserve other values 597185377Ssam * like beaconInterval. 598185377Ssam */ 599185377Ssam OS_REG_WRITE(ah, AR_BEACON, 600185377Ssam (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF))); 601185377Ssam 602185377Ssam /* XXX Setup post reset EAR additions */ 603185377Ssam 604185377Ssam /* QoS support */ 605185377Ssam if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE || 606185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 607185377Ssam AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) { 608185377Ssam OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ 609185377Ssam OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ 610185377Ssam } 611185377Ssam 612185377Ssam /* Turn on NOACK Support for QoS packets */ 613185377Ssam OS_REG_WRITE(ah, AR_NOACK, 614185377Ssam SM(2, AR_NOACK_2BIT_VALUE) | 615185377Ssam SM(5, AR_NOACK_BIT_OFFSET) | 616185377Ssam SM(0, AR_NOACK_BYTE_OFFSET)); 617185377Ssam 618185377Ssam /* Get Antenna Gain reduction */ 619187831Ssam if (IEEE80211_IS_CHAN_5GHZ(chan)) { 620185377Ssam ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain); 621185377Ssam } else { 622185377Ssam ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain); 623185377Ssam } 624185377Ssam twiceAntennaReduction = 625185377Ssam ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 626185377Ssam 627185377Ssam /* TPC for self-generated frames */ 628185377Ssam 629185377Ssam ackTpcPow = MS(ahp->ah_macTPC, AR_TPC_ACK); 630187831Ssam if ((ackTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 631187831Ssam ackTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 632185377Ssam 633187831Ssam if (ackTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 634187831Ssam ackTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 635185377Ssam + ahp->ah_txPowerIndexOffset; 636185377Ssam 637185377Ssam ctsTpcPow = MS(ahp->ah_macTPC, AR_TPC_CTS); 638187831Ssam if ((ctsTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 639187831Ssam ctsTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 640185377Ssam 641187831Ssam if (ctsTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 642187831Ssam ctsTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 643185377Ssam + ahp->ah_txPowerIndexOffset; 644185377Ssam 645185377Ssam chirpTpcPow = MS(ahp->ah_macTPC, AR_TPC_CHIRP); 646187831Ssam if ((chirpTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 647187831Ssam chirpTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 648185377Ssam 649187831Ssam if (chirpTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 650187831Ssam chirpTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 651185377Ssam + ahp->ah_txPowerIndexOffset; 652185377Ssam 653185377Ssam if (ackTpcPow > 63) 654185377Ssam ackTpcPow = 63; 655185377Ssam if (ctsTpcPow > 63) 656185377Ssam ctsTpcPow = 63; 657185377Ssam if (chirpTpcPow > 63) 658185377Ssam chirpTpcPow = 63; 659185377Ssam 660185377Ssam powerVal = SM(ackTpcPow, AR_TPC_ACK) | 661185377Ssam SM(ctsTpcPow, AR_TPC_CTS) | 662185377Ssam SM(chirpTpcPow, AR_TPC_CHIRP); 663185377Ssam 664185377Ssam OS_REG_WRITE(ah, AR_TPC, powerVal); 665185377Ssam 666185377Ssam /* Restore user-specified settings */ 667185377Ssam if (ahp->ah_miscMode != 0) 668185377Ssam OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 669185377Ssam if (ahp->ah_sifstime != (u_int) -1) 670185377Ssam ar5212SetSifsTime(ah, ahp->ah_sifstime); 671185377Ssam if (ahp->ah_slottime != (u_int) -1) 672185377Ssam ar5212SetSlotTime(ah, ahp->ah_slottime); 673185377Ssam if (ahp->ah_acktimeout != (u_int) -1) 674185377Ssam ar5212SetAckTimeout(ah, ahp->ah_acktimeout); 675185377Ssam if (ahp->ah_ctstimeout != (u_int) -1) 676185377Ssam ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); 677185377Ssam if (AH_PRIVATE(ah)->ah_diagreg != 0) 678185377Ssam OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 679185377Ssam 680185377Ssam AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 681187831Ssam#if 0 682187831Ssamdone: 683187831Ssam#endif 684187831Ssam if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan)) 685187831Ssam chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 686185377Ssam 687185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 688185377Ssam 689185377Ssam RESTORE_CCK(ah, chan, isBmode); 690185377Ssam 691185377Ssam OS_MARK(ah, AH_MARK_RESET_DONE, 0); 692185377Ssam 693185377Ssam return AH_TRUE; 694185377Ssambad: 695185377Ssam RESTORE_CCK(ah, chan, isBmode); 696185377Ssam 697185377Ssam OS_MARK(ah, AH_MARK_RESET_DONE, ecode); 698187611Ssam if (status != AH_NULL) 699185377Ssam *status = ecode; 700185377Ssam return AH_FALSE; 701185377Ssam#undef FAIL 702185377Ssam#undef N 703185377Ssam} 704185377Ssam 705185377Ssam/* 706185377Ssam * Call the rf backend to change the channel. 707185377Ssam */ 708185377SsamHAL_BOOL 709187831Ssamar5212SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 710185377Ssam{ 711185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 712185377Ssam 713185377Ssam /* Change the synth */ 714185377Ssam if (!ahp->ah_rfHal->setChannel(ah, chan)) 715185377Ssam return AH_FALSE; 716185377Ssam return AH_TRUE; 717185377Ssam} 718185377Ssam 719185377Ssam/* 720185377Ssam * This channel change evaluates whether the selected hardware can 721185377Ssam * perform a synthesizer-only channel change (no reset). If the 722185377Ssam * TX is not stopped, or the RFBus cannot be granted in the given 723185377Ssam * time, the function returns false as a reset is necessary 724185377Ssam */ 725185377SsamHAL_BOOL 726187831Ssamar5212ChannelChange(struct ath_hal *ah, const struct ieee80211_channel *chan) 727185377Ssam{ 728185377Ssam uint32_t ulCount; 729185377Ssam uint32_t data, synthDelay, qnum; 730185377Ssam uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 731185377Ssam HAL_BOOL txStopped = AH_TRUE; 732185377Ssam HAL_CHANNEL_INTERNAL *ichan; 733185377Ssam 734185377Ssam /* 735185377Ssam * Map public channel to private. 736185377Ssam */ 737185377Ssam ichan = ath_hal_checkchannel(ah, chan); 738185377Ssam 739185377Ssam /* TX must be stopped or RF Bus grant will not work */ 740185377Ssam for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) { 741185377Ssam if (ar5212NumTxPending(ah, qnum)) { 742185377Ssam txStopped = AH_FALSE; 743185377Ssam break; 744185377Ssam } 745185377Ssam } 746185377Ssam if (!txStopped) 747185377Ssam return AH_FALSE; 748185377Ssam 749185377Ssam /* Kill last Baseband Rx Frame */ 750185377Ssam OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); /* Request analog bus grant */ 751185377Ssam for (ulCount = 0; ulCount < 100; ulCount++) { 752185377Ssam if (OS_REG_READ(ah, AR_PHY_RFBUS_GNT)) 753185377Ssam break; 754185377Ssam OS_DELAY(5); 755185377Ssam } 756185377Ssam if (ulCount >= 100) 757185377Ssam return AH_FALSE; 758185377Ssam 759185377Ssam /* Change the synth */ 760187831Ssam if (!ar5212SetChannel(ah, chan)) 761185377Ssam return AH_FALSE; 762185377Ssam 763185377Ssam /* 764185377Ssam * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). 765185377Ssam * Read the phy active delay register. Value is in 100ns increments. 766185377Ssam */ 767185377Ssam data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 768187831Ssam if (IEEE80211_IS_CHAN_B(chan)) { 769185377Ssam synthDelay = (4 * data) / 22; 770185377Ssam } else { 771185377Ssam synthDelay = data / 10; 772185377Ssam } 773185377Ssam OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 774185377Ssam 775185377Ssam /* Setup the transmit power values. */ 776187831Ssam if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) { 777185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 778185377Ssam "%s: error init'ing transmit power\n", __func__); 779185377Ssam return AH_FALSE; 780185377Ssam } 781185377Ssam 782185377Ssam /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 783187831Ssam if (IEEE80211_IS_CHAN_OFDM(chan)) { 784187831Ssam if (IS_5413(ah) || 785187831Ssam AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3) 786187831Ssam ar5212SetSpurMitigation(ah, chan); 787185377Ssam ar5212SetDeltaSlope(ah, chan); 788185377Ssam } 789185377Ssam 790185377Ssam /* Release the RFBus Grant */ 791185377Ssam OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 792185377Ssam 793185377Ssam /* Start Noise Floor Cal */ 794185377Ssam OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 795185377Ssam return AH_TRUE; 796185377Ssam} 797185377Ssam 798185377Ssamvoid 799185377Ssamar5212SetOperatingMode(struct ath_hal *ah, int opmode) 800185377Ssam{ 801185377Ssam uint32_t val; 802185377Ssam 803185377Ssam val = OS_REG_READ(ah, AR_STA_ID1); 804185377Ssam val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 805185377Ssam switch (opmode) { 806185377Ssam case HAL_M_HOSTAP: 807185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 808185377Ssam | AR_STA_ID1_KSRCH_MODE); 809185377Ssam OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 810185377Ssam break; 811185377Ssam case HAL_M_IBSS: 812185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 813185377Ssam | AR_STA_ID1_KSRCH_MODE); 814185377Ssam OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 815185377Ssam break; 816185377Ssam case HAL_M_STA: 817185377Ssam case HAL_M_MONITOR: 818185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 819185377Ssam break; 820185377Ssam } 821185377Ssam} 822185377Ssam 823185377Ssam/* 824185377Ssam * Places the PHY and Radio chips into reset. A full reset 825185377Ssam * must be called to leave this state. The PCI/MAC/PCU are 826185377Ssam * not placed into reset as we must receive interrupt to 827185377Ssam * re-enable the hardware. 828185377Ssam */ 829185377SsamHAL_BOOL 830185377Ssamar5212PhyDisable(struct ath_hal *ah) 831185377Ssam{ 832185377Ssam return ar5212SetResetReg(ah, AR_RC_BB); 833185377Ssam} 834185377Ssam 835185377Ssam/* 836185377Ssam * Places all of hardware into reset 837185377Ssam */ 838185377SsamHAL_BOOL 839185377Ssamar5212Disable(struct ath_hal *ah) 840185377Ssam{ 841185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 842185377Ssam return AH_FALSE; 843185377Ssam /* 844185377Ssam * Reset the HW - PCI must be reset after the rest of the 845185377Ssam * device has been reset. 846185377Ssam */ 847185377Ssam return ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI); 848185377Ssam} 849185377Ssam 850185377Ssam/* 851185377Ssam * Places the hardware into reset and then pulls it out of reset 852185377Ssam * 853185377Ssam * TODO: Only write the PLL if we're changing to or from CCK mode 854185377Ssam * 855185377Ssam * WARNING: The order of the PLL and mode registers must be correct. 856185377Ssam */ 857185377SsamHAL_BOOL 858187831Ssamar5212ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan) 859185377Ssam{ 860185377Ssam 861187831Ssam OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); 862185377Ssam 863185377Ssam /* 864185377Ssam * Reset the HW - PCI must be reset after the rest of the 865185377Ssam * device has been reset 866185377Ssam */ 867185377Ssam if (!ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI)) 868185377Ssam return AH_FALSE; 869185377Ssam 870185377Ssam /* Bring out of sleep mode (AGAIN) */ 871185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 872185377Ssam return AH_FALSE; 873185377Ssam 874185377Ssam /* Clear warm reset register */ 875185377Ssam if (!ar5212SetResetReg(ah, 0)) 876185377Ssam return AH_FALSE; 877185377Ssam 878185377Ssam /* 879185377Ssam * Perform warm reset before the mode/PLL/turbo registers 880185377Ssam * are changed in order to deactivate the radio. Mode changes 881185377Ssam * with an active radio can result in corrupted shifts to the 882185377Ssam * radio device. 883185377Ssam */ 884185377Ssam 885185377Ssam /* 886185377Ssam * Set CCK and Turbo modes correctly. 887185377Ssam */ 888185377Ssam if (chan != AH_NULL) { /* NB: can be null during attach */ 889185377Ssam uint32_t rfMode, phyPLL = 0, curPhyPLL, turbo; 890185377Ssam 891185380Ssam if (IS_5413(ah)) { /* NB: =>'s 5424 also */ 892185377Ssam rfMode = AR_PHY_MODE_AR5112; 893187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) 894185377Ssam rfMode |= AR_PHY_MODE_HALF; 895187831Ssam else if (IEEE80211_IS_CHAN_QUARTER(chan)) 896185377Ssam rfMode |= AR_PHY_MODE_QUARTER; 897185377Ssam 898187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) 899185377Ssam phyPLL = AR_PHY_PLL_CTL_44_5112; 900185377Ssam else 901185377Ssam phyPLL = AR_PHY_PLL_CTL_40_5413; 902185380Ssam } else if (IS_RAD5111(ah)) { 903185380Ssam rfMode = AR_PHY_MODE_AR5111; 904187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) 905185380Ssam phyPLL = AR_PHY_PLL_CTL_44; 906185380Ssam else 907185380Ssam phyPLL = AR_PHY_PLL_CTL_40; 908187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) 909185380Ssam phyPLL = AR_PHY_PLL_CTL_HALF; 910187831Ssam else if (IEEE80211_IS_CHAN_QUARTER(chan)) 911185380Ssam phyPLL = AR_PHY_PLL_CTL_QUARTER; 912185380Ssam } else { /* 5112, 2413, 2316, 2317 */ 913185377Ssam rfMode = AR_PHY_MODE_AR5112; 914187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) 915185377Ssam phyPLL = AR_PHY_PLL_CTL_44_5112; 916185380Ssam else 917185380Ssam phyPLL = AR_PHY_PLL_CTL_40_5112; 918187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) 919185380Ssam phyPLL |= AR_PHY_PLL_CTL_HALF; 920187831Ssam else if (IEEE80211_IS_CHAN_QUARTER(chan)) 921185380Ssam phyPLL |= AR_PHY_PLL_CTL_QUARTER; 922185377Ssam } 923187831Ssam if (IEEE80211_IS_CHAN_G(chan)) 924185377Ssam rfMode |= AR_PHY_MODE_DYNAMIC; 925187831Ssam else if (IEEE80211_IS_CHAN_OFDM(chan)) 926185377Ssam rfMode |= AR_PHY_MODE_OFDM; 927185377Ssam else 928185377Ssam rfMode |= AR_PHY_MODE_CCK; 929187831Ssam if (IEEE80211_IS_CHAN_5GHZ(chan)) 930185377Ssam rfMode |= AR_PHY_MODE_RF5GHZ; 931185377Ssam else 932185377Ssam rfMode |= AR_PHY_MODE_RF2GHZ; 933187831Ssam turbo = IEEE80211_IS_CHAN_TURBO(chan) ? 934185377Ssam (AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT) : 0; 935185377Ssam curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL); 936185377Ssam /* 937185377Ssam * PLL, Mode, and Turbo values must be written in the correct 938185377Ssam * order to ensure: 939185377Ssam * - The PLL cannot be set to 44 unless the CCK or DYNAMIC 940185377Ssam * mode bit is set 941185377Ssam * - Turbo cannot be set at the same time as CCK or DYNAMIC 942185377Ssam */ 943187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) { 944185377Ssam OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); 945185377Ssam OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 946185377Ssam if (curPhyPLL != phyPLL) { 947185377Ssam OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); 948185377Ssam /* Wait for the PLL to settle */ 949185377Ssam OS_DELAY(PLL_SETTLE_DELAY); 950185377Ssam } 951185377Ssam } else { 952185377Ssam if (curPhyPLL != phyPLL) { 953185377Ssam OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); 954185377Ssam /* Wait for the PLL to settle */ 955185377Ssam OS_DELAY(PLL_SETTLE_DELAY); 956185377Ssam } 957185377Ssam OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); 958185377Ssam OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 959185377Ssam } 960185377Ssam } 961185377Ssam return AH_TRUE; 962185377Ssam} 963185377Ssam 964185377Ssam/* 965185377Ssam * Recalibrate the lower PHY chips to account for temperature/environment 966185377Ssam * changes. 967185377Ssam */ 968185377SsamHAL_BOOL 969187831Ssamar5212PerCalibrationN(struct ath_hal *ah, 970187831Ssam struct ieee80211_channel *chan, 971187831Ssam u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone) 972185377Ssam{ 973185377Ssam#define IQ_CAL_TRIES 10 974185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 975185377Ssam HAL_CHANNEL_INTERNAL *ichan; 976185377Ssam int32_t qCoff, qCoffDenom; 977185377Ssam int32_t iqCorrMeas, iCoff, iCoffDenom; 978185377Ssam uint32_t powerMeasQ, powerMeasI; 979188011Ssam HAL_BOOL isBmode = AH_FALSE; 980185377Ssam 981187831Ssam OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq); 982185380Ssam *isCalDone = AH_FALSE; 983185377Ssam ichan = ath_hal_checkchannel(ah, chan); 984185377Ssam if (ichan == AH_NULL) { 985185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 986185377Ssam "%s: invalid channel %u/0x%x; no mapping\n", 987187831Ssam __func__, chan->ic_freq, chan->ic_flags); 988185377Ssam return AH_FALSE; 989185377Ssam } 990185377Ssam SAVE_CCK(ah, chan, isBmode); 991185377Ssam 992185380Ssam if (ahp->ah_bIQCalibration == IQ_CAL_DONE || 993185380Ssam ahp->ah_bIQCalibration == IQ_CAL_INACTIVE) 994185380Ssam *isCalDone = AH_TRUE; 995185377Ssam 996185377Ssam /* IQ calibration in progress. Check to see if it has finished. */ 997185377Ssam if (ahp->ah_bIQCalibration == IQ_CAL_RUNNING && 998185377Ssam !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) { 999185377Ssam int i; 1000185377Ssam 1001185377Ssam /* IQ Calibration has finished. */ 1002185377Ssam ahp->ah_bIQCalibration = IQ_CAL_INACTIVE; 1003185380Ssam *isCalDone = AH_TRUE; 1004185377Ssam 1005185377Ssam /* workaround for misgated IQ Cal results */ 1006185377Ssam i = 0; 1007185377Ssam do { 1008185377Ssam /* Read calibration results. */ 1009185377Ssam powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I); 1010185377Ssam powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q); 1011185377Ssam iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS); 1012185377Ssam if (powerMeasI && powerMeasQ) 1013185377Ssam break; 1014185377Ssam /* Do we really need this??? */ 1015188191Ssam OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1016188191Ssam AR_PHY_TIMING_CTRL4_DO_IQCAL); 1017185377Ssam } while (++i < IQ_CAL_TRIES); 1018185377Ssam 1019188194Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 1020188194Ssam "%s: IQ cal finished: %d tries\n", __func__, i); 1021188194Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 1022188194Ssam "%s: powerMeasI %u powerMeasQ %u iqCorrMeas %d\n", 1023188194Ssam __func__, powerMeasI, powerMeasQ, iqCorrMeas); 1024188194Ssam 1025185377Ssam /* 1026185377Ssam * Prescale these values to remove 64-bit operation 1027185377Ssam * requirement at the loss of a little precision. 1028185377Ssam */ 1029185377Ssam iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 1030185377Ssam qCoffDenom = powerMeasQ / 128; 1031185377Ssam 1032185377Ssam /* Protect against divide-by-0 and loss of sign bits. */ 1033185377Ssam if (iCoffDenom != 0 && qCoffDenom >= 2) { 1034185377Ssam iCoff = (int8_t)(-iqCorrMeas) / iCoffDenom; 1035185377Ssam /* IQCORR_Q_I_COFF is a signed 6 bit number */ 1036185377Ssam if (iCoff < -32) { 1037185377Ssam iCoff = -32; 1038185377Ssam } else if (iCoff > 31) { 1039185377Ssam iCoff = 31; 1040185377Ssam } 1041185377Ssam 1042185377Ssam /* IQCORR_Q_Q_COFF is a signed 5 bit number */ 1043185377Ssam qCoff = (powerMeasI / qCoffDenom) - 128; 1044185377Ssam if (qCoff < -16) { 1045185377Ssam qCoff = -16; 1046185377Ssam } else if (qCoff > 15) { 1047185377Ssam qCoff = 15; 1048185377Ssam } 1049185377Ssam 1050185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 1051188194Ssam "%s: iCoff %d qCoff %d\n", __func__, iCoff, qCoff); 1052185377Ssam 1053185377Ssam /* Write values and enable correction */ 1054185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1055185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff); 1056185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1057185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff); 1058185377Ssam OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1059185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 1060185377Ssam 1061185377Ssam ahp->ah_bIQCalibration = IQ_CAL_DONE; 1062187831Ssam ichan->privFlags |= CHANNEL_IQVALID; 1063185377Ssam ichan->iCoff = iCoff; 1064185377Ssam ichan->qCoff = qCoff; 1065185377Ssam } 1066188192Ssam } else if (!IEEE80211_IS_CHAN_B(chan) && 1067188192Ssam ahp->ah_bIQCalibration == IQ_CAL_DONE && 1068187831Ssam (ichan->privFlags & CHANNEL_IQVALID) == 0) { 1069185377Ssam /* 1070185377Ssam * Start IQ calibration if configured channel has changed. 1071185377Ssam * Use a magic number of 15 based on default value. 1072185377Ssam */ 1073185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1074185377Ssam AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 1075185377Ssam INIT_IQCAL_LOG_COUNT_MAX); 1076185377Ssam OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1077185377Ssam AR_PHY_TIMING_CTRL4_DO_IQCAL); 1078185377Ssam ahp->ah_bIQCalibration = IQ_CAL_RUNNING; 1079185377Ssam } 1080185377Ssam /* XXX EAR */ 1081185377Ssam 1082185380Ssam if (longCal) { 1083185380Ssam /* Check noise floor results */ 1084187831Ssam ar5212GetNf(ah, chan); 1085187831Ssam if (!IEEE80211_IS_CHAN_CWINT(chan)) { 1086185380Ssam /* Perform cal for 5Ghz channels and any OFDM on 5112 */ 1087187831Ssam if (IEEE80211_IS_CHAN_5GHZ(chan) || 1088187831Ssam (IS_RAD5112(ah) && IEEE80211_IS_CHAN_OFDM(chan))) 1089185380Ssam ar5212RequestRfgain(ah); 1090185380Ssam } 1091185377Ssam } 1092185377Ssam RESTORE_CCK(ah, chan, isBmode); 1093185377Ssam 1094185377Ssam return AH_TRUE; 1095185377Ssam#undef IQ_CAL_TRIES 1096185377Ssam} 1097185377Ssam 1098185380SsamHAL_BOOL 1099187831Ssamar5212PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan, 1100187831Ssam HAL_BOOL *isIQdone) 1101185380Ssam{ 1102185380Ssam return ar5212PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone); 1103185380Ssam} 1104185380Ssam 1105185380SsamHAL_BOOL 1106187831Ssamar5212ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan) 1107185380Ssam{ 1108188193Ssam HAL_CHANNEL_INTERNAL *ichan; 1109188193Ssam 1110188193Ssam ichan = ath_hal_checkchannel(ah, chan); 1111188193Ssam if (ichan == AH_NULL) { 1112188193Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 1113188193Ssam "%s: invalid channel %u/0x%x; no mapping\n", 1114188193Ssam __func__, chan->ic_freq, chan->ic_flags); 1115188193Ssam return AH_FALSE; 1116188193Ssam } 1117188193Ssam ichan->privFlags &= ~CHANNEL_IQVALID; 1118185380Ssam return AH_TRUE; 1119185380Ssam} 1120185380Ssam 1121226489Sadrian/************************************************************** 1122226489Sadrian * ar5212MacStop 1123226489Sadrian * 1124226489Sadrian * Disables all active QCUs and ensure that the mac is in a 1125226489Sadrian * quiessence state. 1126226489Sadrian */ 1127226489Sadrianstatic HAL_BOOL 1128226489Sadrianar5212MacStop(struct ath_hal *ah) 1129226489Sadrian{ 1130226489Sadrian HAL_BOOL status; 1131226489Sadrian uint32_t count; 1132226489Sadrian uint32_t pendFrameCount; 1133226489Sadrian uint32_t macStateFlag; 1134226489Sadrian uint32_t queue; 1135226489Sadrian 1136226489Sadrian status = AH_FALSE; 1137226489Sadrian 1138226489Sadrian /* Disable Rx Operation ***********************************/ 1139226489Sadrian OS_REG_SET_BIT(ah, AR_CR, AR_CR_RXD); 1140226489Sadrian 1141226489Sadrian /* Disable TX Operation ***********************************/ 1142226489Sadrian#ifdef NOT_YET 1143226489Sadrian ar5212SetTxdpInvalid(ah); 1144226489Sadrian#endif 1145226489Sadrian OS_REG_SET_BIT(ah, AR_Q_TXD, AR_Q_TXD_M); 1146226489Sadrian 1147226489Sadrian /* Polling operation for completion of disable ************/ 1148226489Sadrian macStateFlag = TX_ENABLE_CHECK | RX_ENABLE_CHECK; 1149226489Sadrian 1150226489Sadrian for (count = 0; count < MAX_RESET_WAIT; count++) { 1151226489Sadrian if (macStateFlag & RX_ENABLE_CHECK) { 1152226489Sadrian if (!OS_REG_IS_BIT_SET(ah, AR_CR, AR_CR_RXE)) { 1153226489Sadrian macStateFlag &= ~RX_ENABLE_CHECK; 1154226489Sadrian } 1155226489Sadrian } 1156226489Sadrian 1157226489Sadrian if (macStateFlag & TX_ENABLE_CHECK) { 1158226489Sadrian if (!OS_REG_IS_BIT_SET(ah, AR_Q_TXE, AR_Q_TXE_M)) { 1159226489Sadrian macStateFlag &= ~TX_ENABLE_CHECK; 1160226489Sadrian macStateFlag |= TX_QUEUEPEND_CHECK; 1161226489Sadrian } 1162226489Sadrian } 1163226489Sadrian if (macStateFlag & TX_QUEUEPEND_CHECK) { 1164226489Sadrian pendFrameCount = 0; 1165226489Sadrian for (queue = 0; queue < AR_NUM_DCU; queue++) { 1166226489Sadrian pendFrameCount += OS_REG_READ(ah, 1167226489Sadrian AR_Q0_STS + (queue * 4)) & 1168226489Sadrian AR_Q_STS_PEND_FR_CNT; 1169226489Sadrian } 1170226489Sadrian if (pendFrameCount == 0) { 1171226489Sadrian macStateFlag &= ~TX_QUEUEPEND_CHECK; 1172226489Sadrian } 1173226489Sadrian } 1174226489Sadrian if (macStateFlag == 0) { 1175226489Sadrian status = AH_TRUE; 1176226489Sadrian break; 1177226489Sadrian } 1178226489Sadrian OS_DELAY(50); 1179226489Sadrian } 1180226489Sadrian 1181226489Sadrian if (status != AH_TRUE) { 1182226489Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 1183226489Sadrian "%s:Failed to stop the MAC state 0x%x\n", 1184226489Sadrian __func__, macStateFlag); 1185226489Sadrian } 1186226489Sadrian 1187226489Sadrian return status; 1188226489Sadrian} 1189226489Sadrian 1190226489Sadrian 1191185377Ssam/* 1192185377Ssam * Write the given reset bit mask into the reset register 1193185377Ssam */ 1194185377Ssamstatic HAL_BOOL 1195185377Ssamar5212SetResetReg(struct ath_hal *ah, uint32_t resetMask) 1196185377Ssam{ 1197185377Ssam uint32_t mask = resetMask ? resetMask : ~0; 1198185377Ssam HAL_BOOL rt; 1199185377Ssam 1200226489Sadrian /* Never reset the PCIE core */ 1201188979Ssam if (AH_PRIVATE(ah)->ah_ispcie) { 1202185377Ssam resetMask &= ~AR_RC_PCI; 1203185377Ssam } 1204185377Ssam 1205226489Sadrian if (resetMask & (AR_RC_MAC | AR_RC_PCI)) { 1206226489Sadrian /* 1207226489Sadrian * To ensure that the driver can reset the 1208226489Sadrian * MAC, wake up the chip 1209226489Sadrian */ 1210226489Sadrian rt = ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE); 1211226489Sadrian 1212226489Sadrian if (rt != AH_TRUE) { 1213226489Sadrian return rt; 1214226489Sadrian } 1215226489Sadrian 1216226489Sadrian /* 1217226489Sadrian * Disable interrupts 1218226489Sadrian */ 1219226489Sadrian OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 1220226489Sadrian OS_REG_READ(ah, AR_IER); 1221226489Sadrian 1222226489Sadrian if (ar5212MacStop(ah) != AH_TRUE) { 1223226489Sadrian /* 1224226489Sadrian * Failed to stop the MAC gracefully; let's be more forceful then 1225226489Sadrian */ 1226226489Sadrian 1227226489Sadrian /* need some delay before flush any pending MMR writes */ 1228226489Sadrian OS_DELAY(15); 1229226489Sadrian OS_REG_READ(ah, AR_RXDP); 1230226489Sadrian 1231226489Sadrian resetMask |= AR_RC_MAC | AR_RC_BB; 1232226489Sadrian /* _Never_ reset PCI Express core */ 1233226489Sadrian if (! AH_PRIVATE(ah)->ah_ispcie) { 1234226489Sadrian resetMask |= AR_RC_PCI; 1235226489Sadrian } 1236226489Sadrian#if 0 1237226489Sadrian /* 1238226489Sadrian * Flush the park address of the PCI controller 1239226489Sadrian */ 1240226489Sadrian /* Read PCI slot information less than Hainan revision */ 1241226489Sadrian if (AH_PRIVATE(ah)->ah_bustype == HAL_BUS_TYPE_PCI) { 1242226489Sadrian if (!IS_5112_REV5_UP(ah)) { 1243226489Sadrian#define PCI_COMMON_CONFIG_STATUS 0x06 1244226489Sadrian u_int32_t i; 1245226489Sadrian u_int16_t reg16; 1246226489Sadrian 1247226489Sadrian for (i = 0; i < 32; i++) { 1248226489Sadrian ath_hal_read_pci_config_space(ah, 1249226489Sadrian PCI_COMMON_CONFIG_STATUS, 1250226489Sadrian ®16, sizeof(reg16)); 1251226489Sadrian } 1252226489Sadrian } 1253226489Sadrian#undef PCI_COMMON_CONFIG_STATUS 1254226489Sadrian } 1255226489Sadrian#endif 1256226489Sadrian } else { 1257226489Sadrian /* 1258226489Sadrian * MAC stopped gracefully; no need to warm-reset the PCI bus 1259226489Sadrian */ 1260226489Sadrian 1261226489Sadrian resetMask &= ~AR_RC_PCI; 1262226489Sadrian 1263226489Sadrian /* need some delay before flush any pending MMR writes */ 1264226489Sadrian OS_DELAY(15); 1265226489Sadrian OS_REG_READ(ah, AR_RXDP); 1266226489Sadrian } 1267226489Sadrian } 1268226489Sadrian 1269185377Ssam (void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */ 1270185377Ssam OS_REG_WRITE(ah, AR_RC, resetMask); 1271185377Ssam OS_DELAY(15); /* need to wait at least 128 clocks 1272185377Ssam when reseting PCI before read */ 1273185377Ssam mask &= (AR_RC_MAC | AR_RC_BB); 1274185377Ssam resetMask &= (AR_RC_MAC | AR_RC_BB); 1275185377Ssam rt = ath_hal_wait(ah, AR_RC, mask, resetMask); 1276185377Ssam if ((resetMask & AR_RC_MAC) == 0) { 1277185377Ssam if (isBigEndian()) { 1278185377Ssam /* 1279234450Sadrian * Set CFG, little-endian for descriptor accesses. 1280185377Ssam */ 1281234450Sadrian mask = INIT_CONFIG_STATUS | AR_CFG_SWRD; 1282185377Ssam#ifndef AH_NEED_DESC_SWAP 1283185377Ssam mask |= AR_CFG_SWTD; 1284185377Ssam#endif 1285234450Sadrian OS_REG_WRITE(ah, AR_CFG, mask); 1286185377Ssam } else 1287185377Ssam OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 1288185377Ssam if (ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 1289185377Ssam (void) OS_REG_READ(ah, AR_ISR_RAC); 1290185377Ssam } 1291185380Ssam 1292185380Ssam /* track PHY power state so we don't try to r/w BB registers */ 1293185380Ssam AH5212(ah)->ah_phyPowerOn = ((resetMask & AR_RC_BB) == 0); 1294185377Ssam return rt; 1295185377Ssam} 1296185377Ssam 1297185377Ssamint16_t 1298185377Ssamar5212GetNoiseFloor(struct ath_hal *ah) 1299185377Ssam{ 1300185377Ssam int16_t nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 1301185377Ssam if (nf & 0x100) 1302185377Ssam nf = 0 - ((nf ^ 0x1ff) + 1); 1303185377Ssam return nf; 1304185377Ssam} 1305185377Ssam 1306185377Ssamstatic HAL_BOOL 1307187831SsamgetNoiseFloorThresh(struct ath_hal *ah, const struct ieee80211_channel *chan, 1308185377Ssam int16_t *nft) 1309185377Ssam{ 1310185377Ssam const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1311185377Ssam 1312185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 1313185377Ssam 1314187831Ssam switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 1315187831Ssam case IEEE80211_CHAN_A: 1316185377Ssam *nft = ee->ee_noiseFloorThresh[headerInfo11A]; 1317185377Ssam break; 1318187831Ssam case IEEE80211_CHAN_B: 1319185377Ssam *nft = ee->ee_noiseFloorThresh[headerInfo11B]; 1320185377Ssam break; 1321187831Ssam case IEEE80211_CHAN_G: 1322187831Ssam case IEEE80211_CHAN_PUREG: /* NB: really 108G */ 1323185377Ssam *nft = ee->ee_noiseFloorThresh[headerInfo11G]; 1324185377Ssam break; 1325185377Ssam default: 1326187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 1327187831Ssam "%s: invalid channel flags %u/0x%x\n", 1328187831Ssam __func__, chan->ic_freq, chan->ic_flags); 1329185377Ssam return AH_FALSE; 1330185377Ssam } 1331185377Ssam return AH_TRUE; 1332185377Ssam} 1333185377Ssam 1334185377Ssam/* 1335185377Ssam * Setup the noise floor cal history buffer. 1336185377Ssam */ 1337185377Ssamvoid 1338185377Ssamar5212InitNfCalHistBuffer(struct ath_hal *ah) 1339185377Ssam{ 1340185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 1341185377Ssam int i; 1342185377Ssam 1343185377Ssam ahp->ah_nfCalHist.first_run = 1; 1344185377Ssam ahp->ah_nfCalHist.currIndex = 0; 1345185377Ssam ahp->ah_nfCalHist.privNF = AR5212_CCA_MAX_GOOD_VALUE; 1346185377Ssam ahp->ah_nfCalHist.invalidNFcount = AR512_NF_CAL_HIST_MAX; 1347185377Ssam for (i = 0; i < AR512_NF_CAL_HIST_MAX; i ++) 1348185377Ssam ahp->ah_nfCalHist.nfCalBuffer[i] = AR5212_CCA_MAX_GOOD_VALUE; 1349185377Ssam} 1350185377Ssam 1351185377Ssam/* 1352185377Ssam * Add a noise floor value to the ring buffer. 1353185377Ssam */ 1354185377Ssamstatic __inline void 1355185377SsamupdateNFHistBuff(struct ar5212NfCalHist *h, int16_t nf) 1356185377Ssam{ 1357185377Ssam h->nfCalBuffer[h->currIndex] = nf; 1358185377Ssam if (++h->currIndex >= AR512_NF_CAL_HIST_MAX) 1359185377Ssam h->currIndex = 0; 1360185377Ssam} 1361185377Ssam 1362185377Ssam/* 1363185377Ssam * Return the median noise floor value in the ring buffer. 1364185377Ssam */ 1365185377Ssamint16_t 1366185377Ssamar5212GetNfHistMid(const int16_t calData[AR512_NF_CAL_HIST_MAX]) 1367185377Ssam{ 1368185377Ssam int16_t sort[AR512_NF_CAL_HIST_MAX]; 1369185377Ssam int i, j; 1370185377Ssam 1371185377Ssam OS_MEMCPY(sort, calData, AR512_NF_CAL_HIST_MAX*sizeof(int16_t)); 1372185377Ssam for (i = 0; i < AR512_NF_CAL_HIST_MAX-1; i ++) { 1373185377Ssam for (j = 1; j < AR512_NF_CAL_HIST_MAX-i; j ++) { 1374185377Ssam if (sort[j] > sort[j-1]) { 1375185377Ssam int16_t nf = sort[j]; 1376185377Ssam sort[j] = sort[j-1]; 1377185377Ssam sort[j-1] = nf; 1378185377Ssam } 1379185377Ssam } 1380185377Ssam } 1381185377Ssam return sort[(AR512_NF_CAL_HIST_MAX-1)>>1]; 1382185377Ssam} 1383185377Ssam 1384185377Ssam/* 1385185377Ssam * Read the NF and check it against the noise floor threshhold 1386185377Ssam */ 1387185377Ssamint16_t 1388187831Ssamar5212GetNf(struct ath_hal *ah, struct ieee80211_channel *chan) 1389185377Ssam{ 1390185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 1391185377Ssam struct ar5212NfCalHist *h = &ahp->ah_nfCalHist; 1392187831Ssam HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 1393185377Ssam int16_t nf, nfThresh; 1394185377Ssam int32_t val; 1395185377Ssam 1396185377Ssam if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 1397185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 1398185377Ssam "%s: NF did not complete in calibration window\n", __func__); 1399187831Ssam ichan->rawNoiseFloor = h->privNF; /* most recent value */ 1400187831Ssam return ichan->rawNoiseFloor; 1401185377Ssam } 1402185377Ssam 1403185377Ssam /* 1404185377Ssam * Finished NF cal, check against threshold. 1405185377Ssam */ 1406185377Ssam nf = ar5212GetNoiseFloor(ah); 1407185377Ssam if (getNoiseFloorThresh(ah, chan, &nfThresh)) { 1408185377Ssam if (nf > nfThresh) { 1409185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 1410185377Ssam "%s: noise floor failed detected; detected %u, " 1411185377Ssam "threshold %u\n", __func__, nf, nfThresh); 1412185377Ssam /* 1413185377Ssam * NB: Don't discriminate 2.4 vs 5Ghz, if this 1414185377Ssam * happens it indicates a problem regardless 1415185377Ssam * of the band. 1416185377Ssam */ 1417187831Ssam chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 1418185377Ssam nf = 0; 1419185377Ssam } 1420185377Ssam } else 1421185377Ssam nf = 0; 1422185377Ssam 1423185377Ssam /* 1424185377Ssam * Pass through histogram and write median value as 1425185377Ssam * calculated from the accrued window. We require a 1426185377Ssam * full window of in-range values to be seen before we 1427185377Ssam * start using the history. 1428185377Ssam */ 1429185377Ssam updateNFHistBuff(h, nf); 1430185377Ssam if (h->first_run) { 1431185377Ssam if (nf < AR5212_CCA_MIN_BAD_VALUE || 1432185377Ssam nf > AR5212_CCA_MAX_HIGH_VALUE) { 1433185377Ssam nf = AR5212_CCA_MAX_GOOD_VALUE; 1434185377Ssam h->invalidNFcount = AR512_NF_CAL_HIST_MAX; 1435185377Ssam } else if (--(h->invalidNFcount) == 0) { 1436185377Ssam h->first_run = 0; 1437185377Ssam h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer); 1438185377Ssam } else { 1439185377Ssam nf = AR5212_CCA_MAX_GOOD_VALUE; 1440185377Ssam } 1441185377Ssam } else { 1442185377Ssam h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer); 1443185377Ssam } 1444185377Ssam 1445185377Ssam val = OS_REG_READ(ah, AR_PHY(25)); 1446185377Ssam val &= 0xFFFFFE00; 1447185377Ssam val |= (((uint32_t)nf << 1) & 0x1FF); 1448185377Ssam OS_REG_WRITE(ah, AR_PHY(25), val); 1449185377Ssam OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 1450185377Ssam OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 1451185377Ssam OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 1452185377Ssam 1453185377Ssam if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF, 0)) { 1454185377Ssam#ifdef AH_DEBUG 1455185377Ssam ath_hal_printf(ah, "%s: AGC not ready AGC_CONTROL 0x%x\n", 1456185377Ssam __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); 1457185377Ssam#endif 1458185377Ssam } 1459185377Ssam 1460185377Ssam /* 1461185377Ssam * Now load a high maxCCAPower value again so that we're 1462185377Ssam * not capped by the median we just loaded 1463185377Ssam */ 1464185377Ssam val &= 0xFFFFFE00; 1465185377Ssam val |= (((uint32_t)(-50) << 1) & 0x1FF); 1466185377Ssam OS_REG_WRITE(ah, AR_PHY(25), val); 1467185377Ssam OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 1468185377Ssam OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 1469185377Ssam OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 1470185377Ssam 1471187831Ssam return (ichan->rawNoiseFloor = nf); 1472185377Ssam} 1473185377Ssam 1474185377Ssam/* 1475185377Ssam * Set up compression configuration registers 1476185377Ssam */ 1477185377Ssamvoid 1478185377Ssamar5212SetCompRegs(struct ath_hal *ah) 1479185377Ssam{ 1480185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 1481185377Ssam int i; 1482185377Ssam 1483185377Ssam /* Check if h/w supports compression */ 1484185377Ssam if (!AH_PRIVATE(ah)->ah_caps.halCompressSupport) 1485185377Ssam return; 1486185377Ssam 1487185377Ssam OS_REG_WRITE(ah, AR_DCCFG, 1); 1488185377Ssam 1489185377Ssam OS_REG_WRITE(ah, AR_CCFG, 1490185377Ssam (AR_COMPRESSION_WINDOW_SIZE >> 8) & AR_CCFG_WIN_M); 1491185377Ssam 1492185377Ssam OS_REG_WRITE(ah, AR_CCFG, 1493185377Ssam OS_REG_READ(ah, AR_CCFG) | AR_CCFG_MIB_INT_EN); 1494185377Ssam OS_REG_WRITE(ah, AR_CCUCFG, 1495185377Ssam AR_CCUCFG_RESET_VAL | AR_CCUCFG_CATCHUP_EN); 1496185377Ssam 1497185377Ssam OS_REG_WRITE(ah, AR_CPCOVF, 0); 1498185377Ssam 1499185377Ssam /* reset decompression mask */ 1500185377Ssam for (i = 0; i < HAL_DECOMP_MASK_SIZE; i++) { 1501185377Ssam OS_REG_WRITE(ah, AR_DCM_A, i); 1502185377Ssam OS_REG_WRITE(ah, AR_DCM_D, ahp->ah_decompMask[i]); 1503185377Ssam } 1504185377Ssam} 1505185377Ssam 1506185377SsamHAL_BOOL 1507185377Ssamar5212SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings, 1508187831Ssam const struct ieee80211_channel *chan) 1509185377Ssam{ 1510185377Ssam#define ANT_SWITCH_TABLE1 AR_PHY(88) 1511185377Ssam#define ANT_SWITCH_TABLE2 AR_PHY(89) 1512185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 1513185377Ssam const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1514185377Ssam uint32_t antSwitchA, antSwitchB; 1515185377Ssam int ix; 1516185377Ssam 1517185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 1518185380Ssam HALASSERT(ahp->ah_phyPowerOn); 1519185377Ssam 1520187831Ssam switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 1521187831Ssam case IEEE80211_CHAN_A: 1522187831Ssam ix = 0; 1523187831Ssam break; 1524187831Ssam case IEEE80211_CHAN_G: 1525187831Ssam case IEEE80211_CHAN_PUREG: /* NB: 108G */ 1526187831Ssam ix = 2; 1527187831Ssam break; 1528187831Ssam case IEEE80211_CHAN_B: 1529187831Ssam if (IS_2425(ah) || IS_2417(ah)) { 1530187831Ssam /* NB: Nala/Swan: 11b is handled using 11g */ 1531187831Ssam ix = 2; 1532187831Ssam } else 1533187831Ssam ix = 1; 1534187831Ssam break; 1535185377Ssam default: 1536185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1537187831Ssam __func__, chan->ic_flags); 1538185377Ssam return AH_FALSE; 1539185377Ssam } 1540185377Ssam 1541185377Ssam antSwitchA = ee->ee_antennaControl[1][ix] 1542185377Ssam | (ee->ee_antennaControl[2][ix] << 6) 1543185377Ssam | (ee->ee_antennaControl[3][ix] << 12) 1544185377Ssam | (ee->ee_antennaControl[4][ix] << 18) 1545185377Ssam | (ee->ee_antennaControl[5][ix] << 24) 1546185377Ssam ; 1547185377Ssam antSwitchB = ee->ee_antennaControl[6][ix] 1548185377Ssam | (ee->ee_antennaControl[7][ix] << 6) 1549185377Ssam | (ee->ee_antennaControl[8][ix] << 12) 1550185377Ssam | (ee->ee_antennaControl[9][ix] << 18) 1551185377Ssam | (ee->ee_antennaControl[10][ix] << 24) 1552185377Ssam ; 1553185377Ssam /* 1554185377Ssam * For fixed antenna, give the same setting for both switch banks 1555185377Ssam */ 1556185377Ssam switch (settings) { 1557185377Ssam case HAL_ANT_FIXED_A: 1558185377Ssam antSwitchB = antSwitchA; 1559185377Ssam break; 1560185377Ssam case HAL_ANT_FIXED_B: 1561185377Ssam antSwitchA = antSwitchB; 1562185377Ssam break; 1563185377Ssam case HAL_ANT_VARIABLE: 1564185377Ssam break; 1565185377Ssam default: 1566185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n", 1567185377Ssam __func__, settings); 1568185377Ssam return AH_FALSE; 1569185377Ssam } 1570185377Ssam if (antSwitchB == antSwitchA) { 1571185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 1572185377Ssam "%s: Setting fast diversity off.\n", __func__); 1573185377Ssam OS_REG_CLR_BIT(ah,AR_PHY_CCK_DETECT, 1574185377Ssam AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1575185380Ssam ahp->ah_diversity = AH_FALSE; 1576185377Ssam } else { 1577185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 1578185377Ssam "%s: Setting fast diversity on.\n", __func__); 1579185377Ssam OS_REG_SET_BIT(ah,AR_PHY_CCK_DETECT, 1580185377Ssam AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1581185380Ssam ahp->ah_diversity = AH_TRUE; 1582185377Ssam } 1583185380Ssam ahp->ah_antControl = settings; 1584185377Ssam 1585185377Ssam OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA); 1586185377Ssam OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB); 1587185377Ssam 1588185377Ssam return AH_TRUE; 1589185377Ssam#undef ANT_SWITCH_TABLE2 1590185377Ssam#undef ANT_SWITCH_TABLE1 1591185377Ssam} 1592185377Ssam 1593185377SsamHAL_BOOL 1594187831Ssamar5212IsSpurChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 1595185377Ssam{ 1596187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 1597187831Ssam uint32_t clockFreq = 1598187831Ssam ((IS_5413(ah) || IS_RAD5112_ANY(ah) || IS_2417(ah)) ? 40 : 32); 1599187831Ssam return ( ((freq % clockFreq) != 0) 1600187831Ssam && (((freq % clockFreq) < 10) 1601187831Ssam || (((freq) % clockFreq) > 22)) ); 1602185377Ssam} 1603185377Ssam 1604185377Ssam/* 1605185377Ssam * Read EEPROM header info and program the device for correct operation 1606185377Ssam * given the channel value. 1607185377Ssam */ 1608185377SsamHAL_BOOL 1609187831Ssamar5212SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 1610185377Ssam{ 1611185377Ssam#define NO_FALSE_DETECT_BACKOFF 2 1612185377Ssam#define CB22_FALSE_DETECT_BACKOFF 6 1613185377Ssam#define AR_PHY_BIS(_ah, _reg, _mask, _val) \ 1614185377Ssam OS_REG_WRITE(_ah, AR_PHY(_reg), \ 1615185377Ssam (OS_REG_READ(_ah, AR_PHY(_reg)) & _mask) | (_val)); 1616185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 1617185377Ssam const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1618185377Ssam int arrayMode, falseDectectBackoff; 1619187831Ssam int is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 1620187831Ssam HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 1621185377Ssam int8_t adcDesiredSize, pgaDesiredSize; 1622185377Ssam uint16_t switchSettling, txrxAtten, rxtxMargin; 1623185377Ssam int iCoff, qCoff; 1624185377Ssam 1625185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 1626185377Ssam 1627187831Ssam switch (chan->ic_flags & IEEE80211_CHAN_ALLTURBOFULL) { 1628187831Ssam case IEEE80211_CHAN_A: 1629187831Ssam case IEEE80211_CHAN_ST: 1630185377Ssam arrayMode = headerInfo11A; 1631185380Ssam if (!IS_RAD5112_ANY(ah) && !IS_2413(ah) && !IS_5413(ah)) 1632185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 1633185377Ssam AR_PHY_FRAME_CTL_TX_CLIP, 1634185377Ssam ahp->ah_gainValues.currStep->paramVal[GP_TXCLIP]); 1635185377Ssam break; 1636187831Ssam case IEEE80211_CHAN_B: 1637185377Ssam arrayMode = headerInfo11B; 1638185377Ssam break; 1639187831Ssam case IEEE80211_CHAN_G: 1640187831Ssam case IEEE80211_CHAN_108G: 1641185377Ssam arrayMode = headerInfo11G; 1642185377Ssam break; 1643185377Ssam default: 1644185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1645187831Ssam __func__, chan->ic_flags); 1646185377Ssam return AH_FALSE; 1647185377Ssam } 1648185377Ssam 1649185377Ssam /* Set the antenna register(s) correctly for the chip revision */ 1650185377Ssam AR_PHY_BIS(ah, 68, 0xFFFFFC06, 1651185377Ssam (ee->ee_antennaControl[0][arrayMode] << 4) | 0x1); 1652185377Ssam 1653185380Ssam ar5212SetAntennaSwitchInternal(ah, ahp->ah_antControl, chan); 1654185377Ssam 1655185377Ssam /* Set the Noise Floor Thresh on ar5211 devices */ 1656185377Ssam OS_REG_WRITE(ah, AR_PHY(90), 1657185377Ssam (ee->ee_noiseFloorThresh[arrayMode] & 0x1FF) 1658185377Ssam | (1 << 9)); 1659185377Ssam 1660187831Ssam if (ee->ee_version >= AR_EEPROM_VER5_0 && IEEE80211_IS_CHAN_TURBO(chan)) { 1661185377Ssam switchSettling = ee->ee_switchSettlingTurbo[is2GHz]; 1662185377Ssam adcDesiredSize = ee->ee_adcDesiredSizeTurbo[is2GHz]; 1663185377Ssam pgaDesiredSize = ee->ee_pgaDesiredSizeTurbo[is2GHz]; 1664185377Ssam txrxAtten = ee->ee_txrxAttenTurbo[is2GHz]; 1665185377Ssam rxtxMargin = ee->ee_rxtxMarginTurbo[is2GHz]; 1666185377Ssam } else { 1667185377Ssam switchSettling = ee->ee_switchSettling[arrayMode]; 1668185377Ssam adcDesiredSize = ee->ee_adcDesiredSize[arrayMode]; 1669185377Ssam pgaDesiredSize = ee->ee_pgaDesiredSize[is2GHz]; 1670185377Ssam txrxAtten = ee->ee_txrxAtten[is2GHz]; 1671185377Ssam rxtxMargin = ee->ee_rxtxMargin[is2GHz]; 1672185377Ssam } 1673185377Ssam 1674185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 1675185377Ssam AR_PHY_SETTLING_SWITCH, switchSettling); 1676185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 1677185377Ssam AR_PHY_DESIRED_SZ_ADC, adcDesiredSize); 1678185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 1679185377Ssam AR_PHY_DESIRED_SZ_PGA, pgaDesiredSize); 1680185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 1681185377Ssam AR_PHY_RXGAIN_TXRX_ATTEN, txrxAtten); 1682185377Ssam OS_REG_WRITE(ah, AR_PHY(13), 1683185377Ssam (ee->ee_txEndToXPAOff[arrayMode] << 24) 1684185377Ssam | (ee->ee_txEndToXPAOff[arrayMode] << 16) 1685185377Ssam | (ee->ee_txFrameToXPAOn[arrayMode] << 8) 1686185377Ssam | ee->ee_txFrameToXPAOn[arrayMode]); 1687185377Ssam AR_PHY_BIS(ah, 10, 0xFFFF00FF, 1688185377Ssam ee->ee_txEndToXLNAOn[arrayMode] << 8); 1689185377Ssam AR_PHY_BIS(ah, 25, 0xFFF80FFF, 1690185377Ssam (ee->ee_thresh62[arrayMode] << 12) & 0x7F000); 1691185377Ssam 1692185377Ssam /* 1693185377Ssam * False detect backoff - suspected 32 MHz spur causes false 1694185377Ssam * detects in OFDM, causing Tx Hangs. Decrease weak signal 1695185377Ssam * sensitivity for this card. 1696185377Ssam */ 1697185377Ssam falseDectectBackoff = NO_FALSE_DETECT_BACKOFF; 1698185377Ssam if (ee->ee_version < AR_EEPROM_VER3_3) { 1699185377Ssam /* XXX magic number */ 1700185377Ssam if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 && 1701187831Ssam IEEE80211_IS_CHAN_OFDM(chan)) 1702185377Ssam falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF; 1703185377Ssam } else { 1704187831Ssam if (ar5212IsSpurChannel(ah, chan)) 1705185377Ssam falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode]; 1706185377Ssam } 1707185377Ssam AR_PHY_BIS(ah, 73, 0xFFFFFF01, (falseDectectBackoff << 1) & 0xFE); 1708185377Ssam 1709187831Ssam if (ichan->privFlags & CHANNEL_IQVALID) { 1710187831Ssam iCoff = ichan->iCoff; 1711187831Ssam qCoff = ichan->qCoff; 1712185377Ssam } else { 1713185377Ssam iCoff = ee->ee_iqCalI[is2GHz]; 1714185377Ssam qCoff = ee->ee_iqCalQ[is2GHz]; 1715185377Ssam } 1716185377Ssam 1717185377Ssam /* write previous IQ results */ 1718185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1719185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff); 1720185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1721185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff); 1722185377Ssam OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1723185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 1724185377Ssam 1725185377Ssam if (ee->ee_version >= AR_EEPROM_VER4_1) { 1726187831Ssam if (!IEEE80211_IS_CHAN_108G(chan) || ee->ee_version >= AR_EEPROM_VER5_0) 1727185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 1728185377Ssam AR_PHY_GAIN_2GHZ_RXTX_MARGIN, rxtxMargin); 1729185377Ssam } 1730185377Ssam if (ee->ee_version >= AR_EEPROM_VER5_1) { 1731185377Ssam /* for now always disabled */ 1732185377Ssam OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_ENABLE, 0); 1733185377Ssam } 1734185377Ssam 1735185377Ssam return AH_TRUE; 1736185377Ssam#undef AR_PHY_BIS 1737185377Ssam#undef NO_FALSE_DETECT_BACKOFF 1738185377Ssam#undef CB22_FALSE_DETECT_BACKOFF 1739185377Ssam} 1740185377Ssam 1741185377Ssam/* 1742185377Ssam * Apply Spur Immunity to Boards that require it. 1743185377Ssam * Applies only to OFDM RX operation. 1744185377Ssam */ 1745185377Ssam 1746185377Ssamvoid 1747187831Ssamar5212SetSpurMitigation(struct ath_hal *ah, 1748187831Ssam const struct ieee80211_channel *chan) 1749185377Ssam{ 1750185377Ssam uint32_t pilotMask[2] = {0, 0}, binMagMask[4] = {0, 0, 0 , 0}; 1751185377Ssam uint16_t i, finalSpur, curChanAsSpur, binWidth = 0, spurDetectWidth, spurChan; 1752185377Ssam int32_t spurDeltaPhase = 0, spurFreqSd = 0, spurOffset, binOffsetNumT16, curBinOffset; 1753185377Ssam int16_t numBinOffsets; 1754185377Ssam static const uint16_t magMapFor4[4] = {1, 2, 2, 1}; 1755185377Ssam static const uint16_t magMapFor3[3] = {1, 2, 1}; 1756185377Ssam const uint16_t *pMagMap; 1757187831Ssam HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 1758187831Ssam HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 1759185377Ssam uint32_t val; 1760185377Ssam 1761185377Ssam#define CHAN_TO_SPUR(_f, _freq) ( ((_freq) - ((_f) ? 2300 : 4900)) * 10 ) 1762185377Ssam if (IS_2417(ah)) { 1763185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: no spur mitigation\n", 1764185377Ssam __func__); 1765185377Ssam return; 1766185377Ssam } 1767185377Ssam 1768185377Ssam curChanAsSpur = CHAN_TO_SPUR(is2GHz, ichan->channel); 1769185377Ssam 1770185377Ssam if (ichan->mainSpur) { 1771185377Ssam /* Pull out the saved spur value */ 1772185377Ssam finalSpur = ichan->mainSpur; 1773185377Ssam } else { 1774185377Ssam /* 1775185377Ssam * Check if spur immunity should be performed for this channel 1776185377Ssam * Should only be performed once per channel and then saved 1777185377Ssam */ 1778185377Ssam finalSpur = AR_NO_SPUR; 1779185377Ssam spurDetectWidth = HAL_SPUR_CHAN_WIDTH; 1780187831Ssam if (IEEE80211_IS_CHAN_TURBO(chan)) 1781185377Ssam spurDetectWidth *= 2; 1782185377Ssam 1783185377Ssam /* Decide if any spur affects the current channel */ 1784185377Ssam for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 1785185377Ssam spurChan = ath_hal_getSpurChan(ah, i, is2GHz); 1786185377Ssam if (spurChan == AR_NO_SPUR) { 1787185377Ssam break; 1788185377Ssam } 1789185377Ssam if ((curChanAsSpur - spurDetectWidth <= (spurChan & HAL_SPUR_VAL_MASK)) && 1790185377Ssam (curChanAsSpur + spurDetectWidth >= (spurChan & HAL_SPUR_VAL_MASK))) { 1791185377Ssam finalSpur = spurChan & HAL_SPUR_VAL_MASK; 1792185377Ssam break; 1793185377Ssam } 1794185377Ssam } 1795185377Ssam /* Save detected spur (or no spur) for this channel */ 1796185377Ssam ichan->mainSpur = finalSpur; 1797185377Ssam } 1798185377Ssam 1799185377Ssam /* Write spur immunity data */ 1800185377Ssam if (finalSpur == AR_NO_SPUR) { 1801185377Ssam /* Disable Spur Immunity Regs if they appear set */ 1802185377Ssam if (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER) { 1803185377Ssam /* Clear Spur Delta Phase, Spur Freq, and enable bits */ 1804185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0); 1805185377Ssam val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4); 1806185377Ssam val &= ~(AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 1807185377Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 1808185377Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 1809185377Ssam OS_REG_WRITE(ah, AR_PHY_MASK_CTL, val); 1810185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, 0); 1811185377Ssam 1812185377Ssam /* Clear pilot masks */ 1813185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING7, 0); 1814185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, 0); 1815185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING9, 0); 1816185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, 0); 1817185377Ssam 1818185377Ssam /* Clear magnitude masks */ 1819185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, 0); 1820185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, 0); 1821185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, 0); 1822185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, 0); 1823185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, 0); 1824185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, 0); 1825185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, 0); 1826185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, 0); 1827185377Ssam } 1828185377Ssam } else { 1829185377Ssam spurOffset = finalSpur - curChanAsSpur; 1830185377Ssam /* 1831185377Ssam * Spur calculations: 1832185377Ssam * spurDeltaPhase is (spurOffsetIn100KHz / chipFrequencyIn100KHz) << 21 1833185377Ssam * spurFreqSd is (spurOffsetIn100KHz / sampleFrequencyIn100KHz) << 11 1834185377Ssam */ 1835187831Ssam if (IEEE80211_IS_CHAN_TURBO(chan)) { 1836187831Ssam /* Chip Frequency & sampleFrequency are 80 MHz */ 1837187831Ssam spurDeltaPhase = (spurOffset << 16) / 25; 1838185377Ssam spurFreqSd = spurDeltaPhase >> 10; 1839187831Ssam binWidth = HAL_BIN_WIDTH_TURBO_100HZ; 1840187831Ssam } else if (IEEE80211_IS_CHAN_G(chan)) { 1841187831Ssam /* Chip Frequency is 44MHz, sampleFrequency is 40 MHz */ 1842185377Ssam spurFreqSd = (spurOffset << 8) / 55; 1843185377Ssam spurDeltaPhase = (spurOffset << 17) / 25; 1844185377Ssam binWidth = HAL_BIN_WIDTH_BASE_100HZ; 1845187831Ssam } else { 1846187831Ssam HALASSERT(!IEEE80211_IS_CHAN_B(chan)); 1847187831Ssam /* Chip Frequency & sampleFrequency are 40 MHz */ 1848187831Ssam spurDeltaPhase = (spurOffset << 17) / 25; 1849185377Ssam spurFreqSd = spurDeltaPhase >> 10; 1850187831Ssam binWidth = HAL_BIN_WIDTH_BASE_100HZ; 1851185377Ssam } 1852185377Ssam 1853185377Ssam /* Compute Pilot Mask */ 1854185377Ssam binOffsetNumT16 = ((spurOffset * 1000) << 4) / binWidth; 1855185377Ssam /* The spur is on a bin if it's remainder at times 16 is 0 */ 1856185377Ssam if (binOffsetNumT16 & 0xF) { 1857185377Ssam numBinOffsets = 4; 1858185377Ssam pMagMap = magMapFor4; 1859185377Ssam } else { 1860185377Ssam numBinOffsets = 3; 1861185377Ssam pMagMap = magMapFor3; 1862185377Ssam } 1863185377Ssam for (i = 0; i < numBinOffsets; i++) { 1864185377Ssam if ((binOffsetNumT16 >> 4) > HAL_MAX_BINS_ALLOWED) { 1865185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 1866185377Ssam "Too man bins in spur mitigation\n"); 1867185377Ssam return; 1868185377Ssam } 1869185377Ssam 1870185377Ssam /* Get Pilot Mask values */ 1871185377Ssam curBinOffset = (binOffsetNumT16 >> 4) + i + 25; 1872185377Ssam if ((curBinOffset >= 0) && (curBinOffset <= 32)) { 1873185377Ssam if (curBinOffset <= 25) 1874185377Ssam pilotMask[0] |= 1 << curBinOffset; 1875185377Ssam else if (curBinOffset >= 27) 1876185377Ssam pilotMask[0] |= 1 << (curBinOffset - 1); 1877185377Ssam } else if ((curBinOffset >= 33) && (curBinOffset <= 52)) 1878185377Ssam pilotMask[1] |= 1 << (curBinOffset - 33); 1879185377Ssam 1880185377Ssam /* Get viterbi values */ 1881185377Ssam if ((curBinOffset >= -1) && (curBinOffset <= 14)) 1882185377Ssam binMagMask[0] |= pMagMap[i] << (curBinOffset + 1) * 2; 1883185377Ssam else if ((curBinOffset >= 15) && (curBinOffset <= 30)) 1884185377Ssam binMagMask[1] |= pMagMap[i] << (curBinOffset - 15) * 2; 1885185377Ssam else if ((curBinOffset >= 31) && (curBinOffset <= 46)) 1886185377Ssam binMagMask[2] |= pMagMap[i] << (curBinOffset -31) * 2; 1887185377Ssam else if((curBinOffset >= 47) && (curBinOffset <= 53)) 1888185377Ssam binMagMask[3] |= pMagMap[i] << (curBinOffset -47) * 2; 1889185377Ssam } 1890185377Ssam 1891185377Ssam /* Write Spur Delta Phase, Spur Freq, and enable bits */ 1892185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0xFF); 1893185377Ssam val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4); 1894185377Ssam val |= (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 1895185377Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 1896185377Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 1897185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, val); 1898185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_USE_SPUR_IN_AGC | 1899185377Ssam SM(spurFreqSd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 1900185377Ssam SM(spurDeltaPhase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 1901185377Ssam 1902185377Ssam /* Write pilot masks */ 1903185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING7, pilotMask[0]); 1904185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, pilotMask[1]); 1905185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING9, pilotMask[0]); 1906185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, pilotMask[1]); 1907185377Ssam 1908185377Ssam /* Write magnitude masks */ 1909185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, binMagMask[0]); 1910185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, binMagMask[1]); 1911185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, binMagMask[2]); 1912185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, binMagMask[3]); 1913185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, binMagMask[0]); 1914185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, binMagMask[1]); 1915185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, binMagMask[2]); 1916185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, binMagMask[3]); 1917185377Ssam } 1918185377Ssam#undef CHAN_TO_SPUR 1919185377Ssam} 1920185377Ssam 1921185377Ssam 1922185377Ssam/* 1923185377Ssam * Delta slope coefficient computation. 1924185377Ssam * Required for OFDM operation. 1925185377Ssam */ 1926185377Ssamvoid 1927187831Ssamar5212SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan) 1928185377Ssam{ 1929185377Ssam#define COEF_SCALE_S 24 1930185377Ssam#define INIT_CLOCKMHZSCALED 0x64000000 1931187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 1932185377Ssam unsigned long coef_scaled, coef_exp, coef_man, ds_coef_exp, ds_coef_man; 1933185377Ssam unsigned long clockMhzScaled = INIT_CLOCKMHZSCALED; 1934185377Ssam 1935187831Ssam if (IEEE80211_IS_CHAN_TURBO(chan)) 1936185377Ssam clockMhzScaled *= 2; 1937185377Ssam /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */ 1938185377Ssam /* scale for selected channel bandwidth */ 1939187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) { 1940185377Ssam clockMhzScaled = clockMhzScaled >> 1; 1941187831Ssam } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 1942185377Ssam clockMhzScaled = clockMhzScaled >> 2; 1943185377Ssam } 1944185377Ssam 1945185377Ssam /* 1946185377Ssam * ALGO -> coef = 1e8/fcarrier*fclock/40; 1947185377Ssam * scaled coef to provide precision for this floating calculation 1948185377Ssam */ 1949187831Ssam coef_scaled = clockMhzScaled / freq; 1950185377Ssam 1951185377Ssam /* 1952185377Ssam * ALGO -> coef_exp = 14-floor(log2(coef)); 1953185377Ssam * floor(log2(x)) is the highest set bit position 1954185377Ssam */ 1955185377Ssam for (coef_exp = 31; coef_exp > 0; coef_exp--) 1956185377Ssam if ((coef_scaled >> coef_exp) & 0x1) 1957185377Ssam break; 1958185377Ssam /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */ 1959185377Ssam HALASSERT(coef_exp); 1960185377Ssam coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1961185377Ssam 1962185377Ssam /* 1963185377Ssam * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5); 1964185377Ssam * The coefficient is already shifted up for scaling 1965185377Ssam */ 1966185377Ssam coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1967185377Ssam ds_coef_man = coef_man >> (COEF_SCALE_S - coef_exp); 1968185377Ssam ds_coef_exp = coef_exp - 16; 1969185377Ssam 1970185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1971185377Ssam AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 1972185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1973185377Ssam AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 1974185377Ssam#undef INIT_CLOCKMHZSCALED 1975185377Ssam#undef COEF_SCALE_S 1976185377Ssam} 1977185377Ssam 1978185377Ssam/* 1979185377Ssam * Set a limit on the overall output power. Used for dynamic 1980185377Ssam * transmit power control and the like. 1981185377Ssam * 1982185377Ssam * NB: limit is in units of 0.5 dbM. 1983185377Ssam */ 1984185377SsamHAL_BOOL 1985185377Ssamar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 1986185377Ssam{ 1987187831Ssam /* XXX blech, construct local writable copy */ 1988187831Ssam struct ieee80211_channel dummy = *AH_PRIVATE(ah)->ah_curchan; 1989185377Ssam uint16_t dummyXpdGains[2]; 1990187831Ssam HAL_BOOL isBmode; 1991185377Ssam 1992187831Ssam SAVE_CCK(ah, &dummy, isBmode); 1993185377Ssam AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); 1994187831Ssam return ar5212SetTransmitPower(ah, &dummy, dummyXpdGains); 1995185377Ssam} 1996185377Ssam 1997185377Ssam/* 1998185377Ssam * Set the transmit power in the baseband for the given 1999185377Ssam * operating channel and mode. 2000185377Ssam */ 2001185377SsamHAL_BOOL 2002187831Ssamar5212SetTransmitPower(struct ath_hal *ah, 2003187831Ssam const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 2004185377Ssam{ 2005185377Ssam#define POW_OFDM(_r, _s) (((0 & 1)<< ((_s)+6)) | (((_r) & 0x3f) << (_s))) 2006185377Ssam#define POW_CCK(_r, _s) (((_r) & 0x3f) << (_s)) 2007185377Ssam#define N(a) (sizeof (a) / sizeof (a[0])) 2008185377Ssam static const uint16_t tpcScaleReductionTable[5] = 2009185377Ssam { 0, 3, 6, 9, MAX_RATE_POWER }; 2010185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 2011187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 2012185377Ssam const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 2013185377Ssam int16_t minPower, maxPower, tpcInDb, powerLimit; 2014185377Ssam int i; 2015185377Ssam 2016185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 2017185377Ssam 2018185377Ssam OS_MEMZERO(ahp->ah_pcdacTable, ahp->ah_pcdacTableSize); 2019185377Ssam OS_MEMZERO(ahp->ah_ratesArray, sizeof(ahp->ah_ratesArray)); 2020185377Ssam 2021185377Ssam powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 2022185377Ssam if (powerLimit >= MAX_RATE_POWER || powerLimit == 0) 2023185377Ssam tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 2024185377Ssam else 2025185377Ssam tpcInDb = 0; 2026187831Ssam if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit, 2027185377Ssam AH_TRUE, &minPower, &maxPower)) { 2028185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set rate table\n", 2029185377Ssam __func__); 2030185377Ssam return AH_FALSE; 2031185377Ssam } 2032185377Ssam if (!ahp->ah_rfHal->setPowerTable(ah, 2033185377Ssam &minPower, &maxPower, chan, rfXpdGain)) { 2034185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 2035185377Ssam __func__); 2036185377Ssam return AH_FALSE; 2037185377Ssam } 2038185377Ssam 2039185377Ssam /* 2040185377Ssam * Adjust XR power/rate up by 2 dB to account for greater peak 2041185377Ssam * to avg ratio - except in newer avg power designs 2042185377Ssam */ 2043185377Ssam if (!IS_2413(ah) && !IS_5413(ah)) 2044185377Ssam ahp->ah_ratesArray[15] += 4; 2045185377Ssam /* 2046185377Ssam * txPowerIndexOffset is set by the SetPowerTable() call - 2047185377Ssam * adjust the rate table 2048185377Ssam */ 2049185377Ssam for (i = 0; i < N(ahp->ah_ratesArray); i++) { 2050185377Ssam ahp->ah_ratesArray[i] += ahp->ah_txPowerIndexOffset; 2051185377Ssam if (ahp->ah_ratesArray[i] > 63) 2052185377Ssam ahp->ah_ratesArray[i] = 63; 2053185377Ssam } 2054185377Ssam 2055185377Ssam if (ee->ee_eepMap < 2) { 2056185377Ssam /* 2057185377Ssam * Correct gain deltas for 5212 G operation - 2058185377Ssam * Removed with revised chipset 2059185377Ssam */ 2060185377Ssam if (AH_PRIVATE(ah)->ah_phyRev < AR_PHY_CHIP_ID_REV_2 && 2061187831Ssam IEEE80211_IS_CHAN_G(chan)) { 2062185377Ssam uint16_t cckOfdmPwrDelta; 2063185377Ssam 2064187831Ssam if (freq == 2484) 2065185377Ssam cckOfdmPwrDelta = SCALE_OC_DELTA( 2066185377Ssam ee->ee_cckOfdmPwrDelta - 2067185377Ssam ee->ee_scaledCh14FilterCckDelta); 2068185377Ssam else 2069185377Ssam cckOfdmPwrDelta = SCALE_OC_DELTA( 2070185377Ssam ee->ee_cckOfdmPwrDelta); 2071185377Ssam ar5212CorrectGainDelta(ah, cckOfdmPwrDelta); 2072185377Ssam } 2073185377Ssam /* 2074185377Ssam * Finally, write the power values into the 2075185377Ssam * baseband power table 2076185377Ssam */ 2077185377Ssam for (i = 0; i < (PWR_TABLE_SIZE/2); i++) { 2078185377Ssam OS_REG_WRITE(ah, AR_PHY_PCDAC_TX_POWER(i), 2079185377Ssam ((((ahp->ah_pcdacTable[2*i + 1] << 8) | 0xff) & 0xffff) << 16) 2080185377Ssam | (((ahp->ah_pcdacTable[2*i] << 8) | 0xff) & 0xffff) 2081185377Ssam ); 2082185377Ssam } 2083185377Ssam } 2084185377Ssam 2085185377Ssam /* Write the OFDM power per rate set */ 2086185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 2087185377Ssam POW_OFDM(ahp->ah_ratesArray[3], 24) 2088185377Ssam | POW_OFDM(ahp->ah_ratesArray[2], 16) 2089185377Ssam | POW_OFDM(ahp->ah_ratesArray[1], 8) 2090185377Ssam | POW_OFDM(ahp->ah_ratesArray[0], 0) 2091185377Ssam ); 2092185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 2093185377Ssam POW_OFDM(ahp->ah_ratesArray[7], 24) 2094185377Ssam | POW_OFDM(ahp->ah_ratesArray[6], 16) 2095185377Ssam | POW_OFDM(ahp->ah_ratesArray[5], 8) 2096185377Ssam | POW_OFDM(ahp->ah_ratesArray[4], 0) 2097185377Ssam ); 2098185377Ssam 2099185377Ssam /* Write the CCK power per rate set */ 2100185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 2101185377Ssam POW_CCK(ahp->ah_ratesArray[10], 24) 2102185377Ssam | POW_CCK(ahp->ah_ratesArray[9], 16) 2103185377Ssam | POW_CCK(ahp->ah_ratesArray[15], 8) /* XR target power */ 2104185377Ssam | POW_CCK(ahp->ah_ratesArray[8], 0) 2105185377Ssam ); 2106185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 2107185377Ssam POW_CCK(ahp->ah_ratesArray[14], 24) 2108185377Ssam | POW_CCK(ahp->ah_ratesArray[13], 16) 2109185377Ssam | POW_CCK(ahp->ah_ratesArray[12], 8) 2110185377Ssam | POW_CCK(ahp->ah_ratesArray[11], 0) 2111185377Ssam ); 2112185377Ssam 2113185377Ssam /* 2114185377Ssam * Set max power to 30 dBm and, optionally, 2115185377Ssam * enable TPC in tx descriptors. 2116185377Ssam */ 2117185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER | 2118185377Ssam (ahp->ah_tpcEnabled ? AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE : 0)); 2119185377Ssam 2120185377Ssam return AH_TRUE; 2121185377Ssam#undef N 2122185377Ssam#undef POW_CCK 2123185377Ssam#undef POW_OFDM 2124185377Ssam} 2125185377Ssam 2126185377Ssam/* 2127185377Ssam * Sets the transmit power in the baseband for the given 2128185377Ssam * operating channel and mode. 2129185377Ssam */ 2130185377Ssamstatic HAL_BOOL 2131187831Ssamar5212SetRateTable(struct ath_hal *ah, const struct ieee80211_channel *chan, 2132187831Ssam int16_t tpcScaleReduction, int16_t powerLimit, HAL_BOOL commit, 2133187831Ssam int16_t *pMinPower, int16_t *pMaxPower) 2134185377Ssam{ 2135185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 2136187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 2137185377Ssam const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 2138185377Ssam uint16_t *rpow = ahp->ah_ratesArray; 2139185377Ssam uint16_t twiceMaxEdgePower = MAX_RATE_POWER; 2140185377Ssam uint16_t twiceMaxEdgePowerCck = MAX_RATE_POWER; 2141185377Ssam uint16_t twiceMaxRDPower = MAX_RATE_POWER; 2142185377Ssam int i; 2143185377Ssam uint8_t cfgCtl; 2144185377Ssam int8_t twiceAntennaGain, twiceAntennaReduction; 2145185377Ssam const RD_EDGES_POWER *rep; 2146185377Ssam TRGT_POWER_INFO targetPowerOfdm, targetPowerCck; 2147185377Ssam int16_t scaledPower, maxAvailPower = 0; 2148185377Ssam int16_t r13, r9, r7, r0; 2149185377Ssam 2150185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 2151185377Ssam 2152187831Ssam twiceMaxRDPower = chan->ic_maxregpower * 2; 2153185377Ssam *pMaxPower = -MAX_RATE_POWER; 2154185377Ssam *pMinPower = MAX_RATE_POWER; 2155185377Ssam 2156185377Ssam /* Get conformance test limit maximum for this channel */ 2157185377Ssam cfgCtl = ath_hal_getctl(ah, chan); 2158185377Ssam for (i = 0; i < ee->ee_numCtls; i++) { 2159185377Ssam uint16_t twiceMinEdgePower; 2160185377Ssam 2161185377Ssam if (ee->ee_ctl[i] == 0) 2162185377Ssam continue; 2163185377Ssam if (ee->ee_ctl[i] == cfgCtl || 2164185377Ssam cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) { 2165185377Ssam rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 2166187831Ssam twiceMinEdgePower = ar5212GetMaxEdgePower(freq, rep); 2167185377Ssam if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 2168185377Ssam /* Find the minimum of all CTL edge powers that apply to this channel */ 2169185377Ssam twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 2170185377Ssam } else { 2171185377Ssam twiceMaxEdgePower = twiceMinEdgePower; 2172185377Ssam break; 2173185377Ssam } 2174185377Ssam } 2175185377Ssam } 2176185377Ssam 2177187831Ssam if (IEEE80211_IS_CHAN_G(chan)) { 2178185377Ssam /* Check for a CCK CTL for 11G CCK powers */ 2179185377Ssam cfgCtl = (cfgCtl & ~CTL_MODE_M) | CTL_11B; 2180185377Ssam for (i = 0; i < ee->ee_numCtls; i++) { 2181185377Ssam uint16_t twiceMinEdgePowerCck; 2182185377Ssam 2183185377Ssam if (ee->ee_ctl[i] == 0) 2184185377Ssam continue; 2185185377Ssam if (ee->ee_ctl[i] == cfgCtl || 2186185377Ssam cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) { 2187185377Ssam rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 2188187831Ssam twiceMinEdgePowerCck = ar5212GetMaxEdgePower(freq, rep); 2189185377Ssam if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 2190185377Ssam /* Find the minimum of all CTL edge powers that apply to this channel */ 2191185377Ssam twiceMaxEdgePowerCck = AH_MIN(twiceMaxEdgePowerCck, twiceMinEdgePowerCck); 2192185377Ssam } else { 2193185377Ssam twiceMaxEdgePowerCck = twiceMinEdgePowerCck; 2194185377Ssam break; 2195185377Ssam } 2196185377Ssam } 2197185377Ssam } 2198185377Ssam } else { 2199185377Ssam /* Set the 11B cck edge power to the one found before */ 2200185377Ssam twiceMaxEdgePowerCck = twiceMaxEdgePower; 2201185377Ssam } 2202185377Ssam 2203185377Ssam /* Get Antenna Gain reduction */ 2204187831Ssam if (IEEE80211_IS_CHAN_5GHZ(chan)) { 2205185377Ssam ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain); 2206185377Ssam } else { 2207185377Ssam ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain); 2208185377Ssam } 2209185377Ssam twiceAntennaReduction = 2210185377Ssam ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 2211185377Ssam 2212187831Ssam if (IEEE80211_IS_CHAN_OFDM(chan)) { 2213185377Ssam /* Get final OFDM target powers */ 2214187831Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 2215185377Ssam ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11g, 2216185377Ssam ee->ee_numTargetPwr_11g, &targetPowerOfdm); 2217185377Ssam } else { 2218185377Ssam ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11a, 2219185377Ssam ee->ee_numTargetPwr_11a, &targetPowerOfdm); 2220185377Ssam } 2221185377Ssam 2222185377Ssam /* Get Maximum OFDM power */ 2223185377Ssam /* Minimum of target and edge powers */ 2224185377Ssam scaledPower = AH_MIN(twiceMaxEdgePower, 2225185377Ssam twiceMaxRDPower - twiceAntennaReduction); 2226185377Ssam 2227185377Ssam /* 2228185377Ssam * If turbo is set, reduce power to keep power 2229185377Ssam * consumption under 2 Watts. Note that we always do 2230185377Ssam * this unless specially configured. Then we limit 2231185377Ssam * power only for non-AP operation. 2232185377Ssam */ 2233187831Ssam if (IEEE80211_IS_CHAN_TURBO(chan) 2234185377Ssam#ifdef AH_ENABLE_AP_SUPPORT 2235185377Ssam && AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP 2236185377Ssam#endif 2237185377Ssam ) { 2238185377Ssam /* 2239185377Ssam * If turbo is set, reduce power to keep power 2240185377Ssam * consumption under 2 Watts 2241185377Ssam */ 2242185377Ssam if (ee->ee_version >= AR_EEPROM_VER3_1) 2243185377Ssam scaledPower = AH_MIN(scaledPower, 2244185377Ssam ee->ee_turbo2WMaxPower5); 2245185377Ssam /* 2246185377Ssam * EEPROM version 4.0 added an additional 2247185377Ssam * constraint on 2.4GHz channels. 2248185377Ssam */ 2249185377Ssam if (ee->ee_version >= AR_EEPROM_VER4_0 && 2250187831Ssam IEEE80211_IS_CHAN_2GHZ(chan)) 2251185377Ssam scaledPower = AH_MIN(scaledPower, 2252185377Ssam ee->ee_turbo2WMaxPower2); 2253185377Ssam } 2254185377Ssam 2255185377Ssam maxAvailPower = AH_MIN(scaledPower, 2256185377Ssam targetPowerOfdm.twicePwr6_24); 2257185377Ssam 2258185377Ssam /* Reduce power by max regulatory domain allowed restrictions */ 2259185377Ssam scaledPower = maxAvailPower - (tpcScaleReduction * 2); 2260185377Ssam scaledPower = (scaledPower < 0) ? 0 : scaledPower; 2261185377Ssam scaledPower = AH_MIN(scaledPower, powerLimit); 2262185377Ssam 2263185377Ssam if (commit) { 2264185377Ssam /* Set OFDM rates 9, 12, 18, 24 */ 2265185377Ssam r0 = rpow[0] = rpow[1] = rpow[2] = rpow[3] = rpow[4] = scaledPower; 2266185377Ssam 2267185377Ssam /* Set OFDM rates 36, 48, 54, XR */ 2268185377Ssam rpow[5] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr36); 2269185377Ssam rpow[6] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr48); 2270185377Ssam r7 = rpow[7] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr54); 2271185377Ssam 2272185377Ssam if (ee->ee_version >= AR_EEPROM_VER4_0) { 2273185377Ssam /* Setup XR target power from EEPROM */ 2274187831Ssam rpow[15] = AH_MIN(scaledPower, IEEE80211_IS_CHAN_2GHZ(chan) ? 2275185377Ssam ee->ee_xrTargetPower2 : ee->ee_xrTargetPower5); 2276185377Ssam } else { 2277185377Ssam /* XR uses 6mb power */ 2278185377Ssam rpow[15] = rpow[0]; 2279185377Ssam } 2280185377Ssam ahp->ah_ofdmTxPower = *pMaxPower; 2281185377Ssam 2282185377Ssam } else { 2283185377Ssam r0 = scaledPower; 2284185377Ssam r7 = AH_MIN(r0, targetPowerOfdm.twicePwr54); 2285185377Ssam } 2286185377Ssam *pMinPower = r7; 2287185377Ssam *pMaxPower = r0; 2288185377Ssam 2289185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2290185377Ssam "%s: MaxRD: %d TurboMax: %d MaxCTL: %d " 2291185377Ssam "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n", 2292185377Ssam __func__, twiceMaxRDPower, ee->ee_turbo2WMaxPower5, 2293185377Ssam twiceMaxEdgePower, tpcScaleReduction * 2, 2294187831Ssam chan->ic_freq, chan->ic_flags, 2295185377Ssam maxAvailPower, targetPowerOfdm.twicePwr6_24, *pMaxPower); 2296185377Ssam } 2297185377Ssam 2298187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) { 2299185377Ssam /* Get final CCK target powers */ 2300185377Ssam ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11b, 2301185377Ssam ee->ee_numTargetPwr_11b, &targetPowerCck); 2302185377Ssam 2303185377Ssam /* Reduce power by max regulatory domain allowed restrictions */ 2304185377Ssam scaledPower = AH_MIN(twiceMaxEdgePowerCck, 2305185377Ssam twiceMaxRDPower - twiceAntennaReduction); 2306185377Ssam if (maxAvailPower < AH_MIN(scaledPower, targetPowerCck.twicePwr6_24)) 2307185377Ssam maxAvailPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24); 2308185377Ssam 2309185377Ssam /* Reduce power by user selection */ 2310185377Ssam scaledPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24) - (tpcScaleReduction * 2); 2311185377Ssam scaledPower = (scaledPower < 0) ? 0 : scaledPower; 2312185377Ssam scaledPower = AH_MIN(scaledPower, powerLimit); 2313185377Ssam 2314185377Ssam if (commit) { 2315185377Ssam /* Set CCK rates 2L, 2S, 5.5L, 5.5S, 11L, 11S */ 2316185377Ssam rpow[8] = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24); 2317185377Ssam r9 = rpow[9] = AH_MIN(scaledPower, targetPowerCck.twicePwr36); 2318185377Ssam rpow[10] = rpow[9]; 2319185377Ssam rpow[11] = AH_MIN(scaledPower, targetPowerCck.twicePwr48); 2320185377Ssam rpow[12] = rpow[11]; 2321185377Ssam r13 = rpow[13] = AH_MIN(scaledPower, targetPowerCck.twicePwr54); 2322185377Ssam rpow[14] = rpow[13]; 2323185377Ssam } else { 2324185377Ssam r9 = AH_MIN(scaledPower, targetPowerCck.twicePwr36); 2325185377Ssam r13 = AH_MIN(scaledPower, targetPowerCck.twicePwr54); 2326185377Ssam } 2327185377Ssam 2328185377Ssam /* Set min/max power based off OFDM values or initialization */ 2329185377Ssam if (r13 < *pMinPower) 2330185377Ssam *pMinPower = r13; 2331185377Ssam if (r9 > *pMaxPower) 2332185377Ssam *pMaxPower = r9; 2333185377Ssam 2334185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2335185377Ssam "%s: cck: MaxRD: %d MaxCTL: %d " 2336185377Ssam "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n", 2337185377Ssam __func__, twiceMaxRDPower, twiceMaxEdgePowerCck, 2338187831Ssam tpcScaleReduction * 2, chan->ic_freq, chan->ic_flags, 2339185377Ssam maxAvailPower, targetPowerCck.twicePwr6_24, *pMaxPower); 2340185377Ssam } 2341185377Ssam if (commit) { 2342185377Ssam ahp->ah_tx6PowerInHalfDbm = *pMaxPower; 2343185377Ssam AH_PRIVATE(ah)->ah_maxPowerLevel = ahp->ah_tx6PowerInHalfDbm; 2344185377Ssam } 2345185377Ssam return AH_TRUE; 2346185377Ssam} 2347185377Ssam 2348185377SsamHAL_BOOL 2349187831Ssamar5212GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan) 2350185377Ssam{ 2351185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 2352187831Ssam#if 0 2353185377Ssam static const uint16_t tpcScaleReductionTable[5] = 2354185377Ssam { 0, 3, 6, 9, MAX_RATE_POWER }; 2355187831Ssam int16_t tpcInDb, powerLimit; 2356187831Ssam#endif 2357187831Ssam int16_t minPower, maxPower; 2358185377Ssam 2359185377Ssam /* 2360185377Ssam * Get Pier table max and min powers. 2361185377Ssam */ 2362187831Ssam if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) { 2363187831Ssam /* NB: rf code returns 1/4 dBm units, convert */ 2364187831Ssam chan->ic_maxpower = maxPower / 2; 2365187831Ssam chan->ic_minpower = minPower / 2; 2366187831Ssam } else { 2367187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 2368187831Ssam "%s: no min/max power for %u/0x%x\n", 2369187831Ssam __func__, chan->ic_freq, chan->ic_flags); 2370187831Ssam chan->ic_maxpower = MAX_RATE_POWER; 2371187831Ssam chan->ic_minpower = 0; 2372185377Ssam } 2373187831Ssam#if 0 2374185377Ssam /* 2375185377Ssam * Now adjust to reflect any global scale and/or CTL's. 2376185377Ssam * (XXX is that correct?) 2377185377Ssam */ 2378185377Ssam powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 2379185377Ssam if (powerLimit >= MAX_RATE_POWER || powerLimit == 0) 2380185377Ssam tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 2381185377Ssam else 2382185377Ssam tpcInDb = 0; 2383187831Ssam if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit, 2384187831Ssam AH_FALSE, &minPower, &maxPower)) { 2385187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 2386187831Ssam "%s: unable to find max/min power\n",__func__); 2387187831Ssam return AH_FALSE; 2388185377Ssam } 2389187831Ssam if (maxPower < chan->ic_maxpower) 2390187831Ssam chan->ic_maxpower = maxPower; 2391187831Ssam if (minPower < chan->ic_minpower) 2392187831Ssam chan->ic_minpower = minPower; 2393187831Ssam HALDEBUG(ah, HAL_DEBUG_RESET, 2394187831Ssam "Chan %d: MaxPow = %d MinPow = %d\n", 2395187831Ssam chan->ic_freq, chan->ic_maxpower, chans->ic_minpower); 2396185377Ssam#endif 2397185377Ssam return AH_TRUE; 2398185377Ssam} 2399185377Ssam 2400185377Ssam/* 2401185377Ssam * Correct for the gain-delta between ofdm and cck mode target 2402185377Ssam * powers. Write the results to the rate table and the power table. 2403185377Ssam * 2404185377Ssam * Conventions : 2405185377Ssam * 1. rpow[ii] is the integer value of 2*(desired power 2406185377Ssam * for the rate ii in dBm) to provide 0.5dB resolution. rate 2407185377Ssam * mapping is as following : 2408185377Ssam * [0..7] --> ofdm 6, 9, .. 48, 54 2409185377Ssam * [8..14] --> cck 1L, 2L, 2S, .. 11L, 11S 2410185377Ssam * [15] --> XR (all rates get the same power) 2411185377Ssam * 2. powv[ii] is the pcdac corresponding to ii/2 dBm. 2412185377Ssam */ 2413185377Ssamstatic void 2414185377Ssamar5212CorrectGainDelta(struct ath_hal *ah, int twiceOfdmCckDelta) 2415185377Ssam{ 2416185377Ssam#define N(_a) (sizeof(_a) / sizeof(_a[0])) 2417185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 2418185377Ssam const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 2419185377Ssam int16_t ratesIndex[N(ahp->ah_ratesArray)]; 2420185377Ssam uint16_t ii, jj, iter; 2421185377Ssam int32_t cckIndex; 2422185377Ssam int16_t gainDeltaAdjust; 2423185377Ssam 2424185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 2425185377Ssam 2426185377Ssam gainDeltaAdjust = ee->ee_cckOfdmGainDelta; 2427185377Ssam 2428185377Ssam /* make a local copy of desired powers as initial indices */ 2429185377Ssam OS_MEMCPY(ratesIndex, ahp->ah_ratesArray, sizeof(ratesIndex)); 2430185377Ssam 2431185377Ssam /* fix only the CCK indices */ 2432185377Ssam for (ii = 8; ii < 15; ii++) { 2433185377Ssam /* apply a gain_delta correction of -15 for CCK */ 2434185377Ssam ratesIndex[ii] -= gainDeltaAdjust; 2435185377Ssam 2436185377Ssam /* Now check for contention with all ofdm target powers */ 2437185377Ssam jj = 0; 2438185377Ssam iter = 0; 2439185377Ssam /* indicates not all ofdm rates checked forcontention yet */ 2440185377Ssam while (jj < 16) { 2441185377Ssam if (ratesIndex[ii] < 0) 2442185377Ssam ratesIndex[ii] = 0; 2443185377Ssam if (jj == 8) { /* skip CCK rates */ 2444185377Ssam jj = 15; 2445185377Ssam continue; 2446185377Ssam } 2447185377Ssam if (ratesIndex[ii] == ahp->ah_ratesArray[jj]) { 2448185377Ssam if (ahp->ah_ratesArray[jj] == 0) 2449185377Ssam ratesIndex[ii]++; 2450185377Ssam else if (iter > 50) { 2451185377Ssam /* 2452185377Ssam * To avoid pathological case of of 2453185377Ssam * dm target powers 0 and 0.5dBm 2454185377Ssam */ 2455185377Ssam ratesIndex[ii]++; 2456185377Ssam } else 2457185377Ssam ratesIndex[ii]--; 2458185377Ssam /* check with all rates again */ 2459185377Ssam jj = 0; 2460185377Ssam iter++; 2461185377Ssam } else 2462185377Ssam jj++; 2463185377Ssam } 2464185377Ssam if (ratesIndex[ii] >= PWR_TABLE_SIZE) 2465185377Ssam ratesIndex[ii] = PWR_TABLE_SIZE -1; 2466185377Ssam cckIndex = ahp->ah_ratesArray[ii] - twiceOfdmCckDelta; 2467185377Ssam if (cckIndex < 0) 2468185377Ssam cckIndex = 0; 2469185377Ssam 2470185377Ssam /* 2471185377Ssam * Validate that the indexes for the powv are not 2472185377Ssam * out of bounds. 2473185377Ssam */ 2474185377Ssam HALASSERT(cckIndex < PWR_TABLE_SIZE); 2475185377Ssam HALASSERT(ratesIndex[ii] < PWR_TABLE_SIZE); 2476185377Ssam ahp->ah_pcdacTable[ratesIndex[ii]] = 2477185377Ssam ahp->ah_pcdacTable[cckIndex]; 2478185377Ssam } 2479185377Ssam /* Override rate per power table with new values */ 2480185377Ssam for (ii = 8; ii < 15; ii++) 2481185377Ssam ahp->ah_ratesArray[ii] = ratesIndex[ii]; 2482185377Ssam#undef N 2483185377Ssam} 2484185377Ssam 2485185377Ssam/* 2486185377Ssam * Find the maximum conformance test limit for the given channel and CTL info 2487185377Ssam */ 2488185377Ssamstatic uint16_t 2489185377Ssamar5212GetMaxEdgePower(uint16_t channel, const RD_EDGES_POWER *pRdEdgesPower) 2490185377Ssam{ 2491185377Ssam /* temp array for holding edge channels */ 2492185377Ssam uint16_t tempChannelList[NUM_EDGES]; 2493185377Ssam uint16_t clo, chi, twiceMaxEdgePower; 2494185377Ssam int i, numEdges; 2495185377Ssam 2496185377Ssam /* Get the edge power */ 2497185377Ssam for (i = 0; i < NUM_EDGES; i++) { 2498185377Ssam if (pRdEdgesPower[i].rdEdge == 0) 2499185377Ssam break; 2500185377Ssam tempChannelList[i] = pRdEdgesPower[i].rdEdge; 2501185377Ssam } 2502185377Ssam numEdges = i; 2503185377Ssam 2504185377Ssam ar5212GetLowerUpperValues(channel, tempChannelList, 2505185377Ssam numEdges, &clo, &chi); 2506185377Ssam /* Get the index for the lower channel */ 2507185377Ssam for (i = 0; i < numEdges && clo != tempChannelList[i]; i++) 2508185377Ssam ; 2509185377Ssam /* Is lower channel ever outside the rdEdge? */ 2510185377Ssam HALASSERT(i != numEdges); 2511185377Ssam 2512185377Ssam if ((clo == chi && clo == channel) || (pRdEdgesPower[i].flag)) { 2513185377Ssam /* 2514185377Ssam * If there's an exact channel match or an inband flag set 2515185377Ssam * on the lower channel use the given rdEdgePower 2516185377Ssam */ 2517185377Ssam twiceMaxEdgePower = pRdEdgesPower[i].twice_rdEdgePower; 2518185377Ssam HALASSERT(twiceMaxEdgePower > 0); 2519185377Ssam } else 2520185377Ssam twiceMaxEdgePower = MAX_RATE_POWER; 2521185377Ssam return twiceMaxEdgePower; 2522185377Ssam} 2523185377Ssam 2524185377Ssam/* 2525185377Ssam * Returns interpolated or the scaled up interpolated value 2526185377Ssam */ 2527185377Ssamstatic uint16_t 2528185377Ssaminterpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, 2529185377Ssam uint16_t targetLeft, uint16_t targetRight) 2530185377Ssam{ 2531185377Ssam uint16_t rv; 2532185377Ssam int16_t lRatio; 2533185377Ssam 2534185377Ssam /* to get an accurate ratio, always scale, if want to scale, then don't scale back down */ 2535185377Ssam if ((targetLeft * targetRight) == 0) 2536185377Ssam return 0; 2537185377Ssam 2538185377Ssam if (srcRight != srcLeft) { 2539185377Ssam /* 2540185377Ssam * Note the ratio always need to be scaled, 2541185377Ssam * since it will be a fraction. 2542185377Ssam */ 2543185377Ssam lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft); 2544185377Ssam if (lRatio < 0) { 2545185377Ssam /* Return as Left target if value would be negative */ 2546185377Ssam rv = targetLeft; 2547185377Ssam } else if (lRatio > EEP_SCALE) { 2548185377Ssam /* Return as Right target if Ratio is greater than 100% (SCALE) */ 2549185377Ssam rv = targetRight; 2550185377Ssam } else { 2551185377Ssam rv = (lRatio * targetRight + (EEP_SCALE - lRatio) * 2552185377Ssam targetLeft) / EEP_SCALE; 2553185377Ssam } 2554185377Ssam } else { 2555185377Ssam rv = targetLeft; 2556185377Ssam } 2557185377Ssam return rv; 2558185377Ssam} 2559185377Ssam 2560185377Ssam/* 2561185377Ssam * Return the four rates of target power for the given target power table 2562185377Ssam * channel, and number of channels 2563185377Ssam */ 2564185377Ssamstatic void 2565187831Ssamar5212GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, 2566185377Ssam const TRGT_POWER_INFO *powInfo, 2567185377Ssam uint16_t numChannels, TRGT_POWER_INFO *pNewPower) 2568185377Ssam{ 2569187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 2570185377Ssam /* temp array for holding target power channels */ 2571185377Ssam uint16_t tempChannelList[NUM_TEST_FREQUENCIES]; 2572185377Ssam uint16_t clo, chi, ixlo, ixhi; 2573185377Ssam int i; 2574185377Ssam 2575185377Ssam /* Copy the target powers into the temp channel list */ 2576185377Ssam for (i = 0; i < numChannels; i++) 2577185377Ssam tempChannelList[i] = powInfo[i].testChannel; 2578185377Ssam 2579187831Ssam ar5212GetLowerUpperValues(freq, tempChannelList, 2580185377Ssam numChannels, &clo, &chi); 2581185377Ssam 2582185377Ssam /* Get the indices for the channel */ 2583185377Ssam ixlo = ixhi = 0; 2584185377Ssam for (i = 0; i < numChannels; i++) { 2585185377Ssam if (clo == tempChannelList[i]) { 2586185377Ssam ixlo = i; 2587185377Ssam } 2588185377Ssam if (chi == tempChannelList[i]) { 2589185377Ssam ixhi = i; 2590185377Ssam break; 2591185377Ssam } 2592185377Ssam } 2593185377Ssam 2594185377Ssam /* 2595185377Ssam * Get the lower and upper channels, target powers, 2596185377Ssam * and interpolate between them. 2597185377Ssam */ 2598187831Ssam pNewPower->twicePwr6_24 = interpolate(freq, clo, chi, 2599185377Ssam powInfo[ixlo].twicePwr6_24, powInfo[ixhi].twicePwr6_24); 2600187831Ssam pNewPower->twicePwr36 = interpolate(freq, clo, chi, 2601185377Ssam powInfo[ixlo].twicePwr36, powInfo[ixhi].twicePwr36); 2602187831Ssam pNewPower->twicePwr48 = interpolate(freq, clo, chi, 2603185377Ssam powInfo[ixlo].twicePwr48, powInfo[ixhi].twicePwr48); 2604187831Ssam pNewPower->twicePwr54 = interpolate(freq, clo, chi, 2605185377Ssam powInfo[ixlo].twicePwr54, powInfo[ixhi].twicePwr54); 2606185377Ssam} 2607185377Ssam 2608275471Sdimstatic uint32_t 2609275471Sdimudiff(uint32_t u, uint32_t v) 2610275471Sdim{ 2611275471Sdim return (u >= v ? u - v : v - u); 2612275471Sdim} 2613275471Sdim 2614185377Ssam/* 2615185377Ssam * Search a list for a specified value v that is within 2616185377Ssam * EEP_DELTA of the search values. Return the closest 2617185377Ssam * values in the list above and below the desired value. 2618185377Ssam * EEP_DELTA is a factional value; everything is scaled 2619185377Ssam * so only integer arithmetic is used. 2620185377Ssam * 2621185377Ssam * NB: the input list is assumed to be sorted in ascending order 2622185377Ssam */ 2623185377Ssamvoid 2624185377Ssamar5212GetLowerUpperValues(uint16_t v, uint16_t *lp, uint16_t listSize, 2625185377Ssam uint16_t *vlo, uint16_t *vhi) 2626185377Ssam{ 2627185377Ssam uint32_t target = v * EEP_SCALE; 2628185377Ssam uint16_t *ep = lp+listSize; 2629185377Ssam 2630185377Ssam /* 2631185377Ssam * Check first and last elements for out-of-bounds conditions. 2632185377Ssam */ 2633185377Ssam if (target < (uint32_t)(lp[0] * EEP_SCALE - EEP_DELTA)) { 2634185377Ssam *vlo = *vhi = lp[0]; 2635185377Ssam return; 2636185377Ssam } 2637185377Ssam if (target > (uint32_t)(ep[-1] * EEP_SCALE + EEP_DELTA)) { 2638185377Ssam *vlo = *vhi = ep[-1]; 2639185377Ssam return; 2640185377Ssam } 2641185377Ssam 2642185377Ssam /* look for value being near or between 2 values in list */ 2643185377Ssam for (; lp < ep; lp++) { 2644185377Ssam /* 2645185377Ssam * If value is close to the current value of the list 2646185377Ssam * then target is not between values, it is one of the values 2647185377Ssam */ 2648275471Sdim if (udiff(lp[0] * EEP_SCALE, target) < EEP_DELTA) { 2649185377Ssam *vlo = *vhi = lp[0]; 2650185377Ssam return; 2651185377Ssam } 2652185377Ssam /* 2653185377Ssam * Look for value being between current value and next value 2654185377Ssam * if so return these 2 values 2655185377Ssam */ 2656185377Ssam if (target < (uint32_t)(lp[1] * EEP_SCALE - EEP_DELTA)) { 2657185377Ssam *vlo = lp[0]; 2658185377Ssam *vhi = lp[1]; 2659185377Ssam return; 2660185377Ssam } 2661185377Ssam } 2662185377Ssam HALASSERT(AH_FALSE); /* should not reach here */ 2663185377Ssam} 2664185377Ssam 2665185377Ssam/* 2666185377Ssam * Perform analog "swizzling" of parameters into their location 2667185380Ssam * 2668185380Ssam * NB: used by RF backends 2669185377Ssam */ 2670185377Ssamvoid 2671185377Ssamar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, uint32_t numBits, 2672185377Ssam uint32_t firstBit, uint32_t column) 2673185377Ssam{ 2674185380Ssam#define MAX_ANALOG_START 319 /* XXX */ 2675185377Ssam uint32_t tmp32, mask, arrayEntry, lastBit; 2676185377Ssam int32_t bitPosition, bitsLeft; 2677185377Ssam 2678185377Ssam HALASSERT(column <= 3); 2679185377Ssam HALASSERT(numBits <= 32); 2680185377Ssam HALASSERT(firstBit + numBits <= MAX_ANALOG_START); 2681185377Ssam 2682185377Ssam tmp32 = ath_hal_reverseBits(reg32, numBits); 2683185377Ssam arrayEntry = (firstBit - 1) / 8; 2684185377Ssam bitPosition = (firstBit - 1) % 8; 2685185377Ssam bitsLeft = numBits; 2686185377Ssam while (bitsLeft > 0) { 2687185377Ssam lastBit = (bitPosition + bitsLeft > 8) ? 2688185377Ssam 8 : bitPosition + bitsLeft; 2689185377Ssam mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 2690185377Ssam (column * 8); 2691185377Ssam rfBuf[arrayEntry] &= ~mask; 2692185377Ssam rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 2693185377Ssam (column * 8)) & mask; 2694185377Ssam bitsLeft -= 8 - bitPosition; 2695185377Ssam tmp32 = tmp32 >> (8 - bitPosition); 2696185377Ssam bitPosition = 0; 2697185377Ssam arrayEntry++; 2698185377Ssam } 2699185380Ssam#undef MAX_ANALOG_START 2700185377Ssam} 2701185377Ssam 2702185377Ssam/* 2703185377Ssam * Sets the rate to duration values in MAC - used for multi- 2704185377Ssam * rate retry. 2705185377Ssam * The rate duration table needs to cover all valid rate codes; 2706185377Ssam * the 11g table covers all ofdm rates, while the 11b table 2707185377Ssam * covers all cck rates => all valid rates get covered between 2708185377Ssam * these two mode's ratetables! 2709185377Ssam * But if we're turbo, the ofdm phy is replaced by the turbo phy 2710185377Ssam * and cck is not valid with turbo => all rates get covered 2711185377Ssam * by the turbo ratetable only 2712185377Ssam */ 2713185377Ssamvoid 2714187831Ssamar5212SetRateDurationTable(struct ath_hal *ah, 2715187831Ssam const struct ieee80211_channel *chan) 2716185377Ssam{ 2717185377Ssam const HAL_RATE_TABLE *rt; 2718185377Ssam int i; 2719185377Ssam 2720185380Ssam /* NB: band doesn't matter for 1/2 and 1/4 rate */ 2721187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) { 2722185377Ssam rt = ar5212GetRateTable(ah, HAL_MODE_11A_HALF_RATE); 2723187831Ssam } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 2724185377Ssam rt = ar5212GetRateTable(ah, HAL_MODE_11A_QUARTER_RATE); 2725185377Ssam } else { 2726185377Ssam rt = ar5212GetRateTable(ah, 2727187831Ssam IEEE80211_IS_CHAN_TURBO(chan) ? HAL_MODE_TURBO : HAL_MODE_11G); 2728185377Ssam } 2729185377Ssam 2730185377Ssam for (i = 0; i < rt->rateCount; ++i) 2731185377Ssam OS_REG_WRITE(ah, 2732185377Ssam AR_RATE_DURATION(rt->info[i].rateCode), 2733185377Ssam ath_hal_computetxtime(ah, rt, 2734185377Ssam WLAN_CTRL_FRAME_SIZE, 2735185377Ssam rt->info[i].controlRate, AH_FALSE)); 2736187831Ssam if (!IEEE80211_IS_CHAN_TURBO(chan)) { 2737185377Ssam /* 11g Table is used to cover the CCK rates. */ 2738185377Ssam rt = ar5212GetRateTable(ah, HAL_MODE_11G); 2739185377Ssam for (i = 0; i < rt->rateCount; ++i) { 2740185377Ssam uint32_t reg = AR_RATE_DURATION(rt->info[i].rateCode); 2741185377Ssam 2742185377Ssam if (rt->info[i].phy != IEEE80211_T_CCK) 2743185377Ssam continue; 2744185377Ssam 2745185377Ssam OS_REG_WRITE(ah, reg, 2746185377Ssam ath_hal_computetxtime(ah, rt, 2747185377Ssam WLAN_CTRL_FRAME_SIZE, 2748185377Ssam rt->info[i].controlRate, AH_FALSE)); 2749185377Ssam /* cck rates have short preamble option also */ 2750185377Ssam if (rt->info[i].shortPreamble) { 2751185377Ssam reg += rt->info[i].shortPreamble << 2; 2752185377Ssam OS_REG_WRITE(ah, reg, 2753185377Ssam ath_hal_computetxtime(ah, rt, 2754185377Ssam WLAN_CTRL_FRAME_SIZE, 2755185377Ssam rt->info[i].controlRate, 2756185377Ssam AH_TRUE)); 2757185377Ssam } 2758185377Ssam } 2759185377Ssam } 2760185377Ssam} 2761185377Ssam 2762185377Ssam/* Adjust various register settings based on half/quarter rate clock setting. 2763185377Ssam * This includes: +USEC, TX/RX latency, 2764185377Ssam * + IFS params: slot, eifs, misc etc. 2765185377Ssam */ 2766185377Ssamvoid 2767187831Ssamar5212SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan) 2768185377Ssam{ 2769185377Ssam uint32_t txLat, rxLat, usec, slot, refClock, eifs, init_usec; 2770185377Ssam 2771187831Ssam HALASSERT(IEEE80211_IS_CHAN_HALF(chan) || 2772187831Ssam IEEE80211_IS_CHAN_QUARTER(chan)); 2773185380Ssam 2774185377Ssam refClock = OS_REG_READ(ah, AR_USEC) & AR_USEC_USEC32; 2775187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) { 2776185377Ssam slot = IFS_SLOT_HALF_RATE; 2777185377Ssam rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S; 2778185377Ssam txLat = TX_HALF_RATE_LATENCY << AR5212_USEC_TX_LAT_S; 2779185377Ssam usec = HALF_RATE_USEC; 2780185377Ssam eifs = IFS_EIFS_HALF_RATE; 2781185377Ssam init_usec = INIT_USEC >> 1; 2782185377Ssam } else { /* quarter rate */ 2783185377Ssam slot = IFS_SLOT_QUARTER_RATE; 2784185377Ssam rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S; 2785185377Ssam txLat = TX_QUARTER_RATE_LATENCY << AR5212_USEC_TX_LAT_S; 2786185377Ssam usec = QUARTER_RATE_USEC; 2787185377Ssam eifs = IFS_EIFS_QUARTER_RATE; 2788185377Ssam init_usec = INIT_USEC >> 2; 2789185377Ssam } 2790185377Ssam 2791185377Ssam OS_REG_WRITE(ah, AR_USEC, (usec | refClock | txLat | rxLat)); 2792185377Ssam OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot); 2793185377Ssam OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs); 2794185377Ssam OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC, 2795185377Ssam AR_D_GBL_IFS_MISC_USEC_DURATION, init_usec); 2796185377Ssam} 2797