vmm_dev.h revision 268891 
1/*-
2 * Copyright (c) 2011 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/sys/amd64/include/vmm_dev.h 268891 2014-07-19 22:06:46Z jhb $
27 */
28
29#ifndef	_VMM_DEV_H_
30#define	_VMM_DEV_H_
31
32#ifdef _KERNEL
33void	vmmdev_init(void);
34int	vmmdev_cleanup(void);
35#endif
36
37struct vm_memory_segment {
38	vm_paddr_t	gpa;	/* in */
39	size_t		len;
40	int		wired;
41};
42
43struct vm_register {
44	int		cpuid;
45	int		regnum;		/* enum vm_reg_name */
46	uint64_t	regval;
47};
48
49struct vm_seg_desc {			/* data or code segment */
50	int		cpuid;
51	int		regnum;		/* enum vm_reg_name */
52	struct seg_desc desc;
53};
54
55struct vm_run {
56	int		cpuid;
57	uint64_t	rip;		/* start running here */
58	struct vm_exit	vm_exit;
59};
60
61struct vm_exception {
62	int		cpuid;
63	int		vector;
64	uint32_t	error_code;
65	int		error_code_valid;
66};
67
68struct vm_lapic_msi {
69	uint64_t	msg;
70	uint64_t	addr;
71};
72
73struct vm_lapic_irq {
74	int		cpuid;
75	int		vector;
76};
77
78struct vm_ioapic_irq {
79	int		irq;
80};
81
82struct vm_isa_irq {
83	int		atpic_irq;
84	int		ioapic_irq;
85};
86
87struct vm_capability {
88	int		cpuid;
89	enum vm_cap_type captype;
90	int		capval;
91	int		allcpus;
92};
93
94struct vm_pptdev {
95	int		bus;
96	int		slot;
97	int		func;
98};
99
100struct vm_pptdev_mmio {
101	int		bus;
102	int		slot;
103	int		func;
104	vm_paddr_t	gpa;
105	vm_paddr_t	hpa;
106	size_t		len;
107};
108
109struct vm_pptdev_msi {
110	int		vcpu;
111	int		bus;
112	int		slot;
113	int		func;
114	int		numvec;		/* 0 means disabled */
115	uint64_t	msg;
116	uint64_t	addr;
117};
118
119struct vm_pptdev_msix {
120	int		vcpu;
121	int		bus;
122	int		slot;
123	int		func;
124	int		idx;
125	uint64_t	msg;
126	uint32_t	vector_control;
127	uint64_t	addr;
128};
129
130struct vm_nmi {
131	int		cpuid;
132};
133
134#define	MAX_VM_STATS	64
135struct vm_stats {
136	int		cpuid;				/* in */
137	int		num_entries;			/* out */
138	struct timeval	tv;
139	uint64_t	statbuf[MAX_VM_STATS];
140};
141
142struct vm_stat_desc {
143	int		index;				/* in */
144	char		desc[128];			/* out */
145};
146
147struct vm_x2apic {
148	int			cpuid;
149	enum x2apic_state	state;
150};
151
152struct vm_gpa_pte {
153	uint64_t	gpa;				/* in */
154	uint64_t	pte[4];				/* out */
155	int		ptenum;
156};
157
158struct vm_hpet_cap {
159	uint32_t	capabilities;	/* lower 32 bits of HPET capabilities */
160};
161
162enum {
163	/* general routines */
164	IOCNUM_ABIVERS = 0,
165	IOCNUM_RUN = 1,
166	IOCNUM_SET_CAPABILITY = 2,
167	IOCNUM_GET_CAPABILITY = 3,
168
169	/* memory apis */
170	IOCNUM_MAP_MEMORY = 10,
171	IOCNUM_GET_MEMORY_SEG = 11,
172	IOCNUM_GET_GPA_PMAP = 12,
173
174	/* register/state accessors */
175	IOCNUM_SET_REGISTER = 20,
176	IOCNUM_GET_REGISTER = 21,
177	IOCNUM_SET_SEGMENT_DESCRIPTOR = 22,
178	IOCNUM_GET_SEGMENT_DESCRIPTOR = 23,
179
180	/* interrupt injection */
181	IOCNUM_INJECT_EXCEPTION = 30,
182	IOCNUM_LAPIC_IRQ = 31,
183	IOCNUM_INJECT_NMI = 32,
184	IOCNUM_IOAPIC_ASSERT_IRQ = 33,
185	IOCNUM_IOAPIC_DEASSERT_IRQ = 34,
186	IOCNUM_IOAPIC_PULSE_IRQ = 35,
187	IOCNUM_LAPIC_MSI = 36,
188	IOCNUM_LAPIC_LOCAL_IRQ = 37,
189	IOCNUM_IOAPIC_PINCOUNT = 38,
190
191	/* PCI pass-thru */
192	IOCNUM_BIND_PPTDEV = 40,
193	IOCNUM_UNBIND_PPTDEV = 41,
194	IOCNUM_MAP_PPTDEV_MMIO = 42,
195	IOCNUM_PPTDEV_MSI = 43,
196	IOCNUM_PPTDEV_MSIX = 44,
197
198	/* statistics */
199	IOCNUM_VM_STATS = 50,
200	IOCNUM_VM_STAT_DESC = 51,
201
202	/* kernel device state */
203	IOCNUM_SET_X2APIC_STATE = 60,
204	IOCNUM_GET_X2APIC_STATE = 61,
205	IOCNUM_GET_HPET_CAPABILITIES = 62,
206
207	/* legacy interrupt injection */
208	IOCNUM_ISA_ASSERT_IRQ = 80,
209	IOCNUM_ISA_DEASSERT_IRQ = 81,
210	IOCNUM_ISA_PULSE_IRQ = 82,
211};
212
213#define	VM_RUN		\
214	_IOWR('v', IOCNUM_RUN, struct vm_run)
215#define	VM_MAP_MEMORY	\
216	_IOWR('v', IOCNUM_MAP_MEMORY, struct vm_memory_segment)
217#define	VM_GET_MEMORY_SEG \
218	_IOWR('v', IOCNUM_GET_MEMORY_SEG, struct vm_memory_segment)
219#define	VM_SET_REGISTER \
220	_IOW('v', IOCNUM_SET_REGISTER, struct vm_register)
221#define	VM_GET_REGISTER \
222	_IOWR('v', IOCNUM_GET_REGISTER, struct vm_register)
223#define	VM_SET_SEGMENT_DESCRIPTOR \
224	_IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
225#define	VM_GET_SEGMENT_DESCRIPTOR \
226	_IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
227#define	VM_INJECT_EXCEPTION	\
228	_IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception)
229#define	VM_LAPIC_IRQ 		\
230	_IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq)
231#define	VM_LAPIC_LOCAL_IRQ 	\
232	_IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq)
233#define	VM_LAPIC_MSI		\
234	_IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi)
235#define	VM_IOAPIC_ASSERT_IRQ	\
236	_IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq)
237#define	VM_IOAPIC_DEASSERT_IRQ	\
238	_IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq)
239#define	VM_IOAPIC_PULSE_IRQ	\
240	_IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq)
241#define	VM_IOAPIC_PINCOUNT	\
242	_IOR('v', IOCNUM_IOAPIC_PINCOUNT, int)
243#define	VM_ISA_ASSERT_IRQ	\
244	_IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq)
245#define	VM_ISA_DEASSERT_IRQ	\
246	_IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq)
247#define	VM_ISA_PULSE_IRQ	\
248	_IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq)
249#define	VM_SET_CAPABILITY \
250	_IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
251#define	VM_GET_CAPABILITY \
252	_IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability)
253#define	VM_BIND_PPTDEV \
254	_IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev)
255#define	VM_UNBIND_PPTDEV \
256	_IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev)
257#define	VM_MAP_PPTDEV_MMIO \
258	_IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio)
259#define	VM_PPTDEV_MSI \
260	_IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi)
261#define	VM_PPTDEV_MSIX \
262	_IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix)
263#define VM_INJECT_NMI \
264	_IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi)
265#define	VM_STATS \
266	_IOWR('v', IOCNUM_VM_STATS, struct vm_stats)
267#define	VM_STAT_DESC \
268	_IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc)
269#define	VM_SET_X2APIC_STATE \
270	_IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic)
271#define	VM_GET_X2APIC_STATE \
272	_IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic)
273#define	VM_GET_HPET_CAPABILITIES \
274	_IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap)
275#define	VM_GET_GPA_PMAP \
276	_IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte)
277#endif
278