1/* 2 * Copyright (c) 1994 Charles Hannum. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by Charles Hannum. 15 * 4. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#ifndef _PCI_INTERNAL_H_ 31#define _PCI_INTERNAL_H_ 32 33/* 34 * Definitions for PCI autoconfiguration. 35 * 36 * This file describes types and functions which are used only for 37 * communication among the PCI modules implementing autoconfiguration. 38 */ 39 40/* Build options. Debug levels >1 are for helping to bring up new 41 LDT hardware and will be annoyingly verbose otherwise. */ 42 43/* PCI_DEBUG enables general checking and tracing. */ 44#ifndef PCI_DEBUG 45#define PCI_DEBUG 0 46#endif 47 48/* LDT_DEBUG enables progress/error reports for LDT fabric initialization. */ 49#ifndef LDT_DEBUG 50#define LDT_DEBUG 0 51#endif 52 53 54struct pci_attach_args { 55 pcitag_t pa_tag; 56 pcireg_t pa_id; 57 pcireg_t pa_class; 58}; 59 60struct pci_match { 61 pcireg_t class, classmask; 62 pcireg_t id, idmask; 63}; 64 65/* From <cpu>_pci_machdep.c */ 66 67int pci_hwinit(int port, pci_flags_t flags); 68void pci_hwreinit(int port, pci_flags_t flags); 69void pci_businit (int port, int bus, int probe_limit, pci_flags_t flags); 70void pci_businit_hostbridge (pcitag_t tag, pci_flags_t flags); 71int pci_device_preset (pcitag_t tag); 72void pci_device_setup(pcitag_t tag); 73void pci_bridge_setup(pcitag_t tag, pci_flags_t flags); 74void pci_flush(void); 75 76void pci_break_tag(pcitag_t, int *, int *, int *, int *); 77 78int pci_canscan(pcitag_t); 79int pci_probe_tag(pcitag_t tag); 80 81pcireg_t pci_conf_read8(pcitag_t, int); 82void pci_conf_write8(pcitag_t, int, pcireg_t); 83pcireg_t pci_conf_read16(pcitag_t, int); 84void pci_conf_write16(pcitag_t, int, pcireg_t); 85pcireg_t pci_conf_read(pcitag_t, int); 86void pci_conf_write(pcitag_t, int, pcireg_t); 87#define pci_conf_read32 pci_conf_read 88#define pci_conf_write32 pci_conf_write 89int pci_conf_write_acked(pcitag_t, int, pcireg_t); 90 91uint8_t pci_int_line(uint8_t); 92 93unsigned pci_msi_index(void); 94void pci_msi_encode(unsigned, uint64_t *, uint16_t *); 95 96 97/* From <board>_pci.c */ 98 99uint8_t pci_int_shift_0(pcitag_t); 100uint8_t pci_int_map_0(pcitag_t); 101 102/* The following are needed only for boards with chips supporting PCI-X. */ 103 104void pci_clock_reset(void); 105void pci_clock_enable(int); 106unsigned int pci_clock_select(unsigned int); 107 108/* The following are needed only for boards with bcm1x80 chips. */ 109 110int ldt_slave_mode(int); 111 112 113/* From ldtinit.c */ 114 115#define LDT_PRIMARY 0 116#define LDT_SECONDARY 1 117unsigned pci_find_ldt_cap (pcitag_t tag, int secondary); 118 119void ldt_set_max_width (unsigned int width_cap); 120void ldt_link_reset (pcitag_t tag, int delay); 121int ldt_chain_init (pcitag_t tag, int port, int bus, pci_flags_t flags); 122 123 124/* PCI bus parameters */ 125struct pci_bus { 126 unsigned char min_gnt; /* largest min grant */ 127 unsigned char max_lat; /* smallest max latency */ 128 unsigned char devsel; /* slowest devsel */ 129 char fast_b2b; /* support fast b2b */ 130 char prefetch; /* support prefetch */ 131 char freq66; /* support 66MHz */ 132 char width64; /* 64 bit bus */ 133 int bandwidth; /* # of .25us ticks/sec @ 33MHz */ 134 unsigned char ndev; /* # devices (functions) on bus */ 135 unsigned char def_ltim; /* default ltim counter */ 136 unsigned char max_ltim; /* maximum ltim counter */ 137 uint8_t port; /* index of host bridge */ 138 uint8_t primary; /* primary bus number */ 139 pcitag_t tag; /* tag for the bridge to this bus */ 140 uint32_t min_io_addr; /* min I/O address allocated to bus */ 141 uint32_t max_io_addr; /* max I/O address allocated to bus */ 142 uint32_t min_mem_addr; /* min mem address allocated to bus */ 143 uint32_t max_mem_addr; /* max mem address allocated to bus */ 144 uint8_t inta_shift; /* base rotation of interrupt pins */ 145 char no_probe; /* skip businit and query probes */ 146}; 147 148/* From <cpu>_pci_machdep.c */ 149 150int pci_maxport(void); 151int pci_nextbus(int port); 152int pci_maxbus(int port); 153struct pci_bus *pci_businfo(int port, int bus); 154 155pcireg_t pci_minmemaddr(int port); 156pcireg_t pci_maxmemaddr(int port); 157pcireg_t pci_minioaddr(int port); 158pcireg_t pci_maxioaddr(int port); 159 160#endif /* _PCI_INTERNAL_H_ */ 161