1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * MII register definitions File: mii.h 5 * 6 * Register and bit definitions for the standard MII management 7 * interface. 8 * 9 * Author: Mitch Lichtenberg 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48#ifndef _MII_H_ 49#define _MII_H_ 50 51/* Some PHY device identifiers, mostly for quirk handling and 52 debugging. Note that the values for the OUIs are not IEEE OUIs but 53 the values obtained by concatenating the oui fields of PHYIDR1 and 54 PHYIDR2. Done correctly, they are bit reversed within each byte 55 relative to the real OUI, but many vendors get this wrong (marked 56 xx), and some use both correct and incorrect variants. */ 57 58#define OUI_BCMxx 0x001018 /* 000818 xx */ 59#define DEV_BCM5201 0x21 60#define DEV_BCM5221 0x1E 61#define DEV_BCM5380 0x25 62#define DEV_BCM4401 0x36 63 64#define OUI_BCM 0x000818 /* 001018 */ 65#define DEV_BCM5401 0x05 66#define DEV_BCM5411 0x07 67#define DEV_BCM5464 0x0B 68#define DEV_BCM5461 0x0C 69#define DEV_BCM5421 0x0E 70#define DEV_BCM5701 0x11 71#define DEV_BCM5703 0x16 72#define DEV_BCM5705 0x1A 73 74#define OUI_INTEL 0x00AA00 /* 005500 xx */ 75#define DEV_I82555 0x15 76 77#define OUI_LEVEL_ONE 0x1E0400 /* 782000 xx */ 78#define DEV_LXT970 0x00 79 80#define OUI_NAT_SEMI 0x080017 /* 1000E8 xx */ 81#define DEV_DP83840 0x00 82#define DEV_DP83815 0x02 83 84#define OUI_SEEQ 0x0005BE /* 00A07D */ 85#define DEV_SEEQ80220 0x03 86 87 88/* Access/command codes */ 89 90#define MII_COMMAND_START 0x01 91#define MII_COMMAND_READ 0x02 92#define MII_COMMAND_WRITE 0x01 93#define MII_COMMAND_ACK 0x02 94 95 96/* Registers */ 97 98#define MII_BMCR 0x00 /* Basic Mode Control (rw) */ 99#define MII_BMSR 0x01 /* Basic Mode Status (ro) */ 100#define MII_PHYIDR1 0x02 101#define MII_PHYIDR2 0x03 102#define MII_ANAR 0x04 /* Autonegotiation Advertisement */ 103#define MII_ANLPAR 0x05 /* Autonegotiation Link Partner Ability (rw) */ 104#define MII_ANER 0x06 /* Autonegotiation Expansion */ 105#define MII_K1CTL 0x09 /* 1000baseT control */ 106#define MII_K1STSR 0x0A /* 1K Status Register (ro) */ 107#define MII_AUXCTL 0x18 /* aux control register */ 108 109 110/* Basic Mode Control register (RW) */ 111 112#define BMCR_RESET 0x8000 113#define BMCR_LOOPBACK 0x4000 114#define BMCR_SPEED0 0x2000 115#define BMCR_ANENABLE 0x1000 116#define BMCR_POWERDOWN 0x0800 117#define BMCR_ISOLATE 0x0400 118#define BMCR_RESTARTAN 0x0200 119#define BMCR_DUPLEX 0x0100 120#define BMCR_COLTEST 0x0080 121#define BMCR_SPEED1 0x0040 122#define BMCR_SPEED1000 (BMCR_SPEED1) 123#define BMCR_SPEED100 (BMCR_SPEED0) 124#define BMCR_SPEED10 0 125 126 127/* Basic Mode Status register (RO) */ 128 129#define BMSR_100BT4 0x8000 130#define BMSR_100BT_FDX 0x4000 131#define BMSR_100BT_HDX 0x2000 132#define BMSR_10BT_FDX 0x1000 133#define BMSR_10BT_HDX 0x0800 134#define BMSR_100BT2_FDX 0x0400 135#define BMSR_100BT2_HDX 0x0200 136#define BMSR_1000BT_XSR 0x0100 137#define BMSR_PRESUP 0x0040 138#define BMSR_ANCOMPLETE 0x0020 139#define BMSR_REMFAULT 0x0010 140#define BMSR_AUTONEG 0x0008 141#define BMSR_LINKSTAT 0x0004 142#define BMSR_JABDETECT 0x0002 143#define BMSR_EXTCAPAB 0x0001 144 145 146/* Autonegotiation Advertisement register (RW) */ 147 148#define ANAR_NP 0x8000 149#define ANAR_RF 0x2000 150#define ANAR_ASYPAUSE 0x0800 151#define ANAR_PAUSE 0x0400 152#define ANAR_T4 0x0200 153#define ANAR_TXFD 0x0100 154#define ANAR_TXHD 0x0080 155#define ANAR_10FD 0x0040 156#define ANAR_10HD 0x0020 157#define ANAR_PSB 0x001F 158 159#define PSB_802_3 0x0001 /* 802.3 */ 160 161/* Autonegotiation Link Partner Abilities register (RW) */ 162 163#define ANLPAR_NP 0x8000 164#define ANLPAR_ACK 0x4000 165#define ANLPAR_RF 0x2000 166#define ANLPAR_ASYPAUSE 0x0800 167#define ANLPAR_PAUSE 0x0400 168#define ANLPAR_T4 0x0200 169#define ANLPAR_TXFD 0x0100 170#define ANLPAR_TXHD 0x0080 171#define ANLPAR_10FD 0x0040 172#define ANLPAR_10HD 0x0020 173#define ANLPAR_PSB 0x001F 174 175 176/* Autonegotiation Expansion register (RO) */ 177 178#define ANER_PDF 0x0010 179#define ANER_LPNPABLE 0x0008 180#define ANER_NPABLE 0x0004 181#define ANER_PAGERX 0x0002 182#define ANER_LPANABLE 0x0001 183 184 185#define ANNPTR_NP 0x8000 186#define ANNPTR_MP 0x2000 187#define ANNPTR_ACK2 0x1000 188#define ANNPTR_TOGTX 0x0800 189#define ANNPTR_CODE 0x0008 190 191#define ANNPRR_NP 0x8000 192#define ANNPRR_MP 0x2000 193#define ANNPRR_ACK3 0x1000 194#define ANNPRR_TOGTX 0x0800 195#define ANNPRR_CODE 0x0008 196 197 198#define K1TCR_TESTMODE 0x0000 199#define K1TCR_MSMCE 0x1000 200#define K1TCR_MSCV 0x0800 201#define K1TCR_RPTR 0x0400 202#define K1TCR_1000BT_FDX 0x200 203#define K1TCR_1000BT_HDX 0x100 204 205#define K1STSR_MSMCFLT 0x8000 206#define K1STSR_MSCFGRES 0x4000 207#define K1STSR_LRSTAT 0x2000 208#define K1STSR_RRSTAT 0x1000 209#define K1STSR_LP1KFD 0x0800 210#define K1STSR_LP1KHD 0x0400 211#define K1STSR_LPASMDIR 0x0200 212 213#define K1SCR_1KX_FDX 0x8000 214#define K1SCR_1KX_HDX 0x4000 215#define K1SCR_1KT_FDX 0x2000 216#define K1SCR_1KT_HDX 0x1000 217 218#endif /* _MII_H_ */ 219