1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * BCM1250-specific PCI support File: sb1250_pci_machdep.c 5 * 6 ********************************************************************* 7 * 8 * Copyright 2001,2002,2003 9 * Broadcom Corporation. All rights reserved. 10 * 11 * This software is furnished under license and may be used and 12 * copied only in accordance with the following terms and 13 * conditions. Subject to these conditions, you may download, 14 * copy, install, use, modify and distribute modified or unmodified 15 * copies of this software in source and/or binary form. No title 16 * or ownership is transferred hereby. 17 * 18 * 1) Any source code used, modified or distributed must reproduce 19 * and retain this copyright notice and list of conditions 20 * as they appear in the source file. 21 * 22 * 2) No right is granted to use any trade name, trademark, or 23 * logo of Broadcom Corporation. The "Broadcom Corporation" 24 * name may not be used to endorse or promote products derived 25 * from this software without the prior written permission of 26 * Broadcom Corporation. 27 * 28 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 30 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 31 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 32 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 33 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 38 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 40 * THE POSSIBILITY OF SUCH DAMAGE. 41 ********************************************************************* */ 42 43/* 44 * Based in part on the algor p5064 version of pci_machdep.c, 45 * from SiByte sources dated 20000824, which was distributed with 46 * the copyright and license notices below: 47 */ 48 49/* Very loosely based on: */ 50/* $NetBSD: pci_machdep.c,v 1.17 1995/07/27 21:39:59 cgd Exp $ */ 51 52/* 53 * Copyright (c) 1994 Charles Hannum. All rights reserved. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 3. All advertising materials mentioning features or use of this software 64 * must display the following acknowledgement: 65 * This product includes software developed by Charles Hannum. 66 * 4. The name of the author may not be used to endorse or promote products 67 * derived from this software without specific prior written permission. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81/* 82 * Sibyte SB-1250 machine-specific functions for PCI autoconfiguration. 83 */ 84 85#include "cfe.h" 86#include "sbmips.h" 87#include "sb1250_defs.h" 88#include "sb1250_regs.h" 89#include "sb1250_scd.h" 90#include "lib_physio.h" 91#include "env_subr.h" 92extern void cfe_ledstr(const char *); 93 94#include "pcivar.h" 95#include "pci_internal.h" 96#include "pcireg.h" 97#include "ldtreg.h" 98 99#define SBD_DISPLAY(msg) cfe_ledstr(msg) 100 101const cons_t pci_optnames[] = { 102 {"verbose",PCI_FLG_VERBOSE}, 103 {"ldt_rev_017",PCI_FLG_LDT_REV_017}, 104 {NULL,0} 105}; 106 107extern int _pciverbose; 108 109 110/* PCI regions in system physical (ZBbus) space. See Figure 37. */ 111 112#define PCI_PORTMAX (PCI_HOST_PORTS-1) 113 114static struct { 115 /* ZBbus space allocated for mapping to the standard PCI address spaces */ 116 uint32_t mem_space; 117 uint32_t mem_space_size; 118 uint32_t io_space; 119 uint32_t io_space_size; 120 uint32_t cfg_space; 121 uint32_t cfg_space_size; 122 123 /* PCI space available for configuration */ 124 uint32_t pci_mem_base; 125 uint32_t pci_io_base; 126 127 /* Bits for endian policy (0: match bytes, 1: match bits) */ 128 uint32_t mem_bit_endian; 129 uint32_t io_bit_endian; 130 uint32_t cfg_bit_endian; 131 132 /* Match bits base for configuration (convenience variable) */ 133 physaddr_t cfg_base; 134 135 /* Message Signaled Interrupt destinations. */ 136 uint64_t msi_set_base; 137 uint64_t msi_clear_base; 138 uint64_t msi_bit_endian; 139} Q; 140 141static void 142pci_set_root (void) 143{ 144 Q.mem_space = A_PHYS_LDTPCI_IO_MATCH_BYTES_32; /* 0x0040000000 */ 145 Q.mem_space_size = 0x0020000000; 146 Q.io_space = A_PHYS_LDTPCI_IO_MATCH_BYTES; /* 0x00DC000000 */ 147 Q.io_space_size = 0x0002000000; 148 Q.cfg_space = A_PHYS_LDTPCI_CFG_MATCH_BYTES; /* 0x00DE000000 */ 149 Q.cfg_space_size = 0x0001000000; 150 151 Q.pci_mem_base = 0x40000000; 152 Q.pci_io_base = 0x00000000; 153 154 Q.mem_bit_endian = 0x0020000000; 155 Q.io_bit_endian = 0x0020000000; 156 Q.cfg_bit_endian = 0x0020000000; 157 158 Q.cfg_base = PHYS_TO_XKSEG_UNCACHED(Q.cfg_space | Q.cfg_bit_endian); 159 160 Q.msi_set_base = A_IMR_REGISTER(0, R_IMR_ALIAS_MAILBOX_SET_CPU); 161 Q.msi_clear_base = A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU); 162 Q.msi_bit_endian = 0x0020000000; 163} 164 165 166/* Templates for bus attributes. */ 167 168static const struct pci_bus sb1250_pci_bus = { 169 0, /* minimum grant */ 170 255, /* maximum latency */ 171 1, /* devsel time = medium */ 172 1, /* we support fast back-to-back */ 173 1, /* we support prefetch */ 174 1, /* we support 66 MHz */ 175 0, /* we don't support 64 bits */ 176 4000000, /* bandwidth: in 0.25us cycles / sec */ 177 0, /* initially no devices on bus */ 178}; 179 180static const struct pci_bus secondary_pci_bus = { 181 0, /* minimum grant */ 182 255, /* maximum latency */ 183 0, /* devsel time = unknown */ 184 0, /* configure fast back-to-back */ 185 0, /* we don't prefetch */ 186 0, /* configure 66 MHz */ 187 0, /* we don't support 64 bits */ 188 4000000, /* bandwidth: in 0.25us cycles / sec */ 189 0, /* initially no devices on bus */ 190}; 191 192#define MAXBUS 10 193static struct pci_bus _pci_bus[MAXBUS]; 194static int _pci_nbus = 0; 195 196#define SB1250_PCI_MAKE_TAG(b,d,f) \ 197 (((b) << 16) | ((d) << 11) | ((f) << 8)) 198 199#if defined(__MIPSEB) 200/* This is for big-endian with a match bits policy. */ 201#define SB1250_CFG_ADDR(t, o, w) \ 202 ((Q.cfg_base + (t) + (o)) ^ (4 - (w))) 203#elif defined(__MIPSEL) 204/* This is for little-endian, either policy. */ 205#define SB1250_CFG_ADDR(t, o, w) \ 206 (Q.cfg_base + (t) + (o)) 207#else 208#error "Must specifiy either MIPSEL or MIPSEB" 209#endif 210 211pcireg_t pci_conf_read8(pcitag_t, int); 212void pci_conf_write8(pcitag_t, int, pcireg_t); 213#ifndef pci_conf_read32 214#define pci_conf_read32 pci_conf_read 215#endif 216#ifndef pci_conf_write32 217#define pci_conf_write32 pci_conf_write 218#endif 219 220 221/* Access functions */ 222 223/* The following should return the index of the last usable bus port. */ 224int 225pci_maxport (void) 226{ 227 return PCI_PORTMAX; 228} 229 230 231/* The following must either fail or return the next sequential bus 232 number to make secondary/subordinate numbering work correctly. */ 233int 234pci_nextbus (int port) 235{ 236 int bus = _pci_nbus; 237 238 if (bus >= MAXBUS) 239 return -1; 240 _pci_nbus++; 241 return bus; 242} 243 244int 245pci_maxbus (int port) 246{ 247 return _pci_nbus - 1; 248} 249 250struct pci_bus * 251pci_businfo (int port, int bus) 252{ 253 return (bus < _pci_nbus ? &_pci_bus[bus] : NULL); 254} 255 256/* 257 * PCI address resources. 258 * NB: initial limits for address allocation are assumed to be aligned 259 * appropriately for PCI bridges (4K boundaries for I/O, 1M for memory). 260 */ 261 262pcireg_t 263pci_minmemaddr (int port) 264{ 265 /* skip the 16MB reserved for ISA mem space */ 266 return Q.pci_mem_base + 0x1000000; 267} 268 269pcireg_t 270pci_maxmemaddr (int port) 271{ 272 return Q.pci_mem_base + Q.mem_space_size; 273} 274 275pcireg_t 276pci_minioaddr (int port) 277{ 278 /* Skip the 32KB reserved for ISA i/o space. */ 279 return Q.pci_io_base + 0x8000; 280} 281 282pcireg_t 283pci_maxioaddr (int port) 284{ 285 return Q.pci_io_base + Q.io_space_size; 286} 287 288 289/* The SB-1250 integrated host bridges. */ 290 291#define PCI_VENDOR_SIBYTE 0x166d 292 293#define SB1250_PCI_BRIDGE (SB1250_PCI_MAKE_TAG(0,0,0)) 294#define SB1250_LDT_BRIDGE (SB1250_PCI_MAKE_TAG(0,1,0)) 295 296static int sb1250_in_device_mode; 297static int sb1250_ldt_slave_mode; 298static int sb1250_ldt_init; /* Set to one after LHB sees InitDone */ 299 300/* The pass 1 BCM1250 does not implement EOI cycles correctly. Later 301 passes do. The following variable controls whether PCI interrupt 302 mappings are programmed to be level-sensitive (EOI) or 303 edge-sensitive (no EOI) in LDT-PCI bridges. */ 304int eoi_implemented; 305 306 307/* Implementation-specific registers for the PCI Host Bridge (PHB) */ 308 309#define PHB_FEATURE_REG 0x40 310 311#define PHB_FEATURE_DEFAULTS 0x7DB38080 312 313#define PHB_MAP_REG_BASE 0x44 314#define PHB_MAP_N_ENTRIES 16 315 316/* The format of MAP table entries */ 317#define PHB_MAP_ENABLE (1 << 0) 318#define PHB_MAP_SEND_LDT (1 << 1) 319#define PHB_MAP_L2CA (1 << 2) 320#define PHB_MAP_ENDIAN (1 << 3) 321#define PHB_MAP_ADDR_SHIFT 12 322#define PHB_MAP_ADDR_MASK 0xFFFFF000 323#define PHB_MAP_ENTRY_SPAN (1 << 20) 324 325#define PHB_ERRORADDR_REG 0x84 326 327#define PHB_ADD_STAT_CMD_REG 0x88 328 329#define PHB_SUBSYSSET_REG 0x8C 330 331/* pass 2 additions */ 332 333#define PHB_READHOST_REG 0x94 334 335#define PHB_READHOST_DISABLE (0 << 0) /* write only */ 336#define PHB_READHOST_ENABLE (1 << 0) 337 338#define PHB_ADAPTEXT_REG 0x98 339 340#define PHB_DIS_DMAR_IOW_DEP (1 << 6) 341 342/* PCI host bridge configuration 343 * 344 * Note that the PCI host bridge has two, mostly disjoint, sets of 345 * configuration registers. One is used in Host mode and is 346 * accessible from the ZBbus; the other is used in Device mode and is 347 * accessible from the PCI bus. The MAP registers are shared but in 348 * Pass 1 are write-only, from the ZBbus side. In pass 2, they are 349 * readable iff read_host is set. 350 */ 351static void 352phb_init (void) 353{ 354 int i; 355 pcireg_t csr, cr, aer, icr; 356 pcireg_t t; /* used for reads that push writes */ 357 358 /* reset the PCI busses */ 359 /* PCI is only reset at system reset */ 360 361 /* PCI: disable and clear the BAR0 MAP registers */ 362 for (i = 0; i < PHB_MAP_N_ENTRIES; i++) 363 pci_conf_write32(SB1250_PCI_BRIDGE, PHB_MAP_REG_BASE + 4*i, 0); 364 365 /* Because they write to the ZBbus bank of configuration 366 registers, some of the following initializations are noops in 367 Device mode, but they do no harm. */ 368 369 /* PCI: set feature and timeout registers to their default. */ 370 pci_conf_write32(SB1250_PCI_BRIDGE, PHB_FEATURE_REG, PHB_FEATURE_DEFAULTS); 371 372 /* PCI: enable bridge to PCI and PCI memory accesses, including 373 write-invalidate, plus error handling */ 374 csr = PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE | 375 PCI_COMMAND_INVALIDATE_ENABLE | 376 PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE; 377 pci_conf_write32(SB1250_PCI_BRIDGE, PCI_COMMAND_STATUS_REG, csr); 378 379 /* PCI: clear errors */ 380 csr = pci_conf_read32(SB1250_PCI_BRIDGE, PCI_COMMAND_STATUS_REG); 381 csr |= PCI_STATUS_PARITY_ERROR | PCI_STATUS_SYSTEM_ERROR | 382 PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT | 383 PCI_STATUS_TARGET_TARGET_ABORT | PCI_STATUS_PARITY_DETECT; 384 pci_conf_write32(SB1250_PCI_BRIDGE, PCI_COMMAND_STATUS_REG, csr); 385 386 /* PCI: allow liberal ordering rules */ 387 /* Despite the manual, setting dis_dmar_iow_dep is recommended 388 unless strict ordering is required, since it can substantially 389 improve performance in the presence of slow devices. */ 390 aer = pci_conf_read32(SB1250_PCI_BRIDGE, PHB_ADAPTEXT_REG); 391 aer |= PHB_DIS_DMAR_IOW_DEP; 392 pci_conf_write32(SB1250_PCI_BRIDGE, PHB_ADAPTEXT_REG, aer); 393 394 /* PCI: set up interrupt mapping */ 395 icr = pci_conf_read32(SB1250_PCI_BRIDGE, PCI_BPARAM_INTERRUPT_REG); 396 icr &=~ (PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 397 icr |= (pci_int_line(pci_int_map_0(SB1250_PCI_BRIDGE)) 398 << PCI_INTERRUPT_LINE_SHIFT); 399 pci_conf_write32(SB1250_PCI_BRIDGE, PCI_BPARAM_INTERRUPT_REG, icr); 400 401 402 /* PCI: push the writes */ 403 t = pci_conf_read32(SB1250_PCI_BRIDGE, PCI_ID_REG); 404 405 cr = pci_conf_read32(SB1250_PCI_BRIDGE, PCI_CLASS_REG); 406 if (PCI_REVISION(cr) >= 2) { 407 pcireg_t id; 408 409 id = pci_conf_read32(SB1250_PCI_BRIDGE, PCI_ID_REG); 410 pci_conf_write32(SB1250_PCI_BRIDGE, PHB_SUBSYSSET_REG, id); 411 pci_conf_write32(SB1250_PCI_BRIDGE, PHB_READHOST_REG, 412 PHB_READHOST_DISABLE); 413 t = pci_conf_read32(SB1250_PCI_BRIDGE, PHB_READHOST_REG); /* push */ 414 } 415} 416 417 418/* Implementation-specific registers for the LDT Host Bridge (LHB) */ 419 420#define LHB_LINK_BASE 0x40 421 422#define LHB_LINKCMD_REG (LHB_LINK_BASE+LDT_COMMAND_CAP_OFF) 423 424#define LHB_LINKCTRL_REG (LHB_LINK_BASE+LDT_LINKn_OFF(0)) 425 426#define LHB_LINKCTRL_CRCERROR (1 << LDT_LINKCTRL_CRCERROR_SHIFT) 427#define LHB_LINKCTRL_ERRORS (LHB_LINKCTRL_CRCERROR | \ 428 LDT_LINKCTRL_LINKFAIL) 429 430#define LHB_LINKFREQ_REG (LHB_LINK_BASE+LDT_FREQ_OFF) 431#define LHB_LFREQ_REG (LHB_LINKFREQ_REG+1) 432 433#define LHB_LFREQ_200 LDT_FREQ_200 /* 200 MHz */ 434#define LHB_LFREQ_300 LDT_FREQ_300 /* 300 MHz */ 435#define LHB_LFREQ_400 LDT_FREQ_400 /* 400 MHz */ 436#define LHB_LFREQ_500 LDT_FREQ_500 /* 500 MHz */ 437#define LHB_LFREQ_600 LDT_FREQ_600 /* 600 MHz */ 438#define LHB_LFREQ_800 LDT_FREQ_800 /* 800 MHz */ 439 440#define LHB_SRI_CMD_REG 0x50 441 442#define LHB_SRI_CMD_SIPREADY (1 << 16) 443#define LHB_SRI_CMD_SYNCPTRCTL (1 << 17) 444#define LHB_SRI_CMD_REDUCESYNCZERO (1 << 18) 445#define LHB_SRI_CMD_DISSTARVATIONCNT (1 << 19) 446#define LHB_SRI_CMD_RXMARGIN_SHIFT 20 447#define LHB_SRI_CMD_RXMARGIN_MASK (0x1F << LHB_SRI_CMD_RXMARGIN_SHIFT) 448#define LHB_SRI_CMD_PLLCOMPAT (1 << 25) 449#define LHB_SRI_CMD_TXOFFSET_SHIFT 28 450#define LHB_SRI_CMD_TXOFFSET_MASK (0x7 << LHB_SRI_CMD_TXOFFSET_SHIFT) 451#define LHB_SRI_CMD_LINKFREQDIRECT (1 << 31) 452 453#define LHB_SRI_TXNUM_REG 0x54 454#define LHB_SRI_RXNUM_REG 0x58 455 456#define LHB_ERR_CTRL_REG 0x68 457 458#define LHB_ERR_CTRL 0x00FFFFFF 459#define LHB_ERR_STATUS 0xFF000000 460 461#define LHB_SRI_CTRL_REG 0x6C 462 463#define LHB_ASTAT_REG 0x70 464 465#define LHB_ASTAT_TGTDONE_SHIFT 0 466#define LHB_ASTAT_TGTDONE_MASK (0xFF << LHB_ASTAT_TGTDONE_SHIFT) 467 468#define LHB_TXBUFCNT_REG 0xC8 469 470#if (LDT_DEBUG > 1) 471static void 472show_ldt_status (void) 473{ 474 pcireg_t cmd; 475 476 cmd = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_CMD_REG); 477 xprintf(" SriCmd %04x\n", (cmd >> 16) & 0xFFFF); 478 xprintf(" TXNum %08x TxDen %02x RxNum %08x RxDen %02x ErrCtl %08x\n", 479 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_TXNUM_REG), 480 cmd & 0xFF, 481 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_RXNUM_REG), 482 (cmd >> 8) & 0xFF, 483 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG)); 484 xprintf(" LDTCmd %08x LDTCfg %08x LDTFreq %08x\n", 485 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCMD_REG), 486 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG), 487 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKFREQ_REG)); 488} 489#else 490#define show_ldt_status() ((void)0) 491#endif /* LDT_DEBUG */ 492 493/* 494 * Assert warm reset for the given number of ticks. 495 */ 496static void 497lhb_link_reset (int delay) 498{ 499 pcireg_t prev, cmd; 500 pcireg_t brctrl; 501 502 prev = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCMD_REG); 503 cmd = prev | LDT_COMMAND_WARM_RESET; 504 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_LINKCMD_REG, cmd); 505 506 brctrl = pci_conf_read32(SB1250_LDT_BRIDGE, PPB_BRCTL_INTERRUPT_REG); 507 brctrl |= PPB_BRCTL_SECONDARY_RESET; 508 pci_conf_write32(SB1250_LDT_BRIDGE, PPB_BRCTL_INTERRUPT_REG, brctrl); 509 510 cfe_sleep(delay); 511 512 brctrl &=~ PPB_BRCTL_SECONDARY_RESET; 513 pci_conf_write32(SB1250_LDT_BRIDGE, PPB_BRCTL_INTERRUPT_REG, brctrl); 514 brctrl = pci_conf_read32(SB1250_LDT_BRIDGE, PPB_BRCTL_INTERRUPT_REG); 515 516 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_LINKCMD_REG, prev); 517} 518 519/* 520 * Poll for InitDone on LHB's outgoing link. 521 */ 522static int 523lhb_link_ready (int maxwait) 524{ 525 volatile pcireg_t ctrl; 526 int count; 527 int linkerr; 528 529 count = 0; 530 linkerr = 0; 531 ctrl = 0; 532 533 while ((ctrl & (LDT_LINKCTRL_INITDONE | LDT_LINKCTRL_LINKFAIL)) == 0 534 && count < maxwait) { 535 ctrl = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG); 536 if ((ctrl & LHB_LINKCTRL_ERRORS) != 0 && !linkerr) { 537 if (_pciverbose > PCI_FLG_NORMAL) 538 pci_tagprintf(SB1250_LDT_BRIDGE, 539 "LDT Err, count %d Err = 0x%04x\n", 540 count, ctrl & 0xFFFF); 541 linkerr = 1; 542 } 543 if (count >= maxwait) { 544 if (_pciverbose > PCI_FLG_NORMAL) 545 pci_tagprintf(SB1250_LDT_BRIDGE, "Link timeout\n"); 546 linkerr = 1; 547 } 548 cfe_usleep(10); 549 count += 10; 550 } 551 552 if (_pciverbose > PCI_FLG_NORMAL) 553 pci_tagprintf(SB1250_LDT_BRIDGE, "lhb_link_ready: count %d\n", count); 554 return linkerr; 555} 556 557static void 558lhb_null_config (void) 559{ 560 /* Even if the LDT fabric is not to be initialized by us, we must 561 write the bus number, base and limit registers in the host 562 bridge for proper operation (see 8.11.1) */ 563 pcireg_t iodata; 564 pcireg_t memdata; 565 566 /* The primary bus is 0. Set secondary, subordinate to 0 also. */ 567 pci_conf_write32(SB1250_LDT_BRIDGE, PPB_BUSINFO_REG, 0); 568 569 iodata = pci_conf_read32(SB1250_LDT_BRIDGE, PPB_IO_STATUS_REG); 570 iodata &=~ (PPB_IO_BASE_MASK | PPB_IO_LIMIT_MASK); 571 iodata |= (1 << 4) | (0 << (8+4)); 572 pci_conf_write32(SB1250_LDT_BRIDGE, PPB_IO_STATUS_REG, iodata); 573 iodata = 0x0000F200; /* recommended value */ 574 pci_conf_write32(SB1250_LDT_BRIDGE, PPB_IO_UPPER_REG, iodata); 575 576 memdata = pci_conf_read32(SB1250_LDT_BRIDGE, PPB_MEM_REG); 577 memdata &=~ (PPB_MEM_BASE_MASK | PPB_MEM_LIMIT_MASK); 578 memdata |= (1 << 4) | (0 << (16+4)); /* empty window */ 579 pci_conf_write32(SB1250_LDT_BRIDGE, PPB_MEM_REG, memdata); 580} 581 582 583/* 584 * LDT host bridge initialization. 585 */ 586static void 587lhb_init (int rev017, unsigned linkfreq, unsigned linkwidth, unsigned buffctl) 588{ 589 int i; 590 pcireg_t cr; 591 pcireg_t sri_cmd; 592 volatile pcireg_t t; /* used for reads that push writes */ 593 uint8_t ldt_freq; 594 int linkerr; 595 int retry; 596 597 sb1250_ldt_init = 0; 598 599 /* The most recent software advisory for working around PLL 600 startup problems suggests setting LdtPLLCompat, then changing 601 the link frequency to 400 MHz and back. The toggling is to be 602 done "before accessing anything in the HT interface or on the 603 bus (checking for link state, configuration, etc.)", since 604 there is a small chance that a read while the clock is free 605 running could fail with a system hang. 606 607 Unfortunately, with some revisions of the silicon it's then 608 impossible to test for SipReady already set and warn 609 appropriately. In development environments, the latter seems 610 more useful. In other environments, the following read should 611 be replaced by a suitable constant (see below) and a cold 612 system reset should be done if InitDone fails to set. */ 613 614 sri_cmd = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_CMD_REG); 615 616 if ((sri_cmd & LHB_SRI_CMD_SIPREADY) == 0) { 617 /* To bring the PLL into lock, we must set the frequency to 400 618 MHz and back to 200 MHz in Compat mode before otherwise 619 initializing any of the link registers. */ 620 621 t = sri_cmd | LHB_SRI_CMD_PLLCOMPAT; 622 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_SRI_CMD_REG, t); 623 cfe_usleep(100); /* Delay, since we don't want to read back. */ 624 pci_conf_write8(SB1250_LDT_BRIDGE, LHB_LFREQ_REG, LHB_LFREQ_400); 625 cfe_sleep (CFE_HZ/2); 626 pci_conf_write8(SB1250_LDT_BRIDGE, LHB_LFREQ_REG, LHB_LFREQ_200); 627 t = pci_conf_read8(SB1250_LDT_BRIDGE, LHB_LFREQ_REG); /* push */ 628 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_SRI_CMD_REG, sri_cmd); 629 } 630 631 /* Clear any pending error bits */ 632 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG); 633 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG, t | LHB_ERR_STATUS); 634 635 cr = pci_conf_read32(SB1250_LDT_BRIDGE, PCI_CLASS_REG); 636 eoi_implemented = (PCI_REVISION(cr) >= 2); 637 638 /* First set up System Reset Initialization registers (Table 639 8-12). This code is designed to be run following a full reset. 640 After a chip warm reset (SipReady already set), most of it is 641 skipped. Depending on previous history, that can leave things 642 in an inconsistent state, but there's no recovery from that 643 short of a chip cold reset. */ 644 645 if (sri_cmd & LHB_SRI_CMD_SIPREADY) { 646 pci_tagprintf(SB1250_LDT_BRIDGE, "Warning: SipReady already set\n"); 647 /* Try just doing a warm reset. */ 648 lhb_link_reset(CFE_HZ/10); 649 goto finish; 650 } 651 652 if (rev017) { 653 /* LDT 0.17 compatibility mode: 654 SriCmd = (!LinkFreqDirect, LdtPLLCompat, [DisStarveCnt,] 655 TxInitialOffset=5, 656 RxMargin=2, 657 !SipReady) 658 */ 659 sri_cmd = LHB_SRI_CMD_PLLCOMPAT; 660 } else { 661 /* LDT 1.0x partial compatibility mode: 662 SriCmd = (!LinkFreqDirect, !LdtPLLCompat, [DisStarveCnt,] 663 TxInitialOffset=5, 664 RxMargin=2, 665 !SipReady) 666 */ 667 sri_cmd = 0; 668 } 669 670 /* Empirically, RxMargin is not critical with a 200 MHz LDT clock 671 but must be small (less than 15, and 0 seems reliable) with a 672 400 MHz LDT clock. Current default is 2. */ 673 sri_cmd |= ((2 << LHB_SRI_CMD_RXMARGIN_SHIFT) | 674 (5 << LHB_SRI_CMD_TXOFFSET_SHIFT) | 675 0x1010); /* Rx/TxDen defaults */ 676 677 /* Setting DisStarveCnt is recommended for Pass 1 parts. */ 678 if (PCI_REVISION(cr) == 1) 679 sri_cmd |= LHB_SRI_CMD_DISSTARVATIONCNT; 680 681 /* Map the link frequency to a supported value. Note: we assume 682 that the CPU and IOB0 clocks are set high enough for the 683 selected frequency. In LDT 0.17 compatibility mode, this is 684 the final frequency. In LDT 1.0x partial compatibility mode, 685 this becomes the target frequency for link sizing. */ 686 if (linkfreq < 200) 687 linkfreq = 200; 688 else if (linkfreq > 800) 689 linkfreq = 800; 690 691 /* Passes 1 and 2 do not support LINKFREQDIRECT. Force a standard value. */ 692 if (PCI_REVISION(cr) < 3) { 693 linkfreq = ((linkfreq + (50-1))/100) * 100; 694 if (linkfreq == 700) linkfreq = 600; /* No code point */ 695 } 696 else { 697 linkfreq = ((linkfreq + (25-1))/50) * 50; 698 } 699 if (rev017) 700 xprintf("HyperTransport: %d MHz\n", linkfreq); 701 702 if (linkfreq % 100 == 0 && linkfreq != 700) { 703 /* Encode supported standard values per the LDT spec. */ 704 switch (linkfreq) { 705 default: 706 case 200: ldt_freq = LHB_LFREQ_200; break; 707 case 300: ldt_freq = LHB_LFREQ_300; break; 708 case 400: ldt_freq = LHB_LFREQ_400; break; 709 case 500: ldt_freq = LHB_LFREQ_500; break; 710 case 600: ldt_freq = LHB_LFREQ_600; break; 711 case 800: ldt_freq = LHB_LFREQ_800; break; 712 } 713 } else { 714 /* Compute PLL ratio for 100 MHz reference in 3b1 format (Table 23) */ 715 sri_cmd |= LHB_SRI_CMD_LINKFREQDIRECT; 716 ldt_freq = linkfreq / 50; 717 } 718 719 /* Normalize the maximum link width (only 8 and 16 supported) */ 720 if (linkwidth >= 16) { 721 linkwidth = 16; 722#if CFG_LDT 723 ldt_set_max_width(LDT_WIDTH_16); 724#endif 725 } 726 else { 727 linkwidth = 8; 728#if CFG_LDT 729 ldt_set_max_width(LDT_WIDTH_8); 730#endif 731 } 732 733 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_SRI_CMD_REG, sri_cmd); 734 735 /* Set the SRI dividers */ 736 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_SRI_TXNUM_REG, 0x0000FFFF); 737 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_SRI_RXNUM_REG, 0x0000FFFF); 738 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_RXNUM_REG); /* push */ 739 740 /* Directed test: SPIN(10) here */ 741 for (i = 0; i < 10; i++) 742 t = pci_conf_read32(SB1250_LDT_BRIDGE, PCI_ID_REG); 743 744 /* In previous versions of CFE, the Pass 1 workaround for 200 MHz 745 PLL failure was here. See above for a more general solution 746 applicable to all revisions. */ 747 748 if (rev017) { 749 pci_conf_write8(SB1250_LDT_BRIDGE, LHB_LFREQ_REG, ldt_freq); 750 } 751 752 /* Set the Error Control register (some fatal interrupts). */ 753 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG, 0x00001209); 754 755 /* Set the SRI Xmit Control register. */ 756 pci_conf_write32(SB1250_LDT_BRIDGE, 757 LHB_SRI_CTRL_REG, 0x00040000 | buffctl); 758 if (_pciverbose > PCI_FLG_NORMAL) 759 pci_tagprintf(SB1250_LDT_BRIDGE, "BuffCtl = 0x%08x\n", 760 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_CTRL_REG)); 761 762 /* Set the Tx buffer size (16 buffers each). */ 763 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_TXBUFCNT_REG, 0x00FFFFFF); 764 765 /* Push the writes */ 766 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_TXBUFCNT_REG); /* push */ 767 768 /* Indicate SIP Ready */ 769 sri_cmd |= LHB_SRI_CMD_SIPREADY; 770 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_SRI_CMD_REG, sri_cmd); 771 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_SRI_CMD_REG); /* push */ 772 773 retry = (sb1250_ldt_slave_mode ? 4 : 1); 774 for (;;) { 775 /* wait for LinkFail or InitDone */ 776 linkerr = lhb_link_ready(1<<20); /* empirical delay */ 777 778 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG); 779 if ((t & LHB_ERR_STATUS) != 0) { 780 linkerr = 1; 781 if (_pciverbose > PCI_FLG_NORMAL) 782 pci_tagprintf(SB1250_LDT_BRIDGE, 783 "ErrStat = 0x%02x\n", t >> 24); 784 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG, 785 t | LHB_ERR_STATUS); 786 } 787 788 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG); 789 if ((t & LHB_LINKCTRL_ERRORS) != 0) { 790 linkerr = 1; 791 if (_pciverbose > PCI_FLG_NORMAL) 792 pci_tagprintf(SB1250_LDT_BRIDGE, 793 "LinkCtrl CRCErr = 0x%01x\n", (t >> 8) & 0xF); 794 } 795 796 if (!linkerr || retry == 0) 797 break; 798 799 /* Clear errors in preparation for another try. Delay long 800 enough (below) for CRC errors to reappear; otherwise, the 801 link can look good, but subsequent non-posted transactions 802 will hang. */ 803 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG); 804 t |= LDT_LINKCTRL_CRCERROR_MASK; /* Clear CrcErr bits */ 805 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG, t); 806 807 /* Try again. Do a reset iff an LDT master, since a poorly 808 timed reset by a slave will break any link initialization 809 in progress. */ 810 retry--; 811 812 if (sb1250_ldt_slave_mode) 813 cfe_sleep(CFE_HZ/10); 814 else 815 lhb_link_reset(CFE_HZ/10); 816 } 817 818 /* Rev 0.17 does not support dyanmic frequency updates. */ 819 if (!rev017) { 820 /* Leave the target frequency in the LinkFreq register, which is 821 just a shadow until a link reset happens. */ 822 pci_conf_write8(SB1250_LDT_BRIDGE, LHB_LFREQ_REG, ldt_freq); 823 } 824 825 finish: 826 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG); 827 828 if ((t & LDT_LINKCTRL_INITDONE) == 0) { 829#if CFG_LDT 830 xprintf("HyperTransport not initialized: InitDone not set\n"); 831 if (_pciverbose > PCI_FLG_NORMAL) 832 pci_tagprintf(SB1250_LDT_BRIDGE, 833 " Link Cmd = 0x%08x, Link Ctrl = 0x%08x\n", 834 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCMD_REG), 835 pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG)); 836#endif /* CFG_LDT */ 837 /* In production code, consider doing a chip cold reset (via 838 the SCD) here if the system requires an initialized HT bus. 839 See the advisory on HT PLL problems. */ 840 } else if ((t & LHB_LINKCTRL_ERRORS) != 0) { 841 xprintf("HyperTransport not initialized: " 842 "LinkFail or CRCErr set, LinkCtrl = 0x%08x\n", t); 843 } else if (!sb1250_ldt_slave_mode) 844 sb1250_ldt_init = 1; 845 846 /* Clear any pending error bits */ 847 t = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG); 848 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_ERR_CTRL_REG, t & 0xFF000000); 849 850 if (sb1250_ldt_slave_mode) { 851 /* This is LDT slave mode. The documentation is not very clear 852 on how much low level initialization should be done before 853 sleeping. We just set Master Enable so that we can subsequently 854 access LDT space. */ 855 pcireg_t cmd; 856 857 /* If there are intermediate devices on the LDT, we would like 858 our addressing to match the master's, but we don't know it 859 and can't force it here. Instead, we close all the windows 860 into configurable space, which is at least safe. */ 861 lhb_null_config(); 862 863 cmd = pci_conf_read32(SB1250_LDT_BRIDGE, PCI_COMMAND_STATUS_REG); 864 cmd &= (PCI_COMMAND_MASK << PCI_COMMAND_SHIFT); /* preserve status */ 865 cmd |= PCI_COMMAND_MASTER_ENABLE; 866 pci_conf_write32(SB1250_LDT_BRIDGE, PCI_COMMAND_STATUS_REG, cmd); 867 } else if (!sb1250_ldt_init) { 868 pcireg_t lr; 869 870 lhb_null_config(); 871 872 /* Also, terminate the link */ 873 lr = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG); 874 lr |= LDT_LINKCTRL_EOC; 875 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG, lr); 876 lr |= LDT_LINKCTRL_TXOFF; 877 pci_conf_write32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG, lr); 878 } 879 880 show_ldt_status(); 881} 882 883 884/* 885 * Called to initialise IOB0 and the host bridges at the beginning of time. 886 */ 887int 888pci_hwinit (int port, pci_flags_t flags) 889{ 890 int i; 891 int rev017; 892 unsigned linkfreq, linkwidth, buffctl; 893 uint64_t syscfg; 894 const char *str; 895 896 /* define the address spaces and capabilities */ 897 898 if (port != 0) 899 return -1; 900 pci_set_root(); 901 902 /* initialise global data */ 903 904 syscfg = SBREADCSR(A_SCD_SYSTEM_CFG); 905 sb1250_in_device_mode = ((syscfg & M_SYS_PCI_HOST) == 0); 906 if (cfe_startflags & CFE_LDT_SLAVE) 907 sb1250_ldt_slave_mode = 1; 908 else 909 sb1250_ldt_slave_mode = 0; 910 911 eoi_implemented = 0; /* conservative default */ 912 913 /* Check for any relevant environment variables. */ 914 rev017 = ((flags & PCI_FLG_LDT_REV_017) != 0); 915 916 /* Choose the LDT link frequency. [C]SWARM boards are now set for 917 400 MHz by default */ 918 str = env_getenv("LDT_LINKFREQ"); 919 linkfreq = (str ? atoi(str) : 400); 920 921 /* Choose the HT maximum link width. The 1250 itself is 922 restricted to 8 bits, but allow downstream links to be 923 wider. */ 924 925 str = env_getenv("LDT_LINKWIDTH"); 926 linkwidth = (str ? atoi(str) : 16); 927 928 /* Choose the buffer allocation (favor posted writes by default) */ 929 str = env_getenv("LDT_BUFFERS"); 930 buffctl = (str ? atoi(str) & 0xFFFF : 0x2525); 931 932 _pci_bus[_pci_nbus] = sb1250_pci_bus; 933 _pci_bus[_pci_nbus].port = port; 934 _pci_nbus++; 935 for (i = _pci_nbus; i < MAXBUS; i++) 936 _pci_bus[i] = secondary_pci_bus; 937 938 /* stop the SB-1250 from servicing any further PCI or LDT requests */ 939 pci_conf_write32(SB1250_PCI_BRIDGE, PCI_COMMAND_STATUS_REG, 0); 940 pci_conf_write32(SB1250_LDT_BRIDGE, PCI_COMMAND_STATUS_REG, 0); 941 942 /* initialize the PCI host bridge */ 943 phb_init(); 944 945 /* initialize the LDT host bridge */ 946 if (pci_conf_read32(SB1250_LDT_BRIDGE, PCI_ID_REG) != 0xffffffff) 947 lhb_init(rev017, linkfreq, linkwidth, buffctl); 948 949 cfe_sleep(CFE_HZ); /* add some delay */ 950 951 return 0; 952} 953 954/* 955 * Called to update the host bridge after we've scanned each PCI device 956 * and know what is possible. 957 */ 958void 959pci_hwreinit (int port, pci_flags_t flags) 960{ 961 pcireg_t cmd; 962 963 /* note: this is not officially supported by sb1250, perhaps no effect! */ 964 if (_pci_bus[0].fast_b2b) { 965 /* fast back-to-back is supported by all devices */ 966 cmd = pci_conf_read32(SB1250_PCI_BRIDGE, PCI_COMMAND_STATUS_REG); 967 cmd &= (PCI_COMMAND_MASK << PCI_COMMAND_SHIFT); /* preserve status */ 968 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 969 pci_conf_write32(SB1250_PCI_BRIDGE, PCI_COMMAND_STATUS_REG, cmd); 970 } 971 972 /* Latency timer, cache line size set by pci_setup_devices (pciconf.c) */ 973 974 /* enable PCI read/write error interrupts */ 975 /* XXX */ 976} 977 978 979/* The following functions provide for device-specific setup required 980 during configuration. There is nothing SiByte-specific about them, 981 and it would be better to do the packaging and registration in a 982 more modular way. */ 983 984#if CFG_LDT 985#define PCI_VENDOR_ALSC 0x14D9 986#define PCI_PRODUCT_ALSC_SP1011 0x0010 987#define PCI_PRODUCT_ALSC_AS90L10208 0x9000 988extern void sp1011_setup(pcitag_t tag, pci_flags_t flags); 989extern void as90l10208_setup(pcitag_t tag, pci_flags_t flags); 990 991#define PCI_VENDOR_AMD 0x1022 992#define PCI_PRODUCT_PLX_HT7520 0x7450 993#define PCI_PRODUCT_PLX_HT7520_APIC 0x7451 994extern void ht7520apic_preset(pcitag_t tag); 995extern void ht7520apic_setup(pcitag_t tag); 996 997#define PCI_PRODUCT_AMD_8151 0x7454 998#endif /* CFG_LDT */ 999 1000/* Dispatch functions for device pre- and post-configuration hooks. */ 1001 1002/* Called for each hostbridge, to discover and scan secondary buses */ 1003void 1004pci_businit_hostbridge (pcitag_t tag, pci_flags_t flags) 1005{ 1006} 1007 1008/* Called for each function prior to assigning PCI resources. */ 1009int 1010pci_device_preset (pcitag_t tag) 1011{ 1012 pcireg_t id; 1013 int skip; 1014 1015 skip = 0; 1016 id = pci_conf_read(tag, PCI_ID_REG); 1017 switch (PCI_VENDOR(id)) { 1018 case PCI_VENDOR_SIBYTE: 1019 /* Check for a host bridge seen internally, in which case 1020 we don't want to allocate any address space for its 1021 BARs. */ 1022 if (tag == SB1250_PCI_BRIDGE) 1023 skip = 1; 1024 break; 1025#if CFG_LDT 1026 case PCI_VENDOR_AMD: 1027 switch (PCI_PRODUCT(id)) { 1028 case PCI_PRODUCT_PLX_HT7520_APIC: 1029 ht7520apic_preset (tag); 1030 break; 1031 case PCI_PRODUCT_AMD_8151: 1032 skip = 1; 1033 break; 1034 default: 1035 break; 1036 } 1037 break; 1038#endif /* CFG_LDT */ 1039 default: 1040 break; 1041 } 1042 return skip; 1043} 1044 1045 1046/* Called for each non-bridge (Type 0) function after assigning the BAR 1047 and InterruptLine (XXX check this) resources.. */ 1048void 1049pci_device_setup (pcitag_t tag) 1050{ 1051 pcireg_t id = pci_conf_read(tag, PCI_ID_REG); 1052 1053 switch (PCI_VENDOR(id)) { 1054#if CFG_LDT 1055 case PCI_VENDOR_AMD: 1056 if (PCI_PRODUCT(id) == PCI_PRODUCT_PLX_HT7520_APIC) 1057 ht7520apic_setup (tag); 1058 break; 1059#endif /* CFG_LDT */ 1060 default: 1061 break; 1062 } 1063} 1064 1065/* Called for each bridge (Type 1) function after configuring the 1066 secondary bus, to allow device-specific initialization. */ 1067void 1068pci_bridge_setup (pcitag_t tag, pci_flags_t flags) 1069{ 1070 pcireg_t id = pci_conf_read(tag, PCI_ID_REG); 1071 1072 switch (PCI_VENDOR(id)) { 1073#if CFG_LDT 1074 case PCI_VENDOR_ALSC: 1075 switch (PCI_PRODUCT(id)) { 1076 case PCI_PRODUCT_ALSC_SP1011: 1077 sp1011_setup (tag, flags); 1078 break; 1079 case PCI_PRODUCT_ALSC_AS90L10208: 1080 as90l10208_setup (tag, flags); 1081 break; 1082 default: 1083 break; 1084 } 1085 break; 1086 case PCI_VENDOR_AMD: 1087 /* The PLX ht7520 requires configuration of the 1088 interrupt mapping, but it packages the IOAPIC as a 1089 separate function, registers of which will not yet have 1090 been initialized if the standard traversal order is 1091 followed. See pci_device_setup above. */ 1092 break; 1093#endif /* CFG_LDT */ 1094 default: 1095 break; 1096 } 1097} 1098 1099 1100/* Machine dependent access primitives and utility functions */ 1101 1102void 1103pci_flush (void) 1104{ 1105 /* note: this is a noop for the SB-1250. */ 1106} 1107 1108 1109pcitag_t 1110pci_make_tag (int port, int bus, int device, int function) 1111{ 1112 return SB1250_PCI_MAKE_TAG(bus, device, function); 1113} 1114 1115void 1116pci_break_tag (pcitag_t tag, 1117 int *portp, int *busp, int *devicep, int *functionp) 1118{ 1119 if (portp) *portp = (tag >> 24) & PCI_PORTMAX; 1120 if (busp) *busp = (tag >> 16) & PCI_BUSMAX; 1121 if (devicep) *devicep = (tag >> 11) & PCI_DEVMAX; 1122 if (functionp) *functionp = (tag >> 8) & PCI_FUNCMAX; 1123} 1124 1125 1126int 1127pci_canscan (pcitag_t tag) 1128{ 1129 int port, bus, device, function; 1130 1131 pci_break_tag (tag, &port, &bus, &device, &function); 1132 1133 if (port > PCI_PORTMAX 1134 || bus > PCI_BUSMAX || device > PCI_DEVMAX || function > PCI_FUNCMAX) 1135 return 0; 1136 1137 if (bus == 0) { 1138 if (sb1250_in_device_mode) { 1139 /* Scan the LDT chain, but only the LDT host bridge on PCI. */ 1140 if (device != 1) 1141 return 0; 1142 } 1143 if (sb1250_ldt_slave_mode || !sb1250_ldt_init) { 1144 /* Scan the PCI devices but not the LDT chain. */ 1145 if (device == 1) 1146 return 0; 1147 } 1148 if (device > 20) { 1149 /* Chip bug: asserts IDSEL for device 20 for all devices > 20. */ 1150 return 0; 1151 } 1152 } 1153 1154 return 1; 1155} 1156 1157int 1158pci_probe_tag(pcitag_t tag) 1159{ 1160 physaddr_t addrp; 1161 pcireg_t data; 1162 1163 if (!pci_canscan(tag)) 1164 return 0; 1165 1166 addrp = (physaddr_t) SB1250_CFG_ADDR(tag, PCI_ID_REG, 4); 1167 1168 /* An earlier version of this code cleared the MasterAbort and 1169 TargetAbort bits in the PCI host bridge, did the read, and 1170 looked for those bits to be set. For the SB-1250, that's 1171 inappropriate because 1172 - it's the wrong host bridge for devices behind LDT. 1173 - PCI host bridge registers aren't readable in Device mode. 1174 - it loses status if testing the PCI host bridge itself. 1175 We rely on getting 0xffff when reading the vendor ID. Note 1176 that this still has side effects on the host bridge registers. 1177 */ 1178 1179 data = phys_read32(addrp); /* device + vendor ID */ 1180 mips_wbflush(); 1181 1182 /* if it returned all vendor id bits set, it's not a device */ 1183 return (PCI_VENDOR(data) != 0xFFFF); 1184} 1185 1186 1187/* Read/write access to PCI configuration registers. For most 1188 applications, pci_conf_read<N> and pci_conf_write<N> are deprecated 1189 unless N = 32. */ 1190 1191static pcireg_t 1192pci_conf_readn(pcitag_t tag, int reg, int width) 1193{ 1194 physaddr_t addrp; 1195 pcireg_t data; 1196#if (PCI_DEBUG != 0) 1197 int port, bus, device, function; 1198 1199 if (reg & (width-1) || reg < 0 || reg >= PCI_REGMAX) { 1200 if (_pciverbose != 0) 1201 pci_tagprintf(tag, "pci_conf_readn: bad reg 0x%x\n", reg); 1202 return 0; 1203 } 1204 1205 pci_break_tag(tag, &port, &bus, &device, &function); 1206 if (bus > PCI_BUSMAX || device > PCI_DEVMAX || function > PCI_FUNCMAX) { 1207 if (_pciverbose != 0) 1208 pci_tagprintf(tag, "pci_conf_readn: bad tag 0x%x\n", tag); 1209 return 0; 1210 } 1211#endif /* PCI_DEBUG */ 1212 1213 mips_wbflush(); 1214 1215 addrp = (physaddr_t) SB1250_CFG_ADDR(tag, reg, width); 1216 switch (width) { 1217 case 1: 1218 data = (pcireg_t) phys_read8(addrp); 1219 break; 1220 case 2: 1221 data = (pcireg_t) phys_read16(addrp); 1222 break; 1223 default: 1224 case 4: 1225 data = (pcireg_t) phys_read32(addrp); 1226 break; 1227 } 1228 1229 mips_wbflush(); 1230 1231 return data; 1232} 1233 1234pcireg_t 1235pci_conf_read8(pcitag_t tag, int reg) 1236{ 1237 return pci_conf_readn(tag, reg, 1); 1238} 1239 1240pcireg_t 1241pci_conf_read16(pcitag_t tag, int reg) 1242{ 1243 return pci_conf_readn(tag, reg, 2); 1244} 1245 1246pcireg_t 1247pci_conf_read(pcitag_t tag, int reg) 1248{ 1249 return pci_conf_readn(tag, reg, 4); 1250} 1251 1252static void 1253pci_conf_writen(pcitag_t tag, int reg, pcireg_t data, int width) 1254{ 1255 physaddr_t addrp; 1256#if (PCI_DEBUG != 0) 1257 int port, bus, device, function; 1258 1259 if (reg & (width-1) || reg < 0 || reg > PCI_REGMAX) { 1260 if (_pciverbose != 0) 1261 pci_tagprintf(tag, "pci_conf_writen: bad reg 0x%x\n", reg); 1262 return; 1263 } 1264 1265 pci_break_tag(tag, &port, &bus, &device, &function); 1266 if (bus > PCI_BUSMAX || device > PCI_DEVMAX || function > PCI_FUNCMAX) { 1267 if (_pciverbose != 0) 1268 pci_tagprintf(tag, "pci_conf_writen: bad tag 0x%x\n", tag); 1269 return; 1270 } 1271#endif /* PCI_DEBUG */ 1272 1273 mips_wbflush(); 1274 1275 addrp = (physaddr_t) SB1250_CFG_ADDR(tag, reg, width); 1276 switch (width) { 1277 case 1: 1278 phys_write8(addrp, data); 1279 break; 1280 case 2: 1281 phys_write16(addrp, data); 1282 break; 1283 default: 1284 case 4: 1285 phys_write32(addrp, data); 1286 break; 1287 } 1288 1289 mips_wbflush(); 1290} 1291 1292void 1293pci_conf_write8(pcitag_t tag, int reg, pcireg_t data) 1294{ 1295 pci_conf_writen(tag, reg, data, 1); 1296} 1297 1298void 1299pci_conf_write16(pcitag_t tag, int reg, pcireg_t data) 1300{ 1301 pci_conf_writen(tag, reg, data, 2); 1302} 1303 1304void 1305pci_conf_write(pcitag_t tag, int reg, pcireg_t data) 1306{ 1307 pci_conf_writen(tag, reg, data, 4); 1308} 1309 1310/* Acked writes are intended primarily for updating the unitID field 1311 during HT fabric initialization. The write changes the address of 1312 the target, so further accesses should be avoided until the write 1313 completes or times out. */ 1314int 1315pci_conf_write_acked(pcitag_t tag, int reg, pcireg_t data) 1316{ 1317 int done; 1318 1319 if (sb1250_ldt_init) { 1320 int port, bus; 1321 pcireg_t bus_info, cr; 1322 int i; 1323 1324 pci_break_tag(tag, &port, &bus, NULL, NULL); 1325 bus_info = pci_conf_read(SB1250_LDT_BRIDGE, PPB_BUSINFO_REG); 1326 1327 if (bus >= PPB_BUSINFO_SECONDARY(bus_info) 1328 && bus <= PPB_BUSINFO_SUBORD(bus_info)) { 1329 1330 /* Write through the LDT host bridge. An HT configuration 1331 write is non-posted, but the ZBbus write completes as 1332 if it were posted. The following code assumes there 1333 are no overlapping non-posted HT writes. */ 1334 1335 cr = pci_conf_read(SB1250_LDT_BRIDGE, PCI_CLASS_REG); 1336 if (PCI_REVISION(cr) >= 2) { 1337 /* Current parts can count tgt_done responses. */ 1338 unsigned int count, prev_count; 1339 1340 prev_count = pci_conf_read(SB1250_LDT_BRIDGE, LHB_ASTAT_REG); 1341 prev_count &= LHB_ASTAT_TGTDONE_MASK; 1342 1343 pci_conf_write(tag, reg, data); 1344 1345 for (i = 0; i < 1000; i++) { 1346 count = pci_conf_read(SB1250_LDT_BRIDGE, LHB_ASTAT_REG); 1347 count &= LHB_ASTAT_TGTDONE_MASK; 1348 if (count != prev_count) 1349 break; 1350 } 1351 done = (count != prev_count); 1352 } else { 1353 /* For pass 1, a couple of innocuous writes seems the 1354 best we can do (a read with the new tag could hang) */ 1355 pci_conf_write(tag, reg, data); 1356 for (i = 0; i < 10; i++) 1357 pci_conf_write(tag, PCI_ID_REG, 0); 1358 done = 1; 1359 } 1360 } else { 1361 /* Write through the PCI host bridge. Just read it back. */ 1362 1363 pci_conf_write(tag, reg, data); 1364 (void) pci_conf_read(tag, reg); /* Push the write */ 1365 done = 1; 1366 } 1367 } else { 1368 /* No LDT. Write and read back. */ 1369 1370 pci_conf_write(tag, reg, data); 1371 (void) pci_conf_read(tag, reg); 1372 done = 1; 1373 } 1374 return done; 1375} 1376 1377 1378 1379int 1380pci_map_io(pcitag_t tag, int reg, pci_endian_t endian, phys_addr_t *pap) 1381{ 1382 pcireg_t address; 1383 phys_addr_t pa; 1384 1385 if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) { 1386 if (_pciverbose != 0) 1387 pci_tagprintf(tag, "pci_map_io: bad request\n"); 1388 return -1; 1389 } 1390 1391 address = pci_conf_read(tag, reg); 1392 1393 if ((address & PCI_MAPREG_TYPE_IO) == 0) { 1394 if (_pciverbose != 0) 1395 pci_tagprintf(tag, "pci_map_io: attempt to i/o map a memory region\n"); 1396 return -1; 1397 } 1398 1399 pa = ((address & PCI_MAPREG_IO_ADDR_MASK) - Q.pci_io_base) + Q.io_space; 1400 if (endian == PCI_MATCH_BITS) 1401 pa |= Q.io_bit_endian; 1402 *pap = pa; 1403 return 0; 1404} 1405 1406int 1407pci_map_mem(pcitag_t tag, int reg, pci_endian_t endian, phys_addr_t *pap) 1408{ 1409 pcireg_t address; 1410 phys_addr_t pa; 1411 1412 if (reg == PCI_MAPREG_ROM) { 1413 /* expansion ROM */ 1414 address = pci_conf_read(tag, reg); 1415 if ((address & PCI_MAPREG_ROM_ENABLE) == 0) { 1416 pci_tagprintf(tag, "pci_map_mem: attempt to map missing rom\n"); 1417 return -1; 1418 } 1419 pa = address & PCI_MAPREG_ROM_ADDR_MASK; 1420 } else { 1421 if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) { 1422 if (_pciverbose != 0) 1423 pci_tagprintf(tag, "pci_map_mem: bad request\n"); 1424 return -1; 1425 } 1426 1427 address = pci_conf_read(tag, reg); 1428 1429 if ((address & PCI_MAPREG_TYPE_IO) != 0) { 1430 if (_pciverbose != 0) 1431 pci_tagprintf(tag, "pci_map_mem: attempt to memory map an I/O region\n"); 1432 return -1; 1433 } 1434 1435 pa = address & PCI_MAPREG_MEM_ADDR_MASK; 1436 1437 switch (address & PCI_MAPREG_MEM_TYPE_MASK) { 1438 case PCI_MAPREG_MEM_TYPE_32BIT: 1439 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1440 break; 1441 case PCI_MAPREG_MEM_TYPE_64BIT: 1442 if (reg + 4 < PCI_MAPREG_END) 1443 pa |= ((phys_addr_t)pci_conf_read(tag, reg+4) << 32); 1444 else { 1445 if (_pciverbose != 0) 1446 pci_tagprintf(tag, "pci_map_mem: bad 64-bit reguest\n"); 1447 return -1; 1448 } 1449 break; 1450 default: 1451 if (_pciverbose != 0) 1452 pci_tagprintf(tag, "pci_map_mem: reserved mapping type\n"); 1453 return -1; 1454 } 1455 } 1456 1457 pa = (pa - Q.pci_mem_base) + Q.mem_space; 1458 if (endian == PCI_MATCH_BITS) 1459 pa |= Q.mem_bit_endian; 1460 *pap = pa; 1461 return 0; 1462} 1463 1464 1465#define ISAPORT_BASE(x) (Q.io_space + (x)) 1466 1467uint8_t 1468inb (unsigned int port) 1469{ 1470 return phys_read8(ISAPORT_BASE(port)); 1471} 1472 1473uint16_t 1474inw (unsigned int port) 1475{ 1476 return phys_read16(ISAPORT_BASE(port)); 1477} 1478 1479uint32_t 1480inl (unsigned int port) 1481{ 1482 return phys_read32(ISAPORT_BASE(port)); 1483} 1484 1485void 1486outb (unsigned int port, uint8_t val) 1487{ 1488 phys_write8(ISAPORT_BASE(port), val); 1489 mips_wbflush(); 1490} 1491 1492void 1493outw (unsigned int port, uint16_t val) 1494{ 1495 phys_write16(ISAPORT_BASE(port), val); 1496 mips_wbflush(); 1497} 1498 1499void 1500outl (unsigned int port, uint32_t val) 1501{ 1502 phys_write32(ISAPORT_BASE(port), val); 1503 mips_wbflush(); 1504} 1505 1506 1507/* Management of MAP table */ 1508 1509int 1510pci_map_window(phys_addr_t pa, 1511 unsigned int offset, unsigned int len, 1512 int l2ca, int endian) 1513{ 1514 unsigned int first, last; 1515 unsigned int i; 1516 uint32_t addr; 1517 uint32_t entry; 1518 1519 if (len == 0) 1520 return 0; 1521 1522 /* XXX Perhaps check for 1M multiples on offset and len? */ 1523 1524 first = offset / PHB_MAP_ENTRY_SPAN; 1525 last = (offset + (len-1)) / PHB_MAP_ENTRY_SPAN; 1526 1527 if (last >= PHB_MAP_N_ENTRIES) 1528 return -1; 1529 1530 addr = (pa / PHB_MAP_ENTRY_SPAN) << PHB_MAP_ADDR_SHIFT; 1531 for (i = first; i <= last; i++) { 1532 entry = (addr & PHB_MAP_ADDR_MASK) | PHB_MAP_ENABLE; 1533 if (l2ca) 1534 entry |= PHB_MAP_L2CA; 1535 if (endian) 1536 entry |= PHB_MAP_ENDIAN; 1537 pci_conf_write32(SB1250_PCI_BRIDGE, PHB_MAP_REG_BASE + 4*i, entry); 1538 addr += (1 << PHB_MAP_ADDR_SHIFT); 1539 } 1540 1541 return 0; 1542} 1543 1544int 1545pci_unmap_window(unsigned int offset, unsigned int len) 1546{ 1547 unsigned int first, last; 1548 unsigned int i; 1549 1550 if (len == 0) 1551 return 0; 1552 1553 /* XXX Perhaps check for 1M multiples on offset and len? */ 1554 1555 first = offset / PHB_MAP_ENTRY_SPAN; 1556 if (first >= PHB_MAP_N_ENTRIES) 1557 return 0; 1558 1559 last = (offset + (len-1)) / PHB_MAP_ENTRY_SPAN; 1560 if (last >= PHB_MAP_N_ENTRIES) 1561 last = PHB_MAP_N_ENTRIES - 1; 1562 1563 for (i = first; i <= last; i++) 1564 pci_conf_write32(SB1250_PCI_BRIDGE, PHB_MAP_REG_BASE + 4*i, 0); 1565 1566 return 0; 1567} 1568 1569 1570/* Map PCI interrupts A, B, C, D into a value for the IntLine 1571 register. For SB1250, return the source number used by the 1572 interrupt mapper, or 0xff if none. */ 1573uint8_t 1574pci_int_line(uint8_t pci_int) 1575{ 1576 return (pci_int == 0) ? 0xFF : (56 + (pci_int-1)); 1577} 1578 1579 1580/* Assign and map MSI messages and addresses. */ 1581 1582static unsigned int next_msi = 0; 1583 1584unsigned int 1585pci_msi_index(void) 1586{ 1587 unsigned int index = next_msi; 1588 1589 next_msi = (next_msi + 1) % 32; 1590 return index; 1591} 1592 1593void 1594pci_msi_encode(unsigned int index, uint64_t *msg_addr, uint16_t *msg_data) 1595{ 1596 *msg_addr = (Q.msi_set_base | Q.msi_bit_endian) + ((index / 16) << 2); 1597 *msg_data = 0x8000 >> (index % 16); 1598} 1599 1600phys_addr_t 1601pci_msi_clear_addr(uint64_t msg_addr) 1602{ 1603 return Q.msi_clear_base + (msg_addr & (1 << 2)); 1604} 1605