1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * L2 Cache Diagnostic File: diag_l2cache.S 5 * 6 * A diagnostic for the L2 cache. On pass2 parts, this diag 7 * will disable portions of the cache as necessary. 8 * 9 * Author: Zongbo Chen 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48#include "sb1250_defs.h" /* include definitions for MAKEMASK etc. */ 49#include "diag_l1cache.h" 50#include "sb1250_l2c.h" 51#include "sb1250_scd.h" 52#include "sb1250_regs.h" 53#include "sbmips.h" 54#include "diag_l2util.h" 55#include "bsp_config.h" 56#include "cpu_config.h" 57#include "sb1250_genbus.h" 58#include "mipsmacros.h" 59 60/*#define _SIMULATOR_*/ 61 62/* 63 * This lets us override the WID by poking values into our PromICE 64 */ 65#ifdef _MAGICWID_ 66#undef A_SCD_SYSTEM_REVISION 67#define A_SCD_SYSTEM_REVISION 0x1FC00508 68#endif 69 70/* We'll always define pass2. This routine will not be run unless 71 we're on a pass2 cpu */ 72 73#ifndef _SB1250_PASS2_ 74#define _SB1250_PASS2_ 75#endif 76 77#define C0_DEBUG $23 78#define C0_DataLo C0_TAGLO 79#define C0_DataHi C0_TAGHI 80#define C0_TagLo C0_TAGLO 81#define C0_TagHi C0_TAGHI 82 83#define DMTC0s(reg, c0reg, sel) \ 84 dmtc0 reg, c0reg, sel; \ 85 ssnop ; \ 86 ssnop 87 88#define DMFC0s(reg, c0reg, sel) \ 89 dmfc0 reg, c0reg, sel; \ 90 ssnop ; \ 91 ssnop 92 93#define MTC0s(reg, c0reg, sel) \ 94 mtc0 reg, c0reg, sel; \ 95 ssnop ; \ 96 ssnop 97 98#define MFC0s(reg, c0reg, sel) \ 99 mfc0 reg, c0reg, sel; \ 100 ssnop ; \ 101 ssnop 102 103#define DMFC0(reg, c0reg ) \ 104 dmfc0 reg, c0reg; \ 105 ssnop ; \ 106 ssnop 107 108#define DMTC0(reg, c0reg) \ 109 dmtc0 reg, c0reg; \ 110 ssnop ; \ 111 ssnop 112 113#undef MFC0 /* avoid redef'n of mipsmacros.h version */ 114#define MFC0(reg, c0reg ) \ 115 mfc0 reg, c0reg; \ 116 ssnop ; \ 117 ssnop 118 119#undef MTC0 /* avoid redef'n of mipsmacros.h version */ 120#define MTC0(reg, c0reg) \ 121 mtc0 reg, c0reg; \ 122 ssnop ; \ 123 ssnop 124 125#ifdef _SIMULATOR_ 126#define LINES_TO_TEST 2 127#define LOOP_COUNT 0x16 128#else 129#define TEST_ALL_LINES 130#define LOOP_COUNT 0x1600000 131#endif 132 133#define START_BLK 0 134#define TOTAL_BLKS 16 135 136#define XKPHYS_C_COH 0x8000000000000000 137#define XKPHYS_U_ACC 0xb800000000000000 138#define XKPHYS_C_COH_EXC 0xa000000000000000 139#define XKPHYS_UNC 0x9000000000000000 140 141#define L2_RAM_BASE_ADDR 0x00D0180000 142#define L2M_READ_RAW_ACCESS 0x00200000 143#define L2M_WRITE_LAST_ECC 0x00400000 144#define L2M_WRITE_TAG 0x00200000 145#define L2M_WRITE_TAG_LAST_ECC 0x00600000 146 147#undef PHYS_TO_XKPHYS /* avoid redef'n of sbmips.h version */ 148#define PHYS_TO_XKPHYS(x) (0x8000000000000000|(x)) 149#define PHYS_TO_XKPHYS_UNC(x) (0x9000000000000000|(x)) 150 151#define C0_Status $12 152#undef C0_SR /* avoid redef'n of sbmips.h version */ 153#define C0_SR C0_Status 154#define C0_Debug C0_DEBUG 155#define SR_KX (1 << 7) 156 157#ifdef LEDS_PHYS 158 159#define USE_LEDS 160 161/*Turn off LED display as default*/ 162#undef USE_LEDS 163 164#endif 165 166#if 1 167#define RUN_FROM_K0 168#endif 169 170#define LED_CHAR0 (32+8*3) 171#define LED_CHAR1 (32+8*2) 172#define LED_CHAR2 (32+8*1) 173#define LED_CHAR3 (32+8*0) 174 175#define MAC2_HASH0 0x10066240 176 177#define SET_LEDS(leds, temp0, temp1) \ 178 li temp0, PHYS_TO_K1(LEDS_PHYS); \ 179 srl temp1, leds, 24; \ 180 and temp1, temp1, 0xFF; \ 181 sb temp1, LED_CHAR0(temp0); \ 182 srl temp1, leds, 16; \ 183 and temp1, temp1, 0xFF; \ 184 sb temp1, LED_CHAR1(temp0); \ 185 srl temp1, leds, 8; \ 186 and temp1, temp1, 0xFF; \ 187 sb temp1, LED_CHAR2(temp0); \ 188 and temp1, leds, 0xFF; \ 189 sb temp1, LED_CHAR3(temp0) 190 191#if 0 192#define SET_LEDS(leds, temp0, temp1) \ 193 li temp0, PHYS_TO_XKPHYS_UNC(LEDS_PHYS); \ 194 srl temp1, leds, 24; \ 195 and temp1, temp1, 0xFF; \ 196 sb temp1, LED_CHAR0(temp0); \ 197 srl temp1, leds, 16; \ 198 and temp1, temp1, 0xFF; \ 199 sb temp1, LED_CHAR1(temp0); \ 200 srl temp1, leds, 8; \ 201 and temp1, temp1, 0xFF; \ 202 sb temp1, LED_CHAR2(temp0); \ 203 and temp1, leds, 0xFF; \ 204 sb temp1, LED_CHAR3(temp0) 205#endif 206 207#define SET_LEDS_HI(leds, temp0, temp1) \ 208 li temp0, PHYS_TO_XKPHYS_UNC(LEDS_PHYS); \ 209 srl temp1, leds, 8; \ 210 and temp1, temp1, 0xFF; \ 211 sb temp1, LED_CHAR0(temp0); \ 212 and temp1, leds, 0xFF; \ 213 sb temp1, LED_CHAR1(temp0) 214 215#define SET_LEDS_LO(leds, temp0, temp1) \ 216 li temp0, PHYS_TO_XKPHYS_UNC(LEDS_PHYS); \ 217 srl temp1, leds, 8; \ 218 and temp1, temp1, 0xFF; \ 219 sb temp1, LED_CHAR2(temp0); \ 220 and temp1, leds, 0xFF; \ 221 sb temp1, LED_CHAR3(temp0) 222 223#define DATA_TEST 224#define DATA_ECC_TEST 225 226 227#define LED_CHAR0 (32+8*3) 228#define LED_CHAR1 (32+8*2) 229#define LED_CHAR2 (32+8*1) 230#define LED_CHAR3 (32+8*0) 231 232 233 234 .text 235 .set mips64 236 237 238#define DISAB_TOP 0x800 239#define DISAB_BOT 0x400 240#define DISAB_RGT 0x200 241#define DISAB_LFT 0x100 242#define FAILURE 0xFFFFFFFF /* complete failure, cannot continue */ 243 244 245disab_table: 246 247/* 248 * This table maps failure modes to "disable" masks. 249 * For each combination of failed quadrants, disable half 250 * the cache that contains those quadrants. Note that since 251 * we can only disable top OR bottom and left OR right, not 252 * all combinations will work and will yield diagnostic failure. 253 */ 254 255 .word 0 /* Entire cache functional */ 256 .word DISAB_LFT /* BR=Good TR=Good BL=Good TL=BAD */ 257 .word DISAB_LFT /* BR=Good TR=Good BL=BAD TL=Good */ 258 .word DISAB_LFT /* BR=Good TR=Good BL=BAD TL=BAD */ 259 .word DISAB_RGT /* BR=Good TR=BAD BL=Good TL=Good */ 260 .word DISAB_TOP|DISAB_RGT /* BR=Good TR=BAD BL=Good TL=BAD */ 261 .word DISAB_RGT|DISAB_BOT /* BR=Good TR=BAD BL=BAD TL=Good */ 262 .word DISAB_LFT|DISAB_TOP /* BR=Good TR=BAD BL=BAD TL=BAD */ 263 .word DISAB_RGT /* BR=BAD TR=Good BL=Good TL=Good */ 264 .word DISAB_LFT|DISAB_BOT /* BR=BAD TR=Good BL=Good TL=BAD */ 265 .word DISAB_BOT|DISAB_RGT /* BR=BAD TR=Good BL=BAD TL=Good */ 266 .word DISAB_LFT|DISAB_BOT /* BR=BAD TR=Good BL=BAD TL=BAD */ 267 .word DISAB_RGT /* BR=BAD TR=BAD BL=Good TL=Good */ 268 .word DISAB_RGT|DISAB_TOP /* BR=BAD TR=BAD BL=Good TL=BAD */ 269 .word DISAB_RGT|DISAB_BOT /* BR=BAD TR=BAD BL=BAD TL=Good */ 270 .word FAILURE /* BR=BAD TR=BAD BL=BAD TL=BAD */ 271 272 273 274 275LEAF(diag_main) 276 277#define SKIP_DIAGS 1 278#if SKIP_DIAGS 279 li t0, PHYS_TO_K1(MAC2_HASH0) 280 move t1, zero 281 sd t1, 0(t0) 282 j ra /* Disable diagnostics for now */ 283 nop 284#endif 285 286 move fp, ra 287 288 /* 289 * Don't do any of this diagnostic unless we're greater than PASS2 SB1250. 290 */ 291 292 la t0,PHYS_TO_K1(A_SCD_SYSTEM_REVISION) 293 ld t0,0(t0) /* get system revision */ 294 295 and t1,t0,(0xF0FF << S_SYS_PART) /* ignore CPU count */ 296 li t2,V_SYS_PART(0x1050) /* test against ignored count */ 297 bne t2,t1,2f /* go if not a sb1x50 */ 298 nop 299 300 and t1,t0,M_SYS_REVISION 301 li t2,V_SYS_REVISION(K_SYS_REVISION_PASS3) 302 bge t1,t2,3f /* run diags if >= pass3 (0x20) */ 303 nop 304 li t2,V_SYS_REVISION(K_SYS_REVISION_PASS2) 305 bge t1,t2,1f /* go if pass2 or better (>= 0x03) */ 306 nop 3072: j ra 308 nop 309 3101: dsrl t1,t0,S_SYS_WID /* Get Wafer ID register */ 311 bne t1,zero,2b /* leave if register is set (no diags) */ 312 /* Otherwise, run the diagnostic if the wafer ID is not set. */ 313 /* Special case of A6 parts (revid==4 && wid!=0) will NOT run diags */ 314 3153: 316 317#ifdef USE_LEDS 318 dli t8, (('J'<<24)|('U'<<16)|('M'<<8)|'P') 319 SET_LEDS(t8, t6, t7) 320#endif 321 322#ifdef RUN_FROM_K0 323 MFC0 (t2,C0_CONFIG) 324 dsrl t2, t2, 3 325 dsll t2, t2, 3 326 or t2, t2, 1 327 MTC0 (t2,C0_CONFIG) 328 bal to_kseg0 329 nop 330#endif 331 332#ifdef USE_LEDS 333 dli t8, (('C'<<24)|('A'<<16)|('S'<<8)|'H') 334 SET_LEDS(t8, t6, t7) 335#endif 336 337#ifdef RUN_FROM_K0 338 li t0, LOOP_COUNT 3391: addi t0, t0, -1 340 bne t0, zero, 1b 341#endif 342 343/* set up for 64 bit addressing */ 344 DMFC0 (t2,C0_SR) 345 or t1,t2,SR_KX 346 DMTC0 (t1,C0_SR) 347 348 MFC0s (t2,C0_Debug,2) 349 or t1, t2, 0x3004 350 MTC0s (t1,C0_Debug,2) 351 352 /* initialize the cache */ 353 bal sb1250_l2cache_init1 354 355 /* use mac2 hash0 reg as result reg, init it to 0 */ 356 dli t0, PHYS_TO_XKPHYS_UNC(MAC2_HASH0) 357 move t1, zero 358 sd t1, 0(t0) 359 360 /* init quarter number to 0 */ 361 move k0, $0 362 363next_quarter: 364 move v0, $0 365#ifdef DATA_TEST 366 bal l2dtest_bg_rw_uac 367 nop 368 or t0, v0, v1 369 or t0, t0, s4 370 or t0, t0, s5 371 bne t0, $0, test_fail 372data_fail: 373 /*bne v0, $0, data_fail*/ 374 nop 375 376#ifdef RUN_FROM_K0 377 li t0, LOOP_COUNT 3781: addi t0, t0, -1 379 bne t0, zero, 1b 380#endif 381 382#ifdef DATA_ECC_TEST 383 bal l2dtest_data_ecc 384 nop 385 or t0, v0, v1 386 or t0, t0, s4 387 or t0, t0, s5 388 bne t0, $0, test_fail 389ecc_fail: 390 /*bne v0, $0, ecc_fail*/ 391 nop 392#endif 393 394/* 395#else 396*/ 397 398#ifdef RUN_FROM_K0 399 li t0, LOOP_COUNT 4001: addi t0, t0, -1 401 bne t0, zero, 1b 402#endif 403 404 bal l2dtest_tag_data 405 nop 406 or t0, v0, v1 407 or t0, t0, s4 408 or t0, t0, s5 409 bne t0, $0, test_fail 410tag_fail: 411 /*bne v0, $0, tag_fail*/ 412 nop 413 414#ifdef RUN_FROM_K0 415 li t0, LOOP_COUNT 4161: addi t0, t0, -1 417 bne t0, zero, 1b 418#endif 419 420 bal l2dtest_tag_ecc 421 nop 422 or t0, v0, v1 423 or t0, t0, s4 424 or t0, t0, s5 425 bne t0, $0, test_fail 426tagecc_fail: 427 /*bne v0, $0, tagecc_fail*/ 428 nop 429 j test_success 430 nop 431#endif 432 433#ifdef RUN_FROM_K0 434 li t0, LOOP_COUNT 4351: addi t0, t0, -1 436 bne t0, zero, 1b 437 nop 438#endif 439 440test_fail: 441 addi t0, zero, 1 442 sll t0, t0, k0 443 dli t1, PHYS_TO_XKPHYS_UNC(MAC2_HASH0) 444 ld t2, 0(t1) 445 or t0, t0, t2 446 sd t0, 0(t1) 447 448test_success: 449 addi k0, k0, 1 450 slt t0, k0, 4 451 bne t0, zero, next_quarter 452 453 DMFC0 (t2,C0_SR) 454 li t0, SR_KX 455 not t0, t0 456 and t1,t2,t0 457 DMTC0 (t1,C0_SR) 458 459 460/* 461 * Disable the bad quadrant(s) of the cache 462 */ 463 464 li t1,PHYS_TO_K1(MAC2_HASH0) 465 ld t1,0(t1) 466 la t2,disab_table 467 sll t1,2 /* make a word offset */ 468 add t2,t2,t1 /* into the table */ 469 lw t0,(t2) /* this is the disable mask */ 470 blt t0,zero,diag_fail /* go if total failure */ 471 nop 472 473 li t1,PHYS_TO_K1(A_L2_CACHE_DISABLE) 474 or t1,t1,t0 /* OR in appropriate disable bits */ 475 476#ifdef _SB1250_PASS2_ 477 sd t0,0(t1) /* disable the cache */ 478#else 479 bne t0,zero,diag_fail /* on pass1, any failure is bad */ 480 nop 481#endif 482 483 MFC0s (t2,C0_Debug,2) /* turn off things we defeatured */ 484 485#ifdef _DEFEATURE_ECC_ 486 and t1, t2, ~0x0004 487#else 488 and t1, t2, ~0x3004 489#endif 490 MTC0s (t1,C0_Debug,2) 491 492#ifdef USE_LEDS 493 494 dli t8, (('D'<<24)|('O'<<16)|('N'<<8)|'E') 495 SET_LEDS(t8, t6, t7) 496#endif 497 498 move ra, fp 499 j ra 500 nop 501 502diag_fail: 503 504 li t1,PHYS_TO_K1(MAC2_HASH0) 505 ld t1,0(t1) 506 add t1,t1,'0' 507 ble t1,'9',1f 508 nop 509 add t1,t1,('A'-('9'+1)) 5101: 511 dli t8, (('L'<<24)|('2'<<16)|(' '<<8)|0) 512 or t8,t8,t1 513#ifdef USE_LEDS 514 SET_LEDS(t8, t6, t7) 515#endif 516 5171: b 1b 518 519 520END(diag_main) 521 522#ifdef TEST_ALL_LINES 523#define L2_LINES_PER_BLOCK 256 524#else 525#define L2_LINES_PER_BLOCK LINES_TO_TEST 526#endif 527 528#define R_WRBC_RBLK s1 529#define R_WRBC_LINE s2 530#define R_WRBC_NEXT_WAY s3 531#define R_WRBC_RADDR t5 532#define R_WRBC_SCRATCH0 t6 533#define R_WRBC_SCRATCH1 t7 534#define R_WRBC_SCRATCH2 s6 535#define R_WRBC_SCRATCH3 s7 536 537#define R_PASS_FAIL t4 538 539/******************************************************** 540 * l2test_wr_uac_allblocks * 541 * Write all blocks of the L2 using uncached * 542 * accelerated writes in mgmt mode. * 543 * This also marks all blocks as valid and dirty. * 544 * * 545 ********************************************************/ 546 547#define R_BG_PAT0_0 a0 548#define R_BG_PAT0_1 a1 549#define R_BG_PAT0_2 a2 550#define R_BG_PAT0_3 a3 551 552#define R_BG_PAT1_0 t0 553#define R_BG_PAT1_1 t1 554/* 555#define R_BG_PAT1_2 t2 556#define R_BG_PAT1_3 t3 557*/ 558#define R_INV_0 t2 559#define R_INV_1 t3 560 561#define R_PATTERN_IND s0 562#define R_BG_LINE s2 563#define R_BG_NEXT_WAY s3 564#define R_BG_BLOCK s1 565#define R_BG_WADDR t5 566#define R_BG_RADDR t5 567 568#define R_BG_SCRATCH0 t6 569#define R_BG_SCRATCH1 t7 570#define R_BG_SCRATCH2 t8 571#define R_BG_SCRATCH3 t9 572#define R_BG_SCRATCH4 s6 573#define R_BG_SCRATCH5 s7 574 575#define R_ERR_TABLE_0 v0 576#define R_ERR_TABLE_1 v1 577#define R_ERR_TABLE_2 s4 578#define R_ERR_TABLE_3 s5 579 580#define DATA_PATTERN0_0 0 581#define DATA_PATTERN0_1 0 582#define DATA_PATTERN0_2 0 583#define DATA_PATTERN0_3 0 584#define PATTERN0_INV0 0 585#define PATTERN0_INV1 0 586 587#define DATA_PATTERN1_0 0xffffffffffffffff 588#define DATA_PATTERN1_1 0xffffffffffffffff 589#define DATA_PATTERN1_2 0xffffffffffffffff 590#define DATA_PATTERN1_3 0xffffffffffffffff 591#define PATTERN1_INV0 0xffffffffffffffff 592#define PATTERN1_INV1 0xffffffffffffffff 593 594#define DATA_PATTERN2_0 0xffffffffffffffff 595#define DATA_PATTERN2_1 0xffffffffffffffff 596#define DATA_PATTERN2_2 0xffffffffffffffff 597#define DATA_PATTERN2_3 0xffffffffffffffff 598#define PATTERN2_INV0 0 599#define PATTERN2_INV1 0xffffffffffffffff 600 601#define DATA_PATTERN3_0 0x5555555555555555 602#define DATA_PATTERN3_1 0x5555555555555555 603#define DATA_PATTERN3_2 0x5555555555555555 604#define DATA_PATTERN3_3 0x5555555555555555 605#define PATTERN3_INV0 0 606#define PATTERN3_INV1 0 607 608#define DATA_PATTERN4_0 0x3333333333333333 609#define DATA_PATTERN4_1 0x3333333333333333 610#define DATA_PATTERN4_2 0x3333333333333333 611#define DATA_PATTERN4_3 0x3333333333333333 612#define PATTERN4_INV0 0 613#define PATTERN4_INV1 0 614 615#define DATA_PATTERN5_0 0x0f0f0f0f0f0f0f0f 616#define DATA_PATTERN5_1 0x0f0f0f0f0f0f0f0f 617#define DATA_PATTERN5_2 0x0f0f0f0f0f0f0f0f 618#define DATA_PATTERN5_3 0x0f0f0f0f0f0f0f0f 619#define PATTERN5_INV0 0 620#define PATTERN5_INV1 0 621 622#define DATA_PATTERN6_0 0x00ff00ff00ff00ff 623#define DATA_PATTERN6_1 0x00ff00ff00ff00ff 624#define DATA_PATTERN6_2 0x00ff00ff00ff00ff 625#define DATA_PATTERN6_3 0x00ff00ff00ff00ff 626#define PATTERN6_INV0 0 627#define PATTERN6_INV1 0 628 629#define DATA_PATTERN7_0 0x0000ffff0000ffff 630#define DATA_PATTERN7_1 0x0000ffff0000ffff 631#define DATA_PATTERN7_2 0x0000ffff0000ffff 632#define DATA_PATTERN7_3 0x0000ffff0000ffff 633#define PATTERN7_INV0 0 634#define PATTERN7_INV1 0 635 636#define DATA_PATTERN8_0 0x00000000ffffffff 637#define DATA_PATTERN8_1 0x00000000ffffffff 638#define DATA_PATTERN8_2 0x00000000ffffffff 639#define DATA_PATTERN8_3 0x00000000ffffffff 640#define PATTERN8_INV0 0 641#define PATTERN8_INV1 0 642 643#define DATA_PATTERN9_0 0xffffffffffffffff 644#define DATA_PATTERN9_1 0x0000000000000000 645#define DATA_PATTERN9_2 0xffffffffffffffff 646#define DATA_PATTERN9_3 0x0000000000000000 647#define PATTERN9_INV0 0 648#define PATTERN9_INV1 0 649 650#define DATA_PATTERNa_0 0xffffffffffffffff 651#define DATA_PATTERNa_1 0xffffffffffffffff 652#define DATA_PATTERNa_2 0x0000000000000000 653#define DATA_PATTERNa_3 0x0000000000000000 654#define PATTERNa_INV0 0 655#define PATTERNa_INV1 0 656 657#undef MAX_PATTERN /* avoid redef'n of diag_l1cache.h version */ 658#define MAX_PATTERN 11 659 660#define BG_WRITE_PAT(addr,pattern0,pattern1,pattern2,pattern3,inv0,inv1) \ 661 li R_BG_SCRATCH0, 2; \ 6621: sd pattern0, 0(addr); \ 663 sd pattern1, 8(addr); \ 664 sd pattern2, 16(addr); \ 665 sd pattern3, 24(addr); \ 666 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(addr); \ 667 xor pattern0, pattern0, inv0; \ 668 xor pattern1, pattern1, inv0; \ 669 xor pattern2, pattern2, inv0; \ 670 xor pattern3, pattern3, inv0; \ 671 daddu addr, addr, R_BG_NEXT_WAY; \ 672 sd pattern0, 0(addr); \ 673 sd pattern1, 8(addr); \ 674 sd pattern2, 16(addr); \ 675 sd pattern3, 24(addr); \ 676 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(addr); \ 677 xor pattern0, pattern0, inv1; \ 678 xor pattern1, pattern1, inv1; \ 679 xor pattern2, pattern2, inv1; \ 680 xor pattern3, pattern3, inv1; \ 681 addi R_BG_SCRATCH0, R_BG_SCRATCH0, -1; \ 682 bne R_BG_SCRATCH0, zero, 1b; \ 683 daddu addr, addr, R_BG_NEXT_WAY; \ 684 li R_BG_SCRATCH0, -4*2*65536; \ 685 dadd addr, addr, R_BG_SCRATCH0 /* next line */ 686 687#define BG_INVAL_L1(addr) \ 688 move R_BG_SCRATCH0, addr; \ 689 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0); \ 690 daddu R_BG_SCRATCH0, R_BG_SCRATCH0, R_BG_NEXT_WAY; \ 691 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0); \ 692 daddu R_BG_SCRATCH0, R_BG_SCRATCH0, R_BG_NEXT_WAY; \ 693 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0); \ 694 daddu R_BG_SCRATCH0, R_BG_SCRATCH0, R_BG_NEXT_WAY; \ 695 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0) 696 697#define BG_CHECK_PAT(addr,pattern0,pattern1,pattern2,pattern3,inv0,inv1) \ 698 li R_BG_SCRATCH4, 2; \ 699 dli R_BG_SCRATCH5, L2M_READ_RAW_ACCESS; \ 700 or addr, addr, R_BG_SCRATCH5; \ 7011: ld R_BG_SCRATCH0, 0(addr); \ 702 ld R_BG_SCRATCH1, 8(addr); \ 703 sne R_BG_SCRATCH0, R_BG_SCRATCH0, pattern0; \ 704 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH0; \ 705 ld R_BG_SCRATCH2, 16(addr);\ 706 sne R_BG_SCRATCH1, R_BG_SCRATCH1, pattern1; \ 707 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH1; \ 708 ld R_BG_SCRATCH3, 24(addr);\ 709 sne R_BG_SCRATCH2, R_BG_SCRATCH2, pattern2; \ 710 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH2; \ 711 sne R_BG_SCRATCH3, R_BG_SCRATCH3, pattern3; \ 712 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH3; \ 713 xor pattern0, pattern0, inv0; \ 714 xor pattern1, pattern1, inv0; \ 715 xor pattern2, pattern2, inv0; \ 716 xor pattern3, pattern3, inv0; \ 717 daddu addr, addr, R_BG_NEXT_WAY; \ 718 ld R_BG_SCRATCH0, 0(addr); \ 719 ld R_BG_SCRATCH1, 8(addr); \ 720 sne R_BG_SCRATCH0, R_BG_SCRATCH0, pattern0; \ 721 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH0; \ 722 ld R_BG_SCRATCH2, 16(addr);\ 723 sne R_BG_SCRATCH1, R_BG_SCRATCH1, pattern1; \ 724 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH1; \ 725 ld R_BG_SCRATCH3, 24(addr);\ 726 sne R_BG_SCRATCH2, R_BG_SCRATCH2, pattern2; \ 727 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH2; \ 728 sne R_BG_SCRATCH3, R_BG_SCRATCH3, pattern3; \ 729 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH3; \ 730 xor pattern0, pattern0, inv1; \ 731 xor pattern1, pattern1, inv1; \ 732 xor pattern2, pattern2, inv1; \ 733 xor pattern3, pattern3, inv1; \ 734 addi R_BG_SCRATCH4, R_BG_SCRATCH4, -1; \ 735 bne R_BG_SCRATCH4, zero, 1b; \ 736 daddu addr, addr, R_BG_NEXT_WAY; \ 737 li R_BG_SCRATCH0, -4*2*65536; \ 738 dadd addr, addr, R_BG_SCRATCH0; \ 739 nor R_BG_SCRATCH5, R_BG_SCRATCH5, $0; \ 740 and addr, addr, R_BG_SCRATCH5 741 742#define BG_CHECK_PAT1(addr,pattern0,pattern1,pattern2,pattern3,inv0,inv1) \ 743 li R_BG_SCRATCH4, 2; \ 744 dli R_BG_SCRATCH5, 0x00200000; \ 745 or addr, addr, R_BG_SCRATCH5; \ 7461: ld R_BG_SCRATCH0, 0(addr); \ 747 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(addr); \ 748 ld R_BG_SCRATCH0, 0(addr); \ 749 ld R_BG_SCRATCH1, 8(addr); \ 750 sne R_BG_SCRATCH0, R_BG_SCRATCH0, pattern0; \ 751 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH0; \ 752 ld R_BG_SCRATCH2, 16(addr);\ 753 sne R_BG_SCRATCH1, R_BG_SCRATCH1, pattern1; \ 754 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH1; \ 755 ld R_BG_SCRATCH3, 24(addr);\ 756 sne R_BG_SCRATCH2, R_BG_SCRATCH2, pattern2; \ 757 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH2; \ 758 sne R_BG_SCRATCH3, R_BG_SCRATCH3, pattern3; \ 759 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH3; \ 760 xor pattern0, pattern0, inv0; \ 761 xor pattern1, pattern1, inv0; \ 762 xor pattern2, pattern2, inv0; \ 763 xor pattern3, pattern3, inv0; \ 764 daddu addr, addr, R_BG_NEXT_WAY; \ 765 ld R_BG_SCRATCH0, 0(addr); \ 766 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(addr); \ 767 ld R_BG_SCRATCH0, 0(addr); \ 768 ld R_BG_SCRATCH1, 8(addr); \ 769 sne R_BG_SCRATCH0, R_BG_SCRATCH0, pattern0; \ 770 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH0; \ 771 ld R_BG_SCRATCH2, 16(addr);\ 772 sne R_BG_SCRATCH1, R_BG_SCRATCH1, pattern1; \ 773 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH1; \ 774 ld R_BG_SCRATCH3, 24(addr);\ 775 sne R_BG_SCRATCH2, R_BG_SCRATCH2, pattern2; \ 776 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH2; \ 777 sne R_BG_SCRATCH3, R_BG_SCRATCH3, pattern3; \ 778 or R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH3; \ 779 xor pattern0, pattern0, inv1; \ 780 xor pattern1, pattern1, inv1; \ 781 xor pattern2, pattern2, inv1; \ 782 xor pattern3, pattern3, inv1; \ 783 addi R_BG_SCRATCH4, R_BG_SCRATCH4, -1; \ 784 bne R_BG_SCRATCH4, zero, 1b; \ 785 daddu addr, addr, R_BG_NEXT_WAY; \ 786 li R_BG_SCRATCH0, -4*2*65536; \ 787 dadd addr, addr, R_BG_SCRATCH0; \ 788 nor R_BG_SCRATCH5, R_BG_SCRATCH5, $0; \ 789 and addr, addr, R_BG_SCRATCH5 790 791#define INV_PAT(pattern0, pattern1, pattern2, pattern3) \ 792 not pattern0, pattern0; \ 793 not pattern1, pattern1; \ 794 not pattern2, pattern2; \ 795 not pattern3, pattern3 796 797#define SET_ERR_TABLE(pass_fail, line) \ 798 li R_BG_SCRATCH0, 0x3f; \ 799 and R_BG_SCRATCH0, R_BG_SCRATCH0, line; \ 800 dsll R_BG_SCRATCH0, pass_fail, R_BG_SCRATCH0; \ 801 dsrl R_BG_SCRATCH1, line, 6; \ 802 bne R_BG_SCRATCH1, zero, 1f; \ 803 li R_BG_SCRATCH2, 1; \ 804 or R_ERR_TABLE_0, R_ERR_TABLE_0, R_BG_SCRATCH0; \ 805 b 4f; \ 806 nop; \ 8071: bne R_BG_SCRATCH1, R_BG_SCRATCH2, 2f; \ 808 li R_BG_SCRATCH2, 2; \ 809 or R_ERR_TABLE_1, R_ERR_TABLE_1, R_BG_SCRATCH0; \ 810 b 4f; \ 811 nop; \ 8122: bne R_BG_SCRATCH1, R_BG_SCRATCH2, 3f; \ 813 li R_BG_SCRATCH2, 3; \ 814 or R_ERR_TABLE_2, R_ERR_TABLE_2, R_BG_SCRATCH0; \ 815 b 4f; \ 816 nop; \ 8173: or R_ERR_TABLE_3, R_ERR_TABLE_3, R_BG_SCRATCH0; \ 8184: 819 820#ifdef DATA_TEST 821l2dtest_bg_rw_uac: 822 /*li R_BG_BLOCK, START_BLK */ 823 sll R_BG_BLOCK, k0, 2 824 li R_BG_NEXT_WAY,0x20000 825 move R_ERR_TABLE_0, $0 826 move R_ERR_TABLE_1, $0 827 move R_ERR_TABLE_2, $0 828 move R_ERR_TABLE_3, $0 829 830 831bg_next_block: 832 /* form address */ 833#ifdef USE_LEDS 834 addi R_BG_SCRATCH2, R_BG_BLOCK, '0' 835 or R_BG_SCRATCH2, R_BG_SCRATCH2, ('D' << 8) 836 SET_LEDS_HI(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1) 837#endif 838 839 move R_PATTERN_IND, $0 840 841bg_next_patt: 842#ifdef USE_LEDS 843 addi R_BG_SCRATCH2, R_PATTERN_IND, '0' 844 or R_BG_SCRATCH2, R_BG_SCRATCH2, ('P' << 8) 845 SET_LEDS_LO(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1) 846#endif 847 848 bne R_PATTERN_IND, $0, pattern_ne_0 849 dli R_BG_PAT0_0, DATA_PATTERN0_0 # data_pattern = pattern[0] 850 dli R_BG_PAT0_1, DATA_PATTERN0_1 851 dli R_BG_PAT0_2, DATA_PATTERN0_2 852 dli R_BG_PAT0_3, DATA_PATTERN0_3 853 dli R_INV_0, PATTERN0_INV0 854 dli R_INV_1, PATTERN0_INV1 855 j test_0 856 nop 857pattern_ne_0: 858 li R_BG_SCRATCH0, 1 859 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_1 860 dli R_BG_PAT0_0, DATA_PATTERN1_0 # data_pattern = pattern[0] 861 dli R_BG_PAT0_1, DATA_PATTERN1_1 862 dli R_BG_PAT0_2, DATA_PATTERN1_2 863 dli R_BG_PAT0_3, DATA_PATTERN1_3 864 dli R_INV_0, PATTERN1_INV0 865 dli R_INV_1, PATTERN1_INV1 866 j test_0 867 nop 868pattern_ne_1: 869 li R_BG_SCRATCH0, 2 870 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_2 871 dli R_BG_PAT0_0, DATA_PATTERN2_0 # data_pattern = pattern[0] 872 dli R_BG_PAT0_1, DATA_PATTERN2_1 873 dli R_BG_PAT0_2, DATA_PATTERN2_2 874 dli R_BG_PAT0_3, DATA_PATTERN2_3 875 dli R_INV_0, PATTERN2_INV0 876 dli R_INV_1, PATTERN2_INV1 877 j test_0 878 nop 879pattern_ne_2: 880 li R_BG_SCRATCH0, 3 881 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_3 882 dli R_BG_PAT0_0, DATA_PATTERN3_0 # data_pattern = pattern[0] 883 dli R_BG_PAT0_1, DATA_PATTERN3_1 884 dli R_BG_PAT0_2, DATA_PATTERN3_2 885 dli R_BG_PAT0_3, DATA_PATTERN3_3 886 dli R_INV_0, PATTERN3_INV0 887 dli R_INV_1, PATTERN3_INV1 888 j test_0 889 nop 890pattern_ne_3: 891 li R_BG_SCRATCH0, 4 892 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_4 893 dli R_BG_PAT0_0, DATA_PATTERN4_0 # data_pattern = pattern[0] 894 dli R_BG_PAT0_1, DATA_PATTERN4_1 895 dli R_BG_PAT0_2, DATA_PATTERN4_2 896 dli R_BG_PAT0_3, DATA_PATTERN4_3 897 dli R_INV_0, PATTERN4_INV0 898 dli R_INV_1, PATTERN4_INV1 899 j test_0 900 nop 901pattern_ne_4: 902 li R_BG_SCRATCH0, 5 903 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_5 904 dli R_BG_PAT0_0, DATA_PATTERN5_0 # data_pattern = pattern[0] 905 dli R_BG_PAT0_1, DATA_PATTERN5_1 906 dli R_BG_PAT0_2, DATA_PATTERN5_2 907 dli R_BG_PAT0_3, DATA_PATTERN5_3 908 dli R_INV_0, PATTERN5_INV0 909 dli R_INV_1, PATTERN5_INV1 910 j test_0 911 nop 912pattern_ne_5: 913 li R_BG_SCRATCH0, 6 914 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_6 915 dli R_BG_PAT0_0, DATA_PATTERN6_0 # data_pattern = pattern[0] 916 dli R_BG_PAT0_1, DATA_PATTERN6_1 917 dli R_BG_PAT0_2, DATA_PATTERN6_2 918 dli R_BG_PAT0_3, DATA_PATTERN6_3 919 dli R_INV_0, PATTERN6_INV0 920 dli R_INV_1, PATTERN6_INV1 921 j test_0 922 nop 923pattern_ne_6: 924 li R_BG_SCRATCH0, 7 925 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_7 926 dli R_BG_PAT0_0, DATA_PATTERN7_0 # data_pattern = pattern[0] 927 dli R_BG_PAT0_1, DATA_PATTERN7_1 928 dli R_BG_PAT0_2, DATA_PATTERN7_2 929 dli R_BG_PAT0_3, DATA_PATTERN7_3 930 dli R_INV_0, PATTERN7_INV0 931 dli R_INV_1, PATTERN7_INV1 932 j test_0 933 nop 934pattern_ne_7: 935 li R_BG_SCRATCH0, 8 936 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_8 937 dli R_BG_PAT0_0, DATA_PATTERN8_0 # data_pattern = pattern[0] 938 dli R_BG_PAT0_1, DATA_PATTERN8_1 939 dli R_BG_PAT0_2, DATA_PATTERN8_2 940 dli R_BG_PAT0_3, DATA_PATTERN8_3 941 dli R_INV_0, PATTERN8_INV0 942 dli R_INV_1, PATTERN8_INV1 943 j test_0 944 nop 945pattern_ne_8: 946 li R_BG_SCRATCH0, 9 947 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_9 948 dli R_BG_PAT0_0, DATA_PATTERN9_0 # data_pattern = pattern[0] 949 dli R_BG_PAT0_1, DATA_PATTERN9_1 950 dli R_BG_PAT0_2, DATA_PATTERN9_2 951 dli R_BG_PAT0_3, DATA_PATTERN9_3 952 dli R_INV_0, PATTERN9_INV0 953 dli R_INV_1, PATTERN9_INV1 954 j test_0 955 nop 956pattern_ne_9: 957 dli R_BG_PAT0_0, DATA_PATTERNa_0 # data_pattern = pattern[0] 958 dli R_BG_PAT0_1, DATA_PATTERNa_1 959 dli R_BG_PAT0_2, DATA_PATTERNa_2 960 dli R_BG_PAT0_3, DATA_PATTERNa_3 961 dli R_INV_0, PATTERNa_INV0 962 dli R_INV_1, PATTERNa_INV1 963 j test_0 964 nop 965 966test_0: 967 dli R_BG_WADDR, XKPHYS_C_COH_EXC /* uncached accelerated */ 968 dli R_BG_SCRATCH0, L2_RAM_BASE_ADDR /* mgmt mode */ 969 or R_BG_WADDR,R_BG_WADDR,R_BG_SCRATCH0 970 sll R_BG_SCRATCH0, R_BG_BLOCK, L2_BLOCK_SHIFT /* block number */ 971 or R_BG_WADDR, R_BG_WADDR, R_BG_SCRATCH0 972 973 .set noreorder 974 move R_BG_LINE, zero 975bg_init_next_line: 976 /*BG_WRITE_PAT0(R_BG_WADDR) */ 977 BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 978/* for (line = 0; line < max_lines_per_block; line++) */ 979 .set noreorder 980 li R_BG_SCRATCH0, (32) 981 dadd R_BG_WADDR, R_BG_WADDR, R_BG_SCRATCH0 /* next line */ 982 slt R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1 983 bne R_BG_SCRATCH0,$0, bg_init_next_line 984 add R_BG_LINE,R_BG_LINE,1 985 986 987/* march element 1 */ 988 dli R_WRBC_RADDR, XKPHYS_C_COH_EXC 989 dli R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR 990 or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0 991 /* form address for block to be read/written */ 992 sll R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT 993 or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1 994 li R_WRBC_NEXT_WAY, 0x20000 995 996 /* way = 0; */ 997 /* for (line = 0; line < lines_per_block; line++) {*/ 998 move R_BG_LINE, zero 999march1_w0: 1000 move R_PASS_FAIL, zero 1001 BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1002 INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) 1003 BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1004 BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1005 BG_INVAL_L1(R_BG_WADDR) 1006 INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) 1007 SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE) 1008 daddiu R_WRBC_RADDR, R_WRBC_RADDR, 0x20 1009 1010 slt R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1 1011 bne R_BG_SCRATCH0,$0,march1_w0 1012 add R_BG_LINE,R_BG_LINE,1 1013 1014/* march element 2 */ 1015 dli R_WRBC_RADDR, XKPHYS_C_COH_EXC 1016 dli R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR 1017 or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0 1018 /* form address for block to be read/written */ 1019 sll R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT 1020 or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1 1021 li R_WRBC_NEXT_WAY, 0x20000 1022 /* way = 0; */ 1023 /* for (line = 0; line < lines_per_block; line++) {*/ 1024 move R_BG_LINE,zero 1025march2_w0: 1026 move R_PASS_FAIL, zero 1027 INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) 1028 BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1029 INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) 1030 BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1031 BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1032 BG_INVAL_L1(R_BG_WADDR) 1033 SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE) 1034 daddiu R_WRBC_RADDR, R_WRBC_RADDR, 0x20 1035 1036 slt R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1 1037 bne R_BG_SCRATCH0,$0,march2_w0 1038 add R_BG_LINE,R_BG_LINE,1 1039 1040/* march element 3 */ 1041 dli R_WRBC_RADDR, XKPHYS_C_COH_EXC 1042 dli R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR 1043 or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0 1044 /* form address for block to be read/written */ 1045 addi R_WRBC_SCRATCH0, R_WRBC_RBLK, 1 1046#ifdef TEST_ALL_LINES 1047 sll R_WRBC_SCRATCH1, R_WRBC_SCRATCH0, L2_BLOCK_SHIFT 1048#else 1049 sll R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT 1050#endif 1051 or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1 1052#ifdef TEST_ALL_LINES 1053 daddiu R_WRBC_RADDR, R_WRBC_RADDR, -32 1054#else 1055 daddiu R_WRBC_RADDR, R_WRBC_RADDR, L2_LINES_PER_BLOCK*32-32 1056#endif 1057 li R_WRBC_NEXT_WAY, 0x20000 1058 /* way = 0; */ 1059 /* for (line = 0; line < lines_per_block; line++) {*/ 1060 li R_WRBC_LINE,L2_LINES_PER_BLOCK-1 1061march3_w0: 1062 move R_PASS_FAIL, zero 1063 BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1064 INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) 1065 BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1066 BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1067 BG_INVAL_L1(R_BG_WADDR) 1068 INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) 1069 SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE) 1070 daddiu R_WRBC_RADDR, R_WRBC_RADDR, -32 1071 1072 bne R_WRBC_LINE,$0, march3_w0 1073 add R_WRBC_LINE,R_WRBC_LINE,-1 1074 1075/* march element 4 */ 1076 dli R_WRBC_RADDR, XKPHYS_C_COH_EXC 1077 dli R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR 1078 or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0 1079 /* form address for block to be read/written */ 1080 addi R_WRBC_SCRATCH0, R_WRBC_RBLK, 1 1081#ifdef TEST_ALL_LINES 1082 sll R_WRBC_SCRATCH1, R_WRBC_SCRATCH0, L2_BLOCK_SHIFT 1083#else 1084 sll R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT 1085#endif 1086 or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1 1087#ifdef TEST_ALL_LINES 1088 daddiu R_WRBC_RADDR, R_WRBC_RADDR, -32 1089#else 1090 daddiu R_WRBC_RADDR, R_WRBC_RADDR, L2_LINES_PER_BLOCK*32-32 1091#endif 1092 li R_WRBC_NEXT_WAY, 0x20000 1093 /* way = 0; */ 1094 /* for (line = 0; line < lines_per_block; line++) {*/ 1095 li R_WRBC_LINE,L2_LINES_PER_BLOCK-1 1096march4_w0: 1097 move R_PASS_FAIL, zero 1098 INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) 1099 BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1100 INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) 1101 BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1102 BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1103 BG_INVAL_L1(R_BG_WADDR) 1104 SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE) 1105 daddiu R_WRBC_RADDR, R_WRBC_RADDR, -32 1106 1107 bne R_WRBC_LINE,$0, march4_w0 1108 add R_WRBC_LINE,R_WRBC_LINE,-1 1109 1110/* 1111 bne R_BG_PAT0_0, $0, 0f 1112 nop 1113 dli R_BG_PAT0_0, 0x5555555555555555 1114 move R_BG_PAT0_1, R_BG_PAT0_0 1115 move R_BG_PAT0_2, R_BG_PAT0_0 1116 move R_BG_PAT0_3, R_BG_PAT0_0 1117 b bg_next_patt 1118 nop 11190: 1120 beq R_BG_PAT0_2, $0, 3f 1121 nop 1122 bne R_BG_PAT0_3, $0, 4f 1123 nop 1124 move R_BG_PAT0_1, R_BG_PAT0_0 1125 move R_BG_PAT0_2, R_BG_PAT0_3 1126 b bg_next_patt 11274: 1128 dli R_BG_SCRATCH2, 0 1129 move R_BG_SCRATCH0, R_BG_PAT0_0 11301: 1131 dsrl R_BG_SCRATCH0, R_BG_SCRATCH0, 1 1132 and R_BG_SCRATCH1, R_BG_SCRATCH0, 1 1133 addi R_BG_SCRATCH2, R_BG_SCRATCH2, 1 1134 bne R_BG_SCRATCH1, $0, 1b 1135 nop 1136 1137 dsll R_BG_SCRATCH2, R_BG_SCRATCH2, 1 1138 bne R_BG_SCRATCH2, 0x40, 6f 1139 dli R_BG_PAT0_0, -1 1140 move R_BG_PAT0_1, $0 1141 move R_BG_PAT0_2, R_BG_PAT0_0 1142 move R_BG_PAT0_3, $0 1143 b bg_next_patt 11446: 1145 dli R_BG_SCRATCH3, 1 1146 dsll R_BG_SCRATCH3, R_BG_SCRATCH3, R_BG_SCRATCH2 1147 daddiu R_BG_SCRATCH3, R_BG_SCRATCH3, -1 1148 1149 dsll R_BG_SCRATCH2, R_BG_SCRATCH2, 1 1150 move R_BG_PAT0_0, R_BG_SCRATCH3 1151 beq R_BG_SCRATCH2, 0x40, 5f 11522: 1153 dsll R_BG_SCRATCH3, R_BG_SCRATCH3, R_BG_SCRATCH2 1154 or R_BG_PAT0_0, R_BG_PAT0_0, R_BG_SCRATCH3 1155 bne R_BG_SCRATCH3, $0, 2b 1156 nop 1157 11585: 1159 move R_BG_PAT0_1, R_BG_PAT0_0 1160 move R_BG_PAT0_2, R_BG_PAT0_0 1161 move R_BG_PAT0_3, R_BG_PAT0_0 1162 b bg_next_patt 1163 nop 1164 11653: 1166*/ 1167 addu R_PATTERN_IND, R_PATTERN_IND, 1 1168 slt R_BG_SCRATCH0, R_PATTERN_IND, MAX_PATTERN 1169 bne R_BG_SCRATCH0, $0, bg_next_patt 1170 1171 li R_BG_SCRATCH0, 2 11721: 1173 dli R_BG_SCRATCH1, 2 11742: 1175 daddiu R_BG_SCRATCH1, R_BG_SCRATCH1, -1 1176 bne R_BG_SCRATCH1, $0, 2b 1177 nop 1178 daddiu R_BG_SCRATCH0, R_BG_SCRATCH0, -1 1179 bne R_BG_SCRATCH0, $0, 1b 1180 nop 1181 1182/* march element 5 */ 1183 dli R_WRBC_RADDR, XKPHYS_C_COH_EXC 1184 dli R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR 1185 or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0 1186 /* form address for block to be read/written */ 1187 sll R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT 1188 or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1 1189 li R_WRBC_NEXT_WAY, 0x20000 1190 move R_WRBC_LINE,zero 1191march5_w0: 1192 move R_PASS_FAIL, zero 1193 BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1194 INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) 1195 BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1196 INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) 1197 SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE) 1198 daddiu R_WRBC_RADDR, R_WRBC_RADDR, 32 1199 1200 slt R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1 1201 bne R_BG_SCRATCH0,$0,march5_w0 1202 add R_BG_LINE,R_BG_LINE,1 1203 1204 li R_BG_SCRATCH0, 2 12051: 1206 dli R_BG_SCRATCH1, 2 12072: 1208 daddiu R_BG_SCRATCH1, R_BG_SCRATCH1, -1 1209 bne R_BG_SCRATCH1, $0, 2b 1210 nop 1211 daddiu R_BG_SCRATCH0, R_BG_SCRATCH0, -1 1212 bne R_BG_SCRATCH0, $0, 1b 1213 nop 1214 1215/* march element 6 */ 1216 dli R_WRBC_RADDR, XKPHYS_C_COH_EXC 1217 dli R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR 1218 or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0 1219 /* form address for block to be read/written */ 1220 sll R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT 1221 or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1 1222 li R_WRBC_NEXT_WAY, 0x20000 1223 move R_WRBC_LINE,zero 1224march6_w0: 1225 move R_PASS_FAIL, zero 1226 INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) 1227 BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) 1228 INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) 1229 SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE) 1230 daddiu R_WRBC_RADDR, R_WRBC_RADDR, 32 1231 1232 slt R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1 1233 bne R_BG_SCRATCH0,$0,march6_w0 1234 add R_BG_LINE,R_BG_LINE,1 1235 1236 /* if error, put test block info into s0 and return */ 1237 or R_BG_SCRATCH0, R_ERR_TABLE_0, R_ERR_TABLE_1 1238 or R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_2 1239 or R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_3 1240 beq R_BG_SCRATCH0, zero, 1f 1241 nop 1242 move s0, R_BG_BLOCK 1243 or s0, s0, 1 << 8 1244 jr ra 1245 nop 12461: 1247 1248 addu R_BG_BLOCK,R_BG_BLOCK,1 1249 /*slt R_BG_SCRATCH0, R_BG_BLOCK, (L2_BLOCKS_PER_ROW * L2_BLOCK_ROWS)*/ 1250 addi R_BG_SCRATCH1, k0, 1 1251 sll R_BG_SCRATCH1, R_BG_SCRATCH1, 2 1252 /*slt R_BG_SCRATCH0, R_BG_BLOCK, (START_BLK + TOTAL_BLKS)*/ 1253 slt R_BG_SCRATCH0, R_BG_BLOCK, R_BG_SCRATCH1 1254 bne R_BG_SCRATCH0,$0, bg_next_block 1255 nop 1256 1257 .set noreorder 1258 jr ra 1259 nop 1260 1261bg_err: 1262 li v0, 1 1263 jr ra 1264 nop 1265 1266#endif 1267 1268 1269#define SCD_BW_BASE 0x0010020880 1270#define L2_BASE 0x0010040000 1271#define L2_READ_TAG 0x18 1272#define L2_ECC_TAG 0x38 1273#define BUS_ERR_STATUS 0x00 1274#define BUS_L2_ERRORS 0x40 1275 1276#define R_ECC_PAT0_0 a0 1277#define R_ECC_PAT0_1 a1 1278#define R_ECC_PAT0_2 a2 1279#define R_ECC_PAT0_3 a3 1280 1281#define R_ECC_PAT1_0 t0 1282#define R_ECC_PAT1_1 t1 1283#define R_ECC_PAT1_2 t2 1284#define R_ECC_PAT1_3 t3 1285 1286#define R_ECC_PATT_IND s0 1287#define R_ECC_LINE s2 1288#define R_ECC_NEXT_WAY s3 1289#define R_ECC_BLOCK s1 1290#define R_ECC_WADDR t5 1291#define R_ECC_RADDR t5 1292 1293#define R_ECC_SCRATCH0 t6 1294#define R_ECC_SCRATCH1 t7 1295#define R_ECC_SCRATCH2 t8 1296#define R_ECC_SCRATCH3 t9 1297#define R_ECC_SCRATCH4 s6 1298#define R_ECC_SCRATCH5 s7 1299 1300/* 1301#define DATA_FOR_ECC_PATT0 0x0000 1302#define DATA_FOR_ECC_PATT1 0x0020 1303#define DATA_FOR_ECC_PATT2 0x1032 1304#define DATA_FOR_ECC_PATT3 0x0017 1305#define DATA_FOR_ECC_PATT4 0x1822 1306 1307#define DATA_FOR_ECC_INVPATT0 0x0036 1308#define DATA_FOR_ECC_INVPATT1 0x0016 1309#define DATA_FOR_ECC_INVPATT2 0x1004 1310#define DATA_FOR_ECC_INVPATT3 0x0021 1311#define DATA_FOR_ECC_INVPATT4 0x1814 1312*/ 1313#define DATA_FOR_ECC_PATT0 0x0000 1314#define DATA_FOR_ECC_PATT1 0x00ba 1315#define DATA_FOR_ECC_PATT2 0x0438 1316#define DATA_FOR_ECC_PATT3 0x05be 1317#define DATA_FOR_ECC_PATT4 0x0099 1318 1319#define DATA_FOR_ECC_INVPATT0 0x059c 1320#define DATA_FOR_ECC_INVPATT1 0x0526 1321#define DATA_FOR_ECC_INVPATT2 0x01a4 1322#define DATA_FOR_ECC_INVPATT3 0x0022 1323#define DATA_FOR_ECC_INVPATT4 0x0505 1324 1325#define ECC_WRITE_PAT(addr, pattern0, pattern1, pattern2, pattern3)\ 1326 dli R_ECC_SCRATCH2, 4; \ 1327 /*dli R_ECC_SCRATCH0, 0x00400000;*/ \ 1328 /*nor R_ECC_SCRATCH1, R_ECC_SCRATCH0, $0;*/ \ 13291: sd pattern0, 0(addr); \ 1330 sd zero, 8(addr); \ 1331 sd zero, 16(addr); \ 1332 sd zero, 24(addr); \ 1333 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(addr); \ 1334 /*or addr, R_ECC_SCRATCH0, addr;*/ \ 1335 /*sd pattern0, 0(addr);*/ \ 1336 /*sd zero, 8(addr);*/ \ 1337 /*sd zero, 16(addr);*/ \ 1338 /*sd zero, 24(addr);*/ \ 1339 /*cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(addr);*/ \ 1340 /*and addr, addr, R_ECC_SCRATCH1;*/ \ 1341 move R_ECC_SCRATCH3, pattern0; \ 1342 move pattern0, pattern1; \ 1343 move pattern1, pattern2; \ 1344 move pattern2, pattern3; \ 1345 move pattern3, R_ECC_SCRATCH3; \ 1346 addi R_ECC_SCRATCH2, R_ECC_SCRATCH2, -1; \ 1347 bne R_ECC_SCRATCH2, zero, 1b; \ 1348 daddu addr, addr, R_BG_NEXT_WAY; \ 1349 li R_ECC_SCRATCH0, -4*2*65536; \ 1350 dadd addr, addr, R_ECC_SCRATCH0 1351 1352#define ECC_CHECK_PAT(addr,pattern0,pattern1,pattern2,pattern3,fail) \ 1353 dli R_ECC_SCRATCH4, XKPHYS_UNC; \ 1354 dli R_ECC_SCRATCH5, SCD_BW_BASE; \ 1355 or R_ECC_SCRATCH4, R_ECC_SCRATCH4, R_ECC_SCRATCH5; \ 1356 li R_ECC_SCRATCH5, 4; \ 1357 sd zero, BUS_L2_ERRORS(R_ECC_SCRATCH4); \ 1358 sync; \ 13591: ld R_ECC_SCRATCH0, 0(addr); \ 1360 ld R_ECC_SCRATCH1, 8(addr); \ 1361 sne R_ECC_SCRATCH0, R_ECC_SCRATCH0, pattern0; \ 1362 or R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH0; \ 1363 ld R_ECC_SCRATCH2, 16(addr);\ 1364 sne R_ECC_SCRATCH1, R_ECC_SCRATCH1, zero; \ 1365 or R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH1; \ 1366 ld R_ECC_SCRATCH3, 24(addr);\ 1367 sne R_ECC_SCRATCH2, R_ECC_SCRATCH2, zero; \ 1368 or R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH2; \ 1369 ld R_ECC_SCRATCH0, BUS_L2_ERRORS(R_ECC_SCRATCH4); \ 1370 sne R_ECC_SCRATCH3, R_ECC_SCRATCH3, zero; \ 1371 or R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH3; \ 1372 li R_ECC_SCRATCH2, 0xffff; \ 1373 and R_ECC_SCRATCH0, R_ECC_SCRATCH2, R_ECC_SCRATCH0; \ 1374 sne R_ECC_SCRATCH0, R_ECC_SCRATCH0, zero; \ 1375 or R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH0; \ 1376 move R_ECC_SCRATCH3, pattern0; \ 1377 move pattern0, pattern1; \ 1378 move pattern1, pattern2; \ 1379 move pattern2, pattern3; \ 1380 move pattern3, R_ECC_SCRATCH3; \ 1381 addi R_BG_SCRATCH5, R_BG_SCRATCH5, -1; \ 1382 bne R_BG_SCRATCH5, zero, 1b; \ 1383 daddu addr, addr, R_ECC_NEXT_WAY; \ 1384 li R_ECC_SCRATCH0, -4*2*65536; \ 1385 dadd addr, addr, R_ECC_SCRATCH0 1386 1387#define ECC_CHECK_PAT1(addr,pattern0,pattern1,pattern2,pattern3,fail) \ 1388 dli R_ECC_SCRATCH4, XKPHYS_UNC; \ 1389 dli R_ECC_SCRATCH5, SCD_BW_BASE; \ 1390 or R_ECC_SCRATCH4, R_ECC_SCRATCH4, R_ECC_SCRATCH5; \ 1391 li R_ECC_SCRATCH5, 4; \ 13921: sd zero, BUS_L2_ERRORS(R_ECC_SCRATCH4); \ 1393 ld R_ECC_SCRATCH0, 0(addr); \ 1394 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(addr); \ 1395 ld R_ECC_SCRATCH0, 0(addr); \ 1396 ld R_ECC_SCRATCH1, 8(addr); \ 1397 sne R_ECC_SCRATCH0, R_ECC_SCRATCH0, pattern0; \ 1398 or R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH0; \ 1399 ld R_ECC_SCRATCH2, 16(addr);\ 1400 sne R_ECC_SCRATCH1, R_ECC_SCRATCH1, zero; \ 1401 or R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH1; \ 1402 ld R_ECC_SCRATCH3, 24(addr);\ 1403 sne R_ECC_SCRATCH2, R_ECC_SCRATCH2, zero; \ 1404 or R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH2; \ 1405 ld R_ECC_SCRATCH0, BUS_L2_ERRORS(R_ECC_SCRATCH4); \ 1406 sne R_ECC_SCRATCH3, R_ECC_SCRATCH3, zero; \ 1407 or R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH3; \ 1408 sne R_ECC_SCRATCH0, R_ECC_SCRATCH0, zero; \ 1409 or R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH0; \ 1410 move R_ECC_SCRATCH3, pattern0; \ 1411 move pattern0, pattern1; \ 1412 move pattern1, pattern2; \ 1413 move pattern2, pattern3; \ 1414 move pattern3, R_ECC_SCRATCH3; \ 1415 addi R_BG_SCRATCH5, R_BG_SCRATCH5, -1; \ 1416 bne R_BG_SCRATCH5, zero, 1b; \ 1417 daddu addr, addr, R_ECC_NEXT_WAY; \ 1418 li R_ECC_SCRATCH0, -4*2*65536; \ 1419 dadd addr, addr, R_ECC_SCRATCH0 1420 1421#ifdef DATA_TEST 1422#ifdef DATA_ECC_TEST 1423l2dtest_data_ecc: 1424 1425 /*li R_ECC_BLOCK, START_BLK*/ 1426 sll R_ECC_BLOCK, k0, 2 1427 li R_ECC_NEXT_WAY,0x20000 1428ecc_next_block: 1429#ifdef USE_LEDS 1430 addi R_BG_SCRATCH2, R_BG_BLOCK, '0' 1431 or R_BG_SCRATCH2, R_BG_SCRATCH2, ('E' << 8) 1432 SET_LEDS_HI(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1) 1433#endif 1434 1435 move R_ECC_PATT_IND, $0 1436 dli R_ECC_PAT0_0, DATA_FOR_ECC_PATT0 1437 dli R_ECC_PAT0_1, DATA_FOR_ECC_PATT0 1438 dli R_ECC_PAT0_2, DATA_FOR_ECC_PATT0 1439 dli R_ECC_PAT0_3, DATA_FOR_ECC_PATT0 1440 dli R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT0 1441 dli R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT0 1442 dli R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT0 1443 dli R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT0 1444 1445ecc_next_pattern: 1446#ifdef USE_LEDS 1447 addi R_BG_SCRATCH2, R_ECC_PATT_IND, '0' 1448 or R_BG_SCRATCH2, R_BG_SCRATCH2, ('P' << 8) 1449 SET_LEDS_LO(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1) 1450#endif 1451 1452 dli R_ECC_WADDR, XKPHYS_C_COH_EXC /* uncached accelerated */ 1453 dli R_ECC_SCRATCH0, L2_RAM_BASE_ADDR /* mgmt mode */ 1454 or R_ECC_WADDR,R_ECC_WADDR,R_BG_SCRATCH0 1455 sll R_ECC_SCRATCH0, R_ECC_BLOCK, L2_BLOCK_SHIFT /* block number */ 1456 or R_ECC_WADDR, R_ECC_WADDR, R_ECC_SCRATCH0 1457 1458 1459 .set noreorder 1460 move R_ECC_LINE, zero 1461ecc_init_next_line: 1462 ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3) 1463 li R_ECC_SCRATCH0, (32) 1464 dadd R_ECC_WADDR, R_ECC_WADDR, R_ECC_SCRATCH0 /* next line */ 1465 1466 slt R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1 1467 bne R_ECC_SCRATCH0, $0, ecc_init_next_line 1468 add R_ECC_LINE, R_ECC_LINE,1 1469 1470 dli R_ECC_RADDR, XKPHYS_C_COH_EXC 1471 dli R_ECC_SCRATCH0, L2_RAM_BASE_ADDR 1472 or R_ECC_RADDR, R_ECC_RADDR, R_WRBC_SCRATCH0 1473 sll R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT 1474 or R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1 1475 li R_ECC_NEXT_WAY, 0x20000 1476 1477 move R_ECC_LINE, zero 1478ecc_march1: 1479 move R_PASS_FAIL, zero 1480 ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err) 1481 ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3) 1482 ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err) 1483 BG_INVAL_L1(R_BG_WADDR) 1484 SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE) 1485 daddiu R_ECC_RADDR, R_ECC_RADDR, 0x20 1486 1487 slt R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1 1488 bne R_ECC_SCRATCH0, $0, ecc_march1 1489 add R_ECC_LINE, R_ECC_LINE,1 1490 1491 dli R_ECC_RADDR, XKPHYS_C_COH_EXC 1492 dli R_ECC_SCRATCH0, L2_RAM_BASE_ADDR 1493 or R_ECC_RADDR, R_ECC_RADDR, R_WRBC_SCRATCH0 1494 sll R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT 1495 or R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1 1496 li R_ECC_NEXT_WAY, 0x20000 1497 1498 move R_ECC_LINE, zero 1499ecc_march2: 1500 move R_PASS_FAIL, zero 1501 ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err) 1502 ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3) 1503 ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err) 1504 BG_INVAL_L1(R_BG_WADDR) 1505 SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE) 1506 daddiu R_ECC_RADDR, R_ECC_RADDR, 0x20 1507 1508 slt R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1 1509 bne R_ECC_SCRATCH0, $0, ecc_march2 1510 add R_ECC_LINE, R_ECC_LINE,1 1511 1512 dli R_ECC_RADDR, XKPHYS_C_COH_EXC 1513 dli R_ECC_SCRATCH0, L2_RAM_BASE_ADDR 1514 or R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH0 1515 addi R_ECC_SCRATCH0, R_ECC_BLOCK, 1 1516#ifdef TEST_ALL_LINES 1517 sll R_ECC_SCRATCH1, R_ECC_SCRATCH0, L2_BLOCK_SHIFT 1518#else 1519 sll R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT 1520#endif 1521 or R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1 1522#ifdef TEST_ALL_LINES 1523 daddiu R_ECC_RADDR, R_ECC_RADDR, -32 1524#else 1525 daddiu R_ECC_RADDR, R_ECC_RADDR, L2_LINES_PER_BLOCK*32-32 1526#endif 1527 li R_ECC_LINE,L2_LINES_PER_BLOCK-1 1528ecc_march3: 1529 move R_PASS_FAIL, zero 1530 ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err) 1531 ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3) 1532 ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err) 1533 BG_INVAL_L1(R_BG_WADDR) 1534 SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE) 1535 daddiu R_ECC_RADDR, R_ECC_RADDR, -32 1536 1537 bne R_ECC_LINE,$0, ecc_march3 1538 add R_ECC_LINE,R_ECC_LINE,-1 1539 1540 dli R_ECC_RADDR, XKPHYS_C_COH_EXC 1541 dli R_ECC_SCRATCH0, L2_RAM_BASE_ADDR 1542 or R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH0 1543 addi R_ECC_SCRATCH0, R_ECC_BLOCK, 1 1544#ifdef TEST_ALL_LINES 1545 sll R_ECC_SCRATCH1, R_ECC_SCRATCH0, L2_BLOCK_SHIFT 1546#else 1547 sll R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT 1548#endif 1549 or R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1 1550#ifdef TEST_ALL_LINES 1551 daddiu R_ECC_RADDR, R_ECC_RADDR, -32 1552#else 1553 daddiu R_ECC_RADDR, R_ECC_RADDR, L2_LINES_PER_BLOCK*32-32 1554#endif 1555 li R_ECC_LINE,L2_LINES_PER_BLOCK-1 1556ecc_march4: 1557 move R_PASS_FAIL, zero 1558 ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err) 1559 ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3) 1560 ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err) 1561 BG_INVAL_L1(R_BG_WADDR) 1562 SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE) 1563 daddiu R_ECC_RADDR, R_ECC_RADDR, -32 1564 1565 bne R_ECC_LINE,$0, ecc_march4 1566 add R_ECC_LINE,R_ECC_LINE,-1 1567 1568 addi R_ECC_PATT_IND, R_ECC_PATT_IND, 1 1569 li R_ECC_SCRATCH0, 1 1570 bne R_ECC_SCRATCH0, R_ECC_PATT_IND, 2f 1571 nop 1572 dli R_ECC_PAT0_0, DATA_FOR_ECC_INVPATT0 1573 dli R_ECC_PAT0_1, DATA_FOR_ECC_PATT0 1574 dli R_ECC_PAT0_2, DATA_FOR_ECC_INVPATT0 1575 dli R_ECC_PAT0_3, DATA_FOR_ECC_PATT0 1576 dli R_ECC_PAT1_0, DATA_FOR_ECC_PATT0 1577 dli R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT0 1578 dli R_ECC_PAT1_2, DATA_FOR_ECC_PATT0 1579 dli R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT0 1580 b ecc_next_pattern 15812: 1582 li R_ECC_SCRATCH0, 2 1583 bne R_ECC_SCRATCH0, R_ECC_PATT_IND, 3f 1584 nop 1585 dli R_ECC_PAT0_0, DATA_FOR_ECC_INVPATT0 1586 dli R_ECC_PAT0_1, DATA_FOR_ECC_INVPATT0 1587 dli R_ECC_PAT0_2, DATA_FOR_ECC_PATT0 1588 dli R_ECC_PAT0_3, DATA_FOR_ECC_PATT0 1589 dli R_ECC_PAT1_0, DATA_FOR_ECC_PATT0 1590 dli R_ECC_PAT1_1, DATA_FOR_ECC_PATT0 1591 dli R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT0 1592 dli R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT0 1593 b ecc_next_pattern 1594 nop 15953: 1596 li R_ECC_SCRATCH0, 3 1597 bne R_ECC_SCRATCH0, R_ECC_PATT_IND, 4f 1598 nop 1599 dli R_ECC_PAT0_0, DATA_FOR_ECC_PATT1 1600 dli R_ECC_PAT0_1, DATA_FOR_ECC_PATT1 1601 dli R_ECC_PAT0_2, DATA_FOR_ECC_PATT1 1602 dli R_ECC_PAT0_3, DATA_FOR_ECC_PATT1 1603 dli R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT1 1604 dli R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT1 1605 dli R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT1 1606 dli R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT1 1607 b ecc_next_pattern 1608 nop 16094: 1610 li R_ECC_SCRATCH0, 4 1611 bne R_ECC_SCRATCH0, R_ECC_PATT_IND, 5f 1612 nop 1613 dli R_ECC_PAT0_0, DATA_FOR_ECC_PATT2 1614 dli R_ECC_PAT0_1, DATA_FOR_ECC_PATT2 1615 dli R_ECC_PAT0_2, DATA_FOR_ECC_PATT2 1616 dli R_ECC_PAT0_3, DATA_FOR_ECC_PATT2 1617 dli R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT2 1618 dli R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT2 1619 dli R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT2 1620 dli R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT2 1621 b ecc_next_pattern 1622 nop 16235: 1624 li R_ECC_SCRATCH0, 5 1625 bne R_ECC_SCRATCH0, R_ECC_PATT_IND, 6f 1626 nop 1627 dli R_ECC_PAT0_0, DATA_FOR_ECC_PATT3 1628 dli R_ECC_PAT0_1, DATA_FOR_ECC_PATT3 1629 dli R_ECC_PAT0_2, DATA_FOR_ECC_PATT3 1630 dli R_ECC_PAT0_3, DATA_FOR_ECC_PATT3 1631 dli R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT3 1632 dli R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT3 1633 dli R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT3 1634 dli R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT3 1635 b ecc_next_pattern 1636 nop 16376: 1638 li R_ECC_SCRATCH0, 6 1639 bne R_ECC_SCRATCH0, R_ECC_PATT_IND, 7f 1640 nop 1641 dli R_ECC_PAT0_0, DATA_FOR_ECC_PATT4 1642 dli R_ECC_PAT0_1, DATA_FOR_ECC_PATT4 1643 dli R_ECC_PAT0_2, DATA_FOR_ECC_PATT4 1644 dli R_ECC_PAT0_3, DATA_FOR_ECC_PATT4 1645 dli R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT4 1646 dli R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT4 1647 dli R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT4 1648 dli R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT4 1649 b ecc_next_pattern 1650 nop 16517: 1652 1653 li R_BG_SCRATCH0, 2 16541: 1655 dli R_BG_SCRATCH1, 2 16562: 1657 daddiu R_BG_SCRATCH1, R_BG_SCRATCH1, -1 1658 bne R_BG_SCRATCH1, $0, 2b 1659 nop 1660 daddiu R_BG_SCRATCH0, R_BG_SCRATCH0, -1 1661 bne R_BG_SCRATCH0, $0, 1b 1662 nop 1663 1664 dli R_ECC_RADDR, XKPHYS_C_COH_EXC 1665 dli R_ECC_SCRATCH0, L2_RAM_BASE_ADDR 1666 or R_ECC_RADDR, R_ECC_RADDR, R_WRBC_SCRATCH0 1667 sll R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT 1668 or R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1 1669 li R_ECC_NEXT_WAY, 0x20000 1670 1671 move R_ECC_LINE,zero 1672ecc_march5: 1673 move R_PASS_FAIL, zero 1674 ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err) 1675 ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3) 1676 SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE) 1677 daddiu R_ECC_RADDR, R_ECC_RADDR, 0x20 1678 1679 slt R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1 1680 bne R_ECC_SCRATCH0, $0, ecc_march5 1681 add R_ECC_LINE, R_ECC_LINE,1 1682 1683 dli R_ECC_RADDR, XKPHYS_C_COH_EXC 1684 dli R_ECC_SCRATCH0, L2_RAM_BASE_ADDR 1685 or R_ECC_RADDR, R_ECC_RADDR, R_WRBC_SCRATCH0 1686 sll R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT 1687 or R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1 1688 li R_ECC_NEXT_WAY, 0x20000 1689 1690 li R_BG_SCRATCH0, 2 16911: 1692 dli R_BG_SCRATCH1, 2 16932: 1694 daddiu R_BG_SCRATCH1, R_BG_SCRATCH1, -1 1695 bne R_BG_SCRATCH1, $0, 2b 1696 nop 1697 daddiu R_BG_SCRATCH0, R_BG_SCRATCH0, -1 1698 bne R_BG_SCRATCH0, $0, 1b 1699 nop 1700 1701 move R_ECC_LINE,zero 1702ecc_march6: 1703 move R_PASS_FAIL, zero 1704 ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err) 1705 SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE) 1706 daddiu R_ECC_RADDR, R_ECC_RADDR, 0x20 1707 1708 slt R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1 1709 bne R_ECC_SCRATCH0, $0, ecc_march6 1710 add R_ECC_LINE, R_ECC_LINE,1 1711 1712 /* if error, put test block info into s0 and return */ 1713 or R_BG_SCRATCH0, R_ERR_TABLE_0, R_ERR_TABLE_1 1714 or R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_2 1715 or R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_3 1716 beq R_BG_SCRATCH0, zero, 1f 1717 nop 1718 move s0, R_BG_BLOCK 1719 or s0, s0, 2 << 8 1720 jr ra 1721 nop 17221: 1723 1724 addi R_ECC_BLOCK, R_ECC_BLOCK, 1 1725 /*slt R_ECC_SCRATCH0, R_ECC_BLOCK, (L2_BLOCKS_PER_ROW * L2_BLOCK_ROWS)*/ 1726 addi R_ECC_SCRATCH1, k0, 1 1727 sll R_ECC_SCRATCH1, R_ECC_SCRATCH1, 2 1728 slt R_ECC_SCRATCH0, R_ECC_BLOCK, R_ECC_SCRATCH1 1729 /*slt R_ECC_SCRATCH0, R_ECC_BLOCK, (START_BLK + TOTAL_BLKS)*/ 1730 bne R_ECC_SCRATCH0,$0, ecc_next_block 1731 nop 1732 1733 .set noreorder 1734 move v0, v0 1735 jr ra 1736 nop 1737 1738ecc_err: 1739 li v0, 1 1740 jr ra 1741 nop 1742 1743#endif 1744#endif 1745 1746 1747#ifdef DATA_TEST 1748 1749#define L2_TAG_LINES 256 1750#define L2_TAG_BLOCKS 8 1751 1752#define R_PAT0_0 a0 1753#define R_PAT0_1 a1 1754#define R_PAT0_2 a2 1755#define R_PAT0_3 a3 1756 1757#define R_PAT1_0 t0 1758#define R_PAT1_1 t1 1759#define R_PAT1_2 t2 1760#define R_PAT1_3 t3 1761 1762#define R_PATT_IND s0 1763#define R_LINE s2 1764#define R_NEXT_WAY s3 1765#define R_BLOCK s1 1766#define R_WADDR t5 1767#define R_RADDR t5 1768 1769#define R_SCRATCH0 t6 1770#define R_SCRATCH1 t7 1771#define R_SCRATCH2 t8 1772#define R_SCRATCH3 t9 1773#define R_SCRATCH4 s6 1774#define R_SCRATCH5 s7 1775 1776#ifndef _SB1250_PASS2_ 1777#define L2_READ_TAG_MASK 0x300fffffe0000 1778#else 1779#define L2_READ_TAG_MASK 0x3007fffff8000 1780#endif 1781 1782#ifndef _SB1250_PASS2_ 1783 1784#define TAG_PATT0 0x0 1785#define TAG_PATT1 0x1555555 1786#define TAG_PATT2 0x1333333 1787#define TAG_PATT3 0x10f0f0f 1788#define TAG_PATT4 0x0ff00ff 1789#define TAG_PATT5 0x0ffff 1790 1791#define TAG_INVPATT0 0x1ffffff 1792#define TAG_INVPATT1 0x0aaaaaa 1793#define TAG_INVPATT2 0x0cccccc 1794#define TAG_INVPATT3 0x0f0f0f0 1795#define TAG_INVPATT4 0x100ff00 1796#define TAG_INVPATT5 0x1ff0000 1797 1798#else 1799 1800#define TAG_PATT0 0x0 1801#define TAG_PATT1 0x1555555 1802#define TAG_PATT2 0x3333333 1803#define TAG_PATT3 0x10f0f0f 1804#define TAG_PATT4 0x0ff00ff 1805#define TAG_PATT5 0x0ffff 1806 1807#define TAG_INVPATT0 0x3ffffff 1808#define TAG_INVPATT1 0x2aaaaaa 1809#define TAG_INVPATT2 0x0cccccc 1810#define TAG_INVPATT3 0x0f0f0f0 1811#define TAG_INVPATT4 0x300ff00 1812#define TAG_INVPATT5 0x3ff0000 1813 1814#endif 1815 1816 1817#define TAG_WRITE_PAT(addr, pattern0, pattern1)\ 1818 dli R_SCRATCH0, L2M_WRITE_TAG; \ 1819 or R_SCRATCH0, addr, R_SCRATCH0; \ 1820 sd pattern0, 0x18(R_SCRATCH0); \ 1821 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \ 1822 sd pattern1, 0x2018(R_SCRATCH0); \ 1823 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0); \ 1824 daddu R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY; \ 1825 sd pattern0, 0x18(R_SCRATCH0); \ 1826 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \ 1827 sd pattern1, 0x2018(R_SCRATCH0); \ 1828 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0); \ 1829 daddu R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY; \ 1830 sd pattern0, 0x18(R_SCRATCH0); \ 1831 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \ 1832 sd pattern1, 0x2018(R_SCRATCH0); \ 1833 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0); \ 1834 daddu R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY; \ 1835 sd pattern0, 0x18(R_SCRATCH0); \ 1836 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \ 1837 sd pattern1, 0x2018(R_SCRATCH0); \ 1838 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0) 1839 1840#ifndef _SB1250_PASS2_ 1841#define TAG_MAKE_PAT(pattern0, pattern1)\ 1842 li R_SCRATCH4, 0x800000;\ 1843 and R_SCRATCH2, R_SCRATCH4, pattern0;\ 1844 dsll R_SCRATCH2, R_SCRATCH2, 26;\ 1845 li R_SCRATCH4, 0x1000000;\ 1846 and R_SCRATCH4, R_SCRATCH4, pattern0;\ 1847 dsll R_SCRATCH4, R_SCRATCH4, 24;\ 1848 or R_SCRATCH2, R_SCRATCH2, R_SCRATCH4;\ 1849 li R_SCRATCH4, 0x7fffff;\ 1850 and R_SCRATCH4, R_SCRATCH4, pattern0;\ 1851 dsll R_SCRATCH4, R_SCRATCH4, 17;\ 1852 or R_SCRATCH2, R_SCRATCH2, R_SCRATCH4;\ 1853 dli R_SCRATCH4, L2_READ_TAG_MASK; \ 1854 and pattern1, R_SCRATCH2, R_SCRATCH4; 1855 1856#else 1857 1858#define TAG_MAKE_PAT(pattern0, pattern1)\ 1859 li R_SCRATCH4, 0x1000000;\ 1860 and R_SCRATCH2, R_SCRATCH4, pattern0;\ 1861 dsll R_SCRATCH2, R_SCRATCH2, 25;\ 1862 li R_SCRATCH4, 0x2000000;\ 1863 and R_SCRATCH4, R_SCRATCH4, pattern0;\ 1864 dsll R_SCRATCH4, R_SCRATCH4, 23;\ 1865 or R_SCRATCH2, R_SCRATCH2, R_SCRATCH4;\ 1866 li R_SCRATCH4, 0x3fffff;\ 1867 and R_SCRATCH4, R_SCRATCH4, pattern0;\ 1868 dsll R_SCRATCH4, R_SCRATCH4, 17;\ 1869 or R_SCRATCH2, R_SCRATCH2, R_SCRATCH4;\ 1870 li R_SCRATCH4, 0xc00000;\ 1871 and R_SCRATCH4, R_SCRATCH4, pattern0;\ 1872 dsrl R_SCRATCH4, R_SCRATCH4, 7;\ 1873 or R_SCRATCH2, R_SCRATCH2, R_SCRATCH4;\ 1874 dli R_SCRATCH4, L2_READ_TAG_MASK; \ 1875 and pattern1, R_SCRATCH2, R_SCRATCH4; 1876 1877#endif 1878 1879#define TAG_CHECK_PAT(addr, pattern0, pattern1)\ 1880 li R_SCRATCH2, 4;\ 1881 dli R_SCRATCH4, XKPHYS_UNC; \ 1882 dli R_SCRATCH5, L2_BASE; \ 1883 or R_SCRATCH4, R_SCRATCH4, R_SCRATCH5; \ 1884 dli R_SCRATCH5, L2_READ_TAG_MASK;\ 1885 dli R_SCRATCH0, L2M_READ_RAW_ACCESS; \ 1886 or R_SCRATCH0, addr, R_SCRATCH0; \ 18871: ld R_SCRATCH1, (R_SCRATCH0); \ 1888 sync; \ 1889 ld R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \ 1890 and R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \ 1891 sne R_SCRATCH1, R_SCRATCH1, pattern0; \ 1892 or R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1; \ 1893 ld R_SCRATCH1, 0x2000(R_SCRATCH0); \ 1894 sync; \ 1895 ld R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \ 1896 and R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \ 1897 sne R_SCRATCH1, R_SCRATCH1, pattern1; \ 1898 or R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1; \ 1899 addi R_SCRATCH2, R_SCRATCH2, -1; \ 1900 bne R_SCRATCH2, zero, 1b; \ 1901 daddu R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY 1902 1903#define TAG_CHECK_PAT1(addr, pattern0, pattern1)\ 1904 li R_SCRATCH2, 4;\ 1905 dli R_SCRATCH4, XKPHYS_UNC; \ 1906 dli R_SCRATCH5, L2_BASE; \ 1907 or R_SCRATCH4, R_SCRATCH4, R_SCRATCH5; \ 1908 dli R_SCRATCH5, L2_READ_TAG_MASK;\ 1909 dli R_SCRATCH0, 0x00200000; \ 1910 or R_SCRATCH0, addr, R_SCRATCH0; \ 19111: ld R_SCRATCH1, (R_SCRATCH0); \ 1912 sync; \ 1913 ld R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \ 1914 and R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \ 1915 sne R_SCRATCH1, R_SCRATCH1, pattern0; \ 1916 or R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1; \ 1917 ld R_SCRATCH1, 0x2000(R_SCRATCH0); \ 1918 sync; \ 1919 ld R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \ 1920 and R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \ 1921 sne R_SCRATCH1, R_SCRATCH1, pattern1; \ 1922 or R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1; \ 1923 addi R_SCRATCH2, R_SCRATCH2, -1; \ 1924 bne R_SCRATCH2, zero, 1b; \ 1925 daddu R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY 1926 1927 1928l2dtest_tag_data: 1929/* 1930 move R_ERR_TABLE_0, $0 1931 move R_ERR_TABLE_1, $0 1932 move R_ERR_TABLE_2, $0 1933 move R_ERR_TABLE_3, $0 1934*/ 1935#if 1 /* zb */ 1936 /*li R_BLOCK, START_BLK*/ 1937 sll R_BLOCK, k0, 1 1938 li R_NEXT_WAY,0x20000 1939tag_next_block: 1940#ifdef USE_LEDS 1941 addi R_BG_SCRATCH2, R_BG_BLOCK, '0' 1942 or R_BG_SCRATCH2, R_BG_SCRATCH2, ('T' << 8) 1943 SET_LEDS_HI(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1) 1944#endif 1945 1946 move R_PATT_IND, $0 1947 dli R_PAT0_0, TAG_PATT0 1948 dli R_PAT0_1, TAG_PATT0 1949 TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2) 1950 TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3) 1951 dli R_PAT1_0, TAG_INVPATT0 1952 dli R_PAT1_1, TAG_INVPATT0 1953 TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2) 1954 TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3) 1955 1956tag_next_pattern: 1957#ifdef USE_LEDS 1958 addi R_BG_SCRATCH2, R_PATT_IND, '0' 1959 or R_BG_SCRATCH2, R_BG_SCRATCH2, ('P' << 8) 1960 SET_LEDS_LO(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1) 1961#endif 1962 1963 dli R_WADDR, XKPHYS_C_COH_EXC /* uncached accelerated */ 1964 dli R_SCRATCH0, L2_RAM_BASE_ADDR /* mgmt mode */ 1965 or R_WADDR,R_ECC_WADDR,R_BG_SCRATCH0 1966 sll R_SCRATCH0, R_BLOCK, L2_BLOCK_ROW_SHIFT /* block number */ 1967 or R_WADDR, R_WADDR, R_SCRATCH0 1968 1969 .set noreorder 1970 move R_LINE, zero 1971tag_init_next_line: 1972 TAG_WRITE_PAT(R_WADDR,R_PAT0_0,R_PAT0_1) 1973 li R_SCRATCH0, (32) 1974 dadd R_WADDR, R_WADDR, R_SCRATCH0 /* next line */ 1975 1976 slt R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1 1977 bne R_SCRATCH0, $0, tag_init_next_line 1978 add R_LINE, R_LINE,1 1979 1980 dli R_RADDR, XKPHYS_C_COH_EXC 1981 dli R_SCRATCH0, L2_RAM_BASE_ADDR 1982 or R_RADDR, R_RADDR, R_SCRATCH0 1983 sll R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT 1984 or R_RADDR, R_RADDR, R_SCRATCH1 1985 li R_NEXT_WAY, 0x20000 1986 1987 move R_LINE, zero 1988tag_march1: 1989 move R_PASS_FAIL, zero 1990 TAG_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3) 1991 TAG_WRITE_PAT(R_WADDR,R_PAT1_0,R_PAT1_1) 1992 TAG_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3) 1993 SET_ERR_TABLE(R_PASS_FAIL, R_LINE) 1994 daddiu R_RADDR, R_RADDR, 0x20 1995 1996 slt R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1 1997 bne R_SCRATCH0, $0, tag_march1 1998 add R_LINE, R_LINE,1 1999 2000 dli R_RADDR, XKPHYS_C_COH_EXC 2001 dli R_SCRATCH0, L2_RAM_BASE_ADDR 2002 or R_RADDR, R_RADDR, R_SCRATCH0 2003 sll R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT 2004 or R_RADDR, R_RADDR, R_SCRATCH1 2005 2006 move R_LINE,zero 2007tag_march2: 2008 move R_PASS_FAIL, zero 2009 TAG_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3) 2010 TAG_WRITE_PAT(R_WADDR,R_PAT0_0,R_PAT0_1) 2011 TAG_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3) 2012 SET_ERR_TABLE(R_PASS_FAIL, R_LINE) 2013 daddiu R_RADDR, R_RADDR, 0x20 2014 2015 slt R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1 2016 bne R_SCRATCH0, $0, tag_march2 2017 add R_LINE, R_LINE,1 2018 2019 dli R_RADDR, XKPHYS_C_COH_EXC 2020 dli R_SCRATCH0, L2_RAM_BASE_ADDR 2021 or R_RADDR, R_RADDR, R_SCRATCH0 2022#ifdef TEST_ALL_LINES 2023 sll R_SCRATCH0, R_BLOCK, 1 2024 addi R_SCRATCH0, R_SCRATCH0, 1 2025 sll R_SCRATCH1, R_SCRATCH0, L2_BLOCK_SHIFT 2026#else 2027 sll R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT 2028#endif 2029 or R_RADDR, R_RADDR, R_SCRATCH1 2030#ifdef TEST_ALL_LINES 2031 daddiu R_RADDR, R_RADDR, -32 2032#else 2033 daddiu R_RADDR, R_RADDR, L2_LINES_PER_BLOCK*32-32 2034#endif 2035 li R_LINE,L2_LINES_PER_BLOCK-1 2036tag_march3: 2037 move R_PASS_FAIL, zero 2038 TAG_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3) 2039 TAG_WRITE_PAT(R_WADDR,R_PAT1_0,R_PAT1_1) 2040 TAG_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3) 2041 SET_ERR_TABLE(R_PASS_FAIL, R_LINE) 2042 daddiu R_RADDR, R_RADDR, -32 2043 2044 bne R_LINE,$0, tag_march3 2045 add R_LINE,R_LINE,-1 2046 2047 dli R_RADDR, XKPHYS_C_COH_EXC 2048 dli R_SCRATCH0, L2_RAM_BASE_ADDR 2049 or R_RADDR, R_RADDR, R_SCRATCH0 2050#ifdef TEST_ALL_LINES 2051 sll R_SCRATCH0, R_BLOCK, 1 2052 addi R_SCRATCH0, R_SCRATCH0, 1 2053 sll R_SCRATCH1, R_SCRATCH0, L2_BLOCK_SHIFT 2054#else 2055 sll R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT 2056#endif 2057 or R_RADDR, R_RADDR, R_SCRATCH1 2058#ifdef TEST_ALL_LINES 2059 daddiu R_RADDR, R_RADDR, -32 2060#else 2061 daddiu R_RADDR, R_RADDR, L2_LINES_PER_BLOCK*32-32 2062#endif 2063 li R_LINE,L2_LINES_PER_BLOCK-1 2064tag_march4: 2065 move R_PASS_FAIL, zero 2066 TAG_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3) 2067 TAG_WRITE_PAT(R_WADDR,R_PAT0_0,R_PAT0_1) 2068 TAG_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3) 2069 SET_ERR_TABLE(R_PASS_FAIL, R_LINE) 2070 daddiu R_RADDR, R_RADDR, -32 2071 2072 bne R_LINE,$0, tag_march4 2073 add R_LINE,R_LINE,-1 2074 2075 addi R_PATT_IND, R_PATT_IND, 1 2076 li R_SCRATCH0, 1 2077 bne R_SCRATCH0, R_PATT_IND, 2f 2078 nop 2079 dli R_PAT0_0, TAG_INVPATT0 2080 dli R_PAT0_1, TAG_PATT0 2081 TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2) 2082 TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3) 2083 dli R_PAT1_0, TAG_PATT0 2084 dli R_PAT1_1, TAG_INVPATT0 2085 TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2) 2086 TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3) 2087 2088 b tag_next_pattern 20892: 2090 li R_SCRATCH0, 2 2091 bne R_SCRATCH0, R_PATT_IND, 3f 2092 nop 2093 2094 dli R_PAT0_0, TAG_PATT2 2095 dli R_PAT0_1, TAG_PATT2 2096 TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2) 2097 TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3) 2098 dli R_PAT1_0, TAG_INVPATT2 2099 dli R_PAT1_1, TAG_INVPATT2 2100 TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2) 2101 TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3) 2102 b tag_next_pattern 21033: 2104 li R_SCRATCH0, 3 2105 bne R_SCRATCH0, R_PATT_IND, 4f 2106 nop 2107 2108 dli R_PAT0_0, TAG_PATT3 2109 dli R_PAT0_1, TAG_PATT3 2110 TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2) 2111 TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3) 2112 dli R_PAT1_0, TAG_INVPATT3 2113 dli R_PAT1_1, TAG_INVPATT3 2114 TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2) 2115 TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3) 2116 b tag_next_pattern 21174: 2118 li R_SCRATCH0, 4 2119 bne R_SCRATCH0, R_PATT_IND, 5f 2120 nop 2121 2122 dli R_PAT0_0, TAG_PATT4 2123 dli R_PAT0_1, TAG_PATT4 2124 TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2) 2125 TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3) 2126 dli R_PAT1_0, TAG_INVPATT4 2127 dli R_PAT1_1, TAG_INVPATT4 2128 TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2) 2129 TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3) 2130 b tag_next_pattern 21315: 2132 li R_SCRATCH0, 5 2133 bne R_SCRATCH0, R_PATT_IND, 6f 2134 nop 2135 2136 dli R_PAT0_0, TAG_PATT5 2137 dli R_PAT0_1, TAG_PATT5 2138 TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2) 2139 TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3) 2140 dli R_PAT1_0, TAG_INVPATT5 2141 dli R_PAT1_1, TAG_INVPATT5 2142 TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2) 2143 TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3) 2144 b tag_next_pattern 2145 nop 21466: 2147 li R_SCRATCH0, 2 21481: 2149 dli R_SCRATCH1, 2 21502: 2151 daddiu R_SCRATCH1, R_SCRATCH1, -1 2152 bne R_SCRATCH1, $0, 2b 2153 nop 2154 daddiu R_SCRATCH0, R_SCRATCH0, -1 2155 bne R_SCRATCH0, $0, 1b 2156 nop 2157 2158 dli R_RADDR, XKPHYS_C_COH_EXC 2159 dli R_SCRATCH0, L2_RAM_BASE_ADDR 2160 or R_RADDR, R_RADDR, R_SCRATCH0 2161 sll R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT 2162 or R_RADDR, R_RADDR, R_SCRATCH1 2163 li R_NEXT_WAY, 0x20000 2164 2165 move R_LINE,zero 2166tag_march5: 2167 move R_PASS_FAIL, zero 2168 TAG_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3) 2169 TAG_WRITE_PAT(R_WADDR,R_PAT1_0,R_PAT1_1) 2170 SET_ERR_TABLE(R_PASS_FAIL, R_LINE) 2171 daddiu R_RADDR, R_RADDR, 0x20 2172 2173 slt R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1 2174 bne R_SCRATCH0, $0, tag_march5 2175 add R_LINE, R_LINE,1 2176 2177 li R_SCRATCH0, 2 21781: 2179 dli R_SCRATCH1, 2 21802: 2181 daddiu R_SCRATCH1, R_SCRATCH1, -1 2182 bne R_SCRATCH1, $0, 2b 2183 nop 2184 daddiu R_SCRATCH0, R_SCRATCH0, -1 2185 bne R_SCRATCH0, $0, 1b 2186 nop 2187 2188 dli R_RADDR, XKPHYS_C_COH_EXC 2189 dli R_SCRATCH0, L2_RAM_BASE_ADDR 2190 or R_RADDR, R_RADDR, R_SCRATCH0 2191 sll R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT 2192 or R_RADDR, R_RADDR, R_SCRATCH1 2193 2194 move R_LINE,zero 2195tag_march6: 2196 move R_PASS_FAIL, zero 2197 TAG_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3) 2198 SET_ERR_TABLE(R_PASS_FAIL, R_LINE) 2199 daddiu R_RADDR, R_RADDR, 0x20 2200 2201 slt R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1 2202 bne R_SCRATCH0, $0, tag_march6 2203 add R_LINE, R_LINE,1 2204 2205 /* if error, put test block info into s0 and return */ 2206 or R_BG_SCRATCH0, R_ERR_TABLE_0, R_ERR_TABLE_1 2207 or R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_2 2208 or R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_3 2209 beq R_BG_SCRATCH0, zero, 1f 2210 nop 2211 move s0, R_BG_BLOCK 2212 or s0, s0, 3 << 8 2213 jr ra 2214 nop 22151: 2216 2217 addi R_BLOCK, R_BLOCK, 1 2218 addi R_SCRATCH1, k0, 1 2219 sll R_SCRATCH1, R_SCRATCH1, 1 2220 /*slt R_SCRATCH0, R_BLOCK, START_BLK+TOTAL_BLKS/2*/ 2221 slt R_SCRATCH0, R_BLOCK, R_SCRATCH1 2222 bne R_SCRATCH0,$0, tag_next_block 2223 nop 2224#endif /* zb */ 2225 .set noreorder 2226 jr ra 2227 nop 2228 2229tag_err: 2230 li v0, 1 2231 jr ra 2232 nop 2233 2234 2235#define TAG_ECC_PATT0 0x0 2236#define TAG_ECC_PATT1 0x0000003d 2237#define TAG_ECC_PATT2 0x00000009 2238#define TAG_ECC_PATT3 0x0000001d 2239 2240#define TAG_ECC_INVPATT0 0x0000000f 2241#define TAG_ECC_INVPATT1 0x00000032 2242#define TAG_ECC_INVPATT2 0x00000006 2243#define TAG_ECC_INVPATT3 0x00000012 2244 2245 2246#define TAG_ECC_WRITE_PAT(addr, pattern0, pattern1)\ 2247 dli R_SCRATCH0, L2M_WRITE_TAG; \ 2248 or R_SCRATCH0, addr, R_SCRATCH0; \ 2249 sd pattern0, 0x18(R_SCRATCH0); \ 2250 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \ 2251 sync; \ 2252 sd pattern1, 0x2018(R_SCRATCH0); \ 2253 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \ 2254 sync; \ 2255 daddu R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY; \ 2256 sd pattern0, 0x18(R_SCRATCH0); \ 2257 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \ 2258 sync; \ 2259 sd pattern1, 0x2018(R_SCRATCH0); \ 2260 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0); \ 2261 sync; \ 2262 daddu R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY; \ 2263 sd pattern0, 0x18(R_SCRATCH0); \ 2264 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \ 2265 sync; \ 2266 sd pattern1, 0x2018(R_SCRATCH0); \ 2267 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0); \ 2268 sync; \ 2269 daddu R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY; \ 2270 sd pattern0, 0x18(R_SCRATCH0); \ 2271 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \ 2272 sync; \ 2273 sd pattern1, 0x2018(R_SCRATCH0); \ 2274 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0);\ 2275 sync 2276 2277#define TAG_ECC_CHECK_PAT(addr, pattern0, pattern1)\ 2278 li R_SCRATCH2, 2;\ 2279 dli R_SCRATCH5, XKPHYS_UNC; \ 2280 dli R_SCRATCH3, SCD_BW_BASE; \ 2281 or R_SCRATCH3, R_SCRATCH3, R_SCRATCH5; \ 2282 sd zero, BUS_L2_ERRORS(R_SCRATCH3); \ 2283 sync; \ 2284 dli R_SCRATCH4, L2_BASE; \ 2285 or R_SCRATCH4, R_SCRATCH4, R_SCRATCH5; \ 2286 move R_SCRATCH0, addr; \ 22871: dli R_SCRATCH5, L2_READ_TAG_MASK;\ 2288 ld R_SCRATCH1, (R_SCRATCH0); \ 2289 sync; \ 2290 ld R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \ 2291 and R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \ 2292 sne R_SCRATCH1, R_SCRATCH1, pattern0; \ 2293 or R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1; \ 2294 ld R_SCRATCH1, 0x2000(R_SCRATCH0); \ 2295 sync; \ 2296 ld R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \ 2297 and R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \ 2298 sne R_SCRATCH1, R_SCRATCH1, pattern1; \ 2299 or R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1; \ 2300 daddu R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY;\ 2301 ld R_SCRATCH1, (R_SCRATCH0); \ 2302 sync; \ 2303 ld R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \ 2304 and R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \ 2305 sne R_SCRATCH1, R_SCRATCH1, pattern0; \ 2306 or R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1; \ 2307 ld R_SCRATCH1, 0x2000(R_SCRATCH0); \ 2308 sync; \ 2309 ld R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \ 2310 and R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \ 2311 sne R_SCRATCH1, R_SCRATCH1, pattern1; \ 2312 or R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1; \ 2313 addi R_SCRATCH2, R_SCRATCH2, -1; \ 2314 bne R_SCRATCH2, zero, 1b; \ 2315 daddu R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY;\ 2316 /*TAG_CHECK_PAT(addr, pattern0, pattern1) ;*/ \ 2317 dli R_SCRATCH5, XKPHYS_UNC; \ 2318 dli R_SCRATCH3, SCD_BW_BASE; \ 2319 or R_SCRATCH3, R_SCRATCH3, R_SCRATCH5; \ 2320 ld R_SCRATCH5, BUS_L2_ERRORS(R_SCRATCH3); \ 2321 dsrl R_SCRATCH5, R_SCRATCH5, 16; \ 2322 sne R_SCRATCH5, R_ECC_SCRATCH5, $0; \ 2323 or R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH5 2324 2325l2dtest_tag_ecc: 2326 2327 /*li R_BLOCK, START_BLK*/ 2328 sll R_BLOCK, k0, 1 2329 li R_NEXT_WAY,0x20000 2330tag_ecc_next_block: 2331#ifdef USE_LEDS 2332 addi R_BG_SCRATCH2, R_BG_BLOCK, '0' 2333 or R_BG_SCRATCH2, R_BG_SCRATCH2, ('P' << 8) 2334 SET_LEDS_HI(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1) 2335#endif 2336 2337 move R_PATT_IND, $0 2338 dli R_PAT0_0, TAG_ECC_PATT0 2339 dli R_PAT0_1, TAG_ECC_PATT0 2340 TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2) 2341 TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3) 2342 dli R_PAT1_0, TAG_ECC_INVPATT0 2343 dli R_PAT1_1, TAG_ECC_INVPATT0 2344 TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2) 2345 TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3) 2346 2347tag_ecc_next_pattern: 2348#ifdef USE_LEDS 2349 addi R_BG_SCRATCH2, R_PATT_IND, '0' 2350 or R_BG_SCRATCH2, R_BG_SCRATCH2, ('P' << 8) 2351 SET_LEDS_LO(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1) 2352#endif 2353 2354 dli R_WADDR, XKPHYS_C_COH_EXC /* uncached accelerated */ 2355 dli R_SCRATCH0, L2_RAM_BASE_ADDR /* mgmt mode */ 2356 or R_WADDR,R_ECC_WADDR,R_BG_SCRATCH0 2357 sll R_SCRATCH0, R_BLOCK, L2_BLOCK_ROW_SHIFT /* block number */ 2358 or R_WADDR, R_WADDR, R_SCRATCH0 2359 2360 .set noreorder 2361 move R_LINE, zero 2362tag_ecc_init_next_line: 2363 TAG_ECC_WRITE_PAT(R_WADDR,R_PAT0_0,R_PAT0_1) 2364 li R_SCRATCH0, (32) 2365 dadd R_WADDR, R_WADDR, R_SCRATCH0 /* next line */ 2366 2367 slt R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1 2368 bne R_SCRATCH0, $0, tag_ecc_init_next_line 2369 add R_LINE, R_LINE,1 2370 2371 dli R_RADDR, XKPHYS_C_COH_EXC 2372 dli R_SCRATCH0, L2_RAM_BASE_ADDR 2373 or R_RADDR, R_RADDR, R_SCRATCH0 2374 sll R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT 2375 or R_RADDR, R_RADDR, R_SCRATCH1 2376 li R_NEXT_WAY, 0x20000 2377 2378 move R_LINE,zero 2379tag_ecc_march1: 2380 move R_PASS_FAIL, zero 2381 TAG_ECC_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3) 2382 TAG_ECC_WRITE_PAT(R_WADDR,R_PAT1_0,R_PAT1_1) 2383 TAG_ECC_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3) 2384 SET_ERR_TABLE(R_PASS_FAIL, R_LINE) 2385 daddiu R_RADDR, R_RADDR, 0x20 2386 2387 slt R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1 2388 bne R_SCRATCH0, $0, tag_ecc_march1 2389 add R_LINE, R_LINE,1 2390 2391 /* march2 */ 2392 dli R_RADDR, XKPHYS_C_COH_EXC 2393 dli R_SCRATCH0, L2_RAM_BASE_ADDR 2394 or R_RADDR, R_RADDR, R_SCRATCH0 2395 sll R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT 2396 or R_RADDR, R_RADDR, R_SCRATCH1 2397 2398 move R_LINE,zero 2399tag_ecc_march2: 2400 move R_PASS_FAIL, zero 2401 TAG_ECC_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3) 2402 TAG_ECC_WRITE_PAT(R_WADDR,R_PAT0_0,R_PAT0_1) 2403 TAG_ECC_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3) 2404 SET_ERR_TABLE(R_PASS_FAIL, R_LINE) 2405 daddiu R_RADDR, R_RADDR, 0x20 2406 2407 slt R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1 2408 bne R_SCRATCH0, $0, tag_ecc_march2 2409 add R_LINE, R_LINE,1 2410 2411#if 1 /* zb */ 2412 /* march 3 */ 2413 dli R_RADDR, XKPHYS_C_COH_EXC 2414 dli R_SCRATCH0, L2_RAM_BASE_ADDR 2415 or R_RADDR, R_RADDR, R_SCRATCH0 2416#ifdef TEST_ALL_LINES 2417 sll R_SCRATCH0, R_BLOCK, 1 2418 addi R_SCRATCH0, R_SCRATCH0, 1 2419 sll R_SCRATCH1, R_SCRATCH0, L2_BLOCK_SHIFT 2420#else 2421 sll R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT 2422#endif 2423 or R_RADDR, R_RADDR, R_SCRATCH1 2424#ifdef TEST_ALL_LINES 2425 daddiu R_RADDR, R_RADDR, -32 2426#else 2427 daddiu R_RADDR, R_RADDR, L2_LINES_PER_BLOCK*32-32 2428#endif 2429 li R_LINE,L2_LINES_PER_BLOCK-1 2430tag_ecc_march3: 2431 move R_PASS_FAIL, zero 2432 TAG_ECC_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3) 2433 TAG_ECC_WRITE_PAT(R_WADDR,R_PAT1_0,R_PAT1_1) 2434 TAG_ECC_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3) 2435 SET_ERR_TABLE(R_PASS_FAIL, R_LINE) 2436 daddiu R_RADDR, R_RADDR, -32 2437 2438 bne R_LINE,$0, tag_ecc_march3 2439 add R_LINE,R_LINE,-1 2440 2441 /* march 4 */ 2442 dli R_RADDR, XKPHYS_C_COH_EXC 2443 dli R_SCRATCH0, L2_RAM_BASE_ADDR 2444 or R_RADDR, R_RADDR, R_SCRATCH0 2445#ifdef TEST_ALL_LINES 2446 sll R_SCRATCH0, R_BLOCK, 1 2447 addi R_SCRATCH0, R_SCRATCH0, 1 2448 sll R_SCRATCH1, R_SCRATCH0, L2_BLOCK_SHIFT 2449#else 2450 sll R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT 2451#endif 2452 or R_RADDR, R_RADDR, R_SCRATCH1 2453#ifdef TEST_ALL_LINES 2454 daddiu R_RADDR, R_RADDR, -32 2455#else 2456 daddiu R_RADDR, R_RADDR, L2_LINES_PER_BLOCK*32-32 2457#endif 2458 li R_LINE,L2_LINES_PER_BLOCK-1 2459tag_ecc_march4: 2460 move R_PASS_FAIL, zero 2461 TAG_ECC_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3) 2462 TAG_ECC_WRITE_PAT(R_WADDR,R_PAT0_0,R_PAT0_1) 2463 TAG_ECC_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3) 2464 SET_ERR_TABLE(R_PASS_FAIL, R_LINE) 2465 daddiu R_RADDR, R_RADDR, -32 2466 2467 bne R_LINE,$0, tag_ecc_march4 2468 add R_LINE,R_LINE,-1 2469 2470 addi R_PATT_IND, R_PATT_IND, 1 2471 li R_SCRATCH0, 1 2472 bne R_SCRATCH0, R_PATT_IND, 2f 2473 nop 2474 dli R_PAT0_0, TAG_ECC_INVPATT0 2475 dli R_PAT0_1, TAG_ECC_PATT0 2476 TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2) 2477 TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3) 2478 dli R_PAT1_0, TAG_ECC_PATT0 2479 dli R_PAT1_1, TAG_ECC_INVPATT0 2480 TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2) 2481 TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3) 2482 b tag_ecc_next_pattern 24832: 2484 li R_SCRATCH0, 2 2485 bne R_SCRATCH0, R_PATT_IND, 3f 2486 nop 2487 dli R_PAT0_0, TAG_ECC_PATT1 2488 dli R_PAT0_1, TAG_ECC_PATT1 2489 TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2) 2490 TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3) 2491 dli R_PAT1_0, TAG_ECC_INVPATT1 2492 dli R_PAT1_1, TAG_ECC_INVPATT1 2493 TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2) 2494 TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3) 2495 b tag_ecc_next_pattern 2496 nop 24973: 2498 li R_SCRATCH0, 3 2499 bne R_SCRATCH0, R_PATT_IND, 4f 2500 nop 2501 dli R_PAT0_0, TAG_ECC_PATT2 2502 dli R_PAT0_1, TAG_ECC_PATT2 2503 TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2) 2504 TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3) 2505 dli R_PAT1_0, TAG_ECC_INVPATT2 2506 dli R_PAT1_1, TAG_ECC_INVPATT2 2507 TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2) 2508 TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3) 2509 b tag_ecc_next_pattern 2510 nop 25114: 2512 li R_SCRATCH0, 4 2513 bne R_SCRATCH0, R_PATT_IND, 5f 2514 nop 2515 dli R_PAT0_0, TAG_ECC_PATT3 2516 dli R_PAT0_1, TAG_ECC_PATT3 2517 TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2) 2518 TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3) 2519 dli R_PAT1_0, TAG_ECC_INVPATT3 2520 dli R_PAT1_1, TAG_ECC_INVPATT3 2521 TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2) 2522 TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3) 2523 b tag_ecc_next_pattern 2524 nop 25255: 2526 li R_SCRATCH0, 2 25271: 2528 dli R_SCRATCH1, 2 25292: 2530 daddiu R_SCRATCH1, R_SCRATCH1, -1 2531 bne R_SCRATCH1, $0, 2b 2532 nop 2533 daddiu R_SCRATCH0, R_SCRATCH0, -1 2534 bne R_SCRATCH0, $0, 1b 2535 nop 2536 2537 dli R_RADDR, XKPHYS_C_COH_EXC 2538 dli R_SCRATCH0, L2_RAM_BASE_ADDR 2539 or R_RADDR, R_RADDR, R_SCRATCH0 2540 sll R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT 2541 or R_RADDR, R_RADDR, R_SCRATCH1 2542 li R_NEXT_WAY, 0x20000 2543 2544 move R_LINE,zero 2545tag_ecc_march5: 2546 move R_PASS_FAIL, zero 2547 TAG_ECC_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3) 2548 TAG_ECC_WRITE_PAT(R_WADDR,R_PAT1_0,R_PAT1_1) 2549 SET_ERR_TABLE(R_PASS_FAIL, R_LINE) 2550 daddiu R_RADDR, R_RADDR, 0x20 2551 2552 slt R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1 2553 bne R_SCRATCH0, $0, tag_ecc_march5 2554 add R_LINE, R_LINE,1 2555 2556 li R_SCRATCH0, 2 25571: 2558 dli R_SCRATCH1, 2 25592: 2560 daddiu R_SCRATCH1, R_SCRATCH1, -1 2561 bne R_SCRATCH1, $0, 2b 2562 nop 2563 daddiu R_SCRATCH0, R_SCRATCH0, -1 2564 bne R_SCRATCH0, $0, 1b 2565 nop 2566 2567 dli R_RADDR, XKPHYS_C_COH_EXC 2568 dli R_SCRATCH0, L2_RAM_BASE_ADDR 2569 or R_RADDR, R_RADDR, R_SCRATCH0 2570 sll R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT 2571 or R_RADDR, R_RADDR, R_SCRATCH1 2572 2573 move R_LINE,zero 2574tag_ecc_march6: 2575 move R_PASS_FAIL, zero 2576 TAG_ECC_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3) 2577 SET_ERR_TABLE(R_PASS_FAIL, R_LINE) 2578 daddiu R_RADDR, R_RADDR, 0x20 2579 2580 slt R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1 2581 bne R_SCRATCH0, $0, tag_ecc_march6 2582 add R_LINE, R_LINE,1 2583 2584 /* if error, put test block info into s0 and return */ 2585 or R_BG_SCRATCH0, R_ERR_TABLE_0, R_ERR_TABLE_1 2586 or R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_2 2587 or R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_3 2588 beq R_BG_SCRATCH0, zero, 1f 2589 nop 2590 move s0, R_BG_BLOCK 2591 or s0, s0, 4 << 8 2592 jr ra 2593 nop 25941: 2595 2596 addi R_BLOCK, R_BLOCK, 1 2597 addi R_SCRATCH1, k0, 1 2598 sll R_SCRATCH1, R_SCRATCH1, 1 2599 slt R_SCRATCH0, R_BLOCK, R_SCRATCH1 2600 /*slt R_SCRATCH0, R_BLOCK, START_BLK+TOTAL_BLKS/2*/ 2601 bne R_SCRATCH0,$0, tag_ecc_next_block 2602 nop 2603 2604#endif /* zb */ 2605 2606 .set noreorder 2607 jr ra 2608 nop 2609 2610tag_ecc_err: 2611 li v0, 1 2612 jr ra 2613 nop 2614 2615 2616#endif 2617 2618sb1250_l2cache_init1: 2619#define CACHE_LINE_SIZE 32 2620 2621 # Save the old status register, and set the KX bit. 2622/* 2623 dmfc0 t2,C0_SR 2624 or t1,t2,SR_KX 2625 dmtc0 t1,C0_SR 2626*/ 2627 # Start the index at the base of the cache management 2628 # area, but leave the address bit for "Valid" zero. 2629 # Note that the management tags are at 00_D000_0000, 2630 # which cannot be expressed with the PHYS_TO_K1 macro, 2631 # so well need to use a 64-bit address to get to it. 2632 2633 2634# dli t0,PHYS_TO_XKPHYS_UNC(L2C_MGMT_TAG_BASE) 2635 dli t8,PHYS_TO_XKPHYS_UNC(A_L2C_MGMT_TAG_BASE) 2636 dli t7, START_BLK 26373: dsll t4, t7, 13 2638 dadd t4, t8, t4 2639 2640 # Loop through each entry and each way 2641 2642 /* li t1,L2_LINES_PER_BLOCK*L2C_NUM_WAYS */ 2643 li t5, L2C_NUM_WAYS 2644 2645 # Write a zero to the cache management register at each 2646 # address. 26472: move t0, t4 2648 li t1, L2_LINES_PER_BLOCK 26491: sd zero,(t0) 2650 nop 2651 daddu t0,(CACHE_LINE_SIZE) # size of a cache line 2652 subu t1,1 2653 bne t1,0,1b 2654 nop 2655 2656 dli t6, 0x20000 2657 dadd t4, t4, t6 2658 subu t5, 1 2659 bne t5, 0, 2b 2660 nop 2661 2662 addu t7, t7, 1 2663 slt t0, t7, START_BLK+TOTAL_BLKS 2664 bne t0, zero, 3b 2665 nop 2666 2667 # 2668 # Restore old KX bit setting 2669 # 2670/* 2671 dmtc0 t2,C0_SR 2672*/ 2673 j ra # return to caller 2674 2675 .set noreorder 2676 nop;nop;nop;nop 2677 2678 2679#ifdef RUN_FROM_K0 2680 2681to_kseg0: 2682 li v0, ~K1BASE 2683 and ra, ra, v0 2684 li v0, K0BASE 2685 or ra, ra, v0 2686 jr ra; 2687 nop 2688 2689 2690#endif 2691 2692