1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * DRAM Initialization routine definitions File: sb1250_draminit.h 5 * 6 * This file contains constants and data structures specific to 7 * the operation of sb1250_draminit.c 8 * 9 * Author: Mitch Lichtenberg 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48#ifndef _SB1250_MC_H 49#include "sb1250_mc.h" /* memory controller constants */ 50#endif 51 52#ifndef _JEDEC_H 53#include "jedec.h" /* convenience for board packages */ 54#endif 55 56/* ********************************************************************* 57 * DRAMINFO macros - used to construct the DRAM information 58 * table. There are two flavors, for "C" and assembly. 59 ********************************************************************* */ 60 61 62/* 63 * This macro generates a "decimals and tenths" hex value like those used 64 * in an SPD. 'x' is the decimal portion and 't' is the tenths. It's 65 * sort of like a BCD value except 'x' can contain 0..15 66 * 67 * This macro needs to be used for the tCK parameter. 68 * 69 * For example, to specify 7.5, you could say DRT10(7,5) 70 */ 71 72#define DRT10(x,t) (((x)<<4)|(t)) 73 74/* 75 * This macro generates "decimals and quarters" like those used 76 * in an SPD. The 'q' parameter should be 0, 25, 50, or 75 77 * This macro needs to be used by tRP, tRRD, rRCD, tRFC, adn tRC 78 * 79 * For example, to specify 20.25, you could say DRT4(20,25) 80 */ 81 82#define DRT4(x,q) (((x)<<2)|((q)/25)) 83 84 85 86#ifdef __ASSEMBLER__ 87#define DRAM_GLOBALS(chintlv) \ 88 .byte MCR_GLOBALS,chintlv,0,0,0,0,0,0,0,0,0,0 ; 89#define DRAM_CHAN_CFG(chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg) \ 90 .byte MCR_CHCFG,chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg,0,0,0 ; 91#define DRAM_CHAN_CFG2(chan,tMEMCLK,tROUNDTRIP,dramtype,pagepolicy,blksize,csintlv,ecc,flg) \ 92 .byte MCR_CHCFG,chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg,tROUNDTRIP,0,0 ; 93#define DRAM_CHAN_CLKCFG(addrskew,dqoskew,dqiskew,addrdrive,datadrive,clkdrive) \ 94 .byte MCR_CLKCFG,addrskew,dqoskew,dqiskew,addrdrive,datadrive,clkdrive,0,0,0,0,0 ; 95#define DRAM_CHAN_MANTIMING(tCK,rfsh,tval) \ 96 .byte MCR_MANTIMING,tCK,rfsh,0 ; \ 97 .byte (((tval) >> 56)&0xFF), (((tval) >> 48) & 0xFF) ; \ 98 .byte (((tval) >> 40)&0xFF), (((tval) >> 32) & 0xFF) ; \ 99 .byte (((tval) >> 24)&0xFF), (((tval) >> 16) & 0xFF) ; \ 100 .byte (((tval) >> 8)&0xFF), (((tval) >> 0) & 0xFF) ; 101#define DRAM_CS_TIMING(tCK,rfsh,caslatency,attributes,tRAS,tRP,tRRD,tRCD,tRFC,tRC) \ 102 .byte MCR_TIMING,tCK,rfsh,caslatency,attributes,tRAS,tRP,tRRD,tRCD,tRFC,tRC,0 ; 103#define DRAM_CS_GEOM(csel,rows,cols,banks) \ 104 .byte MCR_GEOM,csel,rows,cols,banks,0,0,0,0,0,0,0 ; 105#define DRAM_CS_SPD(csel,flags,chan,dev) \ 106 .byte MCR_SPD,csel,flags,chan,dev,0,0,0,0,0,0,0 ; 107#define DRAM_EOT \ 108 .byte MCR_EOT,0,0,0,0,0,0,0,0,0,0,0 ; 109#else 110#define DRAM_GLOBALS(chintlv) \ 111 {MCR_GLOBALS,chintlv,0,0,0,0,0,0,0,0,0,0} 112#define DRAM_CHAN_CFG(chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg) \ 113 {MCR_CHCFG,chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg,0,0,0} 114#define DRAM_CHAN_CFG2(chan,tMEMCLK,tROUNDTRIP,dramtype,pagepolicy,blksize,csintlv,ecc,flg) \ 115 {MCR_CHCFG,chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg,tROUNDTRIP,0,0} 116#define DRAM_CHAN_CLKCFG(addrskew,dqoskew,dqiskew,addrdrive,datadrive,clkdrive) \ 117 {MCR_CLKCFG,addrskew,dqoskew,dqiskew,addrdrive,datadrive,clkdrive,0,0,0,0,0} 118#define DRAM_CHAN_MANTIMING(tCK,rfsh,tval) \ 119 {MCR_MANTIMING,tCK,rfsh,0, \ 120 (((tval) >> 56)&0xFF), (((tval) >> 48) & 0xFF), \ 121 (((tval) >> 40)&0xFF), (((tval) >> 32) & 0xFF), \ 122 (((tval) >> 24)&0xFF), (((tval) >> 16) & 0xFF), \ 123 (((tval) >> 8)&0xFF), (((tval) >> 0) & 0xFF) } 124#define DRAM_CS_TIMING(tCK,rfsh,caslatency,attributes,tRAS,tRP,tRRD,tRCD,tRFC,tRC) \ 125 {MCR_TIMING,tCK,rfsh,caslatency,attributes,tRAS,tRP,tRRD,tRCD,tRFC,tRC,0} 126#define DRAM_CS_GEOM(csel,rows,cols,banks) \ 127 {MCR_GEOM,csel,rows,cols,banks,0,0,0,0,0,0,0} 128#define DRAM_CS_SPD(csel,flags,chan,dev) \ 129 {MCR_SPD,csel,flags,chan,dev,0,0,0,0,0,0,0} 130#define DRAM_EOT \ 131 {MCR_EOT,0,0,0,0,0,0,0,0,0,0,0} 132#endif 133 134 135#define MCR_GLOBALS 0 136#define MCR_CHCFG 1 137#define MCR_TIMING 2 138#define MCR_CLKCFG 3 139#define MCR_GEOM 4 140#define MCR_SPD 5 141#define MCR_MANTIMING 6 142#define MCR_EOT 0xFF 143 144#ifndef __ASSEMBLER__ 145typedef struct mc_initrec_s { 146 uint8_t mcr_type; /* record type */ 147 uint8_t mcr_reserved1; /* pad to 12 bytes */ 148 uint8_t mcr_reserved2; /* pad to 12 bytes */ 149 uint8_t mcr_reserved3; /* pad to 12 bytes */ 150 uint8_t mcr_reserved4; /* pad to 12 bytes */ 151 uint8_t mcr_reserved5; /* pad to 12 bytes */ 152 uint8_t mcr_reserved6; /* pad to 12 bytes */ 153 uint8_t mcr_reserved7; /* pad to 12 bytes */ 154 uint8_t mcr_reserved8; /* pad to 12 bytes */ 155 uint8_t mcr_reserved9; /* pad to 12 bytes */ 156 uint8_t mcr_reserved10; /* pad to 12 bytes */ 157 uint8_t mcr_reserved11; /* pad to 12 bytes */ 158} mc_initrec_t; 159 160typedef struct mc_globals_s { 161 uint8_t gbl_type; 162 uint8_t gbl_intlv_ch; /* true to interleave channels */ 163 uint8_t gbl_reserved[10]; /* pad to 12 bytes */ 164} mc_globals_t; 165 166typedef struct mc_mantiming_s { 167 uint8_t mtm_type; 168 uint8_t mtm_tCK; 169 uint8_t mtm_rfsh; 170 uint8_t mtm_reserved; 171 uint8_t mtm_timing[8]; /* one 64-bit word, as bytes */ 172} mc_mantiming_t; 173 174typedef struct mc_cfgdata_s { 175 uint8_t cfg_type; 176 uint8_t cfg_chan; 177 uint8_t cfg_mintmemclk; 178 uint8_t cfg_dramtype; 179 uint8_t cfg_pagepolicy; 180 uint8_t cfg_blksize; 181 uint8_t cfg_intlv_cs; 182 uint8_t cfg_ecc; 183 uint8_t cfg_flags; 184 uint8_t cfg_roundtrip; 185 uint8_t cfg_reserved[2]; 186} mc_cfgdata_t; 187 188typedef struct mc_clkcfg_s { 189 uint8_t clk_type; 190 uint8_t clk_addrskew; 191 uint8_t clk_dqoskew; 192 uint8_t clk_dqiskew; 193 uint8_t clk_addrdrive; 194 uint8_t clk_datadrive; 195 uint8_t clk_clkdrive; 196 uint8_t clk_reserved[5]; 197} mc_clkcfg_t; 198 199typedef struct mc_timingdata_s { 200 uint8_t tmg_type; /* record type */ 201 uint8_t tmg_tCK; /* tCK we should use */ 202 uint8_t tmg_rfsh; /* SPD[12] Refresh Rate */ 203 uint8_t tmg_caslatency; /* SPD[18] CAS Latencies Supported (set only one bit) */ 204 uint8_t tmg_attributes; /* SPD[21] Attributes */ 205 uint8_t tmg_tRAS; /* SPD[30] */ 206 uint8_t tmg_tRP; /* SPD[27] */ 207 uint8_t tmg_tRRD; /* SPD[28] */ 208 uint8_t tmg_tRCD; /* SPD[29] */ 209 uint8_t tmg_tRFC; /* SPD[42] */ 210 uint8_t tmg_tRC; /* SPD[41] */ 211 uint8_t tmg_reserved; /* not used */ 212} mc_timingdata_t; 213 214typedef struct mc_geomdata_s { 215 uint8_t geom_type; /* record type */ 216 uint8_t geom_csel; /* Chip Select number */ 217 uint8_t geom_rows; /* rows */ 218 uint8_t geom_cols; /* columns */ 219 uint8_t geom_banks; /* banks */ 220 uint8_t geom_reserved[7]; /* pad to 12 bytes */ 221} mc_geomdata_t; 222 223typedef struct mc_spddata_s { 224 uint8_t spd_type; /* record type */ 225 uint8_t spd_csel; /* Chip Select number */ 226 uint8_t spd_flags; /* flags */ 227 uint8_t spd_smbuschan; /* SMBus Channel */ 228 uint8_t spd_smbusdev; /* SMBus device */ 229 uint8_t spd_reserved[7]; /* pad to 12 bytes */ 230} mc_spddata_t; 231 232typedef union draminittab_s { 233 mc_initrec_t mcr; /* record with just header */ 234 mc_globals_t gbl; /* global data */ 235 mc_cfgdata_t cfg; /* channel configuration data */ 236 mc_clkcfg_t clk; /* clock configuration */ 237 mc_timingdata_t tmg; /* timing data */ 238 mc_geomdata_t geom; /* geometry data */ 239 mc_spddata_t spd; /* SPD data */ 240 mc_mantiming_t mtm; /* manual timing */ 241 uint8_t raw[12]; /* RAW data */ 242} draminittab_t; 243 244#endif 245 246 247 248/* ********************************************************************* 249 * Configuration parameter values and flag shorthands to improve 250 * readability of the tables. 251 ********************************************************************* */ 252 253 254#define CLOSED K_MC_CS_ATTR_CLOSED 255#define CASCHECK K_MC_CS_ATTR_CASCHECK 256#define HINT K_MC_CS_ATTR_HINT 257#define OPEN K_MC_CS_ATTR_OPEN 258 259#define JEDEC K_MC_DRAM_TYPE_JEDEC 260#define FCRAM K_MC_DRAM_TYPE_FCRAM 261#define SGRAM K_MC_DRAM_TYPE_SGRAM 262#define DRAM_TYPE_SPD 3 263 264#define ECCENABLE 1 /* ECC enable DRAM_CHANCFG */ 265#define ECCDISABLE 0 266 267#define BLKSIZE32 32 /* Block size */ 268#define BLKSIZE64 64 269#define BLKSIZE128 128 270 271#define MCFLG_ECC_ENABLE 1 /* flags for channel configuration */ 272#define MCFLG_BIGMEM 2 273#define MCFLG_FORCEREG 4 274#define MCFLG_DS_REDUCED 0x40 /* output Drive Strength reduced */ 275 276#define MC_CHAN0 0 /* shorthands for readability */ 277#define MC_CHAN1 1 278 279#define MC_NOPORTINTLV 0 /* Used in DRAM_GLOBALS() */ 280#define MC_PORTINTLV 1 281 282#define MC_CS0 0 /* shorthands for readability */ 283#define MC_CS1 1 284#define MC_CS2 2 285#define MC_CS3 3 286 287#define NOCSINTLV 0 /* Chip select interleave values */ 288#define CSINTLV1 1 289#define CSINTLV2 2 290 291/* 292 * End 293 */ 294