1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * MIPS64 CPU definitions File: sbmips.h 5 * 6 * This module contains constants and macros specific to the 7 * SB1 MIPS64 core. 8 * 9 ********************************************************************* 10 * 11 * Copyright 2000,2001,2002,2003,2004 12 * Broadcom Corporation. All rights reserved. 13 * 14 * This software is furnished under license and may be used and 15 * copied only in accordance with the following terms and 16 * conditions. Subject to these conditions, you may download, 17 * copy, install, use, modify and distribute modified or unmodified 18 * copies of this software in source and/or binary form. No title 19 * or ownership is transferred hereby. 20 * 21 * 1) Any source code used, modified or distributed must reproduce 22 * and retain this copyright notice and list of conditions 23 * as they appear in the source file. 24 * 25 * 2) No right is granted to use any trade name, trademark, or 26 * logo of Broadcom Corporation. The "Broadcom Corporation" 27 * name may not be used to endorse or promote products derived 28 * from this software without the prior written permission of 29 * Broadcom Corporation. 30 * 31 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 32 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 33 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 34 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 35 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 36 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 39 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 40 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 41 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 42 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 43 * THE POSSIBILITY OF SUCH DAMAGE. 44 ********************************************************************* */ 45 46#ifndef _SB_MIPS_H 47#define _SB_MIPS_H 48 49/* ********************************************************************* 50 * Configure language 51 ********************************************************************* */ 52 53#if defined(__ASSEMBLER__) 54#define _ATYPE_ 55#define _ATYPE32_ 56#define _ATYPE64_ 57#define _MM_MAKE64(x) (x) 58#define _MM_MAKE32(x) (x) 59#else 60#define _ATYPE_ (__SIZE_TYPE__) 61#define _ATYPE32_ (int) 62#define _ATYPE64_ (long long) 63#define _MM_MAKE64(x) ((uint64_t)(x)) 64#define _MM_MAKE32(x) ((uint32_t)(x)) 65#endif 66 67 68/* ********************************************************************* 69 * Bitfield macros 70 ********************************************************************* */ 71 72/* 73 * Make a mask for 1 bit at position 'n' 74 */ 75 76#define _MM_MAKEMASK1(n) (1 << (n)) 77#define _MM_MAKEMASK1_64(n) (_MM_MAKE64(1) << _MM_MAKE64(n)) 78 79/* 80 * Make a mask for 'v' bits at position 'n' 81 */ 82 83#define _MM_MAKEMASK(v,n) (((1<<(v))-1) << (n)) 84#define _MM_MAKEMASK_64(v,n) (_MM_MAKE64((_MM_MAKE64(1)<<(v))-1) << _MM_MAKE64(n)) 85 86/* 87 * Make a value at 'v' at bit position 'n' 88 */ 89 90#define _MM_MAKEVALUE(v,n) ((v) << (n)) 91#define _MM_MAKEVALUE_64(v,n) (_MM_MAKE64(v) << _MM_MAKE64(n)) 92 93/* 94 * Retrieve a value from 'v' at bit position 'n' with 'm' mask bits 95 */ 96 97#define _MM_GETVALUE(v,n,m) (((v) & (m)) >> (n)) 98#define _MM_GETVALUE_64(v,n,m) ((_MM_MAKE64(v) & _MM_MAKE64(m)) >> _MM_MAKE64(n)) 99 100 101 102/* ********************************************************************* 103 * 32-bit MIPS Address Spaces 104 ********************************************************************* */ 105 106#ifdef __ASSEMBLER__ 107 108#ifdef __mips64 /* If 64-bit GPRs, need to sign extend. */ 109/* XXX: This is a kludge, and will only work as long as all addrs it 110 XXX: is applied to should be sign extended. */ 111#define _ACAST32_ 0xffffffff00000000 | 112#else 113#define _ACAST32_ 114#endif /* __mips64 */ 115#define _ACAST64_ 116 117#else 118 119#define _ACAST32_ _ATYPE_ _ATYPE32_ /* widen if necessary */ 120#define _ACAST64_ _ATYPE64_ /* do _not_ narrow */ 121 122#endif 123 124/* 32-bit address map */ 125#define UBASE 0x00000000 /* user+ mapped */ 126#define USIZE 0x80000000 127#define K0BASE (_ACAST32_ 0x80000000) /* kernel unmapped cached */ 128#define K0SIZE 0x20000000 129#define K1BASE (_ACAST32_ 0xa0000000) /* kernel unmapped uncached */ 130#define K1SIZE 0x20000000 131#define KSBASE (_ACAST32_ 0xc0000000) /* supervisor+ mapped */ 132#define KSSIZE 0x20000000 133#define K3BASE (_ACAST32_ 0xe0000000) /* kernel mapped */ 134#define K3SIZE 0x20000000 135 136/* 64-bit address map additions to the above (sign-extended) ranges */ 137#define XUBASE (_ACAST64_ 0x0000000080000000) /* user+ mapped */ 138#define XUSIZE (_ACAST64_ 0x00000FFF80000000) 139#define XSSEGBASE (_ACAST64_ 0x4000000000000000) /* supervisor+ mapped */ 140#define XSSEGSIZE (_ACAST64_ 0x0000100000000000) 141#define XKPHYSBASE (_ACAST64_ 0x8000000000000000) /* kernel unmapped */ 142#define XKPHYSSIZE (_ACAST64_ 0x0000100000000000) 143#define XKSEGBASE (_ACAST64_ 0xC000000000000000) /* kernel mapped */ 144#define XKSEGSIZE (_ACAST64_ 0x00000FFF80000000) 145 146#define GEN_VECT (_ACAST32_ 0x80000080) 147#define UTLB_VECT (_ACAST32_ 0x80000000) 148 149/* ********************************************************************* 150 * Address space coercion macros 151 ********************************************************************* */ 152 153#define PHYS_TO_K0(pa) (K0BASE | (pa)) 154#define PHYS_TO_K1(pa) (K1BASE | (pa)) 155#define K0_TO_PHYS(va) ((va) & (K0SIZE-1)) 156#define K1_TO_PHYS(va) ((va) & (K1SIZE-1)) 157#define K0_TO_K1(va) ((va) | K1SIZE) 158#define K1_TO_K0(va) ((va) & ~K1SIZE) 159 160#define PHYS_TO_XK1(p) (_ACAST64_ (0xffffffffa0000000 | (p))) 161#define XK1_TO_PHYS(p) ((p) & (K1SIZE-1)) 162#define PHYS_TO_XKPHYS(cca,p) (_SB_MAKEMASK1(63) | (_SB_MAKE64(cca) << 59) | (p)) 163/* XXX: The following two defines' names are TOTALLY BOGUS. XKSEG is 164 something else entirely. */ 165#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) 166#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) 167#define PHYS_TO_XKPHYS_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) 168#define XKPHYS_TO_PHYS(p) ((p) & _SB_MAKEMASK(59,0)) 169 170 171#if !defined(__ASSEMBLER__) 172#define mips_wbflush() __asm__ __volatile__ ("sync" : : : "memory") 173#define ISK0SEG(va) ((va) >= K0BASE && (va) <= (K0BASE + K0SIZE - 1)) 174#define ISK1SEG(va) ((va) >= K1BASE && (va) <= (K1BASE + K1SIZE - 1)) 175#endif 176 177/* ********************************************************************* 178 * Register aliases 179 ********************************************************************* */ 180 181#if defined(__ASSEMBLER__) 182#define zero $0 183#define AT $1 /* assembler temporaries */ 184#define v0 $2 /* value holders */ 185#define v1 $3 186#define a0 $4 /* arguments */ 187#define a1 $5 188#define a2 $6 189#define a3 $7 190#define t0 $8 /* temporaries */ 191#define t1 $9 192#define t2 $10 193#define t3 $11 194#define t4 $12 195#define t5 $13 196#define t6 $14 197#define t7 $15 198#define ta0 $12 199#define ta1 $13 200#define ta2 $14 201#define ta3 $15 202#define s0 $16 /* saved registers */ 203#define s1 $17 204#define s2 $18 205#define s3 $19 206#define s4 $20 207#define s5 $21 208#define s6 $22 209#define s7 $23 210#define t8 $24 /* temporaries */ 211#define t9 $25 212#define k0 $26 /* kernel registers */ 213#define k1 $27 214#define gp $28 /* global pointer */ 215#define sp $29 /* stack pointer */ 216#define s8 $30 /* saved register */ 217#define fp $30 /* frame pointer */ 218#define ra $31 /* return address */ 219#endif 220 221/* ********************************************************************* 222 * CP0 Registers 223 ********************************************************************* */ 224 225#if defined(__ASSEMBLER__) 226#define C0_INX $0 /* CP0: TLB Index */ 227#define C0_RAND $1 /* CP0: TLB Random */ 228#define C0_TLBLO0 $2 /* CP0: TLB EntryLo0 */ 229#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */ 230#define C0_TLBLO1 $3 /* CP0: TLB EntryLo1 */ 231#define C0_CTEXT $4 /* CP0: Context */ 232#define C0_PGMASK $5 /* CP0: TLB PageMask */ 233#define C0_WIRED $6 /* CP0: TLB Wired */ 234#define C0_BADVADDR $8 /* CP0: Bad Virtual Address */ 235#define C0_COUNT $9 /* CP0: Count */ 236#define C0_TLBHI $10 /* CP0: TLB EntryHi */ 237#define C0_COMPARE $11 /* CP0: Compare */ 238#define C0_SR $12 /* CP0: Processor Status */ 239#define C0_CAUSE $13 /* CP0: Exception Cause */ 240#define C0_EPC $14 /* CP0: Exception PC */ 241#define C0_PRID $15 /* CP0: Processor Revision Indentifier */ 242#define C0_CONFIG $16 /* CP0: Config */ 243#define C0_LLADDR $17 /* CP0: LLAddr */ 244#define C0_WATCHLO $18 /* CP0: WatchpointLo */ 245#define C0_WATCHHI $19 /* CP0: WatchpointHi */ 246#define C0_XCTEXT $20 /* CP0: XContext */ 247#define C0_PTR $22 /* CP0: Performance Trace Reg (SB-1) */ 248#define C0_DEBUG $23 /* CP0: debug */ 249#define C0_DEPC $24 /* CP0: depc */ 250#define C0_PERFCONT $25 /* CP0: Performance counters */ 251#define C0_ERRCTL $26 /* CP0: Error control */ 252#define C0_BUSERR_DPA $26,1 /* CP0: Bus error physical address */ 253#define C0_CERR $27 /* CP0: cache error */ 254#define C0_CERR_I $27 /* CP0: cache error */ 255#define C0_CERR_D $27,1 /* CP0: Dcache error */ 256#define C0_CERR_DPA $27,3 /* CP0: Dcache error physical address */ 257#define C0_TAGLO $28 /* CP0: TagLo */ 258#define C0_TAGHI $29 /* CP0: TagHi */ 259#define C0_ERREPC $30 /* CP0: ErrorEPC */ 260#define C0_DESAVE $31 /* CP0: JTAG debug exception 261 save register */ 262 263#else 264 265#define C0_INX 0 /* CP0: TLB Index */ 266#define C0_RAND 1 /* CP0: TLB Random */ 267#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */ 268#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */ 269#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */ 270#define C0_CTEXT 4 /* CP0: Context */ 271#define C0_PGMASK 5 /* CP0: TLB PageMask */ 272#define C0_WIRED 6 /* CP0: TLB Wired */ 273#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */ 274#define C0_COUNT 9 /* CP0: Count */ 275#define C0_TLBHI 10 /* CP0: TLB EntryHi */ 276#define C0_COMPARE 11 /* CP0: Compare */ 277#define C0_SR 12 /* CP0: Processor Status */ 278#define C0_CAUSE 13 /* CP0: Exception Cause */ 279#define C0_EPC 14 /* CP0: Exception PC */ 280#define C0_PRID 15 /* CP0: Processor Revision Indentifier */ 281#define C0_CONFIG 16 /* CP0: Config */ 282#define C0_LLADDR 17 /* CP0: LLAddr */ 283#define C0_WATCHLO 18 /* CP0: WatchpointLo */ 284#define C0_WATCHHI 19 /* CP0: WatchpointHi */ 285#define C0_XCTEXT 20 /* CP0: XContext */ 286#define C0_PTR 22 /* CP0: Performance Trace Reg (SB-1) */ 287#define C0_DEBUG 23 /* CP0: debug */ 288#define C0_DEPC 24 /* CP0: depc */ 289#define C0_PERFCONT 25 /* CP0: Performance counters */ 290#define C0_ERRCTL 26 /* CP0: Error control */ 291#define C0_CERR 27 /* CP0: Icache error */ 292#define C0_TAGLO 28 /* CP0: TagLo */ 293#define C0_TAGHI 29 /* CP0: TagHi */ 294#define C0_ERREPC 30 /* CP0: ErrorEPC */ 295#define C0_DESAVE 31 /* CP0: JTAG debug exception 296 save register */ 297 298#endif 299 300/* Aliases to match MIPS manuals. */ 301#define C0_INDEX C0_INX 302#define C0_RANDOM C0_RAND 303#define C0_ENTRYLO0 C0_TLBLO0 304#define C0_ENTRYLO1 C0_TLBLO1 305#define C0_CONTEXT C0_CTEXT 306#define C0_PAGEMASK C0_PGMASK 307#define C0_ENTRYHI C0_TLBHI 308#define C0_STATUS C0_SR 309#define C0_XCONTEXT C0_XCTEXT 310#define C0_PERFCNT C0_PERFCONT 311#define C0_ERROREPC C0_ERREPC 312 313#ifndef __LANGUAGE_ASSEMBLY 314 315/* Functions to get/set all CP0 registers via inline asms. 316 Note that the functions which access 64-bit CP0 register are 317 only provided if __mips64 is defined (i.e., if compiling with 318 "-mips3", "-mips4", or "-mips64". 319 320 The functions are of the form: 321 cp0_get_<name> 322 cp0_set_<name> 323 where <name> is the register name as it appears in MIPS 324 architecture manuals. 325 326 For example, the functions 327 cp0_get_index 328 cp0_set_index 329 get and set the CP0 Index register. */ 330 331#define _cp0_get_reg(name, num, sel, type, d) \ 332 static inline type \ 333 cp0_get_ ## name (void) \ 334 { \ 335 type val; \ 336 __asm__ __volatile__ (".set push;" \ 337 ".set mips64;" \ 338 d "mfc0 %0, $%1, %2;" \ 339 ".set pop;" \ 340 : "=r"(val) : "i"(num), "i"(sel)); \ 341 return val; \ 342 } 343 344#define _cp0_set_reg(name, num, sel, type, d) \ 345 static inline void \ 346 cp0_set_ ## name (type val) \ 347 { \ 348 __asm__ __volatile__ (".set push;" \ 349 ".set mips64;" \ 350 d "mtc0 %0, $%1, %2;" \ 351 ".set pop;" \ 352 : : "r"(val), "i"(num), "i"(sel)); \ 353 } 354 355/* Get and set 32-bit CP0 registers which are treated as unsigned values. */ 356#define _cp0_get_reg_u32(name, num, sel) \ 357 _cp0_get_reg (name, (num), (sel), unsigned int, "") 358#define _cp0_set_reg_u32(name, num, sel) \ 359 _cp0_set_reg (name, (num), (sel), unsigned int, "") 360 361/* Get and set 32-bit CP0 registers which are treated as signed values 362 so the high bit can be tested easily. */ 363#define _cp0_get_reg_s32(name, num, sel) \ 364 _cp0_get_reg (name, (num), (sel), int, "") 365#define _cp0_set_reg_s32(name, num, sel) \ 366 _cp0_set_reg (name, (num), (sel), int, "") 367 368#if defined(__mips64) 369/* Get and set 64-bit CP0 registers which are treated as unsigned values. 370 Note that these functions are only provided if compiling for with 371 64-bit GPRs. */ 372#define _cp0_get_reg_u64(name, num, sel) \ 373 _cp0_get_reg (name, (num), (sel), unsigned long long, "d") 374#define _cp0_set_reg_u64(name, num, sel) \ 375 _cp0_set_reg (name, (num), (sel), unsigned long long, "d") 376#else 377#define _cp0_get_reg_u64(name, num, sel) 378#define _cp0_set_reg_u64(name, num, sel) 379#endif 380 381/* CP0 register 0: index. */ 382_cp0_get_reg_s32 (index, C0_INDEX, 0) 383_cp0_set_reg_s32 (index, C0_INDEX, 0) 384 385/* CP0 register 1: random. */ 386_cp0_get_reg_u32 (random, C0_RANDOM, 0) 387 388/* CP0 register 2: entrylo0. */ 389_cp0_get_reg_u64 (entrylo0, C0_ENTRYLO0, 0) 390_cp0_set_reg_u64 (entrylo0, C0_ENTRYLO0, 0) 391 392/* CP0 register 3: entrylo1. */ 393_cp0_get_reg_u64 (entrylo1, C0_ENTRYLO1, 0) 394_cp0_set_reg_u64 (entrylo1, C0_ENTRYLO1, 0) 395 396/* CP0 register 4: context. */ 397_cp0_get_reg_u64 (context, C0_CONTEXT, 0) 398_cp0_set_reg_u64 (context, C0_CONTEXT, 0) 399 400/* CP0 register 5: pagemask. */ 401_cp0_get_reg_u32 (pagemask, C0_PAGEMASK, 0) 402_cp0_set_reg_u32 (pagemask, C0_PAGEMASK, 0) 403 404/* CP0 register 6: wired. */ 405_cp0_get_reg_u32 (wired, C0_WIRED, 0) 406_cp0_set_reg_u32 (wired, C0_WIRED, 0) 407 408/* CP0 register 7: reserved. */ 409 410/* CP0 register 8: badvaddr. */ 411_cp0_get_reg_u64 (badvaddr, C0_BADVADDR, 0) 412 413/* CP0 register 9: count. */ 414_cp0_get_reg_u32 (count, C0_COUNT, 0) 415_cp0_set_reg_u32 (count, C0_COUNT, 0) 416 417/* CP0 register 10: entryhi. */ 418_cp0_get_reg_u64 (entryhi, C0_ENTRYHI, 0) 419_cp0_set_reg_u64 (entryhi, C0_ENTRYHI, 0) 420 421/* CP0 register 11: compare. */ 422_cp0_get_reg_u32 (compare, C0_COMPARE, 0) 423_cp0_set_reg_u32 (compare, C0_COMPARE, 0) 424 425/* CP0 register 12: status. */ 426_cp0_get_reg_u32 (status, C0_STATUS, 0) 427_cp0_set_reg_u32 (status, C0_STATUS, 0) 428 429/* CP0 register 13: cause. */ 430_cp0_get_reg_u32 (cause, C0_CAUSE, 0) 431_cp0_set_reg_u32 (cause, C0_CAUSE, 0) 432 433/* CP0 register 14: epc. */ 434_cp0_get_reg_u64 (epc, C0_EPC, 0) 435_cp0_set_reg_u64 (epc, C0_EPC, 0) 436 437/* CP0 register 15: prid. */ 438_cp0_get_reg_u32 (prid, C0_PRID, 0) 439 440/* CP0 register 16: config. */ 441_cp0_get_reg_u32 (config, C0_CONFIG, 0) 442_cp0_set_reg_u32 (config, C0_CONFIG, 0) 443 444/* CP0 register 16 sel 1: config1. */ 445_cp0_get_reg_u32 (config1, C0_CONFIG, 1) 446 447/* CP0 register 16 sel 2: config2. */ 448_cp0_get_reg_u32 (config2, C0_CONFIG, 2) 449 450/* CP0 register 16 sel 3: config3. */ 451_cp0_get_reg_u32 (config3, C0_CONFIG, 3) 452 453/* CP0 register 17: lladdr. */ 454_cp0_get_reg_u64 (lladdr, C0_LLADDR, 0) 455 456/* CP0 register 18: watchlo. */ 457_cp0_get_reg_u64 (watchlo, C0_WATCHLO, 0) 458_cp0_set_reg_u64 (watchlo, C0_WATCHLO, 0) 459 460/* CP0 register 18 sel 1: watchlo1. */ 461_cp0_get_reg_u64 (watchlo1, C0_WATCHLO, 1) 462_cp0_set_reg_u64 (watchlo1, C0_WATCHLO, 1) 463 464/* CP0 register 19: watchhi. */ 465_cp0_get_reg_u32 (watchhi, C0_WATCHHI, 0) 466_cp0_set_reg_u32 (watchhi, C0_WATCHHI, 0) 467 468/* CP0 register 19 sel 1: watchhi1. */ 469_cp0_get_reg_u32 (watchhi1, C0_WATCHHI, 1) 470_cp0_set_reg_u32 (watchhi1, C0_WATCHHI, 1) 471 472/* CP0 register 20: xcontext. */ 473_cp0_get_reg_u64 (xcontext, C0_XCONTEXT, 0) 474_cp0_set_reg_u64 (xcontext, C0_XCONTEXT, 0) 475 476/* CP0 register 21: reserved. */ 477 478/* CP0 register 22: Performance Trace Register (SB-1). */ 479_cp0_get_reg_u64 (ptr, C0_PTR, 0) 480 481/* CP0 register 23: debug. */ 482_cp0_get_reg_u32 (debug, C0_DEBUG, 0) 483_cp0_set_reg_u32 (debug, C0_DEBUG, 0) 484/* CP0 register 23 sel 3: edebug. */ 485_cp0_get_reg_u32 (edebug, C0_DEBUG, 3) 486_cp0_set_reg_u32 (edebug, C0_DEBUG, 3) 487 488/* CP0 register 24: depc. */ 489_cp0_get_reg_u64 (depc, C0_DEPC, 0) 490_cp0_set_reg_u64 (depc, C0_DEPC, 0) 491 492/* CP0 register 25: perfcnt. */ 493_cp0_get_reg_u32 (perfcnt, C0_PERFCNT, 0) 494_cp0_set_reg_u32 (perfcnt, C0_PERFCNT, 0) 495 496/* CP0 register 25 sel 1: perfcnt1. */ 497_cp0_get_reg_u32 (perfcnt1, C0_PERFCNT, 1) 498_cp0_set_reg_u32 (perfcnt1, C0_PERFCNT, 1) 499 500/* CP0 register 25 sel 2: perfcnt2. */ 501_cp0_get_reg_u32 (perfcnt2, C0_PERFCNT, 2) 502_cp0_set_reg_u32 (perfcnt2, C0_PERFCNT, 2) 503 504/* CP0 register 25 sel 3: perfcnt3. */ 505_cp0_get_reg_u32 (perfcnt3, C0_PERFCNT, 3) 506_cp0_set_reg_u32 (perfcnt3, C0_PERFCNT, 3) 507 508/* CP0 register 25 sel 4: perfcnt4. */ 509_cp0_get_reg_u32 (perfcnt4, C0_PERFCNT, 4) 510_cp0_set_reg_u32 (perfcnt4, C0_PERFCNT, 4) 511 512/* CP0 register 25 sel 5: perfcnt5. */ 513_cp0_get_reg_u32 (perfcnt5, C0_PERFCNT, 5) 514_cp0_set_reg_u32 (perfcnt5, C0_PERFCNT, 5) 515 516/* CP0 register 25 sel 6: perfcnt6. */ 517_cp0_get_reg_u32 (perfcnt6, C0_PERFCNT, 6) 518_cp0_set_reg_u32 (perfcnt6, C0_PERFCNT, 6) 519 520/* CP0 register 25 sel 7: perfcnt7. */ 521_cp0_get_reg_u32 (perfcnt7, C0_PERFCNT, 7) 522_cp0_set_reg_u32 (perfcnt7, C0_PERFCNT, 7) 523 524/* CP0 register 26: errctl. */ 525_cp0_get_reg_u32 (errctl, C0_ERRCTL, 0) 526_cp0_get_reg_u32 (buserr_pa, C0_ERRCTL, 1) 527 528/* CP0 register 27: cacheerr_i. */ 529_cp0_get_reg_u32 (cacheerr_i, C0_CERR, 0) 530 531/* CP0 register 27 sel 1: cacheerr_d. */ 532_cp0_get_reg_u32 (cacheerr_d, C0_CERR, 1) 533 534/* CP0 register 27 sel 3: cacheerr_d_pa. */ 535_cp0_get_reg_u32 (cacheerr_d_pa, C0_CERR, 3) 536 537/* CP0 register 28: taglo_i. */ 538_cp0_get_reg_u64 (taglo_i, C0_TAGLO, 0) 539_cp0_set_reg_u64 (taglo_i, C0_TAGLO, 0) 540 541/* CP0 register 28 sel 1: datalo_i. */ 542_cp0_get_reg_u64 (datalo_i, C0_TAGLO, 1) 543 544/* CP0 register 28 sel 2: taglo_d. */ 545_cp0_get_reg_u64 (taglo_d, C0_TAGLO, 2) 546_cp0_set_reg_u64 (taglo_d, C0_TAGLO, 2) 547 548/* CP0 register 28 sel 3: datalo_d. */ 549_cp0_get_reg_u64 (datalo_d, C0_TAGLO, 3) 550 551/* CP0 register 29: taghi_i. */ 552_cp0_get_reg_u64 (taghi_i, C0_TAGHI, 0) 553_cp0_set_reg_u64 (taghi_i, C0_TAGHI, 0) 554 555/* CP0 register 29 sel 1: datahi_i. */ 556_cp0_get_reg_u64 (datahi_i, C0_TAGHI, 1) 557 558/* CP0 register 29 sel 2: taghi_d. */ 559_cp0_get_reg_u64 (taghi_d, C0_TAGHI, 2) 560_cp0_set_reg_u64 (taghi_d, C0_TAGHI, 2) 561 562/* CP0 register 29 sel 3: datahi_d. */ 563_cp0_get_reg_u64 (datahi_d, C0_TAGHI, 3) 564 565/* CP0 register 30: errorepc. */ 566_cp0_get_reg_u64 (errorepc, C0_ERROREPC, 0) 567_cp0_set_reg_u64 (errorepc, C0_ERROREPC, 0) 568 569/* CP0 register 31: desave. */ 570_cp0_get_reg_u64 (desave, C0_DESAVE, 0) 571_cp0_set_reg_u64 (desave, C0_DESAVE, 0) 572 573#endif /* __LANGUAGE_ASSEMBLY */ 574 575/* ********************************************************************* 576 * CP1 (floating point) control registers 577 ********************************************************************* */ 578 579#define FPA_IRR 0 /* CP1: Implementation/Revision */ 580#define FPA_CSR 31 /* CP1: Control/Status */ 581 582/* ********************************************************************* 583 * Macros for generating assembly language routines 584 ********************************************************************* */ 585 586#if defined(__ASSEMBLER__) 587 588/* global leaf function (does not call other functions) */ 589#define LEAF(name) \ 590 .globl name; \ 591 .ent name; \ 592name: 593 594/* global alternate entry to (local or global) leaf function */ 595#define XLEAF(name) \ 596 .globl name; \ 597 .aent name; \ 598name: 599 600/* end of a global function */ 601#define END(name) \ 602 .size name,.-name; \ 603 .end name 604 605/* local leaf function (does not call other functions) */ 606#define SLEAF(name) \ 607 .ent name; \ 608name: 609 610/* local alternate entry to (local or global) leaf function */ 611#define SXLEAF(name) \ 612 .aent name; \ 613name: 614 615/* end of a local function */ 616#define SEND(name) \ 617 END(name) 618 619/* define & export a symbol */ 620#define EXPORT(name) \ 621 .globl name; \ 622name: 623 624/* import a symbol */ 625#define IMPORT(name, size) \ 626 .extern name,size 627 628/* define a zero-fill common block (BSS if not overridden) with a global name */ 629#define COMM(name,size) \ 630 .comm name,size 631 632/* define a zero-fill common block (BSS if not overridden) with a local name */ 633#define LCOMM(name,size) \ 634 .lcomm name,size 635 636#endif 637 638 639/* Floating-Point Control register bits */ 640#define CSR_C 0x00800000 641#define CSR_EXC 0x0003f000 642#define CSR_EE 0x00020000 643#define CSR_EV 0x00010000 644#define CSR_EZ 0x00008000 645#define CSR_EO 0x00004000 646#define CSR_EU 0x00002000 647#define CSR_EI 0x00001000 648#define CSR_TV 0x00000800 649#define CSR_TZ 0x00000400 650#define CSR_TO 0x00000200 651#define CSR_TU 0x00000100 652#define CSR_TI 0x00000080 653#define CSR_SV 0x00000040 654#define CSR_SZ 0x00000020 655#define CSR_SO 0x00000010 656#define CSR_SU 0x00000008 657#define CSR_SI 0x00000004 658#define CSR_RM 0x00000003 659 660/* Status Register */ 661 662#define S_SR_CUMASK 28 /* coprocessor usable bits */ 663#define M_SR_CUMASK _MM_MAKEMASK(4,S_SR_CUMASK) 664#define G_SR_CUMASK(x) _MM_GETVALUE(x,S_SR_CUMASK,M_SR_CUMASK) 665 666#define M_SR_CU3 _MM_MAKEMASK1(31) /* coprocessor 3 usable */ 667#define M_SR_CU2 _MM_MAKEMASK1(30) /* coprocessor 2 usable */ 668#define M_SR_CU1 _MM_MAKEMASK1(29) /* coprocessor 1 usable */ 669#define M_SR_CU0 _MM_MAKEMASK1(28) /* coprocessor 0 usable */ 670 671#define S_SR_RP 27 /* reduced power mode */ 672#define M_SR_RP _MM_MAKEMASK1(27) /* reduced power mode */ 673#define G_SR_RP(x) _MM_GETVALUE(x,S_SR_RP,M_SR_RP) 674 675#define S_SR_FR 26 /* fpu regs any data */ 676#define M_SR_FR _MM_MAKEMASK1(26) /* fpu regs any data */ 677#define G_SR_FR(x) _MM_GETVALUE(x,S_SR_FR,M_SR_FR) 678 679#define S_SR_RE 25 /* reverse endian */ 680#define M_SR_RE _MM_MAKEMASK1(25) /* reverse endian */ 681#define G_SR_RE(x) _MM_GETVALUE(x,S_SR_RE,M_SR_RE) 682 683#define S_SR_MX 24 /* MDMX */ 684#define M_SR_MX _MM_MAKEMASK1(24) /* MDMX */ 685#define G_SR_MX(x) _MM_GETVALUE(x,S_SR_MX,M_SR_MX) 686 687#define S_SR_PX 23 /* 64-bit ops in user mode */ 688#define M_SR_PX _MM_MAKEMASK1(23) /* 64-bit ops in user mode */ 689#define G_SR_PX(x) _MM_GETVALUE(x,S_SR_PX,M_SR_PX) 690 691#define S_SR_BEV 22 /* boot exception vectors */ 692#define M_SR_BEV _MM_MAKEMASK1(22) /* boot exception vectors */ 693#define G_SR_BEV(x) _MM_GETVALUE(x,S_SR_BEV,M_SR_BEV) 694 695#define S_SR_TS 21 /* TLB is shut down */ 696#define M_SR_TS _MM_MAKEMASK1(21) /* TLB is shut down */ 697#define G_SR_TS(x) _MM_GETVALUE(x,S_SR_TS,M_SR_TS) 698 699#define S_SR_SR 20 /* soft reset */ 700#define M_SR_SR _MM_MAKEMASK1(20) /* soft reset */ 701 702#define G_SR_SR(x) _MM_GETVALUE(x,S_SR_SR,M_SR_SR) 703 704#define S_SR_NMI 19 /* nonmaskable interrupt */ 705#define M_SR_NMI _MM_MAKEMASK1(19) /* nonmaskable interrupt */ 706#define G_SR_NMI(x) _MM_GETVALUE(x,S_SR_NMI,M_SR_NMI) 707 708#define S_SR_IMMASK 8 709#define M_SR_IMMASK _MM_MAKEMASK(8,S_SR_IMMASK) 710 711#define M_SR_IM7 _MM_MAKEMASK1(15) /* hardware interrupt masks */ 712#define M_SR_IM6 _MM_MAKEMASK1(14) 713#define M_SR_IM5 _MM_MAKEMASK1(13) 714#define M_SR_IM4 _MM_MAKEMASK1(12) 715#define M_SR_IM3 _MM_MAKEMASK1(11) 716#define M_SR_IM2 _MM_MAKEMASK1(10) 717#define M_SR_IM1 _MM_MAKEMASK1(9) /* software interrupt masks */ 718#define M_SR_IM0 _MM_MAKEMASK1(8) 719 720#define S_SR_IMASK 8 /* all interrupt mask bits */ 721#define M_SR_IMASK _MM_MAKEMASK(8,8) /* all interrupt mask bits */ 722#define G_SR_IMASK(x) _MM_GETVALUE(x,S_SR_IMASK,M_SR_IMASK) 723 724#define S_SR_KX 7 /* 64-bit access for kernel */ 725#define M_SR_KX _MM_MAKEMASK1(7) /* 64-bit access for kernel */ 726#define G_SR_KX(x) _MM_GETVALUE(x,S_SR_KX,M_SR_KX) 727 728#define S_SR_SX 6 /* .. for supervisor */ 729#define M_SR_SX _MM_MAKEMASK1(6) /* .. for supervisor */ 730#define G_SR_SX(x) _MM_GETVALUE(x,S_SR_SX,M_SR_SX) 731 732#define S_SR_UX 5 /* .. for user */ 733#define M_SR_UX _MM_MAKEMASK1(5) /* .. for user */ 734#define G_SR_UX(x) _MM_GETVALUE(x,S_SR_UX,M_SR_UX) 735 736#define S_SR_KSU 3 /* base operating mode mode */ 737#define M_SR_KSU _MM_MAKEMASK(2,S_SR_KSU) 738#define V_SR_KSU(x) _MM_MAKEVALUE(x,S_SR_KSU) 739#define G_SR_KSU(x) _MM_GETVALUE(x,S_SR_KSU,M_SR_KSU) 740#define K_SR_KSU_KERNEL 0 741#define K_SR_KSU_SUPR 1 742#define K_SR_KSU_USER 2 743 744#define M_SR_UM _MM_MAKEMASK1(4) 745 746#define S_SR_ERL 2 747#define M_SR_ERL _MM_MAKEMASK1(2) 748#define G_SR_ERL(x) _MM_GETVALUE(x,S_SR_ERL,M_SR_ERL) 749 750#define S_SR_EXL 1 751#define M_SR_EXL _MM_MAKEMASK1(1) 752#define G_SR_EXL(x) _MM_GETVALUE(x,S_SR_EXL,M_SR_EXL) 753 754#define S_SR_IE 0 755#define M_SR_IE _MM_MAKEMASK1(0) 756#define G_SR_IE(x) _MM_GETVALUE(x,S_SR_IE,M_SR_IE) 757 758/* 759 * Cause Register 760 */ 761#define M_CAUSE_BD _MM_MAKEMASK1(31) /* exception in BD slot */ 762 763#define S_CAUSE_CE 28 /* coprocessor error */ 764#define M_CAUSE_CE _MM_MAKEMASK(2,S_CAUSE_CE) 765#define V_CAUSE_CE(x) _MM_MAKEVALUE(x,S_CAUSE_CE) 766#define G_CAUSE_CE(x) _MM_GETVALUE(x,S_CAUSE_CE,M_CAUSE_CE) 767 768#define M_CAUSE_IV _MM_MAKEMASK1(23) /* special interrupt */ 769#define M_CAUSE_WP _MM_MAKEMASK1(22) /* watch interrupt deferred */ 770 771#define S_CAUSE_IPMASK 8 772#define M_CAUSE_IPMASK _MM_MAKEMASK(8,S_CAUSE_IPMASK) 773/* Note: CAUSE interrupt bits were named IP8..IP3 and SW2..SW1 */ 774#define M_CAUSE_IP7 _MM_MAKEMASK1(15) /* hardware interrupts */ 775#define M_CAUSE_IP6 _MM_MAKEMASK1(14) 776#define M_CAUSE_IP5 _MM_MAKEMASK1(13) 777#define M_CAUSE_IP4 _MM_MAKEMASK1(12) 778#define M_CAUSE_IP3 _MM_MAKEMASK1(11) 779#define M_CAUSE_IP2 _MM_MAKEMASK1(10) 780#define M_CAUSE_SW1 _MM_MAKEMASK1(9) /* software interrupts */ 781#define M_CAUSE_SW0 _MM_MAKEMASK1(8) 782 783#define S_CAUSE_EXC 2 784#define M_CAUSE_EXC _MM_MAKEMASK(5,S_CAUSE_EXC) 785#define V_CAUSE_EXC(x) _MM_MAKEVALUE(x,S_CAUSE_EXC) 786#define G_CAUSE_EXC(x) _MM_GETVALUE(x,S_CAUSE_EXC,M_CAUSE_EXC) 787 788/* Exception Code */ 789#define K_CAUSE_EXC_INT 0 /* External interrupt */ 790#define K_CAUSE_EXC_MOD 1 /* TLB modification */ 791#define K_CAUSE_EXC_TLBL 2 /* TLB miss (Load or Ifetch) */ 792#define K_CAUSE_EXC_TLBS 3 /* TLB miss (Save) */ 793#define K_CAUSE_EXC_ADEL 4 /* Address error (Load or Ifetch) */ 794#define K_CAUSE_EXC_ADES 5 /* Address error (Save) */ 795#define K_CAUSE_EXC_IBE 6 /* Bus error (Ifetch) */ 796#define K_CAUSE_EXC_DBE 7 /* Bus error (data load or store) */ 797#define K_CAUSE_EXC_SYS 8 /* System call */ 798#define K_CAUSE_EXC_BP 9 /* Break point */ 799#define K_CAUSE_EXC_RI 10 /* Reserved instruction */ 800#define K_CAUSE_EXC_CPU 11 /* Coprocessor unusable */ 801#define K_CAUSE_EXC_OVF 12 /* Arithmetic overflow */ 802#define K_CAUSE_EXC_TRAP 13 /* Trap exception */ 803#define K_CAUSE_EXC_VCEI 14 /* Virtual Coherency Exception (I) */ 804#define K_CAUSE_EXC_FPE 15 /* Floating Point Exception */ 805#define K_CAUSE_EXC_CP2 16 /* Cp2 Exception */ 806#define K_CAUSE_EXC_WATCH 23 /* Watchpoint exception */ 807#define K_CAUSE_EXC_VCED 31 /* Virtual Coherency Exception (D) */ 808 809#define K_NTLBENTRIES 64 810 811#define HI_HALF(x) ((x) >> 16) 812#define LO_HALF(x) ((x) & 0xffff) 813 814/* FPU stuff */ 815 816#if defined(__ASSEMBLER__) 817#define C1_CSR $31 818#define C1_FRID $0 819#else 820#define C1_CSR 31 821#define C1_FRID 0 822#endif 823 824#define S_FCSR_CAUSE 12 825#define M_FCSR_CAUSE _MM_MAKEMASK(5,S_FCSR_CAUSE) 826#define V_FCSR_CAUSE(x) _MM_MAKEVALUE(x,S_FCSR_CAUSE) 827#define G_FCSR_CAUSE(x) _MM_GETVALUE(x,S_FCSR_CAUSE,M_FCSR_CAUSE) 828 829#define S_FCSR_ENABLES 7 830#define M_FCSR_ENABLES _MM_MAKEMASK(5,S_FCSR_ENABLES) 831#define V_FCSR_ENABLES(x) _MM_MAKEVALUE(x,S_FCSR_ENABLES) 832#define G_FCSR_ENABLES(x) _MM_GETVALUE(x,S_FCSR_ENABLES,M_FCSR_ENABLES) 833 834#define S_FCSR_FLAGS 2 835#define M_FCSR_FLAGS _MM_MAKEMASK(5,S_FCSR_FLAGS) 836#define V_FCSR_FLAGS(x) _MM_MAKEVALUE(x,S_FCSR_FLAGS) 837#define G_FCSR_FLAGS(x) _MM_GETVALUE(x,S_FCSR_FLAGS,M_FCSR_FLAGS) 838 839 840/* 841 * MIPS64 Config Register (select 0) 842 */ 843#define S_CFG_CFG1 31 /* Config1 */ 844#define M_CFG_CFG1 _MM_MAKEMASK1(31) /* config1 select1 is impl */ 845#define G_CFG_CFG1(x) _MM_GETVALUE(x,S_CFG_CFG1,M_CFG_CFG1) 846 847#define S_CFG_MK1 21 /* Map KSEG1, SB-1 rev3+ */ 848#define M_CFG_MK1 _MM_MAKEMASK1(S_CFG_MK1) 849#define V_CFG_MK1(x) _MM_MAKEVALUE(x,S_CFG_MK1) 850#define G_CFG_MK1(x) _MM_GETVALUE(x,S_CFG_MK1,M_CFG_MK1) 851 852#define S_CFG_MK0 20 /* Map KSEG0, SB-1 rev3+ */ 853#define M_CFG_MK0 _MM_MAKEMASK1(S_CFG_MK0) 854#define V_CFG_MK0(x) _MM_MAKEVALUE(x,S_CFG_MK0) 855#define G_CFG_MK0(x) _MM_GETVALUE(x,S_CFG_MK0,M_CFG_MK0) 856 857#define S_CFG_MPV 16 /* Multi proc. vector offset */ 858#define M_CFG_MPV _MM_MAKEMASK(4,S_CFG_MPV) 859#define V_CFG_MPV(x) _MM_MAKEVALUE(x,S_CFG_MPV) 860#define G_CFG_MPV(x) _MM_GETVALUE(x,S_CFG_MPV,M_CFG_MPV) 861 862#define S_CFG_BE 15 /* Endian mode */ 863#define M_CFG_BE _MM_MAKEMASK1(15) /* big-endian mode */ 864#define G_CFG_BE(x) _MM_GETVALUE(x,S_CFG_BE,M_CFG_BE) 865 866#define S_CFG_AT 13 /* Architecture Type */ 867#define M_CFG_AT _MM_MAKEMASK(2,S_CFG_AT) 868#define V_CFG_AT(x) _MM_MAKEVALUE(x,S_CFG_AT) 869#define G_CFG_AT(x) _MM_GETVALUE(x,S_CFG_AT,M_CFG_AT) 870#define K_CFG_AT_MIPS32 0 871#define K_CFG_AT_MIPS64_32 1 872#define K_CFG_AT_MIPS64 2 873 874#define S_CFG_AR 10 /* Architecture Revision */ 875#define M_CFG_AR _MM_MAKEMASK(3,S_CFG_AR) 876#define V_CFG_AR(x) _MM_MAKEVALUE(x,S_CFG_AR) 877#define G_CFG_AR(x) _MM_GETVALUE(x,S_CFG_AR,M_CFG_AR) 878#define K_CFG_AR_REV1 0 879 880#define S_CFG_MMU 7 /* MMU Type */ 881#define M_CFG_MMU _MM_MAKEMASK(3,S_CFG_MMU) 882#define V_CFG_MMU(x) _MM_MAKEVALUE(x,S_CFG_MMU) 883#define G_CFG_MMU(x) _MM_GETVALUE(x,S_CFG_MMU,M_CFG_MMU) 884#define K_CFG_MMU_NONE 0 885#define K_CFG_MMU_TLB 1 886#define K_CFG_MMU_BAT 2 887#define K_CFG_MMU_FIXED 3 888 889#define S_CFG_K0COH 0 /* K0seg coherency */ 890#define M_CFG_K0COH _MM_MAKEMASK(3,S_CFG_K0COH) 891#define V_CFG_K0COH(x) _MM_MAKEVALUE(x,S_CFG_K0COH) 892#define G_CFG_K0COH(x) _MM_GETVALUE(x,S_CFG_K0COH,M_CFG_K0COH) 893#define K_CFG_K0COH_UNCACHED 2 894#define K_CFG_K0COH_CACHEABLE 3 895#define K_CFG_K0COH_COHERENT 5 896 897/* 898 * MIPS64 Config Register (select 1) 899 */ 900 901#define M_CFG_CFG2 _MM_MAKEMASK1(31) /* config2 select2 is impl */ 902 903#define S_CFG_MMUSIZE 25 904#define M_CFG_MMUSIZE _MM_MAKEMASK(6,S_CFG_MMUSIZE) 905#define G_CFG_MMUSIZE(x) _MM_GETVALUE(x,S_CFG_MMUSIZE,M_CFG_MMUSIZE) 906 907#define S_CFG_IS 22 908#define M_CFG_IS _MM_MAKEMASK(3,S_CFG_IS) 909#define V_CFG_IS(x) _MM_MAKEVALUE(x,S_CFG_IS) 910#define G_CFG_IS(x) _MM_GETVALUE(x,S_CFG_IS,M_CFG_IS) 911 912#define S_CFG_IL 19 913#define M_CFG_IL _MM_MAKEMASK(3,S_CFG_IL) 914#define V_CFG_IL(x) _MM_MAKEVALUE(x,S_CFG_IL) 915#define G_CFG_IL(x) _MM_GETVALUE(x,S_CFG_IL,M_CFG_IL) 916 917#define S_CFG_IA 16 918#define M_CFG_IA _MM_MAKEMASK(3,S_CFG_IA) 919#define V_CFG_IA(x) _MM_MAKEVALUE(x,S_CFG_IA) 920#define G_CFG_IA(x) _MM_GETVALUE(x,S_CFG_IA,M_CFG_IA) 921 922#define S_CFG_DS 13 923#define M_CFG_DS _MM_MAKEMASK(3,S_CFG_DS) 924#define V_CFG_DS(x) _MM_MAKEVALUE(x,S_CFG_DS) 925#define G_CFG_DS(x) _MM_GETVALUE(x,S_CFG_DS,M_CFG_DS) 926 927#define S_CFG_DL 10 928#define M_CFG_DL _MM_MAKEMASK(3,S_CFG_DL) 929#define V_CFG_DL(x) _MM_MAKEVALUE(x,S_CFG_DL) 930#define G_CFG_DL(x) _MM_GETVALUE(x,S_CFG_DL,M_CFG_DL) 931 932#define S_CFG_DA 7 933#define M_CFG_DA _MM_MAKEMASK(3,S_CFG_DA) 934#define V_CFG_DA(x) _MM_MAKEVALUE(x,S_CFG_DA) 935#define G_CFG_DA(x) _MM_GETVALUE(x,S_CFG_DA,M_CFG_DA) 936 937#define S_CFG_PC 4 /* perf ctrs present */ 938#define M_CFG_PC _MM_MAKEMASK1(4) /* perf ctrs present */ 939#define G_CFG_PC(x) _MM_GETVALUE(x,S_CFG_PC,M_CFG_PC) 940 941#define S_CFG_WR 3 /* watch regs present */ 942#define M_CFG_WR _MM_MAKEMASK1(3) /* watch regs present */ 943#define G_CFG_WR(x) _MM_GETVALUE(x,S_CFG_WR,M_CFG_WR) 944 945#define S_CFG_CA 2 /* MIPS16 present */ 946#define M_CFG_CA _MM_MAKEMASK1(2) /* MIPS16 present */ 947#define G_CFG_CA(x) _MM_GETVALUE(x,S_CFG_CA,M_CFG_CA) 948 949#define S_CFG_EP 1 /* EJTAG present */ 950#define M_CFG_EP _MM_MAKEMASK1(1) /* EJTAG present */ 951#define G_CFG_EP(x) _MM_GETVALUE(x,S_CFG_EP,M_CFG_EP) 952 953#define S_CFG_FP 0 /* FPU present */ 954#define M_CFG_FP _MM_MAKEMASK1(0) /* FPU present */ 955#define G_CFG_FP(x) _MM_GETVALUE(x,S_CFG_FP,M_CFG_FP) 956 957 958 959/* 960 * Primary Cache TagLo 961 */ 962 963#define S_TAGLO_PTAG 8 964#define M_TAGLO_PTAG _MM_MAKEMASK(56,S_TAGLO_PTAG) 965 966#define S_TAGLO_PSTATE 6 967#define M_TAGLO_PSTATE _MM_MAKEMASK(2,S_TAGLO_PSTATE) 968#define V_TAGLO_PSTATE(x) _MM_MAKEVALUE(x,S_TAGLO_PSTATE) 969#define G_TAGLO_PSTATE(x) _MM_GETVALUE(x,S_TAGLO_PSTATE,M_TAGLO_PSTATE) 970#define K_TAGLO_PSTATE_INVAL 0 971#define K_TAGLO_PSTATE_SHARED 1 972#define K_TAGLO_PSTATE_CLEAN_EXCL 2 973#define K_TAGLO_PSTATE_DIRTY_EXCL 3 974 975#define M_TAGLO_LOCK _MM_MAKEMASK1(5) 976#define M_TAGLO_PARITY _MM_MAKEMASK1(0) 977 978 979/* 980 * CP0 ErrCtl register 981 */ 982#define M_ERRCTL_RECOVERABLE _MM_MAKEMASK1(31) 983#define M_ERRCTL_DCACHE _MM_MAKEMASK1(30) 984#define M_ERRCTL_ICACHE _MM_MAKEMASK1(29) 985#define M_ERRCTL_MULTIBUS _MM_MAKEMASK1(23) 986#define M_ERRCTL_MC_TLB _MM_MAKEMASK1(15) 987#define M_ERRCTL_MC_TIMEOUT _MM_MAKEMASK1(14) 988 989/* 990 * CP0 CacheErr-I register 991 */ 992#define M_CERRI_TAG_PARITY _MM_MAKEMASK1(29) 993#define M_CERRI_DATA_PARITY _MM_MAKEMASK1(28) 994#define M_CERRI_EXTERNAL _MM_MAKEMASK1(26) 995 996/* 997 * CP0 CacheErr-D register 998 */ 999#define M_CERRD_MULTIPLE _MM_MAKEMASK1(31) 1000#define M_CERRD_TAG_STATE _MM_MAKEMASK1(30) 1001#define M_CERRD_TAG_ADDRESS _MM_MAKEMASK1(29) 1002#define M_CERRD_DATA_SBE _MM_MAKEMASK1(28) 1003#define M_CERRD_DATA_DBE _MM_MAKEMASK1(27) 1004#define M_CERRD_EXTERNAL _MM_MAKEMASK1(26) 1005#define M_CERRD_LOAD _MM_MAKEMASK1(25) 1006#define M_CERRD_STORE _MM_MAKEMASK1(24) 1007#define M_CERRD_FILLWB _MM_MAKEMASK1(23) 1008#define M_CERRD_COHERENCY _MM_MAKEMASK1(22) 1009#define M_CERRD_DUPTAG _MM_MAKEMASK1(21) 1010 1011 1012/* 1013 * Primary Cache operations 1014 */ 1015#define Index_Invalidate_I 0x0 /* 0 0 */ 1016#define Index_Writeback_Inv_D 0x1 /* 0 1 */ 1017#define Index_Invalidate_SI 0x2 /* 0 2 */ 1018#define Index_Writeback_Inv_SD 0x3 /* 0 3 */ 1019#define Index_Load_Tag_I 0x4 /* 1 0 */ 1020#define Index_Load_Tag_D 0x5 /* 1 1 */ 1021#define Index_Load_Tag_SI 0x6 /* 1 2 */ 1022#define Index_Load_Tag_SD 0x7 /* 1 3 */ 1023#define Index_Store_Tag_I 0x8 /* 2 0 */ 1024#define Index_Store_Tag_D 0x9 /* 2 1 */ 1025#define Index_Store_Tag_SI 0xA /* 2 2 */ 1026#define Index_Store_Tag_SD 0xB /* 2 3 */ 1027#define Create_Dirty_Exc_D 0xD /* 3 1 */ 1028#define Create_Dirty_Exc_SD 0xF /* 3 3 */ 1029#define Hit_Invalidate_I 0x10 /* 4 0 */ 1030#define Hit_Invalidate_D 0x11 /* 4 1 */ 1031#define Hit_Invalidate_SI 0x12 /* 4 2 */ 1032#define Hit_Invalidate_SD 0x13 /* 4 3 */ 1033#define Fill_I 0x14 /* 5 0 */ 1034#define Hit_Writeback_Inv_D 0x15 /* 5 1 */ 1035#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */ 1036#define Hit_Writeback_I 0x18 /* 6 0 */ 1037#define Hit_Writeback_D 0x19 /* 6 1 */ 1038#define Hit_Writeback_SD 0x1B /* 6 3 */ 1039#define Hit_Set_Virtual_SI 0x1E /* 7 2 */ 1040#define Hit_Set_Virtual_SD 0x1F /* 7 3 */ 1041 1042/* Watchpoint Register */ 1043#define M_WATCH_PA 0xfffffff8 1044#define M_WATCH_R 0x00000002 1045#define M_WATCH_W 0x00000001 1046 1047 1048/* TLB entries */ 1049#define S_TLBHI_ASID 0 1050#define M_TLBHI_ASID _MM_MAKEMASK_64(8,S_TLBHI_ASID) 1051#define V_TLBHI_ASID(x) _MM_MAKEVALUE_64(x,S_TLBHI_ASID) 1052#define G_TLBHI_ASID(x) _MM_GETVALUE_64(x,S_TLBHI_ASID,M_TLBHI_ASID) 1053 1054/* SEGBITS = 44 on sb1 */ 1055#define S_TLBHI_VPN2 13 1056#define M_TLBHI_VPN2 _MM_MAKEMASK_64(31,S_TLBHI_VPN2) 1057#define V_TLBHI_VPN2(x) _MM_MAKEVALUE_64(x,S_TLBHI_VPN2) 1058#define G_TLBHI_VPN2(x) _MM_GETVALUE_64(x,S_TLBHI_VPN2,M_TLBHI_VPN2) 1059 1060#define S_TLBLO_G 0 1061#define M_TLBLO_G _MM_MAKEMASK1_64(S_TLBLO_G) 1062#define V_TLBLO_G(x) _MM_MAKEVALUE_64(x,S_TLBLO_G) 1063#define G_TLBLO_G(x) _MM_GETVALUE_64(x,S_TLBLO_G,M_TLBLO_G) 1064 1065#define S_TLBLO_V 1 1066#define M_TLBLO_V _MM_MAKEMASK1_64(S_TLBLO_V) 1067#define V_TLBLO_V(x) _MM_MAKEVALUE_64(x,S_TLBLO_V) 1068#define G_TLBLO_V(x) _MM_GETVALUE_64(x,S_TLBLO_V,M_TLBLO_V) 1069 1070#define S_TLBLO_D 2 1071#define M_TLBLO_D _MM_MAKEMASK1_64(S_TLBLO_D) 1072#define V_TLBLO_D(x) _MM_MAKEVALUE_64(x,S_TLBLO_D) 1073#define G_TLBLO_D(x) _MM_GETVALUE_64(x,S_TLBLO_D,M_TLBLO_D) 1074 1075#define S_TLBLO_CALG 3 1076#define M_TLBLO_CALG _MM_MAKEMASK_64(3,S_TLBLO_CALG) 1077#define V_TLBLO_CALG(x) _MM_MAKEVALUE_64(x,S_TLBLO_CALG) 1078#define G_TLBLO_CALG(x) _MM_GETVALUE_64(x,S_TLBLO_CALG,M_TLBLO_CALG) 1079 1080/* PABITS = 40 on sb1 */ 1081#define S_TLBLO_PFNMASK 6 1082#define M_TLBLO_PFNMASK _MM_MAKEMASK_64(28,S_TLBLO_PFNMASK) 1083#define V_TLBLO_PFNMASK(x) _MM_MAKEVALUE_64(x,S_TLBLO_PFNMASK) 1084#define G_TLBLO_PFNMASK(x) _MM_GETVALUE_64(x,S_TLBLO_PFNMASK,M_TLBLO_PFNMASK) 1085 1086/* support 4KB - 64MB for pass2 and beyond (14bits) */ 1087#define S_TLB_PGMSK 13 1088#define M_TLB_PGMSK _MM_MAKEMASK(14,S_TLB_PGMSK) 1089#define V_TLB_PGMSK(x) _MM_MAKEVALUE(x,S_TLB_PGMSK) 1090#define G_TLB_PGMSK(x) _MM_GETVALUE(x,S_TLB_PGMSK,M_TLB_PGMSK) 1091 1092#define K_CALG_COH_EXCL1_NOL2 0 1093#define K_CALG_COH_SHRL1_NOL2 1 1094#define K_CALG_UNCACHED 2 1095#define K_CALG_NONCOHERENT 3 1096#define K_CALG_COH_EXCL 4 1097#define K_CALG_COH_SHAREABLE 5 1098#define K_CALG_NOTUSED 6 1099#define K_CALG_UNCACHED_ACCEL 7 1100 1101 1102 1103#endif /* _SB_MIPS_H */ 1104 1105 1106