1/*
2 * BK Id: SCCS/s.uninorth.h 1.13 10/23/01 08:09:35 trini
3 */
4/*
5 * uninorth.h: definitions for using the "UniNorth" host bridge chip
6 *             from Apple. This chip is used on "Core99" machines
7 *
8 */
9#ifdef __KERNEL__
10#ifndef __ASM_UNINORTH_H__
11#define __ASM_UNINORTH_H__
12
13/*
14 * Uni-N config space reg. definitions
15 *
16 * (Little endian)
17 */
18
19/* Address ranges selection. This one should work with Bandit too */
20#define UNI_N_ADDR_SELECT		0x48
21#define UNI_N_ADDR_COARSE_MASK		0xffff0000	/* 256Mb regions at *0000000 */
22#define UNI_N_ADDR_FINE_MASK		0x0000ffff	/*  16Mb regions at f*000000 */
23
24/* AGP registers */
25#define UNI_N_CFG_GART_BASE		0x8c
26#define UNI_N_CFG_AGP_BASE		0x90
27#define UNI_N_CFG_GART_CTRL		0x94
28#define UNI_N_CFG_INTERNAL_STATUS	0x98
29
30/* UNI_N_CFG_GART_CTRL bits definitions */
31#define UNI_N_CFG_GART_INVAL		0x00000001
32#define UNI_N_CFG_GART_ENABLE		0x00000100
33#define UNI_N_CFG_GART_2xRESET		0x00010000
34
35/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
36 * revision 1.5 (x4 AGP) may need further changes.
37 *
38 * AGP_BASE register contains the base address of the AGP aperture on
39 * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x,
40 * even if decoding of this address range is enabled in the address select
41 * register. Apparently, the only supported bases are 256Mb multiples
42 * (high 4 bits of that register).
43 *
44 * GART_BASE register appear to contain the physical address of the GART
45 * in system memory in the high address bits (page aligned), and the
46 * GART size in the low order bits (number of GART pages)
47 *
48 * The GART format itself is one 32bits word per physical memory page.
49 * This word contains, in little-endian format (!!!), the physical address
50 * of the page in the high bits, and what appears to be an "enable" bit
51 * in the LSB bit (0) that must be set to 1 when the entry is valid.
52 *
53 * Obviously, the GART is not cache coherent and so any change to it
54 * must be flushed to memory (or maybe just make the GART space non
55 * cachable). AGP memory itself doens't seem to be cache coherent neither.
56 *
57 * In order to invalidate the GART (which is probably necessary to inval
58 * the bridge internal TLBs), the following sequence has to be written,
59 * in order, to the GART_CTRL register:
60 *
61 *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
62 *   UNI_N_CFG_GART_ENABLE
63 *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET
64 *   UNI_N_CFG_GART_ENABLE
65 *
66 * As far as AGP "features" are concerned, it looks like fast write may
67 * not be supported but this has to be confirmed.
68 *
69 * Turning on AGP seem to require a double invalidate operation, one before
70 * setting the AGP command register, on after.
71 *
72 * Turning off AGP seems to require the following sequence: first wait
73 * for the AGP to be idle by reading the internal status register, then
74 * write in that order to the GART_CTRL register:
75 *
76 *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
77 *   0
78 *   UNI_N_CFG_GART_2xRESET
79 *   0
80 */
81
82/*
83 * Uni-N memory mapped reg. definitions
84 *
85 * Those registers are Big-Endian !!
86 *
87 * Their meaning come from either Darwin and/or from experiments I made with
88 * the bootrom, I'm not sure about their exact meaning yet
89 *
90 */
91
92/* Version of the UniNorth chip */
93#define UNI_N_VERSION			0x0000		/* Known versions: 3,7 and 8 */
94
95/* This register is used to enable/disable various clocks */
96#define UNI_N_CLOCK_CNTL		0x0020
97#define UNI_N_CLOCK_CNTL_PCI		0x00000001	/* PCI2 clock control */
98#define UNI_N_CLOCK_CNTL_GMAC		0x00000002	/* GMAC clock control */
99#define UNI_N_CLOCK_CNTL_FW		0x00000004	/* FireWire clock control */
100
101/* Power Management control */
102#define UNI_N_POWER_MGT			0x0030
103#define UNI_N_POWER_MGT_NORMAL		0x00
104#define UNI_N_POWER_MGT_IDLE2		0x01
105#define UNI_N_POWER_MGT_SLEEP		0x02
106
107/* This register is configured by Darwin depending on the UniN
108 * revision
109 */
110#define UNI_N_ARB_CTRL			0x0040
111#define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT	15
112#define UNI_N_ARB_CTRL_QACK_DELAY_MASK	0x0e1f8000
113#define UNI_N_ARB_CTRL_QACK_DELAY	0x30
114#define UNI_N_ARB_CTRL_QACK_DELAY105	0x00
115
116/* This one _might_ return the CPU number of the CPU reading it;
117 * the bootROM decides wether to boot or to sleep/spinloop depending
118 * on this register beeing 0 or not
119 */
120#define UNI_N_CPU_NUMBER		0x0050
121
122/* This register appear to be read by the bootROM to decide what
123 *  to do on a non-recoverable reset (powerup or wakeup)
124 */
125#define UNI_N_HWINIT_STATE		0x0070
126#define UNI_N_HWINIT_STATE_SLEEPING	0x01
127#define UNI_N_HWINIT_STATE_RUNNING	0x02
128/* This last bit appear to be used by the bootROM to know the second
129 * CPU has started and will enter it's sleep loop with IP=0
130 */
131#define UNI_N_HWINIT_STATE_CPU1_FLAG	0x10000000
132
133/* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
134
135#endif /* __ASM_UNINORTH_H__ */
136#endif /* __KERNEL__ */
137