1/* 2 * Copyright 2000 MontaVista Software Inc. 3 * Author: MontaVista Software, Inc. 4 * stevel@mvista.com or source@mvista.com 5 * 6 * ######################################################################## 7 * 8 * This program is free software; you can distribute it and/or modify it 9 * under the terms of the GNU General Public License (Version 2) as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 20 * 21 * ######################################################################## 22 * 23 * Register offsets of the MIPS GT96100 Advanced Communication Controller. 24 * 25 */ 26#ifndef _GT96100_H 27#define _GT96100_H 28 29/* 30 * Galileo GT96100 internal register base. 31 */ 32#define MIPS_GT96100_BASE (KSEG1ADDR(0x14000000)) 33 34#define GT96100_WRITE(ofs, data) \ 35 *(volatile u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data) 36#define GT96100_READ(ofs) \ 37 le32_to_cpu(*(volatile u32 *)(MIPS_GT96100_BASE+ofs)) 38 39#define GT96100_ETH_IO_SIZE 0x4000 40 41/************************************************************************ 42 * Register offset addresses follow 43 ************************************************************************/ 44 45/* CPU Interface Control Registers */ 46#define GT96100_CPU_INTERF_CONFIG 0x000000 47 48/* Ethernet Ports */ 49#define GT96100_ETH_PHY_ADDR_REG 0x080800 50#define GT96100_ETH_SMI_REG 0x080810 51/* 52 These are offsets to port 0 registers. Add GT96100_ETH_IO_SIZE to 53 get offsets to port 1 registers. 54*/ 55#define GT96100_ETH_PORT_CONFIG 0x084800 56#define GT96100_ETH_PORT_CONFIG_EXT 0x084808 57#define GT96100_ETH_PORT_COMM 0x084810 58#define GT96100_ETH_PORT_STATUS 0x084818 59#define GT96100_ETH_SER_PARAM 0x084820 60#define GT96100_ETH_HASH_TBL_PTR 0x084828 61#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_L 0x084830 62#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_H 0x084838 63#define GT96100_ETH_SDMA_CONFIG 0x084840 64#define GT96100_ETH_SDMA_COMM 0x084848 65#define GT96100_ETH_INT_CAUSE 0x084850 66#define GT96100_ETH_INT_MASK 0x084858 67#define GT96100_ETH_1ST_RX_DESC_PTR0 0x084880 68#define GT96100_ETH_1ST_RX_DESC_PTR1 0x084884 69#define GT96100_ETH_1ST_RX_DESC_PTR2 0x084888 70#define GT96100_ETH_1ST_RX_DESC_PTR3 0x08488C 71#define GT96100_ETH_CURR_RX_DESC_PTR0 0x0848A0 72#define GT96100_ETH_CURR_RX_DESC_PTR1 0x0848A4 73#define GT96100_ETH_CURR_RX_DESC_PTR2 0x0848A8 74#define GT96100_ETH_CURR_RX_DESC_PTR3 0x0848AC 75#define GT96100_ETH_CURR_TX_DESC_PTR0 0x0848E0 76#define GT96100_ETH_CURR_TX_DESC_PTR1 0x0848E4 77#define GT96100_ETH_MIB_COUNT_BASE 0x085800 78 79/* SDMAs */ 80#define GT96100_SDMA_GROUP_CONFIG 0x101AF0 81/* SDMA Group 0 */ 82#define GT96100_SDMA_G0_CHAN0_CONFIG 0x000900 83#define GT96100_SDMA_G0_CHAN0_COMM 0x000908 84#define GT96100_SDMA_G0_CHAN0_RX_DESC_BASE 0x008900 85#define GT96100_SDMA_G0_CHAN0_CURR_RX_DESC_PTR 0x008910 86#define GT96100_SDMA_G0_CHAN0_TX_DESC_BASE 0x00C900 87#define GT96100_SDMA_G0_CHAN0_CURR_TX_DESC_PTR 0x00C910 88#define GT96100_SDMA_G0_CHAN0_1ST_TX_DESC_PTR 0x00C914 89#define GT96100_SDMA_G0_CHAN1_CONFIG 0x010900 90#define GT96100_SDMA_G0_CHAN1_COMM 0x010908 91#define GT96100_SDMA_G0_CHAN1_RX_DESC_BASE 0x018900 92#define GT96100_SDMA_G0_CHAN1_CURR_RX_DESC_PTR 0x018910 93#define GT96100_SDMA_G0_CHAN1_TX_DESC_BASE 0x01C900 94#define GT96100_SDMA_G0_CHAN1_CURR_TX_DESC_PTR 0x01C910 95#define GT96100_SDMA_G0_CHAN1_1ST_TX_DESC_PTR 0x01C914 96#define GT96100_SDMA_G0_CHAN2_CONFIG 0x020900 97#define GT96100_SDMA_G0_CHAN2_COMM 0x020908 98#define GT96100_SDMA_G0_CHAN2_RX_DESC_BASE 0x028900 99#define GT96100_SDMA_G0_CHAN2_CURR_RX_DESC_PTR 0x028910 100#define GT96100_SDMA_G0_CHAN2_TX_DESC_BASE 0x02C900 101#define GT96100_SDMA_G0_CHAN2_CURR_TX_DESC_PTR 0x02C910 102#define GT96100_SDMA_G0_CHAN2_1ST_TX_DESC_PTR 0x02C914 103#define GT96100_SDMA_G0_CHAN3_CONFIG 0x030900 104#define GT96100_SDMA_G0_CHAN3_COMM 0x030908 105#define GT96100_SDMA_G0_CHAN3_RX_DESC_BASE 0x038900 106#define GT96100_SDMA_G0_CHAN3_CURR_RX_DESC_PTR 0x038910 107#define GT96100_SDMA_G0_CHAN3_TX_DESC_BASE 0x03C900 108#define GT96100_SDMA_G0_CHAN3_CURR_TX_DESC_PTR 0x03C910 109#define GT96100_SDMA_G0_CHAN3_1ST_TX_DESC_PTR 0x03C914 110#define GT96100_SDMA_G0_CHAN4_CONFIG 0x040900 111#define GT96100_SDMA_G0_CHAN4_COMM 0x040908 112#define GT96100_SDMA_G0_CHAN4_RX_DESC_BASE 0x048900 113#define GT96100_SDMA_G0_CHAN4_CURR_RX_DESC_PTR 0x048910 114#define GT96100_SDMA_G0_CHAN4_TX_DESC_BASE 0x04C900 115#define GT96100_SDMA_G0_CHAN4_CURR_TX_DESC_PTR 0x04C910 116#define GT96100_SDMA_G0_CHAN4_1ST_TX_DESC_PTR 0x04C914 117#define GT96100_SDMA_G0_CHAN5_CONFIG 0x050900 118#define GT96100_SDMA_G0_CHAN5_COMM 0x050908 119#define GT96100_SDMA_G0_CHAN5_RX_DESC_BASE 0x058900 120#define GT96100_SDMA_G0_CHAN5_CURR_RX_DESC_PTR 0x058910 121#define GT96100_SDMA_G0_CHAN5_TX_DESC_BASE 0x05C900 122#define GT96100_SDMA_G0_CHAN5_CURR_TX_DESC_PTR 0x05C910 123#define GT96100_SDMA_G0_CHAN5_1ST_TX_DESC_PTR 0x05C914 124#define GT96100_SDMA_G0_CHAN6_CONFIG 0x060900 125#define GT96100_SDMA_G0_CHAN6_COMM 0x060908 126#define GT96100_SDMA_G0_CHAN6_RX_DESC_BASE 0x068900 127#define GT96100_SDMA_G0_CHAN6_CURR_RX_DESC_PTR 0x068910 128#define GT96100_SDMA_G0_CHAN6_TX_DESC_BASE 0x06C900 129#define GT96100_SDMA_G0_CHAN6_CURR_TX_DESC_PTR 0x06C910 130#define GT96100_SDMA_G0_CHAN6_1ST_TX_DESC_PTR 0x06C914 131#define GT96100_SDMA_G0_CHAN7_CONFIG 0x070900 132#define GT96100_SDMA_G0_CHAN7_COMM 0x070908 133#define GT96100_SDMA_G0_CHAN7_RX_DESC_BASE 0x078900 134#define GT96100_SDMA_G0_CHAN7_CURR_RX_DESC_PTR 0x078910 135#define GT96100_SDMA_G0_CHAN7_TX_DESC_BASE 0x07C900 136#define GT96100_SDMA_G0_CHAN7_CURR_TX_DESC_PTR 0x07C910 137#define GT96100_SDMA_G0_CHAN7_1ST_TX_DESC_PTR 0x07C914 138/* SDMA Group 1 */ 139#define GT96100_SDMA_G1_CHAN0_CONFIG 0x100900 140#define GT96100_SDMA_G1_CHAN0_COMM 0x100908 141#define GT96100_SDMA_G1_CHAN0_RX_DESC_BASE 0x108900 142#define GT96100_SDMA_G1_CHAN0_CURR_RX_DESC_PTR 0x108910 143#define GT96100_SDMA_G1_CHAN0_TX_DESC_BASE 0x10C900 144#define GT96100_SDMA_G1_CHAN0_CURR_TX_DESC_PTR 0x10C910 145#define GT96100_SDMA_G1_CHAN0_1ST_TX_DESC_PTR 0x10C914 146#define GT96100_SDMA_G1_CHAN1_CONFIG 0x110900 147#define GT96100_SDMA_G1_CHAN1_COMM 0x110908 148#define GT96100_SDMA_G1_CHAN1_RX_DESC_BASE 0x118900 149#define GT96100_SDMA_G1_CHAN1_CURR_RX_DESC_PTR 0x118910 150#define GT96100_SDMA_G1_CHAN1_TX_DESC_BASE 0x11C900 151#define GT96100_SDMA_G1_CHAN1_CURR_TX_DESC_PTR 0x11C910 152#define GT96100_SDMA_G1_CHAN1_1ST_TX_DESC_PTR 0x11C914 153#define GT96100_SDMA_G1_CHAN2_CONFIG 0x120900 154#define GT96100_SDMA_G1_CHAN2_COMM 0x120908 155#define GT96100_SDMA_G1_CHAN2_RX_DESC_BASE 0x128900 156#define GT96100_SDMA_G1_CHAN2_CURR_RX_DESC_PTR 0x128910 157#define GT96100_SDMA_G1_CHAN2_TX_DESC_BASE 0x12C900 158#define GT96100_SDMA_G1_CHAN2_CURR_TX_DESC_PTR 0x12C910 159#define GT96100_SDMA_G1_CHAN2_1ST_TX_DESC_PTR 0x12C914 160#define GT96100_SDMA_G1_CHAN3_CONFIG 0x130900 161#define GT96100_SDMA_G1_CHAN3_COMM 0x130908 162#define GT96100_SDMA_G1_CHAN3_RX_DESC_BASE 0x138900 163#define GT96100_SDMA_G1_CHAN3_CURR_RX_DESC_PTR 0x138910 164#define GT96100_SDMA_G1_CHAN3_TX_DESC_BASE 0x13C900 165#define GT96100_SDMA_G1_CHAN3_CURR_TX_DESC_PTR 0x13C910 166#define GT96100_SDMA_G1_CHAN3_1ST_TX_DESC_PTR 0x13C914 167#define GT96100_SDMA_G1_CHAN4_CONFIG 0x140900 168#define GT96100_SDMA_G1_CHAN4_COMM 0x140908 169#define GT96100_SDMA_G1_CHAN4_RX_DESC_BASE 0x148900 170#define GT96100_SDMA_G1_CHAN4_CURR_RX_DESC_PTR 0x148910 171#define GT96100_SDMA_G1_CHAN4_TX_DESC_BASE 0x14C900 172#define GT96100_SDMA_G1_CHAN4_CURR_TX_DESC_PTR 0x14C910 173#define GT96100_SDMA_G1_CHAN4_1ST_TX_DESC_PTR 0x14C914 174#define GT96100_SDMA_G1_CHAN5_CONFIG 0x150900 175#define GT96100_SDMA_G1_CHAN5_COMM 0x150908 176#define GT96100_SDMA_G1_CHAN5_RX_DESC_BASE 0x158900 177#define GT96100_SDMA_G1_CHAN5_CURR_RX_DESC_PTR 0x158910 178#define GT96100_SDMA_G1_CHAN5_TX_DESC_BASE 0x15C900 179#define GT96100_SDMA_G1_CHAN5_CURR_TX_DESC_PTR 0x15C910 180#define GT96100_SDMA_G1_CHAN5_1ST_TX_DESC_PTR 0x15C914 181#define GT96100_SDMA_G1_CHAN6_CONFIG 0x160900 182#define GT96100_SDMA_G1_CHAN6_COMM 0x160908 183#define GT96100_SDMA_G1_CHAN6_RX_DESC_BASE 0x168900 184#define GT96100_SDMA_G1_CHAN6_CURR_RX_DESC_PTR 0x168910 185#define GT96100_SDMA_G1_CHAN6_TX_DESC_BASE 0x16C900 186#define GT96100_SDMA_G1_CHAN6_CURR_TX_DESC_PTR 0x16C910 187#define GT96100_SDMA_G1_CHAN6_1ST_TX_DESC_PTR 0x16C914 188#define GT96100_SDMA_G1_CHAN7_CONFIG 0x170900 189#define GT96100_SDMA_G1_CHAN7_COMM 0x170908 190#define GT96100_SDMA_G1_CHAN7_RX_DESC_BASE 0x178900 191#define GT96100_SDMA_G1_CHAN7_CURR_RX_DESC_PTR 0x178910 192#define GT96100_SDMA_G1_CHAN7_TX_DESC_BASE 0x17C900 193#define GT96100_SDMA_G1_CHAN7_CURR_TX_DESC_PTR 0x17C910 194#define GT96100_SDMA_G1_CHAN7_1ST_TX_DESC_PTR 0x17C914 195/* MPSCs */ 196#define GT96100_MPSC0_MAIN_CONFIG_LOW 0x000A00 197#define GT96100_MPSC0_MAIN_CONFIG_HIGH 0x000A04 198#define GT96100_MPSC0_PROTOCOL_CONFIG 0x000A08 199#define GT96100_MPSC_CHAN0_REG1 0x000A0C 200#define GT96100_MPSC_CHAN0_REG2 0x000A10 201#define GT96100_MPSC_CHAN0_REG3 0x000A14 202#define GT96100_MPSC_CHAN0_REG4 0x000A18 203#define GT96100_MPSC_CHAN0_REG5 0x000A1C 204#define GT96100_MPSC_CHAN0_REG6 0x000A20 205#define GT96100_MPSC_CHAN0_REG7 0x000A24 206#define GT96100_MPSC_CHAN0_REG8 0x000A28 207#define GT96100_MPSC_CHAN0_REG9 0x000A2C 208#define GT96100_MPSC_CHAN0_REG10 0x000A30 209#define GT96100_MPSC_CHAN0_REG11 0x000A34 210#define GT96100_MPSC1_MAIN_CONFIG_LOW 0x008A00 211#define GT96100_MPSC1_MAIN_CONFIG_HIGH 0x008A04 212#define GT96100_MPSC1_PROTOCOL_CONFIG 0x008A08 213#define GT96100_MPSC_CHAN1_REG1 0x008A0C 214#define GT96100_MPSC_CHAN1_REG2 0x008A10 215#define GT96100_MPSC_CHAN1_REG3 0x008A14 216#define GT96100_MPSC_CHAN1_REG4 0x008A18 217#define GT96100_MPSC_CHAN1_REG5 0x008A1C 218#define GT96100_MPSC_CHAN1_REG6 0x008A20 219#define GT96100_MPSC_CHAN1_REG7 0x008A24 220#define GT96100_MPSC_CHAN1_REG8 0x008A28 221#define GT96100_MPSC_CHAN1_REG9 0x008A2C 222#define GT96100_MPSC_CHAN1_REG10 0x008A30 223#define GT96100_MPSC_CHAN1_REG11 0x008A34 224#define GT96100_MPSC2_MAIN_CONFIG_LOW 0x010A00 225#define GT96100_MPSC2_MAIN_CONFIG_HIGH 0x010A04 226#define GT96100_MPSC2_PROTOCOL_CONFIG 0x010A08 227#define GT96100_MPSC_CHAN2_REG1 0x010A0C 228#define GT96100_MPSC_CHAN2_REG2 0x010A10 229#define GT96100_MPSC_CHAN2_REG3 0x010A14 230#define GT96100_MPSC_CHAN2_REG4 0x010A18 231#define GT96100_MPSC_CHAN2_REG5 0x010A1C 232#define GT96100_MPSC_CHAN2_REG6 0x010A20 233#define GT96100_MPSC_CHAN2_REG7 0x010A24 234#define GT96100_MPSC_CHAN2_REG8 0x010A28 235#define GT96100_MPSC_CHAN2_REG9 0x010A2C 236#define GT96100_MPSC_CHAN2_REG10 0x010A30 237#define GT96100_MPSC_CHAN2_REG11 0x010A34 238#define GT96100_MPSC3_MAIN_CONFIG_LOW 0x018A00 239#define GT96100_MPSC3_MAIN_CONFIG_HIGH 0x018A04 240#define GT96100_MPSC3_PROTOCOL_CONFIG 0x018A08 241#define GT96100_MPSC_CHAN3_REG1 0x018A0C 242#define GT96100_MPSC_CHAN3_REG2 0x018A10 243#define GT96100_MPSC_CHAN3_REG3 0x018A14 244#define GT96100_MPSC_CHAN3_REG4 0x018A18 245#define GT96100_MPSC_CHAN3_REG5 0x018A1C 246#define GT96100_MPSC_CHAN3_REG6 0x018A20 247#define GT96100_MPSC_CHAN3_REG7 0x018A24 248#define GT96100_MPSC_CHAN3_REG8 0x018A28 249#define GT96100_MPSC_CHAN3_REG9 0x018A2C 250#define GT96100_MPSC_CHAN3_REG10 0x018A30 251#define GT96100_MPSC_CHAN3_REG11 0x018A34 252#define GT96100_MPSC4_MAIN_CONFIG_LOW 0x020A00 253#define GT96100_MPSC4_MAIN_CONFIG_HIGH 0x020A04 254#define GT96100_MPSC4_PROTOCOL_CONFIG 0x020A08 255#define GT96100_MPSC_CHAN4_REG1 0x020A0C 256#define GT96100_MPSC_CHAN4_REG2 0x020A10 257#define GT96100_MPSC_CHAN4_REG3 0x020A14 258#define GT96100_MPSC_CHAN4_REG4 0x020A18 259#define GT96100_MPSC_CHAN4_REG5 0x020A1C 260#define GT96100_MPSC_CHAN4_REG6 0x020A20 261#define GT96100_MPSC_CHAN4_REG7 0x020A24 262#define GT96100_MPSC_CHAN4_REG8 0x020A28 263#define GT96100_MPSC_CHAN4_REG9 0x020A2C 264#define GT96100_MPSC_CHAN4_REG10 0x020A30 265#define GT96100_MPSC_CHAN4_REG11 0x020A34 266#define GT96100_MPSC5_MAIN_CONFIG_LOW 0x028A00 267#define GT96100_MPSC5_MAIN_CONFIG_HIGH 0x028A04 268#define GT96100_MPSC5_PROTOCOL_CONFIG 0x028A08 269#define GT96100_MPSC_CHAN5_REG1 0x028A0C 270#define GT96100_MPSC_CHAN5_REG2 0x028A10 271#define GT96100_MPSC_CHAN5_REG3 0x028A14 272#define GT96100_MPSC_CHAN5_REG4 0x028A18 273#define GT96100_MPSC_CHAN5_REG5 0x028A1C 274#define GT96100_MPSC_CHAN5_REG6 0x028A20 275#define GT96100_MPSC_CHAN5_REG7 0x028A24 276#define GT96100_MPSC_CHAN5_REG8 0x028A28 277#define GT96100_MPSC_CHAN5_REG9 0x028A2C 278#define GT96100_MPSC_CHAN5_REG10 0x028A30 279#define GT96100_MPSC_CHAN5_REG11 0x028A34 280#define GT96100_MPSC6_MAIN_CONFIG_LOW 0x030A00 281#define GT96100_MPSC6_MAIN_CONFIG_HIGH 0x030A04 282#define GT96100_MPSC6_PROTOCOL_CONFIG 0x030A08 283#define GT96100_MPSC_CHAN6_REG1 0x030A0C 284#define GT96100_MPSC_CHAN6_REG2 0x030A10 285#define GT96100_MPSC_CHAN6_REG3 0x030A14 286#define GT96100_MPSC_CHAN6_REG4 0x030A18 287#define GT96100_MPSC_CHAN6_REG5 0x030A1C 288#define GT96100_MPSC_CHAN6_REG6 0x030A20 289#define GT96100_MPSC_CHAN6_REG7 0x030A24 290#define GT96100_MPSC_CHAN6_REG8 0x030A28 291#define GT96100_MPSC_CHAN6_REG9 0x030A2C 292#define GT96100_MPSC_CHAN6_REG10 0x030A30 293#define GT96100_MPSC_CHAN6_REG11 0x030A34 294#define GT96100_MPSC7_MAIN_CONFIG_LOW 0x038A00 295#define GT96100_MPSC7_MAIN_CONFIG_HIGH 0x038A04 296#define GT96100_MPSC7_PROTOCOL_CONFIG 0x038A08 297#define GT96100_MPSC_CHAN7_REG1 0x038A0C 298#define GT96100_MPSC_CHAN7_REG2 0x038A10 299#define GT96100_MPSC_CHAN7_REG3 0x038A14 300#define GT96100_MPSC_CHAN7_REG4 0x038A18 301#define GT96100_MPSC_CHAN7_REG5 0x038A1C 302#define GT96100_MPSC_CHAN7_REG6 0x038A20 303#define GT96100_MPSC_CHAN7_REG7 0x038A24 304#define GT96100_MPSC_CHAN7_REG8 0x038A28 305#define GT96100_MPSC_CHAN7_REG9 0x038A2C 306#define GT96100_MPSC_CHAN7_REG10 0x038A30 307#define GT96100_MPSC_CHAN7_REG11 0x038A34 308/* FlexTDMs */ 309/* TDPR0 - Transmit Dual Port RAM. block size 0xff */ 310#define GT96100_FXTDM0_TDPR0_BLK0_BASE 0x000B00 311#define GT96100_FXTDM0_TDPR0_BLK1_BASE 0x001B00 312#define GT96100_FXTDM0_TDPR0_BLK2_BASE 0x002B00 313#define GT96100_FXTDM0_TDPR0_BLK3_BASE 0x003B00 314/* RDPR0 - Receive Dual Port RAM. block size 0xff */ 315#define GT96100_FXTDM0_RDPR0_BLK0_BASE 0x004B00 316#define GT96100_FXTDM0_RDPR0_BLK1_BASE 0x005B00 317#define GT96100_FXTDM0_RDPR0_BLK2_BASE 0x006B00 318#define GT96100_FXTDM0_RDPR0_BLK3_BASE 0x007B00 319#define GT96100_FXTDM0_TX_READ_PTR 0x008B00 320#define GT96100_FXTDM0_RX_READ_PTR 0x008B04 321#define GT96100_FXTDM0_CONFIG 0x008B08 322#define GT96100_FXTDM0_AUX_CHANA_TX 0x008B0C 323#define GT96100_FXTDM0_AUX_CHANA_RX 0x008B10 324#define GT96100_FXTDM0_AUX_CHANB_TX 0x008B14 325#define GT96100_FXTDM0_AUX_CHANB_RX 0x008B18 326#define GT96100_FXTDM1_TDPR1_BLK0_BASE 0x010B00 327#define GT96100_FXTDM1_TDPR1_BLK1_BASE 0x011B00 328#define GT96100_FXTDM1_TDPR1_BLK2_BASE 0x012B00 329#define GT96100_FXTDM1_TDPR1_BLK3_BASE 0x013B00 330#define GT96100_FXTDM1_RDPR1_BLK0_BASE 0x014B00 331#define GT96100_FXTDM1_RDPR1_BLK1_BASE 0x015B00 332#define GT96100_FXTDM1_RDPR1_BLK2_BASE 0x016B00 333#define GT96100_FXTDM1_RDPR1_BLK3_BASE 0x017B00 334#define GT96100_FXTDM1_TX_READ_PTR 0x018B00 335#define GT96100_FXTDM1_RX_READ_PTR 0x018B04 336#define GT96100_FXTDM1_CONFIG 0x018B08 337#define GT96100_FXTDM1_AUX_CHANA_TX 0x018B0C 338#define GT96100_FXTDM1_AUX_CHANA_RX 0x018B10 339#define GT96100_FLTDM1_AUX_CHANB_TX 0x018B14 340#define GT96100_FLTDM1_AUX_CHANB_RX 0x018B18 341#define GT96100_FLTDM2_TDPR2_BLK0_BASE 0x020B00 342#define GT96100_FLTDM2_TDPR2_BLK1_BASE 0x021B00 343#define GT96100_FLTDM2_TDPR2_BLK2_BASE 0x022B00 344#define GT96100_FLTDM2_TDPR2_BLK3_BASE 0x023B00 345#define GT96100_FLTDM2_RDPR2_BLK0_BASE 0x024B00 346#define GT96100_FLTDM2_RDPR2_BLK1_BASE 0x025B00 347#define GT96100_FLTDM2_RDPR2_BLK2_BASE 0x026B00 348#define GT96100_FLTDM2_RDPR2_BLK3_BASE 0x027B00 349#define GT96100_FLTDM2_TX_READ_PTR 0x028B00 350#define GT96100_FLTDM2_RX_READ_PTR 0x028B04 351#define GT96100_FLTDM2_CONFIG 0x028B08 352#define GT96100_FLTDM2_AUX_CHANA_TX 0x028B0C 353#define GT96100_FLTDM2_AUX_CHANA_RX 0x028B10 354#define GT96100_FLTDM2_AUX_CHANB_TX 0x028B14 355#define GT96100_FLTDM2_AUX_CHANB_RX 0x028B18 356#define GT96100_FLTDM3_TDPR3_BLK0_BASE 0x030B00 357#define GT96100_FLTDM3_TDPR3_BLK1_BASE 0x031B00 358#define GT96100_FLTDM3_TDPR3_BLK2_BASE 0x032B00 359#define GT96100_FLTDM3_TDPR3_BLK3_BASE 0x033B00 360#define GT96100_FXTDM3_RDPR3_BLK0_BASE 0x034B00 361#define GT96100_FXTDM3_RDPR3_BLK1_BASE 0x035B00 362#define GT96100_FXTDM3_RDPR3_BLK2_BASE 0x036B00 363#define GT96100_FXTDM3_RDPR3_BLK3_BASE 0x037B00 364#define GT96100_FXTDM3_TX_READ_PTR 0x038B00 365#define GT96100_FXTDM3_RX_READ_PTR 0x038B04 366#define GT96100_FXTDM3_CONFIG 0x038B08 367#define GT96100_FXTDM3_AUX_CHANA_TX 0x038B0C 368#define GT96100_FXTDM3_AUX_CHANA_RX 0x038B10 369#define GT96100_FXTDM3_AUX_CHANB_TX 0x038B14 370#define GT96100_FXTDM3_AUX_CHANB_RX 0x038B18 371/* Baud Rate Generators */ 372#define GT96100_BRG0_CONFIG 0x102A00 373#define GT96100_BRG0_BAUD_TUNE 0x102A04 374#define GT96100_BRG1_CONFIG 0x102A08 375#define GT96100_BRG1_BAUD_TUNE 0x102A0C 376#define GT96100_BRG2_CONFIG 0x102A10 377#define GT96100_BRG2_BAUD_TUNE 0x102A14 378#define GT96100_BRG3_CONFIG 0x102A18 379#define GT96100_BRG3_BAUD_TUNE 0x102A1C 380#define GT96100_BRG4_CONFIG 0x102A20 381#define GT96100_BRG4_BAUD_TUNE 0x102A24 382#define GT96100_BRG5_CONFIG 0x102A28 383#define GT96100_BRG5_BAUD_TUNE 0x102A2C 384#define GT96100_BRG6_CONFIG 0x102A30 385#define GT96100_BRG6_BAUD_TUNE 0x102A34 386#define GT96100_BRG7_CONFIG 0x102A38 387#define GT96100_BRG7_BAUD_TUNE 0x102A3C 388/* Routing Registers */ 389#define GT96100_ROUTE_MAIN 0x101A00 390#define GT96100_ROUTE_RX_CLOCK 0x101A10 391#define GT96100_ROUTE_TX_CLOCK 0x101A20 392/* General Purpose Ports */ 393#define GT96100_GPP_CONFIG0 0x100A00 394#define GT96100_GPP_CONFIG1 0x100A04 395#define GT96100_GPP_CONFIG2 0x100A08 396#define GT96100_GPP_CONFIG3 0x100A0C 397#define GT96100_GPP_IO0 0x100A20 398#define GT96100_GPP_IO1 0x100A24 399#define GT96100_GPP_IO2 0x100A28 400#define GT96100_GPP_IO3 0x100A2C 401#define GT96100_GPP_DATA0 0x100A40 402#define GT96100_GPP_DATA1 0x100A44 403#define GT96100_GPP_DATA2 0x100A48 404#define GT96100_GPP_DATA3 0x100A4C 405#define GT96100_GPP_LEVEL0 0x100A60 406#define GT96100_GPP_LEVEL1 0x100A64 407#define GT96100_GPP_LEVEL2 0x100A68 408#define GT96100_GPP_LEVEL3 0x100A6C 409/* Watchdog */ 410#define GT96100_WD_CONFIG 0x101A80 411#define GT96100_WD_VALUE 0x101A84 412/* Communication Unit Arbiter */ 413#define GT96100_COMM_UNIT_ARBTR_CONFIG 0x101AC0 414/* PCI Arbiters */ 415#define GT96100_PCI0_ARBTR_CONFIG 0x101AE0 416#define GT96100_PCI1_ARBTR_CONFIG 0x101AE4 417/* CIU Arbiter */ 418#define GT96100_CIU_ARBITER_CONFIG 0x101AC0 419/* Interrupt Controller */ 420#define GT96100_MAIN_CAUSE 0x000C18 421#define GT96100_INT0_MAIN_MASK 0x000C1C 422#define GT96100_INT1_MAIN_MASK 0x000C24 423#define GT96100_HIGH_CAUSE 0x000C98 424#define GT96100_INT0_HIGH_MASK 0x000C9C 425#define GT96100_INT1_HIGH_MASK 0x000CA4 426#define GT96100_INT0_SELECT 0x000C70 427#define GT96100_INT1_SELECT 0x000C74 428#define GT96100_SERIAL_CAUSE 0x103A00 429#define GT96100_SERINT0_MASK 0x103A80 430#define GT96100_SERINT1_MASK 0x103A88 431 432#endif /* _GT96100_H */ 433