1/* 2 * This header file contains simple Read/Write macros for addressing the SDRAM, 3 * devices, GT`s internal registers and PCI (using the PCI`s address space). 4 * 5 * Copyright Galileo Technology. 6 */ 7#ifndef __INCcoreh 8#define __INCcoreh 9 10#include <linux/types.h> 11#include <asm/byteorder.h> 12#include <asm/gt64120.h> 13 14#define INTERNAL_REG_BASE_ADDR 0x14000000 15 16#define NO_BIT 0x00000000 17#define BIT0 0x00000001 18#define BIT1 0x00000002 19#define BIT2 0x00000004 20#define BIT3 0x00000008 21#define BIT4 0x00000010 22#define BIT5 0x00000020 23#define BIT6 0x00000040 24#define BIT7 0x00000080 25#define BIT8 0x00000100 26#define BIT9 0x00000200 27#define BIT10 0x00000400 28#define BIT11 0x00000800 29#define BIT12 0x00001000 30#define BIT13 0x00002000 31#define BIT14 0x00004000 32#define BIT15 0x00008000 33#define BIT16 0x00010000 34#define BIT17 0x00020000 35#define BIT18 0x00040000 36#define BIT19 0x00080000 37#define BIT20 0x00100000 38#define BIT21 0x00200000 39#define BIT22 0x00400000 40#define BIT23 0x00800000 41#define BIT24 0x01000000 42#define BIT25 0x02000000 43#define BIT26 0x04000000 44#define BIT27 0x08000000 45#define BIT28 0x10000000 46#define BIT29 0x20000000 47#define BIT30 0x40000000 48#define BIT31 0x80000000 49 50#define _1K 0x00000400 51#define _2K 0x00000800 52#define _4K 0x00001000 53#define _8K 0x00002000 54#define _16K 0x00004000 55#define _32K 0x00008000 56#define _64K 0x00010000 57#define _128K 0x00020000 58#define _256K 0x00040000 59#define _512K 0x00080000 60 61#define _1M 0x00100000 62#define _2M 0x00200000 63#define _3M 0x00300000 64#define _4M 0x00400000 65#define _5M 0x00500000 66#define _6M 0x00600000 67#define _7M 0x00700000 68#define _8M 0x00800000 69#define _9M 0x00900000 70#define _10M 0x00a00000 71#define _11M 0x00b00000 72#define _12M 0x00c00000 73#define _13M 0x00d00000 74#define _14M 0x00e00000 75#define _15M 0x00f00000 76#define _16M 0x01000000 77 78typedef enum _bool{false,true} bool; 79 80#ifndef NULL 81#define NULL 0 82#endif 83 84/* The two following defines are according to MIPS architecture. */ 85#define NONE_CACHEABLE 0xa0000000 86#define MIPS_CACHEABLE 0x80000000 87 88/* Read/Write to/from GT`s internal registers */ 89#define GT_REG_READ(offset, pData) \ 90do { \ 91 *pData = (*((u32 *)(NONE_CACHEABLE | \ 92 INTERNAL_REG_BASE_ADDR | (offset)))); \ 93 *pData = cpu_to_le32(*pData); \ 94} while(0) 95 96#define GT_REG_WRITE(offset, data) \ 97 (*((u32 *)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \ 98 (offset))) = cpu_to_le32(data)) 99 100#define VIRTUAL_TO_PHY(y) ((u32)(y) & (u32)0x5fffffff) 101#define PHY_TO_VIRTUAL(y) ((u32)(y) | NONE_CACHEABLE) 102 103/* Write 32/16/8 bit Non-Cache-able */ 104#define WRITE_CHAR(address, data) \ 105 (*((u8 *)((address) | NONE_CACHEABLE)) = (data)) 106#define WRITE_SHORT(address, data) \ 107 (*((u16 *)((address) | NONE_CACHEABLE)) = (u16) data) 108#define WRITE_WORD(address, data) \ 109 (*((u32 *)((address) | NONE_CACHEABLE)) = (u32) data) 110 111/* Write 32/16/8 bits Cacheable */ 112#define WRITE_CHAR_CACHEABLE(address, data) \ 113 (*((u8 *)((address) | MIPS_CACHEABLE)) = (data)) 114 115#define WRITE_SHORT_CACHEABLE(address, data) \ 116 (*((u16 *)((address) | MIPS_CACHEABLE)) = (u16) data) 117 118#define WRITE_WORD_CACHEABLE(address, data) \ 119 (*((u32 *)((address) | MIPS_CACHEABLE )) = (u32) data) 120 121/* Read 32/16/8 bits NonCacheable - returns data in variable. */ 122#define READ_CHAR(address,pData) \ 123 (*(pData) = *((u8 *)((address) | NONE_CACHEABLE))) 124 125#define READ_SHORT(address,pData) \ 126 (*(pData) = *((u16 *)((address) | NONE_CACHEABLE))) 127 128#define READ_WORD(address,pData) \ 129 (*(pData) = *((u32 *)((address) | NONE_CACHEABLE))) 130 131/* Read 32/16/8 bit NonCacheable - returns data direct. */ 132#define READCHAR(address) \ 133 (*((u8 *)((address) | NONE_CACHEABLE))) 134 135#define READSHORT(address) \ 136 (*((u16 *)((address) | NONE_CACHEABLE))) 137 138#define READWORD(address) \ 139 (*((u32 *)((address) | NONE_CACHEABLE))) 140 141/* Read 32/16/8 bit Cacheable - returns data in variable. */ 142#define READ_CHAR_CACHEABLE(address,pData) \ 143 (*(pData) = *((u8 *)((address) | MIPS_CACHEABLE))) 144 145#define READ_SHORT_CACHEABLE(address,pData) \ 146 (*(pData) = *((u16 *)((address) | MIPS_CACHEABLE))) 147#define READ_WORD_CACHEABLE(address,pData) \ 148 (*(pData) = *((u32 *)((address) | MIPS_CACHEABLE))) 149 150/* Read 32/16/8 bit Cacheable - returns data direct. */ 151#define READCHAR_CACHEABLE(address) \ 152 (*((u8 *)((address) | MIPS_CACHEABLE))) 153 154#define READSHORT_CACHEABLE(address) \ 155 (*((u16 *)((address) | MIPS_CACHEABLE))) 156 157#define READWORD_CACHEABLE(address) \ 158 (*((u32 *)((address) | MIPS_CACHEABLE))) 159 160/* 161 * SET_REG_BITS(regOffset,bits) - 162 * gets register offset and bits: a 32bit value. It set to logic '1' in the 163 * internal register the bits which given as an input example: 164 * SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic 165 * '1' in register 0x840 while the other bits stays as is. 166 */ 167#define SET_REG_BITS(regOffset,bits) \ 168 (*(u32*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \ 169 (regOffset)) |= (u32)cpu_to_le32(bits)) 170 171/* 172 * RESET_REG_BITS(regOffset,bits) - 173 * gets register offset and bits: a 32bit value. It set to logic '0' in the 174 * internal register the bits which given as an input example: 175 * RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic 176 * '0' in register 0x840 while the other bits stays as is. 177 */ 178#define RESET_REG_BITS(regOffset,bits) \ 179 (*(u32 *)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \ 180 (regOffset)) &= ~((u32)cpu_to_le32(bits))) 181 182#endif /* __INCcoreh */ 183