1/*
2 *  linux/include/asm-arm/arch-clps711x/hardware.h
3 *
4 *  This file contains the hardware definitions of the Prospector P720T.
5 *
6 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21 */
22#ifndef __ASM_ARCH_HARDWARE_H
23#define __ASM_ARCH_HARDWARE_H
24
25#include <linux/config.h>
26
27#define CLPS7111_VIRT_BASE	0xff000000
28#define CLPS7111_BASE		CLPS7111_VIRT_BASE
29
30/*
31 * The physical addresses that the external chip select signals map to is
32 * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212
33 * processors.  CONFIG_EP72XX_BOOT_ROM is only available if these
34 * processors are in use.
35 */
36#ifndef CONFIG_EP72XX_ROM_BOOT
37#define CS0_PHYS_BASE		(0x00000000)
38#define CS1_PHYS_BASE		(0x10000000)
39#define CS2_PHYS_BASE		(0x20000000)
40#define CS3_PHYS_BASE		(0x30000000)
41#define CS4_PHYS_BASE		(0x40000000)
42#define CS5_PHYS_BASE		(0x50000000)
43#define CS6_PHYS_BASE		(0x60000000)
44#define CS7_PHYS_BASE		(0x70000000)
45#else
46#define CS0_PHYS_BASE		(0x70000000)
47#define CS1_PHYS_BASE		(0x60000000)
48#define CS2_PHYS_BASE		(0x50000000)
49#define CS3_PHYS_BASE		(0x40000000)
50#define CS4_PHYS_BASE		(0x30000000)
51#define CS5_PHYS_BASE		(0x20000000)
52#define CS6_PHYS_BASE		(0x10000000)
53#define CS7_PHYS_BASE		(0x00000000)
54#endif
55
56#if defined(CONFIG_ARCH_EP7211)
57
58#define EP7211_VIRT_BASE	CLPS7111_VIRT_BASE
59#define EP7211_BASE		CLPS7111_VIRT_BASE
60#include <asm/hardware/ep7211.h>
61
62#elif defined(CONFIG_ARCH_EP7212)
63
64#define EP7212_VIRT_BASE	CLPS7111_VIRT_BASE
65#define EP7212_BASE		CLPS7111_VIRT_BASE
66#include <asm/hardware/ep7212.h>
67
68
69#endif
70
71#define SYSPLD_VIRT_BASE	0xfe000000
72#define SYSPLD_BASE		SYSPLD_VIRT_BASE
73
74#ifndef __ASSEMBLER__
75
76#define PCIO_BASE		IO_BASE
77
78#endif
79
80
81#if  defined(CONFIG_ARCH_AUTCPU12)
82
83#define  CS89712_VIRT_BASE	CLPS7111_VIRT_BASE
84#define  CS89712_BASE		CLPS7111_VIRT_BASE
85
86#include <asm/hardware/clps7111.h>
87#include <asm/hardware/ep7212.h>
88#include <asm/hardware/cs89712.h>
89
90#endif
91
92
93#if defined(CONFIG_ARCH_CDB89712)
94
95#include <asm/hardware/clps7111.h>
96#include <asm/hardware/ep7212.h>
97#include <asm/hardware/cs89712.h>
98
99/* dynamic ioremap() areas */
100#define FLASH_START      0x00000000
101#define FLASH_SIZE       0x800000
102#define FLASH_WIDTH      4
103
104#define SRAM_START       0x60000000
105#define SRAM_SIZE        0xc000
106#define SRAM_WIDTH       4
107
108#define BOOTROM_START    0x70000000
109#define BOOTROM_SIZE     0x80
110#define BOOTROM_WIDTH    4
111
112
113/* static cdb89712_map_io() areas */
114#define REGISTER_START   0x80000000
115#define REGISTER_SIZE    0x4000
116#define REGISTER_BASE    0xff000000
117
118#define ETHER_START      0x20000000
119#define ETHER_SIZE       0x1000
120#define ETHER_BASE       0xfe000000
121
122#endif
123
124
125#if defined(CONFIG_ARCH_EDB7211)
126
127/*
128 * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3)
129 * and repeat across it. This is the mapping for it.
130 *
131 * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This
132 * was cause for much consternation and headscratching. This should probably
133 * be made a compile/run time kernel option.
134 */
135#define EP7211_PHYS_EXTKBD		CS3_PHYS_BASE	/* physical */
136
137#define EP7211_VIRT_EXTKBD		(0xfd000000)	/* virtual */
138
139
140/*
141 * The CS8900A ethernet chip has its I/O registers wired to chip select 2
142 * (nCS2). This is the mapping for it.
143 *
144 * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This
145 * was cause for much consternation and headscratching. This should probably
146 * be made a compile/run time kernel option.
147 */
148#define EP7211_PHYS_CS8900A		CS2_PHYS_BASE	/* physical */
149
150#define EP7211_VIRT_CS8900A		(0xfc000000)	/* virtual */
151
152
153/*
154 * The two flash banks are wired to chip selects 0 and 1. This is the mapping
155 * for them.
156 *
157 * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
158 * in jumpered boot mode.
159 */
160#define EP7211_PHYS_FLASH1		CS0_PHYS_BASE	/* physical */
161#define EP7211_PHYS_FLASH2		CS1_PHYS_BASE	/* physical */
162
163#define EP7211_VIRT_FLASH1		(0xfa000000)	/* virtual */
164#define EP7211_VIRT_FLASH2		(0xfb000000)	/* virtual */
165
166#endif /* CONFIG_ARCH_EDB7211 */
167
168
169/*
170 * Relevant bits in port D, which controls power to the various parts of
171 * the LCD on the EDB7211.
172 */
173#define EDB_PD1_LCD_DC_DC_EN	(1<<1)
174#define EDB_PD2_LCDEN		(1<<2)
175#define EDB_PD3_LCDBL		(1<<3)
176
177
178#endif
179
180