1/* 2 ********************************************************************** 3 * 8010.h 4 * Copyright 1999, 2000 Creative Labs, Inc. 5 * 6 ********************************************************************** 7 * 8 * Date Author Summary of changes 9 * ---- ------ ------------------ 10 * October 20, 1999 Bertrand Lee base code release 11 * November 2, 1999 Alan Cox Cleaned of 8bit chars, DOS 12 * line endings 13 * December 8, 1999 Jon Taylor Added lots of new register info 14 * 15 ********************************************************************** 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public 28 * License along with this program; if not, write to the Free 29 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, 30 * USA. 31 * 32 * 33 ********************************************************************** 34 */ 35 36 37#ifndef _8010_H 38#define _8010_H 39 40#include <linux/types.h> 41 42/************************************************************************************************/ 43/* PCI function 0 registers, address = <val> + PCIBASE0 */ 44/************************************************************************************************/ 45 46#define PTR 0x00 /* Indexed register set pointer register */ 47 /* NOTE: The CHANNELNUM and ADDRESS words can */ 48 /* be modified independently of each other. */ 49#define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */ 50 /* channel number of the register to be */ 51 /* accessed. For non per-channel registers the */ 52 /* value should be set to zero. */ 53#define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */ 54 55#define DATA 0x04 /* Indexed register set data register */ 56 57#define IPR 0x08 /* Global interrupt pending register */ 58 /* Clear pending interrupts by writing a 1 to */ 59 /* the relevant bits and zero to the other bits */ 60#define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */ 61#define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */ 62#define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */ 63#define IPR_PCIERROR 0x00200000 /* PCI bus error */ 64#define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */ 65#define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */ 66#define IPR_MUTE 0x00040000 /* Mute button pressed */ 67#define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */ 68#define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */ 69#define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */ 70#define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */ 71#define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */ 72#define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */ 73#define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */ 74#define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */ 75#define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */ 76#define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */ 77#define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */ 78#define IPR_CHANNELLOOP 0x00000040 /* One or more channel loop interrupts pending */ 79#define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */ 80 /* Highest set channel in CLIPL or CLIPH. When */ 81 /* IP is written with CL set, the bit in CLIPL */ 82 /* or CLIPH corresponding to the CIN value */ 83 /* written will be cleared. */ 84 85#define INTE 0x0c /* Interrupt enable register */ 86#define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */ 87#define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */ 88#define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */ 89#define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */ 90#define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */ 91#define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */ 92#define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */ 93#define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */ 94#define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */ 95#define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */ 96#define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */ 97#define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */ 98#define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */ 99#define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */ 100#define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */ 101#define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */ 102#define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */ 103#define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */ 104 105#define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */ 106 /* NOTE: There is no reason to use this under */ 107 /* Linux, and it will cause odd hardware */ 108 /* behavior and possibly random segfaults and */ 109 /* lockups if enabled. */ 110 111#define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */ 112 /* NOTE: This bit must always be enabled */ 113#define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */ 114#define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */ 115#define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */ 116#define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */ 117#define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */ 118#define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */ 119#define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */ 120#define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */ 121#define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */ 122#define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */ 123#define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */ 124#define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */ 125#define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */ 126 127#define WC 0x10 /* Wall Clock register */ 128#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */ 129#define WC_SAMPLECOUNTER 0x14060010 130#define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */ 131 /* NOTE: Each channel takes 1/64th of a sample */ 132 /* period to be serviced. */ 133 134#define HCFG 0x14 /* Hardware config register */ 135 /* NOTE: There is no reason to use the legacy */ 136 /* SoundBlaster emulation stuff described below */ 137 /* under Linux, and all kinds of weird hardware */ 138 /* behavior can result if you try. Don't. */ 139#define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */ 140#define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */ 141#define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */ 142#define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */ 143#define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */ 144#define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */ 145#define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */ 146#define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */ 147#define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */ 148#define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */ 149#define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */ 150#define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */ 151 /* NOTE: The rest of the bits in this register */ 152 /* _are_ relevant under Linux. */ 153#define HCFG_CODECFORMAT_MASK 0x00070000 /* CODEC format */ 154#define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */ 155#define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */ 156#define HCFG_GPINPUT0 0x00004000 /* External pin112 */ 157#define HCFG_GPINPUT1 0x00002000 /* External pin110 */ 158 159#define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */ 160#define HCFG_GPOUT0 0x00001000 /* set to enable digital out on 5.1 cards */ 161 162#define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */ 163#define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */ 164 /* 1 = Force all 3 async digital inputs to use */ 165 /* the same async sample rate tracker (ZVIDEO) */ 166#define HCFG_AC3ENABLE_MASK 0x0x0000e0 /* AC3 async input control - Not implemented */ 167#define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */ 168#define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */ 169#define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */ 170#define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */ 171 /* will automatically mute their output when */ 172 /* they are not rate-locked to the external */ 173 /* async audio source */ 174#define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */ 175 /* NOTE: This should generally never be used. */ 176#define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */ 177 /* NOTE: This should generally never be used. */ 178#define HCFG_LOCKTANKCACHE 0x01020014 179#define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */ 180 /* NOTE: This is a 'cheap' way to implement a */ 181 /* master mute function on the mute button, and */ 182 /* in general should not be used unless a more */ 183 /* sophisticated master mute function has not */ 184 /* been written. */ 185#define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */ 186 /* Should be set to 1 when the EMU10K1 is */ 187 /* completely initialized. */ 188 189#define MUDATA 0x18 /* MPU401 data register (8 bits) */ 190 191#define MUCMD 0x19 /* MPU401 command register (8 bits) */ 192#define MUCMD_RESET 0xff /* RESET command */ 193#define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */ 194 /* NOTE: All other commands are ignored */ 195 196#define MUSTAT MUCMD /* MPU401 status register (8 bits) */ 197#define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */ 198#define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */ 199 200#define TIMER 0x1a /* Timer terminal count register */ 201 /* NOTE: After the rate is changed, a maximum */ 202 /* of 1024 sample periods should be allowed */ 203 /* before the new rate is guaranteed accurate. */ 204#define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */ 205 /* 0 == 1024 periods, [1..4] are not useful */ 206#define TIMER_RATE 0x0a00001a 207 208#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */ 209 210#define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */ 211#define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */ 212#define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */ 213 214/********************************************************************************************************/ 215/* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */ 216/********************************************************************************************************/ 217 218#define CPF 0x00 /* Current pitch and fraction register */ 219#define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */ 220#define CPF_CURRENTPITCH 0x10100000 221#define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */ 222#define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */ 223#define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */ 224 225#define PTRX 0x01 /* Pitch target and send A/B amounts register */ 226#define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */ 227#define PTRX_PITCHTARGET 0x10100001 228#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */ 229#define PTRX_FXSENDAMOUNT_A 0x08080001 230#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */ 231#define PTRX_FXSENDAMOUNT_B 0x08000001 232 233#define CVCF 0x02 /* Current volume and filter cutoff register */ 234#define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */ 235#define CVCF_CURRENTVOL 0x10100002 236#define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */ 237#define CVCF_CURRENTFILTER 0x10000002 238 239#define VTFT 0x03 /* Volume target and filter cutoff target register */ 240#define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */ 241#define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */ 242 243#define Z1 0x05 /* Filter delay memory 1 register */ 244 245#define Z2 0x04 /* Filter delay memory 2 register */ 246 247#define PSST 0x06 /* Send C amount and loop start address register */ 248#define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */ 249 250#define PSST_FXSENDAMOUNT_C 0x08180006 251 252#define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */ 253#define PSST_LOOPSTARTADDR 0x18000006 254 255#define DSL 0x07 /* Send D amount and loop start address register */ 256#define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */ 257 258#define DSL_FXSENDAMOUNT_D 0x08180007 259 260#define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */ 261#define DSL_LOOPENDADDR 0x18000007 262 263#define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */ 264#define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */ 265#define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */ 266 /* 1 == full band, 7 == lowpass */ 267 /* ROM 0 is used when pitch shifting downward or less */ 268 /* then 3 semitones upward. Increasingly higher ROM */ 269 /* numbers are used, typically in steps of 3 semitones, */ 270 /* as upward pitch shifting is performed. */ 271#define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */ 272#define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */ 273#define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */ 274#define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */ 275#define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */ 276#define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */ 277#define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */ 278#define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */ 279#define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */ 280#define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */ 281#define CCCA_CURRADDR 0x18000008 282 283#define CCR 0x09 /* Cache control register */ 284#define CCR_CACHEINVALIDSIZE 0x07190009 285#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */ 286#define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */ 287#define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */ 288#define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */ 289#define CCR_READADDRESS 0x06100009 290#define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */ 291#define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */ 292 /* NOTE: This is valid only if CACHELOOPFLAG is set */ 293#define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */ 294#define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */ 295 296#define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */ 297 /* NOTE: This register is normally not used */ 298#define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */ 299 300#define FXRT 0x0b /* Effects send routing register */ 301 /* NOTE: It is illegal to assign the same routing to */ 302 /* two effects sends. */ 303#define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */ 304#define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */ 305#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */ 306#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */ 307 308#define MAPA 0x0c /* Cache map A */ 309 310#define MAPB 0x0d /* Cache map B */ 311 312#define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */ 313#define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */ 314 315#define ENVVOL 0x10 /* Volume envelope register */ 316#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */ 317 /* 0x8000-n == 666*n usec delay */ 318 319#define ATKHLDV 0x11 /* Volume envelope hold and attack register */ 320#define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */ 321#define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */ 322#define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */ 323 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */ 324 325#define DCYSUSV 0x12 /* Volume envelope sustain and decay register */ 326#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */ 327#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ 328#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */ 329 /* this channel and from writing to pitch, filter and */ 330 /* volume targets. */ 331#define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */ 332 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */ 333 334#define LFOVAL1 0x13 /* Modulation LFO value */ 335#define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */ 336 /* 0x8000-n == 666*n usec delay */ 337 338#define ENVVAL 0x14 /* Modulation envelope register */ 339#define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */ 340 /* 0x8000-n == 666*n usec delay */ 341 342#define ATKHLDM 0x15 /* Modulation envelope hold and attack register */ 343#define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */ 344#define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */ 345#define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */ 346 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */ 347 348#define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */ 349#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */ 350#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ 351#define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */ 352 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */ 353 354#define LFOVAL2 0x17 /* Vibrato LFO register */ 355#define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */ 356 /* 0x8000-n == 666*n usec delay */ 357 358#define IP 0x18 /* Initial pitch register */ 359#define IP_MASK 0x0000ffff /* Exponential initial pitch shift */ 360 /* 4 bits of octave, 12 bits of fractional octave */ 361#define IP_UNITY 0x0000e000 /* Unity pitch shift */ 362 363#define IFATN 0x19 /* Initial filter cutoff and attenuation register */ 364#define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */ 365 /* 6 most significant bits are semitones */ 366 /* 2 least significant bits are fractions */ 367#define IFATN_FILTERCUTOFF 0x08080019 368#define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */ 369#define IFATN_ATTENUATION 0x08000019 370 371 372#define PEFE 0x1a /* Pitch envelope and filter envelope amount register */ 373#define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */ 374 /* Signed 2's complement, +/- one octave peak extremes */ 375#define PEFE_PITCHAMOUNT 0x0808001a 376#define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */ 377 /* Signed 2's complement, +/- six octaves peak extremes */ 378#define PEFE_FILTERAMOUNT 0x0800001a 379#define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */ 380#define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */ 381 /* Signed 2's complement, +/- one octave extremes */ 382#define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */ 383 /* Signed 2's complement, +/- three octave extremes */ 384 385 386#define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */ 387#define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */ 388 /* Signed 2's complement, with +/- 12dB extremes */ 389 390#define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */ 391#define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */ 392 /* Signed 2's complement, +/- one octave extremes */ 393#define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */ 394 /* 0.039Hz steps, maximum of 9.85 Hz. */ 395 396#define TEMPENV 0x1e /* Tempory envelope register */ 397#define TEMPENV_MASK 0x0000ffff /* 16-bit value */ 398 /* NOTE: All channels contain internal variables; do */ 399 /* not write to these locations. */ 400 401#define CD0 0x20 /* Cache data 0 register */ 402#define CD1 0x21 /* Cache data 1 register */ 403#define CD2 0x22 /* Cache data 2 register */ 404#define CD3 0x23 /* Cache data 3 register */ 405#define CD4 0x24 /* Cache data 4 register */ 406#define CD5 0x25 /* Cache data 5 register */ 407#define CD6 0x26 /* Cache data 6 register */ 408#define CD7 0x27 /* Cache data 7 register */ 409#define CD8 0x28 /* Cache data 8 register */ 410#define CD9 0x29 /* Cache data 9 register */ 411#define CDA 0x2a /* Cache data A register */ 412#define CDB 0x2b /* Cache data B register */ 413#define CDC 0x2c /* Cache data C register */ 414#define CDD 0x2d /* Cache data D register */ 415#define CDE 0x2e /* Cache data E register */ 416#define CDF 0x2f /* Cache data F register */ 417 418#define PTB 0x40 /* Page table base register */ 419#define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */ 420 421#define TCB 0x41 /* Tank cache base register */ 422#define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */ 423 424#define ADCCR 0x42 /* ADC sample rate/stereo control register */ 425#define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */ 426#define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */ 427 /* NOTE: To guarantee phase coherency, both channels */ 428 /* must be disabled prior to enabling both channels. */ 429#define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */ 430#define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */ 431#define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */ 432#define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */ 433#define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */ 434#define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */ 435#define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */ 436#define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */ 437#define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */ 438 439#define FXWC 0x43 /* FX output write channels register */ 440 /* When set, each bit enables the writing of the */ 441 /* corresponding FX output channel into host memory */ 442 443#define TCBS 0x44 /* Tank cache buffer size register */ 444#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */ 445#define TCBS_BUFFSIZE_16K 0x00000000 446#define TCBS_BUFFSIZE_32K 0x00000001 447#define TCBS_BUFFSIZE_64K 0x00000002 448#define TCBS_BUFFSIZE_128K 0x00000003 449#define TCBS_BUFFSIZE_256K 0x00000004 450#define TCBS_BUFFSIZE_512K 0x00000005 451#define TCBS_BUFFSIZE_1024K 0x00000006 452#define TCBS_BUFFSIZE_2048K 0x00000007 453 454#define MICBA 0x45 /* AC97 microphone buffer address register */ 455#define MICBA_MASK 0xfffff000 /* 20 bit base address */ 456 457#define ADCBA 0x46 /* ADC buffer address register */ 458#define ADCBA_MASK 0xfffff000 /* 20 bit base address */ 459 460#define FXBA 0x47 /* FX Buffer Address */ 461#define FXBA_MASK 0xfffff000 /* 20 bit base address */ 462 463#define MICBS 0x49 /* Microphone buffer size register */ 464 465#define ADCBS 0x4a /* ADC buffer size register */ 466 467#define FXBS 0x4b /* FX buffer size register */ 468 469/* The following mask values define the size of the ADC, MIX and FX buffers in bytes */ 470#define ADCBS_BUFSIZE_NONE 0x00000000 471#define ADCBS_BUFSIZE_384 0x00000001 472#define ADCBS_BUFSIZE_448 0x00000002 473#define ADCBS_BUFSIZE_512 0x00000003 474#define ADCBS_BUFSIZE_640 0x00000004 475#define ADCBS_BUFSIZE_768 0x00000005 476#define ADCBS_BUFSIZE_896 0x00000006 477#define ADCBS_BUFSIZE_1024 0x00000007 478#define ADCBS_BUFSIZE_1280 0x00000008 479#define ADCBS_BUFSIZE_1536 0x00000009 480#define ADCBS_BUFSIZE_1792 0x0000000a 481#define ADCBS_BUFSIZE_2048 0x0000000b 482#define ADCBS_BUFSIZE_2560 0x0000000c 483#define ADCBS_BUFSIZE_3072 0x0000000d 484#define ADCBS_BUFSIZE_3584 0x0000000e 485#define ADCBS_BUFSIZE_4096 0x0000000f 486#define ADCBS_BUFSIZE_5120 0x00000010 487#define ADCBS_BUFSIZE_6144 0x00000011 488#define ADCBS_BUFSIZE_7168 0x00000012 489#define ADCBS_BUFSIZE_8192 0x00000013 490#define ADCBS_BUFSIZE_10240 0x00000014 491#define ADCBS_BUFSIZE_12288 0x00000015 492#define ADCBS_BUFSIZE_14366 0x00000016 493#define ADCBS_BUFSIZE_16384 0x00000017 494#define ADCBS_BUFSIZE_20480 0x00000018 495#define ADCBS_BUFSIZE_24576 0x00000019 496#define ADCBS_BUFSIZE_28672 0x0000001a 497#define ADCBS_BUFSIZE_32768 0x0000001b 498#define ADCBS_BUFSIZE_40960 0x0000001c 499#define ADCBS_BUFSIZE_49152 0x0000001d 500#define ADCBS_BUFSIZE_57344 0x0000001e 501#define ADCBS_BUFSIZE_65536 0x0000001f 502 503 504#define CDCS 0x50 /* CD-ROM digital channel status register */ 505 506#define GPSCS 0x51 /* General Purpose SPDIF channel status register*/ 507 508#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ 509 510/* definitions for debug register - taken from the alsa drivers */ 511#define DBG_ZC 0x80000000 /* zero tram counter */ 512#define DBG_SATURATION_OCCURED 0x02000000 /* saturation control */ 513#define DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */ 514#define DBG_SINGLE_STEP 0x00008000 /* single step mode */ 515#define DBG_STEP 0x00004000 /* start single step */ 516#define DBG_CONDITION_CODE 0x00003e00 /* condition code */ 517#define DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */ 518 519 520#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ 521 522#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */ 523 524#define SPCS1 0x55 /* SPDIF output Channel Status 1 register */ 525 526#define SPCS2 0x56 /* SPDIF output Channel Status 2 register */ 527 528#define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */ 529#define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */ 530#define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */ 531#define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */ 532#define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */ 533#define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */ 534#define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */ 535#define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */ 536#define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */ 537#define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */ 538#define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */ 539#define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */ 540#define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */ 541#define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */ 542#define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */ 543#define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */ 544#define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */ 545#define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */ 546#define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */ 547#define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */ 548#define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */ 549#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */ 550#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */ 551 552/* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */ 553#define CLIEL 0x58 /* Channel loop interrupt enable low register */ 554 555#define CLIEH 0x59 /* Channel loop interrupt enable high register */ 556 557#define CLIPL 0x5a /* Channel loop interrupt pending low register */ 558 559#define CLIPH 0x5b /* Channel loop interrupt pending high register */ 560 561#define SOLEL 0x5c /* Stop on loop enable low register */ 562 563#define SOLEH 0x5d /* Stop on loop enable high register */ 564 565#define SPBYPASS 0x5e /* SPDIF BYPASS mode register */ 566#define SPBYPASS_ENABLE 0x00000001 /* Enable SPDIF bypass mode */ 567 568#define AC97SLOT 0x5f /* additional AC97 slots enable bits */ 569#define AC97SLOT_CNTR 0x10 /* Center enable */ 570#define AC97SLOT_LFE 0x20 /* LFE enable */ 571 572#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */ 573 574#define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */ 575 576#define ZVSRCS 0x62 /* ZVideo sample rate converter status */ 577 /* NOTE: This one has no SPDIFLOCKED field */ 578 /* Assumes sample lock */ 579 580/* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */ 581#define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */ 582#define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */ 583#define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */ 584 585#define MICIDX 0x63 /* Microphone recording buffer index register */ 586#define MICIDX_MASK 0x0000ffff /* 16-bit value */ 587#define MICIDX_IDX 0x10000063 588 589#define ADCIDX 0x64 /* ADC recording buffer index register */ 590#define ADCIDX_MASK 0x0000ffff /* 16 bit index field */ 591#define ADCIDX_IDX 0x10000064 592 593#define FXIDX 0x65 /* FX recording buffer index register */ 594#define FXIDX_MASK 0x0000ffff /* 16-bit value */ 595#define FXIDX_IDX 0x10000065 596 597/* Each FX general purpose register is 32 bits in length, all bits are used */ 598#define FXGPREGBASE 0x100 /* FX general purpose registers base */ 599 600/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */ 601/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */ 602/* locations are for external TRAM. */ 603#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */ 604#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */ 605 606/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */ 607#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */ 608#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */ 609#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */ 610#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */ 611#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */ 612#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */ 613 614#define MICROCODEBASE 0x400 /* Microcode data base address */ 615 616/* Each DSP microcode instruction is mapped into 2 doublewords */ 617/* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */ 618#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */ 619#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */ 620#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */ 621#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */ 622#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */ 623 624#endif /* _8010_H */ 625