1/* blz2060.c: Driver for Blizzard 2060 SCSI Controller. 2 * 3 * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk) 4 * 5 * This driver is based on the CyberStorm driver, hence the occasional 6 * reference to CyberStorm. 7 */ 8 9/* TODO: 10 * 11 * 1) Figure out how to make a cleaner merge with the sparc driver with regard 12 * to the caches and the Sparc MMU mapping. 13 * 2) Make as few routines required outside the generic driver. A lot of the 14 * routines in this file used to be inline! 15 */ 16 17#include <linux/module.h> 18 19#include <linux/init.h> 20#include <linux/kernel.h> 21#include <linux/delay.h> 22#include <linux/types.h> 23#include <linux/string.h> 24#include <linux/slab.h> 25#include <linux/blk.h> 26#include <linux/proc_fs.h> 27#include <linux/stat.h> 28 29#include "scsi.h" 30#include "hosts.h" 31#include "NCR53C9x.h" 32#include "blz2060.h" 33 34#include <linux/zorro.h> 35#include <asm/irq.h> 36#include <asm/amigaints.h> 37#include <asm/amigahw.h> 38 39#include <asm/pgtable.h> 40 41static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count); 42static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp); 43static void dma_dump_state(struct NCR_ESP *esp); 44static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length); 45static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length); 46static void dma_ints_off(struct NCR_ESP *esp); 47static void dma_ints_on(struct NCR_ESP *esp); 48static int dma_irq_p(struct NCR_ESP *esp); 49static void dma_led_off(struct NCR_ESP *esp); 50static void dma_led_on(struct NCR_ESP *esp); 51static int dma_ports_p(struct NCR_ESP *esp); 52static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write); 53 54static volatile unsigned char cmd_buffer[16]; 55 /* This is where all commands are put 56 * before they are transferred to the ESP chip 57 * via PIO. 58 */ 59 60/***************************************************************** Detection */ 61int __init blz2060_esp_detect(Scsi_Host_Template *tpnt) 62{ 63 struct NCR_ESP *esp; 64 struct zorro_dev *z = NULL; 65 unsigned long address; 66 67 if ((z = zorro_find_device(ZORRO_PROD_PHASE5_BLIZZARD_2060, z))) { 68 unsigned long board = z->resource.start; 69 if (request_mem_region(board+BLZ2060_ESP_ADDR, 70 sizeof(struct ESP_regs), "NCR53C9x")) { 71 esp = esp_allocate(tpnt, (void *)board+BLZ2060_ESP_ADDR); 72 73 /* Do command transfer with programmed I/O */ 74 esp->do_pio_cmds = 1; 75 76 /* Required functions */ 77 esp->dma_bytes_sent = &dma_bytes_sent; 78 esp->dma_can_transfer = &dma_can_transfer; 79 esp->dma_dump_state = &dma_dump_state; 80 esp->dma_init_read = &dma_init_read; 81 esp->dma_init_write = &dma_init_write; 82 esp->dma_ints_off = &dma_ints_off; 83 esp->dma_ints_on = &dma_ints_on; 84 esp->dma_irq_p = &dma_irq_p; 85 esp->dma_ports_p = &dma_ports_p; 86 esp->dma_setup = &dma_setup; 87 88 /* Optional functions */ 89 esp->dma_barrier = 0; 90 esp->dma_drain = 0; 91 esp->dma_invalidate = 0; 92 esp->dma_irq_entry = 0; 93 esp->dma_irq_exit = 0; 94 esp->dma_led_on = &dma_led_on; 95 esp->dma_led_off = &dma_led_off; 96 esp->dma_poll = 0; 97 esp->dma_reset = 0; 98 99 /* SCSI chip speed */ 100 esp->cfreq = 40000000; 101 102 /* The DMA registers on the Blizzard are mapped 103 * relative to the device (i.e. in the same Zorro 104 * I/O block). 105 */ 106 address = (unsigned long)ZTWO_VADDR(board); 107 esp->dregs = (void *)(address + BLZ2060_DMA_ADDR); 108 109 /* ESP register base */ 110 esp->eregs = (struct ESP_regs *)(address + BLZ2060_ESP_ADDR); 111 112 /* Set the command buffer */ 113 esp->esp_command = (volatile unsigned char*) cmd_buffer; 114 esp->esp_command_dvma = virt_to_bus(cmd_buffer); 115 116 esp->irq = IRQ_AMIGA_PORTS; 117 request_irq(IRQ_AMIGA_PORTS, esp_intr, SA_SHIRQ, 118 "Blizzard 2060 SCSI", esp_intr); 119 120 /* Figure out our scsi ID on the bus */ 121 esp->scsi_id = 7; 122 123 /* We don't have a differential SCSI-bus. */ 124 esp->diff = 0; 125 126 esp_initialize(esp); 127 128 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use); 129 esps_running = esps_in_use; 130 return esps_in_use; 131 } 132 } 133 return 0; 134} 135 136/************************************************************* DMA Functions */ 137static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count) 138{ 139 /* Since the Blizzard DMA is fully dedicated to the ESP chip, 140 * the number of bytes sent (to the ESP chip) equals the number 141 * of bytes in the FIFO - there is no buffering in the DMA controller. 142 * XXXX Do I read this right? It is from host to ESP, right? 143 */ 144 return fifo_count; 145} 146 147static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp) 148{ 149 /* I don't think there's any limit on the Blizzard DMA. So we use what 150 * the ESP chip can handle (24 bit). 151 */ 152 unsigned long sz = sp->SCp.this_residual; 153 if(sz > 0x1000000) 154 sz = 0x1000000; 155 return sz; 156} 157 158static void dma_dump_state(struct NCR_ESP *esp) 159{ 160 ESPLOG(("intreq:<%04x>, intena:<%04x>\n", 161 custom.intreqr, custom.intenar)); 162} 163 164static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length) 165{ 166 struct blz2060_dma_registers *dregs = 167 (struct blz2060_dma_registers *) (esp->dregs); 168 169 cache_clear(addr, length); 170 171 addr >>= 1; 172 addr &= ~(BLZ2060_DMA_WRITE); 173 dregs->dma_addr3 = (addr ) & 0xff; 174 dregs->dma_addr2 = (addr >> 8) & 0xff; 175 dregs->dma_addr1 = (addr >> 16) & 0xff; 176 dregs->dma_addr0 = (addr >> 24) & 0xff; 177} 178 179static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length) 180{ 181 struct blz2060_dma_registers *dregs = 182 (struct blz2060_dma_registers *) (esp->dregs); 183 184 cache_push(addr, length); 185 186 addr >>= 1; 187 addr |= BLZ2060_DMA_WRITE; 188 dregs->dma_addr3 = (addr ) & 0xff; 189 dregs->dma_addr2 = (addr >> 8) & 0xff; 190 dregs->dma_addr1 = (addr >> 16) & 0xff; 191 dregs->dma_addr0 = (addr >> 24) & 0xff; 192} 193 194static void dma_ints_off(struct NCR_ESP *esp) 195{ 196 disable_irq(esp->irq); 197} 198 199static void dma_ints_on(struct NCR_ESP *esp) 200{ 201 enable_irq(esp->irq); 202} 203 204static int dma_irq_p(struct NCR_ESP *esp) 205{ 206 return (esp_read(esp->eregs->esp_status) & ESP_STAT_INTR); 207} 208 209static void dma_led_off(struct NCR_ESP *esp) 210{ 211 ((struct blz2060_dma_registers *) (esp->dregs))->dma_led_ctrl = 212 BLZ2060_DMA_LED; 213} 214 215static void dma_led_on(struct NCR_ESP *esp) 216{ 217 ((struct blz2060_dma_registers *) (esp->dregs))->dma_led_ctrl = 0; 218} 219 220static int dma_ports_p(struct NCR_ESP *esp) 221{ 222 return ((custom.intenar) & IF_PORTS); 223} 224 225static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write) 226{ 227 /* On the Sparc, DMA_ST_WRITE means "move data from device to memory" 228 * so when (write) is true, it actually means READ! 229 */ 230 if(write){ 231 dma_init_read(esp, addr, count); 232 } else { 233 dma_init_write(esp, addr, count); 234 } 235} 236 237#define HOSTS_C 238 239#include "blz2060.h" 240 241static Scsi_Host_Template driver_template = SCSI_BLZ2060; 242 243#include "scsi_module.c" 244 245int blz2060_esp_release(struct Scsi_Host *instance) 246{ 247#ifdef MODULE 248 unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev; 249 250 esp_deallocate((struct NCR_ESP *)instance->hostdata); 251 esp_release(); 252 release_mem_region(address, sizeof(struct ESP_regs)); 253 free_irq(IRQ_AMIGA_PORTS, esp_intr); 254#endif 255 return 1; 256} 257 258MODULE_LICENSE("GPL"); 259