1/*
2 * ti113x.h 1.16 1999/10/25 20:03:34
3 *
4 * The contents of this file are subject to the Mozilla Public License
5 * Version 1.1 (the "License"); you may not use this file except in
6 * compliance with the License. You may obtain a copy of the License
7 * at http://www.mozilla.org/MPL/
8 *
9 * Software distributed under the License is distributed on an "AS IS"
10 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
11 * the License for the specific language governing rights and
12 * limitations under the License.
13 *
14 * The initial developer of the original code is David A. Hinds
15 * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
16 * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
17 *
18 * Alternatively, the contents of this file may be used under the
19 * terms of the GNU General Public License version 2 (the "GPL"), in which
20 * case the provisions of the GPL are applicable instead of the
21 * above.  If you wish to allow the use of your version of this file
22 * only under the terms of the GPL and not to allow others to use
23 * your version of this file under the MPL, indicate your decision by
24 * deleting the provisions above and replace them with the notice and
25 * other provisions required by the GPL.  If you do not delete the
26 * provisions above, a recipient may use your version of this file
27 * under either the MPL or the GPL.
28 */
29
30#ifndef _LINUX_TI113X_H
31#define _LINUX_TI113X_H
32
33#include <linux/config.h>
34
35/* Register definitions for TI 113X PCI-to-CardBus bridges */
36
37/* System Control Register */
38#define TI113X_SYSTEM_CONTROL		0x0080	/* 32 bit */
39#define  TI113X_SCR_SMIROUTE		0x04000000
40#define  TI113X_SCR_SMISTATUS		0x02000000
41#define  TI113X_SCR_SMIENB		0x01000000
42#define  TI113X_SCR_VCCPROT		0x00200000
43#define  TI113X_SCR_REDUCEZV		0x00100000
44#define  TI113X_SCR_CDREQEN		0x00080000
45#define  TI113X_SCR_CDMACHAN		0x00070000
46#define  TI113X_SCR_SOCACTIVE		0x00002000
47#define  TI113X_SCR_PWRSTREAM		0x00000800
48#define  TI113X_SCR_DELAYUP		0x00000400
49#define  TI113X_SCR_DELAYDOWN		0x00000200
50#define  TI113X_SCR_INTERROGATE		0x00000100
51#define  TI113X_SCR_CLKRUN_SEL		0x00000080
52#define  TI113X_SCR_PWRSAVINGS		0x00000040
53#define  TI113X_SCR_SUBSYSRW		0x00000020
54#define  TI113X_SCR_CB_DPAR		0x00000010
55#define  TI113X_SCR_CDMA_EN		0x00000008
56#define  TI113X_SCR_ASYNC_IRQ		0x00000004
57#define  TI113X_SCR_KEEPCLK		0x00000002
58#define  TI113X_SCR_CLKRUN_ENA		0x00000001
59
60#define  TI122X_SCR_SER_STEP		0xc0000000
61#define  TI122X_SCR_INTRTIE		0x20000000
62#define  TI122X_SCR_CBRSVD		0x00400000
63#define  TI122X_SCR_MRBURSTDN		0x00008000
64#define  TI122X_SCR_MRBURSTUP		0x00004000
65#define  TI122X_SCR_RIMUX		0x00000001
66
67/* Multimedia Control Register */
68#define TI1250_MULTIMEDIA_CTL		0x0084	/* 8 bit */
69#define  TI1250_MMC_ZVOUTEN		0x80
70#define  TI1250_MMC_PORTSEL		0x40
71#define  TI1250_MMC_ZVEN1		0x02
72#define  TI1250_MMC_ZVEN0		0x01
73
74#define TI1250_GENERAL_STATUS		0x0085	/* 8 bit */
75#define TI1250_GPIO0_CONTROL		0x0088	/* 8 bit */
76#define TI1250_GPIO1_CONTROL		0x0089	/* 8 bit */
77#define TI1250_GPIO2_CONTROL		0x008a	/* 8 bit */
78#define TI1250_GPIO3_CONTROL		0x008b	/* 8 bit */
79#define TI122X_IRQMUX			0x008c	/* 32 bit */
80
81/* Retry Status Register */
82#define TI113X_RETRY_STATUS		0x0090	/* 8 bit */
83#define  TI113X_RSR_PCIRETRY		0x80
84#define  TI113X_RSR_CBRETRY		0x40
85#define  TI113X_RSR_TEXP_CBB		0x20
86#define  TI113X_RSR_MEXP_CBB		0x10
87#define  TI113X_RSR_TEXP_CBA		0x08
88#define  TI113X_RSR_MEXP_CBA		0x04
89#define  TI113X_RSR_TEXP_PCI		0x02
90#define  TI113X_RSR_MEXP_PCI		0x01
91
92/* Card Control Register */
93#define TI113X_CARD_CONTROL		0x0091	/* 8 bit */
94#define  TI113X_CCR_RIENB		0x80
95#define  TI113X_CCR_ZVENABLE		0x40
96#define  TI113X_CCR_PCI_IRQ_ENA		0x20
97#define  TI113X_CCR_PCI_IREQ		0x10
98#define  TI113X_CCR_PCI_CSC		0x08
99#define  TI113X_CCR_SPKROUTEN		0x02
100#define  TI113X_CCR_IFG			0x01
101
102#define  TI1220_CCR_PORT_SEL		0x20
103#define  TI122X_CCR_AUD2MUX		0x04
104
105/* Device Control Register */
106#define TI113X_DEVICE_CONTROL		0x0092	/* 8 bit */
107#define  TI113X_DCR_5V_FORCE		0x40
108#define  TI113X_DCR_3V_FORCE		0x20
109#define  TI113X_DCR_IMODE_MASK		0x06
110#define  TI113X_DCR_IMODE_ISA		0x02
111#define  TI113X_DCR_IMODE_SERIAL	0x04
112
113#define  TI12XX_DCR_IMODE_PCI_ONLY	0x00
114#define  TI12XX_DCR_IMODE_ALL_SERIAL	0x06
115
116/* Buffer Control Register */
117#define TI113X_BUFFER_CONTROL		0x0093	/* 8 bit */
118#define  TI113X_BCR_CB_READ_DEPTH	0x08
119#define  TI113X_BCR_CB_WRITE_DEPTH	0x04
120#define  TI113X_BCR_PCI_READ_DEPTH	0x02
121#define  TI113X_BCR_PCI_WRITE_DEPTH	0x01
122
123/* Diagnostic Register */
124#define TI1250_DIAGNOSTIC		0x0093	/* 8 bit */
125#define  TI1250_DIAG_TRUE_VALUE		0x80
126#define  TI1250_DIAG_PCI_IREQ		0x40
127#define  TI1250_DIAG_PCI_CSC		0x20
128#define  TI1250_DIAG_ASYNC_CSC		0x01
129
130/* DMA Registers */
131#define TI113X_DMA_0			0x0094	/* 32 bit */
132#define TI113X_DMA_1			0x0098	/* 32 bit */
133
134/* ExCA IO offset registers */
135#define TI113X_IO_OFFSET(map)		(0x36+((map)<<1))
136
137#ifdef CONFIG_CARDBUS
138
139/*
140 * Generic TI init - TI has an extension for the
141 * INTCTL register that sets the PCI CSC interrupt.
142 * Make sure we set it correctly at open and init
143 * time
144 * - open: disable the PCI CSC interrupt. This makes
145 *   it possible to use the CSC interrupt to probe the
146 *   ISA interrupts.
147 * - init: set the interrupt to match our PCI state.
148 *   This makes us correctly get PCI CSC interrupt
149 *   events.
150 */
151static int ti_open(pci_socket_t *socket)
152{
153	u8 new, reg = exca_readb(socket, I365_INTCTL);
154
155	new = reg & ~I365_INTR_ENA;
156	if (new != reg)
157		exca_writeb(socket, I365_INTCTL, new);
158	return 0;
159}
160
161static int ti_intctl(pci_socket_t *socket)
162{
163	u8 new, reg = exca_readb(socket, I365_INTCTL);
164
165	new = reg & ~I365_INTR_ENA;
166	if (socket->cb_irq)
167		new |= I365_INTR_ENA;
168	if (new != reg)
169		exca_writeb(socket, I365_INTCTL, new);
170	return 0;
171}
172
173/*
174 *	Zoom video control for TI122x/113x chips
175 */
176
177static void ti_zoom_video(pci_socket_t *socket, int onoff)
178{
179	u8 reg;
180
181	/* If we don't have a Zoom Video switch this is harmless,
182	   we just tristate the unused (ZV) lines */
183	reg = config_readb(socket, TI113X_CARD_CONTROL);
184	if (onoff)
185		/* Zoom zoom, we will all go together, zoom zoom, zoom zoom */
186		reg |= TI113X_CCR_ZVENABLE;
187	else
188		reg &= ~TI113X_CCR_ZVENABLE;
189	config_writeb(socket, TI113X_CARD_CONTROL, reg);
190}
191
192
193static void ti1250_zoom_video(pci_socket_t *socket, int onoff)
194{
195	int shift = 0;
196	u8 reg;
197
198	ti_zoom_video(socket, onoff);
199
200	reg = config_readb(socket, 0x84);
201	reg |= (1<<7);	/* ZV bus enable */
202
203	if(PCI_FUNC(socket->dev->devfn)==1)
204		shift = 1;
205
206	if(onoff)
207	{
208		reg &= ~(1<<6); 	/* Clear select bit */
209		reg |= shift<<6;	/* Favour our socket */
210		reg |= 1<<shift;	/* Socket zoom video on */
211	}
212	else
213	{
214		reg &= ~(1<<6); 	/* Clear select bit */
215		reg |= (1^shift)<<6;	/* Favour other socket */
216		reg &= ~(1<<shift);	/* Socket zoon video off */
217	}
218
219	config_writeb(socket, 0x84, reg);
220}
221
222static void ti_set_zv(pci_socket_t *socket)
223{
224	if(socket->dev->vendor == PCI_VENDOR_ID_TI)
225	{
226		switch(socket->dev->device)
227		{
228			/* There may be more .. */
229			case PCI_DEVICE_ID_TI_1220:
230			case PCI_DEVICE_ID_TI_1221:
231			case PCI_DEVICE_ID_TI_1225:
232				socket->zoom_video = ti_zoom_video;
233				break;
234			case PCI_DEVICE_ID_TI_1250:
235			case PCI_DEVICE_ID_TI_1251A:
236			case PCI_DEVICE_ID_TI_1251B:
237			case PCI_DEVICE_ID_TI_1450:
238				socket->zoom_video = ti1250_zoom_video;
239		}
240	}
241}
242
243static int ti_init(pci_socket_t *socket)
244{
245	yenta_init(socket);
246	ti_set_zv(socket);
247	ti_intctl(socket);
248	return 0;
249}
250
251static struct pci_socket_ops ti_ops = {
252	ti_open,
253	yenta_close,
254	ti_init,
255	yenta_suspend,
256	yenta_get_status,
257	yenta_get_socket,
258	yenta_set_socket,
259	yenta_get_io_map,
260	yenta_set_io_map,
261	yenta_get_mem_map,
262	yenta_set_mem_map,
263	yenta_proc_setup
264};
265
266#define ti_sysctl(socket)	((socket)->private[0])
267#define ti_cardctl(socket)	((socket)->private[1])
268#define ti_devctl(socket)	((socket)->private[2])
269
270static int ti113x_open(pci_socket_t *socket)
271{
272	ti_sysctl(socket) = config_readl(socket, TI113X_SYSTEM_CONTROL);
273	ti_cardctl(socket) = config_readb(socket, TI113X_CARD_CONTROL);
274	ti_devctl(socket) = config_readb(socket, TI113X_DEVICE_CONTROL);
275
276	ti_cardctl(socket) &= ~(TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_IREQ | TI113X_CCR_PCI_CSC);
277	if (socket->cb_irq)
278		ti_cardctl(socket) |= TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_CSC | TI113X_CCR_PCI_IREQ;
279	ti_open(socket);
280	return 0;
281}
282
283static int ti113x_init(pci_socket_t *socket)
284{
285	yenta_init(socket);
286
287	config_writel(socket, TI113X_SYSTEM_CONTROL, ti_sysctl(socket));
288	config_writeb(socket, TI113X_CARD_CONTROL, ti_cardctl(socket));
289	config_writeb(socket, TI113X_DEVICE_CONTROL, ti_devctl(socket));
290	ti_intctl(socket);
291	return 0;
292}
293
294static struct pci_socket_ops ti113x_ops = {
295	ti113x_open,
296	yenta_close,
297	ti113x_init,
298	yenta_suspend,
299	yenta_get_status,
300	yenta_get_socket,
301	yenta_set_socket,
302	yenta_get_io_map,
303	yenta_set_io_map,
304	yenta_get_mem_map,
305	yenta_set_mem_map,
306	yenta_proc_setup
307};
308
309#define ti_diag(socket)		((socket)->private[0])
310
311static int ti1250_open(pci_socket_t *socket)
312{
313	ti_diag(socket) = config_readb(socket, TI1250_DIAGNOSTIC);
314
315	ti_diag(socket) &= ~(TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ);
316	if (socket->cb_irq)
317		ti_diag(socket) |= TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ;
318	ti_open(socket);
319	return 0;
320}
321
322static int ti1250_init(pci_socket_t *socket)
323{
324	yenta_init(socket);
325	ti_set_zv(socket);
326	config_writeb(socket, TI1250_DIAGNOSTIC, ti_diag(socket));
327	ti_intctl(socket);
328	return 0;
329}
330
331static struct pci_socket_ops ti1250_ops = {
332	ti1250_open,
333	yenta_close,
334	ti1250_init,
335	yenta_suspend,
336	yenta_get_status,
337	yenta_get_socket,
338	yenta_set_socket,
339	yenta_get_io_map,
340	yenta_set_io_map,
341	yenta_get_mem_map,
342	yenta_set_mem_map,
343	yenta_proc_setup
344};
345
346#endif /* CONFIG_CARDBUS */
347
348#endif /* _LINUX_TI113X_H */
349
350