1/* 2 * linux/arch/alpha/kernel/sys_miata.c 3 * 4 * Copyright (C) 1995 David A Rusling 5 * Copyright (C) 1996 Jay A Estabrook 6 * Copyright (C) 1998, 1999, 2000 Richard Henderson 7 * 8 * Code supporting the MIATA (EV56+PYXIS). 9 */ 10 11#include <linux/kernel.h> 12#include <linux/types.h> 13#include <linux/mm.h> 14#include <linux/sched.h> 15#include <linux/pci.h> 16#include <linux/init.h> 17#include <linux/reboot.h> 18 19#include <asm/ptrace.h> 20#include <asm/system.h> 21#include <asm/dma.h> 22#include <asm/irq.h> 23#include <asm/mmu_context.h> 24#include <asm/io.h> 25#include <asm/pgtable.h> 26#include <asm/core_cia.h> 27 28#include "proto.h" 29#include "irq_impl.h" 30#include "pci_impl.h" 31#include "machvec_impl.h" 32 33 34static void 35miata_srm_device_interrupt(unsigned long vector, struct pt_regs * regs) 36{ 37 int irq; 38 39 irq = (vector - 0x800) >> 4; 40 41 /* 42 * I really hate to do this, but the MIATA SRM console ignores the 43 * low 8 bits in the interrupt summary register, and reports the 44 * vector 0x80 *lower* than I expected from the bit numbering in 45 * the documentation. 46 * This was done because the low 8 summary bits really aren't used 47 * for reporting any interrupts (the PCI-ISA bridge, bit 7, isn't 48 * used for this purpose, as PIC interrupts are delivered as the 49 * vectors 0x800-0x8f0). 50 * But I really don't want to change the fixup code for allocation 51 * of IRQs, nor the alpha_irq_mask maintenance stuff, both of which 52 * look nice and clean now. 53 * So, here's this grotty hack... :-( 54 */ 55 if (irq >= 16) 56 irq = irq + 8; 57 58 handle_irq(irq, regs); 59} 60 61static void __init 62miata_init_irq(void) 63{ 64 if (alpha_using_srm) 65 alpha_mv.device_interrupt = miata_srm_device_interrupt; 66 67 68 init_i8259a_irqs(); 69 70 /* Not interested in the bogus interrupts (3,10), Fan Fault (0), 71 NMI (1), or EIDE (9). 72 73 We also disable the risers (4,5), since we don't know how to 74 route the interrupts behind the bridge. */ 75 init_pyxis_irqs(0x63b0000); 76 77 common_init_isa_dma(); 78 setup_irq(16+2, &halt_switch_irqaction); /* SRM only? */ 79 setup_irq(16+6, &timer_cascade_irqaction); 80} 81 82 83/* 84 * PCI Fixup configuration. 85 * 86 * Summary @ PYXIS_INT_REQ: 87 * Bit Meaning 88 * 0 Fan Fault 89 * 1 NMI 90 * 2 Halt/Reset switch 91 * 3 none 92 * 4 CID0 (Riser ID) 93 * 5 CID1 (Riser ID) 94 * 6 Interval timer 95 * 7 PCI-ISA Bridge 96 * 8 Ethernet 97 * 9 EIDE (deprecated, ISA 14/15 used) 98 *10 none 99 *11 USB 100 *12 Interrupt Line A from slot 4 101 *13 Interrupt Line B from slot 4 102 *14 Interrupt Line C from slot 4 103 *15 Interrupt Line D from slot 4 104 *16 Interrupt Line A from slot 5 105 *17 Interrupt line B from slot 5 106 *18 Interrupt Line C from slot 5 107 *19 Interrupt Line D from slot 5 108 *20 Interrupt Line A from slot 1 109 *21 Interrupt Line B from slot 1 110 *22 Interrupt Line C from slot 1 111 *23 Interrupt Line D from slot 1 112 *24 Interrupt Line A from slot 2 113 *25 Interrupt Line B from slot 2 114 *26 Interrupt Line C from slot 2 115 *27 Interrupt Line D from slot 2 116 *27 Interrupt Line A from slot 3 117 *29 Interrupt Line B from slot 3 118 *30 Interrupt Line C from slot 3 119 *31 Interrupt Line D from slot 3 120 * 121 * The device to slot mapping looks like: 122 * 123 * Slot Device 124 * 3 DC21142 Ethernet 125 * 4 EIDE CMD646 126 * 5 none 127 * 6 USB 128 * 7 PCI-ISA bridge 129 * 8 PCI-PCI Bridge (SBU Riser) 130 * 9 none 131 * 10 none 132 * 11 PCI on board slot 4 (SBU Riser) 133 * 12 PCI on board slot 5 (SBU Riser) 134 * 135 * These are behind the bridge, so I'm not sure what to do... 136 * 137 * 13 PCI on board slot 1 (SBU Riser) 138 * 14 PCI on board slot 2 (SBU Riser) 139 * 15 PCI on board slot 3 (SBU Riser) 140 * 141 * 142 * This two layered interrupt approach means that we allocate IRQ 16 and 143 * above for PCI interrupts. The IRQ relates to which bit the interrupt 144 * comes in on. This makes interrupt processing much easier. 145 */ 146 147static int __init 148miata_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 149{ 150 static char irq_tab[18][5] __initdata = { 151 /*INT INTA INTB INTC INTD */ 152 {16+ 8, 16+ 8, 16+ 8, 16+ 8, 16+ 8}, /* IdSel 14, DC21142 */ 153 { -1, -1, -1, -1, -1}, /* IdSel 15, EIDE */ 154 { -1, -1, -1, -1, -1}, /* IdSel 16, none */ 155 { -1, -1, -1, -1, -1}, /* IdSel 17, none */ 156 { -1, -1, -1, -1, -1}, /* IdSel 18, PCI-ISA */ 157 { -1, -1, -1, -1, -1}, /* IdSel 19, PCI-PCI */ 158 { -1, -1, -1, -1, -1}, /* IdSel 20, none */ 159 { -1, -1, -1, -1, -1}, /* IdSel 21, none */ 160 {16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 22, slot 4 */ 161 {16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 23, slot 5 */ 162 /* the next 7 are actually on PCI bus 1, across the bridge */ 163 {16+11, 16+11, 16+11, 16+11, 16+11}, /* IdSel 24, QLISP/GL*/ 164 { -1, -1, -1, -1, -1}, /* IdSel 25, none */ 165 { -1, -1, -1, -1, -1}, /* IdSel 26, none */ 166 { -1, -1, -1, -1, -1}, /* IdSel 27, none */ 167 {16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 28, slot 1 */ 168 {16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 29, slot 2 */ 169 {16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 30, slot 3 */ 170 /* This bridge is on the main bus of the later orig MIATA */ 171 { -1, -1, -1, -1, -1}, /* IdSel 31, PCI-PCI */ 172 }; 173 const long min_idsel = 3, max_idsel = 20, irqs_per_slot = 5; 174 175 /* the USB function of the 82c693 has it's interrupt connected to 176 the 2nd 8259 controller. So we have to check for it first. */ 177 178 if((slot == 7) && (PCI_FUNC(dev->devfn) == 3)) { 179 u8 irq=0; 180 181 if(pci_read_config_byte(pci_find_slot(dev->bus->number, dev->devfn & ~(7)), 0x40,&irq)!=PCIBIOS_SUCCESSFUL) 182 return -1; 183 else 184 return irq; 185 } 186 187 return COMMON_TABLE_LOOKUP; 188} 189 190static u8 __init 191miata_swizzle(struct pci_dev *dev, u8 *pinp) 192{ 193 int slot, pin = *pinp; 194 195 if (dev->bus->number == 0) { 196 slot = PCI_SLOT(dev->devfn); 197 } 198 /* Check for the built-in bridge. */ 199 else if ((PCI_SLOT(dev->bus->self->devfn) == 8) || 200 (PCI_SLOT(dev->bus->self->devfn) == 20)) { 201 slot = PCI_SLOT(dev->devfn) + 9; 202 } 203 else 204 { 205 /* Must be a card-based bridge. */ 206 do { 207 if ((PCI_SLOT(dev->bus->self->devfn) == 8) || 208 (PCI_SLOT(dev->bus->self->devfn) == 20)) { 209 slot = PCI_SLOT(dev->devfn) + 9; 210 break; 211 } 212 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); 213 214 /* Move up the chain of bridges. */ 215 dev = dev->bus->self; 216 /* Slot of the next bridge. */ 217 slot = PCI_SLOT(dev->devfn); 218 } while (dev->bus->self); 219 } 220 *pinp = pin; 221 return slot; 222} 223 224static void __init 225miata_init_pci(void) 226{ 227 cia_init_pci(); 228 /* The PYXIS has data corruption problem with scatter/gather 229 burst DMA reads crossing 8K boundary. It had been fixed 230 with off-chip logic on all PYXIS systems except first 231 MIATAs, so disable SG DMA on such machines. */ 232 if (!SMC669_Init(0)) { /* MIATA GL has SMC37c669 Super I/O */ 233 alpha_mv.mv_pci_tbi = NULL; 234 printk(KERN_INFO "pci: pyxis 8K boundary dma bug - " 235 "sg dma disabled\n"); 236 } 237 es1888_init(); 238} 239 240static void 241miata_kill_arch(int mode) 242{ 243 switch(mode) { 244 case LINUX_REBOOT_CMD_RESTART: 245 /* Who said DEC engineers have no sense of humor? ;-) */ 246 if (alpha_using_srm) { 247 *(vuip) PYXIS_RESET = 0x0000dead; 248 mb(); 249 } 250 break; 251 case LINUX_REBOOT_CMD_HALT: 252 break; 253 case LINUX_REBOOT_CMD_POWER_OFF: 254 break; 255 } 256 257 halt(); 258} 259 260 261/* 262 * The System Vector 263 */ 264 265struct alpha_machine_vector miata_mv __initmv = { 266 vector_name: "Miata", 267 DO_EV5_MMU, 268 DO_DEFAULT_RTC, 269 DO_PYXIS_IO, 270 DO_CIA_BUS, 271 machine_check: cia_machine_check, 272 max_dma_address: ALPHA_MAX_DMA_ADDRESS, 273 min_io_address: DEFAULT_IO_BASE, 274 min_mem_address: DEFAULT_MEM_BASE, 275 pci_dac_offset: PYXIS_DAC_OFFSET, 276 277 nr_irqs: 48, 278 device_interrupt: pyxis_device_interrupt, 279 280 init_arch: pyxis_init_arch, 281 init_irq: miata_init_irq, 282 init_rtc: common_init_rtc, 283 init_pci: miata_init_pci, 284 kill_arch: miata_kill_arch, 285 pci_map_irq: miata_map_irq, 286 pci_swizzle: miata_swizzle, 287}; 288ALIAS_MV(miata) 289