1/*
2 * HND SiliconBackplane MIPS core software interface.
3 *
4 * Copyright 2007, Broadcom Corporation
5 * All Rights Reserved.
6 *
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11 *
12 * $Id: hndmips.h,v 1.1.1.1 2008/10/15 03:25:54 james26_jang Exp $
13 */
14
15#ifndef _hndmips_h_
16#define _hndmips_h_
17
18extern void sb_mips_init(sb_t *sbh, uint shirq_map_base);
19extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
20extern void enable_pfc(uint32 mode);
21extern uint32 sb_memc_get_ncdl(sb_t *sbh);
22
23#if defined(BCMPERFSTATS)
24/* enable counting - exclusive version. Only one set of counters allowed at a time */
25extern void hndmips_perf_cyclecount_enable(void);
26extern void hndmips_perf_instrcount_enable(void);
27extern void hndmips_perf_icachecount_enable(void);
28extern void hndmips_perf_dcachecount_enable(void);
29/* start and stop counting */
30#define hndmips_perf_start01() \
31	MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000)
32#define hndmips_perf_stop01() \
33	MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000)
34/* retrieve coutners - counters *decrement* */
35#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0))
36#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1))
37#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2))
38/* enable counting - modular version. Each counters can be enabled separately. */
39extern void hndmips_perf_icache_hit_enable(void);
40extern void hndmips_perf_icache_miss_enable(void);
41extern uint32 hndmips_perf_read_instrcount(void);
42extern uint32 hndmips_perf_read_cache_miss(void);
43extern uint32 hndmips_perf_read_cache_hit(void);
44#endif
45
46#endif /* _hndmips_h_ */
47