Searched refs:vuint8 (Results 1 - 25 of 40) sorted by path

12

/haiku/headers/private/graphics/matrox/
H A Dmga_macros.h308 #define MGA_REG8(r_) ((vuint8 *)regs)[(r_)]
/haiku/headers/private/graphics/neomagic/
H A Dnm_macros.h302 #define NM_REG8(r_) ((vuint8 *)regs)[(r_)]
306 #define NM_2REG8(r_) ((vuint8 *)regs2)[(r_)]
/haiku/headers/private/graphics/radeon/
H A Dpll_access.h19 void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic );
24 void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic );
36 uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr );
39 void Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val );
42 void Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val, uint32 mask );
/haiku/headers/private/graphics/skeleton/
H A Dmacros.h741 #define ENG_REG8(r_) ((vuint8 *)regs)[(r_)]
/haiku/headers/private/graphics/via/
H A Dmacros.h804 #define ENG_REG8(r_) ((vuint8 *)regs)[(r_)]
/haiku/src/add-ons/accelerants/3dfx/
H A Daccelerant.h177 #define INREG8(addr) *((vuint8*)(gInfo.regs + addr))
181 #define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val
/haiku/src/add-ons/accelerants/ati/
H A Daccelerant.h236 #define INREG8(addr) *((vuint8*)(gInfo.regs + addr))
240 #define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val
/haiku/src/add-ons/accelerants/et6x00/
H A DAcceleration.c201 ((vuint8 *)((uint32)si->memory + srcAddr))[i] = ((uint8 *)&color)[i];
/haiku/src/add-ons/accelerants/intel_810/
H A Di810_regs.h111 #define INREG8(addr) (*((vuint8*)(gInfo.regs + (addr))))
115 #define OUTREG8(addr, val) (*((vuint8*)(gInfo.regs + (addr))) = (val))
/haiku/src/add-ons/accelerants/matrox/engine/
H A Dmga_crtc.c613 vuint8 * cursor;
616 cursor = (vuint8*) si->framebuffer;
/haiku/src/add-ons/accelerants/radeon/
H A DSetDisplayMode.c86 vuint8 *regs = ai->regs;
111 vuint8 *regs = ai->regs;
H A Dcrtc.c22 vuint8 *regs = ai->regs;
H A Ddpms.c59 vuint8 *regs = ai->regs;
97 vuint8 *regs = ai->regs;
119 vuint8 *regs = ai->regs;
150 vuint8 *regs = ai->regs;
172 vuint8 *regs = ai->regs;
198 vuint8 *regs = ai->regs;
240 vuint8 *regs = ai->regs;
H A Dflat_panel.c23 vuint8 *regs = ai->regs;
110 vuint8 *regs = ai->regs;
120 vuint8 *regs = ai->regs;
254 vuint8 *regs = ai->regs;
H A Dinternal_tv_out.c93 vuint8 *regs = ai->regs;
129 vuint8 *regs = ai->regs;
161 vuint8 *regs = ai->regs;
233 vuint8 *regs = ai->regs;
H A Dmonitor_detection.c40 vuint8 *regs = info->ai->regs;
56 vuint8 *regs = info->ai->regs;
104 vuint8 *regs = ai->regs;
180 vuint8 *regs = ai->regs;
231 vuint8 *regs = ai->regs;
334 vuint8 *regs = ai->regs;
419 vuint8 *regs = ai->regs;
H A Dmonitor_routing.c29 vuint8 *regs = ai->regs;
422 vuint8 *regs = ai->regs;
H A Doverlay.c56 vuint8 *regs = ai->regs;
162 vuint8 *regs = ai->regs;
317 vuint8 *regs = ai->regs;
534 vuint8 *regs = ai->regs;
965 vuint8 *regs = ai->regs;
H A Dradeon_accelerant.h44 vuint8 *regs; // pointer to mapped registers
/haiku/src/add-ons/accelerants/s3/
H A Dregister_io.cpp17 #define INREG8(addr) *((vuint8*)(gInfo.regs + addr))
21 #define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val
/haiku/src/add-ons/kernel/drivers/graphics/radeon/
H A Dirq.c30 Radeon_ThreadInterruptWork(vuint8 *regs, device_info *di, uint32 int_status)
71 Radeon_HandleCaptureInterrupt(vuint8 *regs, device_info *di, uint32 cap_status)
106 vuint8 *regs = di->regs;
154 vuint8 *regs = di->regs;
H A Dpll_access.c16 void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic )
28 void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic )
59 uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr )
71 void Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val )
84 void Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr,
H A Dradeon_driver.h103 vuint8 *regs;
/haiku/headers/os/support/
H A DSupportDefs.h31 typedef volatile uint8 vuint8; typedef
/haiku/headers/private/graphics/nvidia/
H A Dnv_macros.h888 #define NV_REG8(r_) ((vuint8 *)regs)[(r_)]

Completed in 268 milliseconds

12