1/* NV registers definitions and macros for access to them */ 2 3/* PCI_config_space */ 4#define NVCFG_DEVID 0x00 5#define NVCFG_DEVCTRL 0x04 6#define NVCFG_CLASS 0x08 7#define NVCFG_HEADER 0x0c 8#define NVCFG_BASE1REGS 0x10 9#define NVCFG_BASE2FB 0x14 10#define NVCFG_BASE3 0x18 11#define NVCFG_BASE4 0x1c //unknown if used 12#define NVCFG_BASE5 0x20 //unknown if used 13#define NVCFG_BASE6 0x24 //unknown if used 14#define NVCFG_BASE7 0x28 //unknown if used 15#define NVCFG_SUBSYSID1 0x2c 16#define NVCFG_ROMBASE 0x30 17#define NVCFG_CAPPTR 0x34 18#define NVCFG_CFG_1 0x38 //unknown if used 19#define NVCFG_INTERRUPT 0x3c 20#define NVCFG_SUBSYSID2 0x40 21#define NVCFG_AGPREF 0x44 22#define NVCFG_AGPSTAT 0x48 23#define NVCFG_AGPCMD 0x4c 24#define NVCFG_ROMSHADOW 0x50 25#define NVCFG_VGA 0x54 26#define NVCFG_SCHRATCH 0x58 27#define NVCFG_CFG_10 0x5c 28#define NVCFG_CFG_11 0x60 29#define NVCFG_CFG_12 0x64 30#define NVCFG_CFG_13 0x68 //unknown if used 31#define NVCFG_CFG_14 0x6c //unknown if used 32#define NVCFG_CFG_15 0x70 //unknown if used 33#define NVCFG_CFG_16 0x74 //unknown if used 34#define NVCFG_PCIEREF 0x78 35#define NVCFG_PCIEDCAP 0x7c 36#define NVCFG_PCIEDCTST 0x80 37#define NVCFG_PCIELCAP 0x84 38#define NVCFG_PCIELCTST 0x88 39#define NVCFG_CFG_22 0x8c //unknown if used 40#define NVCFG_CFG_23 0x90 //unknown if used 41#define NVCFG_CFG_24 0x94 //unknown if used 42#define NVCFG_CFG_25 0x98 //unknown if used 43#define NVCFG_CFG_26 0x9c //unknown if used 44#define NVCFG_CFG_27 0xa0 //unknown if used 45#define NVCFG_CFG_28 0xa4 //unknown if used 46#define NVCFG_CFG_29 0xa8 //unknown if used 47#define NVCFG_CFG_30 0xac //unknown if used 48#define NVCFG_CFG_31 0xb0 //unknown if used 49#define NVCFG_CFG_32 0xb4 //unknown if used 50#define NVCFG_CFG_33 0xb8 //unknown if used 51#define NVCFG_CFG_34 0xbc //unknown if used 52#define NVCFG_CFG_35 0xc0 //unknown if used 53#define NVCFG_CFG_36 0xc4 //unknown if used 54#define NVCFG_CFG_37 0xc8 //unknown if used 55#define NVCFG_CFG_38 0xcc //unknown if used 56#define NVCFG_CFG_39 0xd0 //unknown if used 57#define NVCFG_CFG_40 0xd4 //unknown if used 58#define NVCFG_CFG_41 0xd8 //unknown if used 59#define NVCFG_CFG_42 0xdc //unknown if used 60#define NVCFG_CFG_43 0xe0 //unknown if used 61#define NVCFG_CFG_44 0xe4 //unknown if used 62#define NVCFG_CFG_45 0xe8 //unknown if used 63#define NVCFG_CFG_46 0xec //unknown if used 64#define NVCFG_CFG_47 0xf0 //unknown if used 65#define NVCFG_CFG_48 0xf4 //unknown if used 66#define NVCFG_CFG_49 0xf8 //unknown if used 67#define NVCFG_CFG_50 0xfc //unknown if used 68 69/* used NV INT registers for vblank */ 70#define NV32_MAIN_INTE 0x00000140 71#define NV32_CRTC_INTS 0x00600100 72#define NV32_CRTC_INTE 0x00600140 73#define NV32_CRTC2_INTS 0x00602100 74#define NV32_CRTC2_INTE 0x00602140 75 76/* NV ACCeleration registers */ 77/* engine initialisation registers */ 78#define NVACC_ABS_UCLP_XMIN 0x0040053c 79#define NVACC_ABS_UCLP_YMIN 0x00400540 80#define NVACC_ABS_UCLP_XMAX 0x00400544 81#define NVACC_ABS_UCLP_YMAX 0x00400548 82#define NVACC_BETA_AND_VAL 0x00400608 83#define NVACC_FORMATS 0x00400618 84#define NVACC_OFFSET0 0x00400640 85#define NVACC_OFFSET1 0x00400644 86#define NVACC_OFFSET2 0x00400648 87#define NVACC_OFFSET3 0x0040064c 88#define NVACC_OFFSET4 0x00400650 89#define NVACC_OFFSET5 0x00400654 90#define NVACC_BBASE0 0x00400658 91#define NVACC_BBASE1 0x0040065c 92#define NVACC_BBASE2 0x00400660 93#define NVACC_BBASE3 0x00400664 94#define NVACC_NV10_BBASE4 0x00400668 95#define NVACC_NV10_BBASE5 0x0040066c 96#define NVACC_PITCH0 0x00400670 97#define NVACC_PITCH1 0x00400674 98#define NVACC_PITCH2 0x00400678 99#define NVACC_PITCH3 0x0040067c 100#define NVACC_PITCH4 0x00400680 101#define NVACC_BLIMIT0 0x00400684 102#define NVACC_BLIMIT1 0x00400688 103#define NVACC_BLIMIT2 0x0040068c 104#define NVACC_BLIMIT3 0x00400690 105#define NVACC_NV10_BLIMIT4 0x00400694 106#define NVACC_NV10_BLIMIT5 0x00400698 107#define NVACC_BPIXEL 0x00400724 108#define NVACC_NV20_OFFSET0 0x00400820 109#define NVACC_NV20_OFFSET1 0x00400824 110#define NVACC_NV20_OFFSET2 0x00400828 111#define NVACC_NV20_OFFSET3 0x0040082c 112#define NVACC_STRD_FMT 0x00400830 113#define NVACC_NV20_PITCH0 0x00400850 114#define NVACC_NV20_PITCH1 0x00400854 115#define NVACC_NV20_PITCH2 0x00400858 116#define NVACC_NV20_PITCH3 0x0040085c 117#define NVACC_NV20_BLIMIT6 0x00400864 118#define NVACC_NV20_BLIMIT7 0x00400868 119#define NVACC_NV20_BLIMIT8 0x0040086c 120#define NVACC_NV20_BLIMIT9 0x00400870 121#define NVACC_NV25_WHAT1 0x00400890 122 123/* specials */ 124#define NVACC_DEBUG0 0x00400080 125#define NVACC_DEBUG1 0x00400084 126#define NVACC_DEBUG2 0x00400088 127#define NVACC_DEBUG3 0x0040008c 128#define NVACC_NV10_DEBUG4 0x00400090 129#define NVACC_NV10_DEBUG5 0x00400094 130#define NVACC_NV20_WHAT5 0x00400098 131#define NVACC_NV20_WHAT1 0x0040009c 132#define NVACC_ACC_INTS 0x00400100 133#define NVACC_ACC_INTE 0x00400140 134#define NVACC_NV10_CTX_CTRL 0x00400144 135#define NVACC_NV4X_DMA_SRC 0x00400220 136#define NVACC_NV4X_WHAT1 0x0040032c 137#define NVACC_NV4X_WHAT2 0x00405000 138#define NVACC_NV25_WHAT0 0x00400610 139#define NVACC_STATUS 0x00400700 140#define NVACC_NV04_SURF_TYP 0x0040070c 141#define NVACC_NV10_SURF_TYP 0x00400710 142#define NVACC_NV04_ACC_STAT 0x00400710 143#define NVACC_NV10_ACC_STAT 0x00400714 144#define NVACC_FIFO_EN 0x00400720 145#define NVACC_RDI_INDEX 0x00400750 146#define NVACC_RDI_DATA 0x00400754 147#define NVACC_PAT_SHP 0x00400810 148#define NVACC_NV40P_WHAT0 0x00400820 149#define NVACC_NV40P_WHAT1 0x00400824 150#define NVACC_NV40P_WHAT2 0x00400828 151#define NVACC_NV40P_WHAT3 0x0040082c 152#define NVACC_NV40P_OFFSET0 0x00400840 153#define NVACC_NV40P_OFFSET1 0x00400844 154#define NVACC_NV44_WHAT2 0x00400860 155#define NVACC_NV44_WHAT3 0x00400864 156//fixme? (guessed) 157#define NVACC_NV40P_PITCH0 0x00400870 158#define NVACC_NV40P_PITCH1 0x00400874 159#define NVACC_NV20_WHAT2 0x00400880 160//end fixme. 161#define NVACC_NV40P_BLIMIT6 0x004008a0 162#define NVACC_NV40P_BLIMIT7 0x004008a4 163#define NVACC_NV20_WHAT0 0x00400900 164#define NVACC_NV41_WHAT0 0x00400d00 165#define NVACC_NV20_2_WHAT0 0x00406900 166#define NVACC_NV40_WHAT0 0x004009b0 167#define NVACC_NV40_WHAT1 0x004009b4 168#define NVACC_NV40_WHAT2 0x004009b8 169#define NVACC_NV40_WHAT3 0x004009bc 170#define NVACC_NV20_WHAT3 0x00400b80 171#define NVACC_NV20_WHAT4 0x00400b84 172#define NVACC_NV25_WHAT2 0x00400b88 173#define NVACC_WINCLIP_H_0 0x00400f00 174#define NVACC_WINCLIP_H_1 0x00400f04 175#define NVACC_WINCLIP_H_2 0x00400f08 176#define NVACC_WINCLIP_H_3 0x00400f0c 177#define NVACC_WINCLIP_H_4 0x00400f10 178#define NVACC_WINCLIP_H_5 0x00400f14 179#define NVACC_WINCLIP_H_6 0x00400f18 180#define NVACC_WINCLIP_H_7 0x00400f1c 181#define NVACC_WINCLIP_V_0 0x00400f20 182#define NVACC_WINCLIP_V_1 0x00400f24 183#define NVACC_WINCLIP_V_2 0x00400f28 184#define NVACC_WINCLIP_V_3 0x00400f2c 185#define NVACC_WINCLIP_V_4 0x00400f30 186#define NVACC_WINCLIP_V_5 0x00400f34 187#define NVACC_WINCLIP_V_6 0x00400f38 188#define NVACC_WINCLIP_V_7 0x00400f3c 189#define NVACC_NV10_XFMOD0 0x00400f40 190#define NVACC_NV10_XFMOD1 0x00400f44 191#define NVACC_GLOB_STAT_0 0x00400f48 192#define NVACC_GLOB_STAT_1 0x00400f4c 193#define NVACC_NV10_PIPEADR 0x00400f50 194#define NVACC_NV10_PIPEDAT 0x00400f54 195/* PGRAPH unknown registers */ 196#define NVACC_PGWHAT_00 0x00400e00 197#define NVACC_PGWHAT_01 0x00400e04 198#define NVACC_PGWHAT_02 0x00400e08 199#define NVACC_PGWHAT_03 0x00400e0c 200#define NVACC_PGWHAT_04 0x00400e10 201#define NVACC_PGWHAT_05 0x00400e14 202#define NVACC_PGWHAT_06 0x00400e18 203#define NVACC_PGWHAT_07 0x00400e1c 204#define NVACC_PGWHAT_08 0x00400e20 205#define NVACC_PGWHAT_09 0x00400e24 206#define NVACC_PGWHAT_0A 0x00400e28 207#define NVACC_PGWHAT_0B 0x00400e2c 208#define NVACC_PGWHAT_0C 0x00400e30 209#define NVACC_PGWHAT_0D 0x00400e34 210#define NVACC_PGWHAT_0E 0x00400e38 211#define NVACC_PGWHAT_0F 0x00400e3c 212#define NVACC_PGWHAT_10 0x00400e40 213#define NVACC_PGWHAT_11 0x00400e44 214#define NVACC_PGWHAT_12 0x00400e48 215#define NVACC_PGWHAT_13 0x00400e4c 216#define NVACC_PGWHAT_14 0x00400e50 217#define NVACC_PGWHAT_15 0x00400e54 218#define NVACC_PGWHAT_16 0x00400e58 219#define NVACC_PGWHAT_17 0x00400e5c 220#define NVACC_PGWHAT_18 0x00400e60 221#define NVACC_PGWHAT_19 0x00400e64 222#define NVACC_PGWHAT_1A 0x00400e68 223#define NVACC_PGWHAT_1B 0x00400e6c 224#define NVACC_PGWHAT_1C 0x00400e70 225#define NVACC_PGWHAT_1D 0x00400e74 226#define NVACC_PGWHAT_1E 0x00400e78 227#define NVACC_PGWHAT_1F 0x00400e7c 228#define NVACC_PGWHAT_20 0x00400e80 229#define NVACC_PGWHAT_21 0x00400e84 230#define NVACC_PGWHAT_22 0x00400e88 231#define NVACC_PGWHAT_23 0x00400e8c 232#define NVACC_PGWHAT_24 0x00400e90 233#define NVACC_PGWHAT_25 0x00400e94 234#define NVACC_PGWHAT_26 0x00400e98 235#define NVACC_PGWHAT_27 0x00400e9c 236#define NVACC_PGWHAT_28 0x00400ea0 237#define NVACC_PGWHAT_29 0x00400ea4 238#define NVACC_PGWHAT_2A 0x00400ea8 239/* PGRAPH cache registers */ 240#define NVACC_CACHE1_1 0x00400160 241#define NVACC_CACHE1_2 0x00400180 242#define NVACC_CACHE1_3 0x004001a0 243#define NVACC_CACHE1_4 0x004001c0 244#define NVACC_CACHE1_5 0x004001e0 245#define NVACC_CACHE2_1 0x00400164 246#define NVACC_CACHE2_2 0x00400184 247#define NVACC_CACHE2_3 0x004001a4 248#define NVACC_CACHE2_4 0x004001c4 249#define NVACC_CACHE2_5 0x004001e4 250#define NVACC_CACHE3_1 0x00400168 251#define NVACC_CACHE3_2 0x00400188 252#define NVACC_CACHE3_3 0x004001a8 253#define NVACC_CACHE3_4 0x004001c8 254#define NVACC_CACHE3_5 0x004001e8 255#define NVACC_CACHE4_1 0x0040016c 256#define NVACC_CACHE4_2 0x0040018c 257#define NVACC_CACHE4_3 0x004001ac 258#define NVACC_CACHE4_4 0x004001cc 259#define NVACC_CACHE4_5 0x004001ec 260#define NVACC_NV10_CACHE5_1 0x00400170 261#define NVACC_NV04_CTX_CTRL 0x00400170 262#define NVACC_CACHE5_2 0x00400190 263#define NVACC_CACHE5_3 0x004001b0 264#define NVACC_CACHE5_4 0x004001d0 265#define NVACC_CACHE5_5 0x004001f0 266#define NVACC_NV10_CACHE6_1 0x00400174 267#define NVACC_CACHE6_2 0x00400194 268#define NVACC_CACHE6_3 0x004001b4 269#define NVACC_CACHE6_4 0x004001d4 270#define NVACC_CACHE6_5 0x004001f4 271#define NVACC_NV10_CACHE7_1 0x00400178 272#define NVACC_CACHE7_2 0x00400198 273#define NVACC_CACHE7_3 0x004001b8 274#define NVACC_CACHE7_4 0x004001d8 275#define NVACC_CACHE7_5 0x004001f8 276#define NVACC_NV10_CACHE8_1 0x0040017c 277#define NVACC_CACHE8_2 0x0040019c 278#define NVACC_CACHE8_3 0x004001bc 279#define NVACC_CACHE8_4 0x004001dc 280#define NVACC_CACHE8_5 0x004001fc 281#define NVACC_NV10_CTX_SW1 0x0040014c 282#define NVACC_NV10_CTX_SW2 0x00400150 283#define NVACC_NV10_CTX_SW3 0x00400154 284#define NVACC_NV10_CTX_SW4 0x00400158 285#define NVACC_NV10_CTX_SW5 0x0040015c 286/* engine tile registers src */ 287#define NVACC_NV10_FBTIL0AD 0x00100240 288#define NVACC_NV10_FBTIL0ED 0x00100244 289#define NVACC_NV10_FBTIL0PT 0x00100248 290#define NVACC_NV10_FBTIL0ST 0x0010024c 291#define NVACC_NV10_FBTIL1AD 0x00100250 292#define NVACC_NV10_FBTIL1ED 0x00100254 293#define NVACC_NV10_FBTIL1PT 0x00100258 294#define NVACC_NV10_FBTIL1ST 0x0010025c 295#define NVACC_NV10_FBTIL2AD 0x00100260 296#define NVACC_NV10_FBTIL2ED 0x00100264 297#define NVACC_NV10_FBTIL2PT 0x00100268 298#define NVACC_NV10_FBTIL2ST 0x0010026c 299#define NVACC_NV10_FBTIL3AD 0x00100270 300#define NVACC_NV10_FBTIL3ED 0x00100274 301#define NVACC_NV10_FBTIL3PT 0x00100278 302#define NVACC_NV10_FBTIL3ST 0x0010027c 303#define NVACC_NV10_FBTIL4AD 0x00100280 304#define NVACC_NV10_FBTIL4ED 0x00100284 305#define NVACC_NV10_FBTIL4PT 0x00100288 306#define NVACC_NV10_FBTIL4ST 0x0010028c 307#define NVACC_NV10_FBTIL5AD 0x00100290 308#define NVACC_NV10_FBTIL5ED 0x00100294 309#define NVACC_NV10_FBTIL5PT 0x00100298 310#define NVACC_NV10_FBTIL5ST 0x0010029c 311#define NVACC_NV10_FBTIL6AD 0x001002a0 312#define NVACC_NV10_FBTIL6ED 0x001002a4 313#define NVACC_NV10_FBTIL6PT 0x001002a8 314#define NVACC_NV10_FBTIL6ST 0x001002ac 315#define NVACC_NV10_FBTIL7AD 0x001002b0 316#define NVACC_NV10_FBTIL7ED 0x001002b4 317#define NVACC_NV10_FBTIL7PT 0x001002b8 318#define NVACC_NV10_FBTIL7ST 0x001002bc 319#define NVACC_NV41_FBTIL0AD 0x00100600 320#define NVACC_NV41_FBTIL0ED 0x00100604 321#define NVACC_NV41_FBTIL0PT 0x00100608 322#define NVACC_NV41_FBTIL0ST 0x0010060c 323#define NVACC_NV41_FBTIL1AD 0x00100610 324#define NVACC_NV41_FBTIL1ED 0x00100614 325#define NVACC_NV41_FBTIL1PT 0x00100618 326#define NVACC_NV41_FBTIL1ST 0x0010061c 327#define NVACC_NV41_FBTIL2AD 0x00100620 328#define NVACC_NV41_FBTIL2ED 0x00100624 329#define NVACC_NV41_FBTIL2PT 0x00100628 330#define NVACC_NV41_FBTIL2ST 0x0010062c 331#define NVACC_NV41_FBTIL3AD 0x00100630 332#define NVACC_NV41_FBTIL3ED 0x00100634 333#define NVACC_NV41_FBTIL3PT 0x00100638 334#define NVACC_NV41_FBTIL3ST 0x0010063c 335#define NVACC_NV41_FBTIL4AD 0x00100640 336#define NVACC_NV41_FBTIL4ED 0x00100644 337#define NVACC_NV41_FBTIL4PT 0x00100648 338#define NVACC_NV41_FBTIL4ST 0x0010064c 339#define NVACC_NV41_FBTIL5AD 0x00100650 340#define NVACC_NV41_FBTIL5ED 0x00100654 341#define NVACC_NV41_FBTIL5PT 0x00100658 342#define NVACC_NV41_FBTIL5ST 0x0010065c 343#define NVACC_NV41_FBTIL6AD 0x00100660 344#define NVACC_NV41_FBTIL6ED 0x00100664 345#define NVACC_NV41_FBTIL6PT 0x00100668 346#define NVACC_NV41_FBTIL6ST 0x0010066c 347#define NVACC_NV41_FBTIL7AD 0x00100670 348#define NVACC_NV41_FBTIL7ED 0x00100674 349#define NVACC_NV41_FBTIL7PT 0x00100678 350#define NVACC_NV41_FBTIL7ST 0x0010067c 351#define NVACC_NV41_FBTIL8AD 0x00100680 352#define NVACC_NV41_FBTIL8ED 0x00100684 353#define NVACC_NV41_FBTIL8PT 0x00100688 354#define NVACC_NV41_FBTIL8ST 0x0010068c 355#define NVACC_NV41_FBTIL9AD 0x00100690 356#define NVACC_NV41_FBTIL9ED 0x00100694 357#define NVACC_NV41_FBTIL9PT 0x00100698 358#define NVACC_NV41_FBTIL9ST 0x0010069c 359#define NVACC_NV41_FBTILAAD 0x001006a0 360#define NVACC_NV41_FBTILAED 0x001006a4 361#define NVACC_NV41_FBTILAPT 0x001006a8 362#define NVACC_NV41_FBTILAST 0x001006ac 363#define NVACC_NV41_FBTILBAD 0x001006b0 364#define NVACC_NV41_FBTILBED 0x001006b4 365#define NVACC_NV41_FBTILBPT 0x001006b8 366#define NVACC_NV41_FBTILBST 0x001006bc 367#define NVACC_G70_FBTILCAD 0x001006c0 368#define NVACC_G70_FBTILCED 0x001006c4 369#define NVACC_G70_FBTILCPT 0x001006c8 370#define NVACC_G70_FBTILCST 0x001006cc 371#define NVACC_G70_FBTILDAD 0x001006d0 372#define NVACC_G70_FBTILDED 0x001006d4 373#define NVACC_G70_FBTILDPT 0x001006d8 374#define NVACC_G70_FBTILDST 0x001006dc 375#define NVACC_G70_FBTILEAD 0x001006e0 376#define NVACC_G70_FBTILEED 0x001006e4 377#define NVACC_G70_FBTILEPT 0x001006e8 378#define NVACC_G70_FBTILEST 0x001006ec 379/* engine tile registers dst */ 380#define NVACC_NV20_WHAT_T0 0x004009a4 381#define NVACC_NV20_WHAT_T1 0x004009a8 382#define NVACC_NV40_WHAT_T2 0x004069a4 383#define NVACC_NV40_WHAT_T3 0x004069a8 384#define NVACC_NV40P_WHAT_T0 0x004009f0 385#define NVACC_NV40P_WHAT_T1 0x004009f4 386#define NVACC_G70_WHAT_T0 0x00400df0 387#define NVACC_G70_WHAT_T1 0x00400df4 388#define NVACC_NV40P_WHAT_T2 0x004069f0 389#define NVACC_NV40P_WHAT_T3 0x004069f4 390#define NVACC_NV10_TIL0AD 0x00400b00 391#define NVACC_NV10_TIL0ED 0x00400b04 392#define NVACC_NV10_TIL0PT 0x00400b08 393#define NVACC_NV10_TIL0ST 0x00400b0c 394#define NVACC_NV10_TIL1AD 0x00400b10 395#define NVACC_NV10_TIL1ED 0x00400b14 396#define NVACC_NV10_TIL1PT 0x00400b18 397#define NVACC_NV10_TIL1ST 0x00400b1c 398#define NVACC_NV10_TIL2AD 0x00400b20 399#define NVACC_NV10_TIL2ED 0x00400b24 400#define NVACC_NV10_TIL2PT 0x00400b28 401#define NVACC_NV10_TIL2ST 0x00400b2c 402#define NVACC_NV10_TIL3AD 0x00400b30 403#define NVACC_NV10_TIL3ED 0x00400b34 404#define NVACC_NV10_TIL3PT 0x00400b38 405#define NVACC_NV10_TIL3ST 0x00400b3c 406#define NVACC_NV10_TIL4AD 0x00400b40 407#define NVACC_NV10_TIL4ED 0x00400b44 408#define NVACC_NV10_TIL4PT 0x00400b48 409#define NVACC_NV10_TIL4ST 0x00400b4c 410#define NVACC_NV10_TIL5AD 0x00400b50 411#define NVACC_NV10_TIL5ED 0x00400b54 412#define NVACC_NV10_TIL5PT 0x00400b58 413#define NVACC_NV10_TIL5ST 0x00400b5c 414#define NVACC_NV10_TIL6AD 0x00400b60 415#define NVACC_NV10_TIL6ED 0x00400b64 416#define NVACC_NV10_TIL6PT 0x00400b68 417#define NVACC_NV10_TIL6ST 0x00400b6c 418#define NVACC_NV10_TIL7AD 0x00400b70 419#define NVACC_NV10_TIL7ED 0x00400b74 420#define NVACC_NV10_TIL7PT 0x00400b78 421#define NVACC_NV10_TIL7ST 0x00400b7c 422/* cache setup registers */ 423#define NVACC_PF_INTSTAT 0x00002100 424#define NVACC_PF_INTEN 0x00002140 425#define NVACC_PF_RAMHT 0x00002210 426#define NVACC_PF_RAMFC 0x00002214 427#define NVACC_PF_RAMRO 0x00002218 428#define NVACC_PF_CACHES 0x00002500 429#define NVACC_PF_MODE 0x00002504 430#define NVACC_PF_SIZE 0x0000250c 431#define NVACC_PF_CACH0_PSH0 0x00003000 432#define NVACC_PF_CACH0_PUL0 0x00003050 433#define NVACC_PF_CACH0_PUL1 0x00003054 434#define NVACC_PF_CACH1_PSH0 0x00003200 435#define NVACC_PF_CACH1_PSH1 0x00003204 436#define NVACC_PF_CACH1_DMAS 0x00003220 437#define NVACC_PF_CACH1_DMAF 0x00003224 438#define NVACC_PF_CACH1_DMAI 0x0000322c 439#define NVACC_PF_CACH1_DMAC 0x00003230 440#define NVACC_PF_CACH1_DMAP 0x00003240 441#define NVACC_PF_CACH1_DMAG 0x00003244 442#define NVACC_PF_CACH1_PUL0 0x00003250 443#define NVACC_PF_CACH1_PUL1 0x00003254 444#define NVACC_PF_CACH1_HASH 0x00003258 445#define NVACC_PF_CACH1_ENG 0x00003280 446/* Ptimer registers */ 447#define NVACC_PT_INTSTAT 0x00009100 448#define NVACC_PT_INTEN 0x00009140 449#define NVACC_PT_NUMERATOR 0x00009200 450#define NVACC_PT_DENOMINATR 0x00009210 451/* used PRAMIN registers */ 452#define NVACC_PR_CTX0_R 0x00711400 453#define NVACC_PR_CTX1_R 0x00711404 454#define NVACC_PR_CTX2_R 0x00711408 455#define NVACC_PR_CTX3_R 0x0071140c 456#define NVACC_PR_CTX0_0 0x00711420 457#define NVACC_PR_CTX1_0 0x00711424 458#define NVACC_PR_CTX2_0 0x00711428 459#define NVACC_PR_CTX3_0 0x0071142c 460#define NVACC_PR_CTX0_1 0x00711430 461#define NVACC_PR_CTX1_1 0x00711434 462#define NVACC_PR_CTX2_1 0x00711438 463#define NVACC_PR_CTX3_1 0x0071143c 464#define NVACC_PR_CTX0_2 0x00711440 465#define NVACC_PR_CTX1_2 0x00711444 466#define NVACC_PR_CTX2_2 0x00711448 467#define NVACC_PR_CTX3_2 0x0071144c 468#define NVACC_PR_CTX0_3 0x00711450 469#define NVACC_PR_CTX1_3 0x00711454 470#define NVACC_PR_CTX2_3 0x00711458 471#define NVACC_PR_CTX3_3 0x0071145c 472#define NVACC_PR_CTX0_4 0x00711460 473#define NVACC_PR_CTX1_4 0x00711464 474#define NVACC_PR_CTX2_4 0x00711468 475#define NVACC_PR_CTX3_4 0x0071146c 476#define NVACC_PR_CTX0_5 0x00711470 477#define NVACC_PR_CTX1_5 0x00711474 478#define NVACC_PR_CTX2_5 0x00711478 479#define NVACC_PR_CTX3_5 0x0071147c 480#define NVACC_PR_CTX0_6 0x00711480 481#define NVACC_PR_CTX1_6 0x00711484 482#define NVACC_PR_CTX2_6 0x00711488 483#define NVACC_PR_CTX3_6 0x0071148c 484#define NVACC_PR_CTX0_7 0x00711490 485#define NVACC_PR_CTX1_7 0x00711494 486#define NVACC_PR_CTX2_7 0x00711498 487#define NVACC_PR_CTX3_7 0x0071149c 488#define NVACC_PR_CTX0_8 0x007114a0 489#define NVACC_PR_CTX1_8 0x007114a4 490#define NVACC_PR_CTX2_8 0x007114a8 491#define NVACC_PR_CTX3_8 0x007114ac 492#define NVACC_PR_CTX0_9 0x007114b0 493#define NVACC_PR_CTX1_9 0x007114b4 494#define NVACC_PR_CTX2_9 0x007114b8 495#define NVACC_PR_CTX3_9 0x007114bc 496#define NVACC_PR_CTX0_A 0x007114c0 497#define NVACC_PR_CTX1_A 0x007114c4 /* not used */ 498#define NVACC_PR_CTX2_A 0x007114c8 499#define NVACC_PR_CTX3_A 0x007114cc 500#define NVACC_PR_CTX0_B 0x007114d0 501#define NVACC_PR_CTX1_B 0x007114d4 502#define NVACC_PR_CTX2_B 0x007114d8 503#define NVACC_PR_CTX3_B 0x007114dc 504#define NVACC_PR_CTX0_C 0x007114e0 505#define NVACC_PR_CTX1_C 0x007114e4 506#define NVACC_PR_CTX2_C 0x007114e8 507#define NVACC_PR_CTX3_C 0x007114ec 508#define NVACC_PR_CTX0_D 0x007114f0 509#define NVACC_PR_CTX1_D 0x007114f4 510#define NVACC_PR_CTX2_D 0x007114f8 511#define NVACC_PR_CTX3_D 0x007114fc 512#define NVACC_PR_CTX0_E 0x00711500 513#define NVACC_PR_CTX1_E 0x00711504 514#define NVACC_PR_CTX2_E 0x00711508 515#define NVACC_PR_CTX3_E 0x0071150c 516#define NVACC_PR_CTX0_F 0x00711510 517#define NVACC_PR_CTX1_F 0x00711514 518#define NVACC_PR_CTX2_F 0x00711518 519#define NVACC_PR_CTX3_F 0x0071151c 520#define NVACC_PR_CTX0_10 0x00711520 521#define NVACC_PR_CTX1_10 0x00711524 522#define NVACC_PR_CTX2_10 0x00711528 523#define NVACC_PR_CTX3_10 0x0071152c 524/* used RAMHT registers (hash-table) */ 525#define NVACC_HT_HANDL_00 0x00710000 526#define NVACC_HT_VALUE_00 0x00710004 527#define NVACC_HT_HANDL_01 0x00710008 528#define NVACC_HT_VALUE_01 0x0071000c 529#define NVACC_HT_HANDL_02 0x00710010 530#define NVACC_HT_VALUE_02 0x00710014 531#define NVACC_HT_HANDL_03 0x00710018 532#define NVACC_HT_VALUE_03 0x0071001c 533#define NVACC_HT_HANDL_04 0x00710020 534#define NVACC_HT_VALUE_04 0x00710024 535#define NVACC_HT_HANDL_05 0x00710028 536#define NVACC_HT_VALUE_05 0x0071002c 537#define NVACC_HT_HANDL_06 0x00710030 538#define NVACC_HT_VALUE_06 0x00710034 539#define NVACC_HT_HANDL_10 0x00710080 540#define NVACC_HT_VALUE_10 0x00710084 541#define NVACC_HT_HANDL_11 0x00710088 542#define NVACC_HT_VALUE_11 0x0071008c 543#define NVACC_HT_HANDL_12 0x00710090 544#define NVACC_HT_VALUE_12 0x00710094 545#define NVACC_HT_HANDL_13 0x00710098 546#define NVACC_HT_VALUE_13 0x0071009c 547#define NVACC_HT_HANDL_14 0x007100a0 548#define NVACC_HT_VALUE_14 0x007100a4 549#define NVACC_HT_HANDL_15 0x007100a8 550#define NVACC_HT_VALUE_15 0x007100ac 551#define NVACC_HT_HANDL_16 0x007100b0 552#define NVACC_HT_VALUE_16 0x007100b4 553#define NVACC_HT_HANDL_17 0x007100b8 554#define NVACC_HT_VALUE_17 0x007100bc 555 556/* acc engine fifo setup registers (for function_register 'mappings') */ 557#define NVACC_FIFO 0x00800000 558#define NVACC_FIFO_CH0 0x00800000 559#define NVACC_FIFO_CH1 0x00802000 560#define NVACC_FIFO_CH2 0x00804000 561#define NVACC_FIFO_CH3 0x00806000 562#define NVACC_FIFO_CH4 0x00808000 563#define NVACC_FIFO_CH5 0x0080a000 564#define NVACC_FIFO_CH6 0x0080c000 565#define NVACC_FIFO_CH7 0x0080e000 566 567/* Nvidia PCI direct registers */ 568#define NV32_PWRUPCTRL 0x00000200 569#define NV32_DUALHEAD_CTRL 0x000010f0//verify!!! 570#define NV8_MISCW 0x000c03c2 571#define NV8_MISCR 0x000c03cc 572#define NV8_VSE2 0x000c03c3 573#define NV8_SEQIND 0x000c03c4 574#define NV16_SEQIND 0x000c03c4 575#define NV8_SEQDAT 0x000c03c5 576#define NV8_GRPHIND 0x000c03ce 577#define NV16_GRPHIND 0x000c03ce 578#define NV8_GRPHDAT 0x000c03cf 579 580/* bootstrap info registers */ 581#define NV32_NV4STRAPINFO 0x00100000 582#define NV32_PFB_CONFIG_0 0x00100200 583#define NV32_PFB_CONFIG_1 0x00100204 584#define NV32_NV10STRAPINFO 0x0010020c 585#define NV32_FB_MRS1 0x001002c0 586#define NV32_FB_MRS2 0x001002c8 587#define NV32_PFB_CLS_PAGE2 0x0010033c 588#define NV32_NVSTRAPINFO2 0x00101000 589 590/* registers needed for 'coldstart' */ 591#define NV32_PFB_DEBUG_0 0x00100080 592#define NV32_PFB_REFCTRL 0x00100210 593#define NV32_COREPLL 0x00680500 594#define NV32_MEMPLL 0x00680504 595#define NV32_PLL_CTRL 0x00680510 596#define NV32_COREPLL2 0x00680570 /* NV31, NV36 only */ 597#define NV32_MEMPLL2 0x00680574 /* NV31, NV36 only */ 598#define NV32_CONFIG 0x00600804 599 600/* primary head */ 601#define NV8_ATTRINDW 0x006013c0 602#define NV8_ATTRDATW 0x006013c0 603#define NV8_ATTRDATR 0x006013c1 604#define NV8_CRTCIND 0x006013d4 605#define NV16_CRTCIND 0x006013d4 606#define NV8_CRTCDAT 0x006013d5 607#define NV8_INSTAT1 0x006013da 608#define NV32_NV10FBSTADD32 0x00600800 609#define NV32_RASTER 0x00600808 610#define NV32_NV10CURADD32 0x0060080c 611#define NV32_CURCONF 0x00600810 612#define NV32_PANEL_PWR 0x0060081c 613#define NV32_FUNCSEL 0x00600860 614#define NV32_NV4E_I2CBUS_0 0x00600870 615#define NV32_NV4E_I2CBUS_1 0x00600874 616#define NV32_NV4E_I2CBUS_2 0x00600850 617 618#define NV32_NV50_I2CBUS_0 0x0000e138 //confirmed 619#define NV32_NV50_I2CBUS_8 0x0000e150 //? 620#define NV32_NV50_I2CBUS_1 0x0000e168 //confirmed HDMI 621#define NV32_NV50_I2CBUS_2 0x0000e180 //confirmed laptop panel 622#define NV32_NV50_I2CBUS_6 0x0000e254 //? 623#define NV32_NV50_I2CBUS_7 0x0000e274 //? 624 625/* secondary head */ 626#define NV8_ATTR2INDW 0x006033c0 627#define NV8_ATTR2DATW 0x006033c0 628#define NV8_ATTR2DATR 0x006033c1 629#define NV8_CRTC2IND 0x006033d4 630#define NV16_CRTC2IND 0x006033d4 631#define NV8_CRTC2DAT 0x006033d5 632#define NV8_2INSTAT1 0x006033da//verify!!! 633#define NV32_NV10FB2STADD32 0x00602800 634#define NV32_RASTER2 0x00602808 635#define NV32_NV10CUR2ADD32 0x0060280c 636#define NV32_2CURCONF 0x00602810 637#define NV32_2PANEL_PWR 0x0060281c//verify!!! 638#define NV32_2FUNCSEL 0x00602860 639 640/* both heads */ 641#define NVACC_NV11_CRTC_LO 0x00600830 642#define NVACC_NV11_CRTC_HI 0x00600834 643 644/* Nvidia DAC direct registers (standard VGA palette RAM registers) */ 645/* primary head */ 646#define NV8_PALMASK 0x006813c6 647#define NV8_PALINDR 0x006813c7 648#define NV8_PALINDW 0x006813c8 649#define NV8_PALDATA 0x006813c9 650/* secondary head */ 651#define NV8_PAL2MASK 0x006833c6 652#define NV8_PAL2INDR 0x006833c7 653#define NV8_PAL2INDW 0x006833c8 654#define NV8_PAL2DATA 0x006833c9 655 656/* Nvidia PCI direct DAC registers (32bit) */ 657/* primary head */ 658#define NVDAC_CURPOS 0x00680300 659#define NVDAC_NV10_CURSYNC 0x00680404 660#define NVDAC_PIXPLLC 0x00680508 661#define NVDAC_PLLSEL 0x0068050c 662#define NVDAC_NV30_PLLSETUP 0x00680524 663#define NVDAC_NV11_DITHER 0x00680528 664#define NVDAC_OUTPUT 0x0068052c 665#define NVDAC_PIXPLLC2 0x00680578 666#define NVDAC_NV40_PLLSEL2 0x00680580 667#define NVDAC_GENCTRL 0x00680600 668#define NVDAC_TSTCTRL 0x00680608 669#define NVDAC_TSTDATA 0x00680610 670#define NVDAC_TV_SETUP 0x00680700 671/* (flatpanel registers: confirmed for TNT2 and up) */ 672#define NVDAC_FP_VDISPEND 0x00680800 673#define NVDAC_FP_VTOTAL 0x00680804 674#define NVDAC_FP_VCRTC 0x00680808 675#define NVDAC_FP_VSYNC_S 0x0068080c 676#define NVDAC_FP_VSYNC_E 0x00680810 677#define NVDAC_FP_VVALID_S 0x00680814 678#define NVDAC_FP_VVALID_E 0x00680818 679#define NVDAC_FP_HDISPEND 0x00680820 680#define NVDAC_FP_HTOTAL 0x00680824 681#define NVDAC_FP_HCRTC 0x00680828 682#define NVDAC_FP_HSYNC_S 0x0068082c 683#define NVDAC_FP_HSYNC_E 0x00680830 684#define NVDAC_FP_HVALID_S 0x00680834 685#define NVDAC_FP_HVALID_E 0x00680838 686#define NVDAC_FP_DITHER 0x0068083c 687#define NVDAC_FP_CHKSUM 0x00680840 688#define NVDAC_FP_TST_CTRL 0x00680844 689#define NVDAC_FP_TG_CTRL 0x00680848 690#define NVDAC_FP_DITH_PATT1 0x00680850 691#define NVDAC_FP_DITH_PATT2 0x00680854 692#define NVDAC_FP_DITH_PATT3 0x00680858 693#define NVDAC_FP_DITH_PATT4 0x0068085c 694#define NVDAC_FP_DITH_PATT5 0x00680860 695#define NVDAC_FP_DITH_PATT6 0x00680864 696#define NVDAC_FP_DEBUG0 0x00680880 697#define NVDAC_FP_DEBUG1 0x00680884 698#define NVDAC_FP_DEBUG2 0x00680888 699#define NVDAC_FP_DEBUG3 0x0068088c 700#define NVDAC_FP_TMDS_CTRL 0x006808b0 701#define NVDAC_FP_TMDS_DATA 0x006808b4 702 703/* secondary head */ 704#define NVDAC2_CURPOS 0x00682300 705#define NVDAC2_NV10_CURSYNC 0x00682404 706#define NVDAC2_PIXPLLC 0x00680520 707#define NVDAC2_OUTPUT 0x0068252c 708#define NVDAC2_PIXPLLC2 0x0068057c 709#define NVDAC2_GENCTRL 0x00682600 710#define NVDAC2_TSTCTRL 0x00682608 711#define NVDAC2_TV_SETUP 0x00682700 712/* (flatpanel registers) */ 713#define NVDAC2_FP_VDISPEND 0x00682800 714#define NVDAC2_FP_VTOTAL 0x00682804 715#define NVDAC2_FP_VCRTC 0x00682808 716#define NVDAC2_FP_VSYNC_S 0x0068280c 717#define NVDAC2_FP_VSYNC_E 0x00682810 718#define NVDAC2_FP_VVALID_S 0x00682814 719#define NVDAC2_FP_VVALID_E 0x00682818 720#define NVDAC2_FP_HDISPEND 0x00682820 721#define NVDAC2_FP_HTOTAL 0x00682824 722#define NVDAC2_FP_HCRTC 0x00682828 723#define NVDAC2_FP_HSYNC_S 0x0068282c 724#define NVDAC2_FP_HSYNC_E 0x00682830 725#define NVDAC2_FP_HVALID_S 0x00682834 726#define NVDAC2_FP_HVALID_E 0x00682838 727#define NVDAC2_FP_CHKSUM 0x00682840 728#define NVDAC2_FP_TST_CTRL 0x00682844 729#define NVDAC2_FP_TG_CTRL 0x00682848 730#define NVDAC2_FP_DEBUG0 0x00682880 731#define NVDAC2_FP_DEBUG1 0x00682884 732#define NVDAC2_FP_DEBUG2 0x00682888 733#define NVDAC2_FP_DEBUG3 0x0068288c 734#define NVDAC2_FP_TMDS_CTRL 0x006828b0//verify!!! 735#define NVDAC2_FP_TMDS_DATA 0x006828b4//verify!!! 736 737/* NV50 specific, CRTC offset = 0x540 */ 738#define NVDAC_CRTC_FB_PITCH 0x00610b20 // | linear = 0x00100000 739#define NVDAC_CRTC_FB_POS 0x00610b28 740 741/* Nvidia CRTC indexed registers */ 742/* VGA standard registers: */ 743#define NVCRTCX_HTOTAL 0x00 744#define NVCRTCX_HDISPE 0x01 745#define NVCRTCX_HBLANKS 0x02 746#define NVCRTCX_HBLANKE 0x03 747#define NVCRTCX_HSYNCS 0x04 748#define NVCRTCX_HSYNCE 0x05 749#define NVCRTCX_VTOTAL 0x06 750#define NVCRTCX_OVERFLOW 0x07 751#define NVCRTCX_PRROWSCN 0x08 752#define NVCRTCX_MAXSCLIN 0x09 753#define NVCRTCX_VGACURCTRL 0x0a 754#define NVCRTCX_FBSTADDH 0x0c 755#define NVCRTCX_FBSTADDL 0x0d 756#define NVCRTCX_VSYNCS 0x10 757#define NVCRTCX_VSYNCE 0x11 758#define NVCRTCX_VDISPE 0x12 759#define NVCRTCX_PITCHL 0x13 760#define NVCRTCX_VBLANKS 0x15 761#define NVCRTCX_VBLANKE 0x16 762#define NVCRTCX_MODECTL 0x17 763#define NVCRTCX_LINECOMP 0x18 764/* Nvidia specific registers: */ 765#define NVCRTCX_REPAINT0 0x19 766#define NVCRTCX_REPAINT1 0x1a 767#define NVCRTCX_FIFO 0x1b 768#define NVCRTCX_LOCK 0x1f 769#define NVCRTCX_FIFO_LWM 0x20 770#define NVCRTCX_BUFFER 0x21 771#define NVCRTCX_LSR 0x25 772#define NVCRTCX_PIXEL 0x28 773#define NVCRTCX_HEB 0x2d 774#define NVCRTCX_CURCTL2 0x2f 775#define NVCRTCX_CURCTL1 0x30 776#define NVCRTCX_CURCTL0 0x31 777#define NVCRTCX_LCD 0x33 778#define NVCRTCX_RD_I2CBUS_1 0x36 779#define NVCRTCX_WR_I2CBUS_1 0x37 780#define NVCRTCX_RMA 0x38 781#define NVCRTCX_INTERLACE 0x39 782#define NVCRTCX_TREG 0x3d 783#define NVCRTCX_RD_I2CBUS_0 0x3e 784#define NVCRTCX_WR_I2CBUS_0 0x3f 785#define NVCRTCX_EXTRA 0x41 786#define NVCRTCX_OWNER 0x44 787#define NVCRTCX_I2C_LOCK 0x49 788#define NVCRTCX_RD_I2CBUS_2 0x50 789#define NVCRTCX_WR_I2CBUS_2 0x51 790#define NVCRTCX_FP_HTIMING 0x53 791#define NVCRTCX_FP_VTIMING 0x54 792#define NVCRTCX_0x59 0x59 793#define NVCRTCX_0x9f 0x9f 794 795/* Nvidia ATTRIBUTE indexed registers */ 796/* VGA standard registers: */ 797#define NVATBX_MODECTL 0x10 798#define NVATBX_OSCANCOLOR 0x11 799#define NVATBX_COLPLANE_EN 0x12 800#define NVATBX_HORPIXPAN 0x13 801#define NVATBX_COLSEL 0x14 802 803/* Nvidia SEQUENCER indexed registers */ 804/* VGA standard registers: */ 805#define NVSEQX_RESET 0x00 806#define NVSEQX_CLKMODE 0x01 807#define NVSEQX_MEMMODE 0x04 808 809/* Nvidia GRAPHICS indexed registers */ 810/* VGA standard registers: */ 811#define NVGRPHX_ENSETRESET 0x01 812#define NVGRPHX_DATAROTATE 0x03 813#define NVGRPHX_READMAPSEL 0x04 814#define NVGRPHX_MODE 0x05 815#define NVGRPHX_MISC 0x06 816#define NVGRPHX_BITMASK 0x08 817 818/* Nvidia BES (Back End Scaler) registers (< NV10, including NV03, so RIVA128(ZX)) */ 819#define NVBES_NV04_INTE 0x00680140 820#define NVBES_NV04_ISCALVH 0x00680200 821#define NVBES_NV04_CTRL_V 0x00680204 822#define NVBES_NV04_CTRL_H 0x00680208 823#define NVBES_NV04_OE_STATE 0x00680224 824#define NVBES_NV04_SU_STATE 0x00680228 825#define NVBES_NV04_RM_STATE 0x0068022c 826#define NVBES_NV04_DSTREF 0x00680230 827#define NVBES_NV04_DSTSIZE 0x00680234 828#define NVBES_NV04_FIFOTHRS 0x00680238 829#define NVBES_NV04_FIFOBURL 0x0068023c 830#define NVBES_NV04_COLKEY 0x00680240 831#define NVBES_NV04_GENCTRL 0x00680244 832#define NVBES_NV04_RED_AMP 0x00680280 833#define NVBES_NV04_GRN_AMP 0x00680284 834#define NVBES_NV04_BLU_AMP 0x00680288 835#define NVBES_NV04_SAT 0x0068028c 836/* buffer 0 */ 837#define NVBES_NV04_0BUFADR 0x0068020c 838#define NVBES_NV04_0SRCPTCH 0x00680214 839#define NVBES_NV04_0OFFSET 0x0068021c 840/* buffer 1 */ 841#define NVBES_NV04_1BUFADR 0x00680210 842#define NVBES_NV04_1SRCPTCH 0x00680218 843#define NVBES_NV04_1OFFSET 0x00680220 844 845/* Nvidia BES (Back End Scaler) registers (>= NV10) */ 846#define NVBES_NV10_INTE 0x00008140 847#define NVBES_NV10_BUFSEL 0x00008700 848#define NVBES_NV10_GENCTRL 0x00008704 849#define NVBES_NV10_COLKEY 0x00008b00 850/* buffer 0 */ 851#define NVBES_NV10_0BUFADR 0x00008900 852#define NVBES_NV10_0MEMMASK 0x00008908 853#define NVBES_NV10_0BRICON 0x00008910 854#define NVBES_NV10_0SAT 0x00008918 855#define NVBES_NV10_0OFFSET 0x00008920 856#define NVBES_NV10_0SRCSIZE 0x00008928 857#define NVBES_NV10_0SRCREF 0x00008930 858#define NVBES_NV10_0ISCALH 0x00008938 859#define NVBES_NV10_0ISCALV 0x00008940 860#define NVBES_NV10_0DSTREF 0x00008948 861#define NVBES_NV10_0DSTSIZE 0x00008950 862#define NVBES_NV10_0SRCPTCH 0x00008958 863/* buffer 1 */ 864#define NVBES_NV10_1BUFADR 0x00008904 865#define NVBES_NV10_1MEMMASK 0x0000890c 866#define NVBES_NV10_1BRICON 0x00008914 867#define NVBES_NV10_1SAT 0x0000891c 868#define NVBES_NV10_1OFFSET 0x00008924 869#define NVBES_NV10_1SRCSIZE 0x0000892c 870#define NVBES_NV10_1SRCREF 0x00008934 871#define NVBES_NV10_1ISCALH 0x0000893c 872#define NVBES_NV10_1ISCALV 0x00008944 873#define NVBES_NV10_1DSTREF 0x0000894c 874#define NVBES_NV10_1DSTSIZE 0x00008954 875#define NVBES_NV10_1SRCPTCH 0x0000895c 876/* Nvidia MPEG2 hardware decoder (GeForce4MX only) */ 877#define NVBES_DEC_GENCTRL 0x00001588 878/* LVDS panel related registers */ 879#define NV32_LVDS_PWR 0x0000130c 880/* unknown registers */ 881#define NV32_NV4X_WHAT0 0x00001540 882#define NV32_NV44_WHAT10 0x00001700 883#define NV32_NV44_WHAT11 0x00001704 884#define NV32_NV44_WHAT12 0x00001708 885#define NV32_NV44_WHAT13 0x0000170c 886 887/* Macros for convenient accesses to the NV chips */ 888#define NV_REG8(r_) ((vuint8 *)regs)[(r_)] 889#define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 890#define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] 891 892/* read and write to PCI config space */ 893#define CFGR(A) (*(nv_pci_access.offset=NVCFG_##A, ioctl(fd,NV_GET_PCI, &nv_pci_access,sizeof(nv_pci_access)), &nv_pci_access.value)) 894#define CFGW(A,B) (nv_pci_access.offset=NVCFG_##A, nv_pci_access.value = B, ioctl(fd,NV_SET_PCI,&nv_pci_access,sizeof(nv_pci_access))) 895 896/* read and write from ISA I/O space */ 897#define ISAWB(A,B)(nv_isa_access.adress=A, nv_isa_access.data = (uint8)B, nv_isa_access.size = 1, ioctl(fd,NV_ISA_OUT, &nv_isa_access,sizeof(nv_isa_access))) 898#define ISAWW(A,B)(nv_isa_access.adress=A, nv_isa_access.data = B, nv_isa_access.size = 2, ioctl(fd,NV_ISA_OUT, &nv_isa_access,sizeof(nv_isa_access))) 899#define ISARB(A) (nv_isa_access.adress=A, ioctl(fd,NV_ISA_IN, &nv_isa_access,sizeof(nv_isa_access)), (uint8)nv_isa_access.data) 900#define ISARW(A) (nv_isa_access.adress=A, ioctl(fd,NV_ISA_IN, &nv_isa_access,sizeof(nv_isa_access)), nv_isa_access.data) 901 902/* read and write from the dac registers */ 903#define DACR(A) (NV_REG32(NVDAC_##A)) 904#define DACW(A,B) (NV_REG32(NVDAC_##A)=B) 905 906/* read and write from the secondary dac registers */ 907#define DAC2R(A) (NV_REG32(NVDAC2_##A)) 908#define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B) 909 910/* read and write from the backend scaler registers */ 911#define BESR(A) (NV_REG32(NVBES_##A)) 912#define BESW(A,B) (NV_REG32(NVBES_##A)=B) 913 914/* read and write from CRTC indexed registers */ 915#define CRTCW(A,B)(NV_REG16(NV16_CRTCIND) = ((NVCRTCX_##A) | ((B) << 8))) 916#define CRTCR(A) (NV_REG8(NV8_CRTCIND) = (NVCRTCX_##A), NV_REG8(NV8_CRTCDAT)) 917 918/* read and write from second CRTC indexed registers */ 919#define CRTC2W(A,B)(NV_REG16(NV16_CRTC2IND) = ((NVCRTCX_##A) | ((B) << 8))) 920#define CRTC2R(A) (NV_REG8(NV8_CRTC2IND) = (NVCRTCX_##A), NV_REG8(NV8_CRTC2DAT)) 921 922/* read and write from ATTRIBUTE indexed registers */ 923#define ATBW(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATW) = (B)) 924#define ATBR(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATR)) 925 926/* read and write from ATTRIBUTE indexed registers */ 927#define ATB2W(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATW) = (B)) 928#define ATB2R(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATR)) 929 930/* read and write from SEQUENCER indexed registers */ 931#define SEQW(A,B)(NV_REG16(NV16_SEQIND) = ((NVSEQX_##A) | ((B) << 8))) 932#define SEQR(A) (NV_REG8(NV8_SEQIND) = (NVSEQX_##A), NV_REG8(NV8_SEQDAT)) 933 934/* read and write from PCI GRAPHICS indexed registers */ 935#define GRPHW(A,B)(NV_REG16(NV16_GRPHIND) = ((NVGRPHX_##A) | ((B) << 8))) 936#define GRPHR(A) (NV_REG8(NV8_GRPHIND) = (NVGRPHX_##A), NV_REG8(NV8_GRPHDAT)) 937 938/* read and write from the acceleration engine registers */ 939#define ACCR(A) (NV_REG32(NVACC_##A)) 940#define ACCW(A,B) (NV_REG32(NVACC_##A)=B) 941