Searched refs:vclk_ecp_cntl (Results 1 - 2 of 2) sorted by relevance

/haiku/src/add-ons/accelerants/radeon/
H A Dmonitor_routing.c37 values->vclk_ecp_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL );
347 values->vclk_ecp_cntl &=
350 values->vclk_ecp_cntl |= RADEON_VCLK_SRC_BYTE_CLK;
351 values->vclk_ecp_cntl |= 0 << RADEON_VCLK_ECP_CNTL_BYTE_CLK_POST_DIV_SHIFT;
355 values->vclk_ecp_cntl |= RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb;
359 values->vclk_ecp_cntl &= ~RADEON_VCLK_SRC_SEL_MASK;
360 values->vclk_ecp_cntl |= RADEON_VCLK_SRC_PPLL_CLK;
363 values->vclk_ecp_cntl |= RADEON_PIXCLK_ALWAYS_ONb;
486 RADEON_VCLK_ECP_CNTL, values->vclk_ecp_cntl,
H A Dset_mode.h194 uint32 vclk_ecp_cntl; member in struct:__anon1242

Completed in 38 milliseconds