/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar9001/ |
H A D | ar9130_phy.c | 36 uint32_t pll; local 42 pll = 0x1450; 44 pll = 0x1458; 46 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
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H A D | ar9160_attach.c | 94 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); local 97 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 99 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 102 pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV); 104 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); 106 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); 108 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
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/haiku/src/add-ons/accelerants/radeon_hd/ |
H A D | pll.cpp | 10 #include "pll.h" 71 pll_limit_probe(pll_info* pll) argument 99 pll->referenceFreq 103 pll->pllOutMin 107 pll->pllOutMin 112 pll->pllOutMax 117 pll->lcdPllOutMin 121 if (pll->lcdPllOutMin == 0) 122 pll->lcdPllOutMin = pll 163 pll_ppll_ss_probe(pll_info* pll, uint32 ssID) argument 207 pll_asic_ss_probe(pll_info* pll, uint32 ssID) argument 345 pll_compute_post_divider(pll_info* pll) argument 393 pll_compute(pll_info* pll) argument 540 pll_setup_flags(pll_info* pll, uint8 crtcID) argument 595 pll_adjust(pll_info* pll, display_mode* mode, uint8 crtcID) argument 750 pll_info* pll = &gConnector[connectorIndex]->encoder.pll; local 1141 pll_info pll; local 1165 pll_info* pll = &gConnector[id]->encoder.pll; local 1185 pll_info* pll = &gConnector[id]->encoder.pll; local 1206 pll_info* pll = &gConnector[id]->encoder.pll; local 1250 pll_info* pll = &gConnector[connectorIndex]->encoder.pll; local [all...] |
H A D | pll.h | 30 /* pll flags */ 55 /* pll id */ 67 /* pll in/out limits */ 99 /* pixel clock to be used in pll calculations (kHz) */ 108 status_t pll_adjust(pll_info* pll, display_mode* mode, uint8 crtcID); 113 status_t pll_compute(pll_info* pll); 114 void pll_setup_flags(pll_info* pll, uint8 crtcID); 115 status_t pll_limit_probe(pll_info* pll); 116 status_t pll_ppll_ss_probe(pll_info* pll, uint32 ssID); 117 status_t pll_asic_ss_probe(pll_info* pll, uint3 [all...] |
H A D | display.h | 15 #include "pll.h" 24 void display_crtc_ss(pll_info* pll, int command);
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H A D | display.cpp | 998 display_crtc_ss(pll_info* pll, int command) argument 1004 if (pll->ssPercentage == 0) { 1008 if ((pll->ssType & ATOM_EXTERNAL_SS_MASK) != 0) { 1013 if (pll_usage_count(pll->id) > 1) { 1036 = pll->ssType & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 1037 switch (pll->id) { 1053 args.v3.usSpreadSpectrumAmount = B_HOST_TO_LENDIAN_INT16(pll->ssAmount); 1054 args.v3.usSpreadSpectrumStep = B_HOST_TO_LENDIAN_INT16(pll->ssStep); 1058 = B_HOST_TO_LENDIAN_INT16(pll->ssPercentage); 1060 = pll [all...] |
H A D | mode.cpp | 28 #include "pll.h" 218 pll_info* pll = &gConnector[connectorIndex]->encoder.pll; local 219 TRACE("%s: pll %d selected for connector %" B_PRIu32 "\n", __func__, 220 pll->id, connectorIndex); 485 pll_info* pll = &connector->encoder.pll; local 487 transmitter_dig_setup(connectorIndex, pll->pixelClock, 489 transmitter_dig_setup(connectorIndex, pll->pixelClock,
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H A D | encoder.cpp | 394 pll_info* pll = &gConnector[connectorIndex]->encoder.pll; local 396 // TODO: Should this be the adjusted pll or the original? 397 uint32 pixelClock = pll->pixelClock; 953 uint32 pixelClock = encoder->pll.pixelClock; 1333 pll_info* pll = &gConnector[connectorIndex]->encoder.pll; local 1527 args.v3.acConfig.ucRefClkSource = pll->id; 1599 args.v4.acConfig.ucRefClkSource = pll->id; 1678 args.v5.asConfig.ucPhyClkSrcId = pll 1997 pll_info* pll = &connector->encoder.pll; local [all...] |
H A D | gpu.h | 16 #include "pll.h" 184 status_t radeon_gpu_ss_control(pll_info* pll, bool enable);
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H A D | gpu.cpp | 19 #include "pll.h" 765 radeon_gpu_ss_control(pll_info* pll, bool enable) argument 773 switch (pll->id) { 796 switch (pll->id) {
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/haiku/src/add-ons/accelerants/radeon/ |
H A D | pll.c | 47 // pll - info about PLL 52 const pll_info *pll, uint32 freq, uint fixed_post_div, pll_dividers *dividers ) 96 pll->post_divs[max_post_div_idx].divider != 0; 103 pll->post_divs[min_post_div_idx].divider != fixed_post_div; 113 for( extra_post_div_idx = 0; pll->extra_post_divs[extra_post_div_idx].divider != 0; ++extra_post_div_idx ) { 117 pll->post_divs[post_div_idx].divider 118 * pll->extra_post_divs[extra_post_div_idx].divider; 127 if( vco < pll->vco_min || vco > pll->vco_max ) 134 for( ref_div = pll 51 Radeon_CalcPLLDividers( const pll_info *pll, uint32 freq, uint fixed_post_div, pll_dividers *dividers ) argument 210 Radeon_MatchCRTPLL( const pll_info *pll, uint32 tv_v_total, uint32 tv_h_total, uint32 tv_frame_size_adjust, uint32 freq, const display_mode *mode, uint32 max_v_tweak, uint32 max_h_tweak, uint32 max_frame_rate_drift, uint32 fixed_post_div, pll_dividers *dividers, display_mode *tweaked_mode ) argument 348 Radeon_GetTVPLLConfiguration( const general_pll_info *general_pll, pll_info *pll, bool internal_encoder ) argument 373 Radeon_GetTVCRTPLLConfiguration( const general_pll_info *general_pll, pll_info *pll, bool internal_tv_encoder ) argument 410 pll_info pll; local [all...] |
H A D | set_mode.h | 214 // pll.c 218 void Radeon_CalcPLLDividers( const pll_info *pll, uint32 freq, uint fixed_post_div, pll_dividers *dividers ); 220 const pll_info *pll, 226 void Radeon_GetTVPLLConfiguration( const general_pll_info *general_pll, pll_info *pll, 228 void Radeon_GetTVCRTPLLConfiguration( const general_pll_info *general_pll, pll_info *pll,
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H A D | ProposeDisplayMode.c | 145 general_pll_info *pll, display_mode *target, 349 if( target->timing.pixel_clock / 10 > pll->max_pll_freq || 350 target->timing.pixel_clock / 10 * 12 < pll->min_pll_freq ) 353 pll->max_pll_freq * 10, pll->min_pll_freq / 12 ); 491 &si->pll, dst, &low, &high ) == B_OK ) 502 &si->pll, dst, &low, &high ) == B_OK ) 670 &si->pll, target, low, high ); 678 &si->pll, target, low, high ); 144 Radeon_ProposeDisplayMode(shared_info *si, crtc_info *crtc, general_pll_info *pll, display_mode *target, const display_mode *low, const display_mode *high) argument
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H A D | GetModeInfo.c | 56 uint32 clock_limit = ai->si->pll.max_pll_freq * 10;
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/haiku/src/add-ons/accelerants/intel_extreme/ |
H A D | dpms.cpp | 92 uint32 pll = read32(INTEL_DISPLAY_A_PLL); local 93 if ((pll & DISPLAY_PLL_ENABLED) == 0) { 95 write32(INTEL_DISPLAY_A_PLL, pll); 98 write32(INTEL_DISPLAY_A_PLL, pll | DISPLAY_PLL_ENABLED); 101 write32(INTEL_DISPLAY_A_PLL, pll | DISPLAY_PLL_ENABLED); 106 pll = read32(INTEL_DISPLAY_B_PLL); 107 if ((pll & DISPLAY_PLL_ENABLED) == 0) { 109 write32(INTEL_DISPLAY_B_PLL, pll); 112 write32(INTEL_DISPLAY_B_PLL, pll | DISPLAY_PLL_ENABLED); 115 write32(INTEL_DISPLAY_B_PLL, pll | DISPLAY_PLL_ENABLE [all...] |
H A D | Pipes.cpp | 446 uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL | extraFlags; local 451 pll |= ((1 << (divisors.p1 - 1)) 455 pll |= ((1 << (divisors.p1 - 1)) 458 // pll |= ((divisors.p1 - 1) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) 464 pll |= ((1 << (divisors.p1 - 1)) 470 pll |= DISPLAY_PLL_DIVIDE_HIGH; 473 pll |= 6 << DISPLAY_PLL_PULSE_PHASE_SHIFT; 476 pll |= DISPLAY_PLL_DIVIDE_4X; 478 pll |= DISPLAY_PLL_2X_CLOCK; 482 pll | [all...] |
/haiku/src/add-ons/accelerants/ati/ |
H A D | rage128_mode.cpp | 146 R128_PLLParams& pll = si.r128PLLParams; local 150 int xClkFreq = pll.xclk; 152 int vClkFreq = DivideWithRounding(pll.reference_freq * params.feedback_div, 153 pll.reference_div * params.post_div); 215 R128_PLLParams& pll = gInfo.sharedInfo->r128PLLParams; local 218 if (freq > pll.max_pll_freq) 219 freq = pll.max_pll_freq; 220 if (freq * 12 < pll.min_pll_freq) 221 freq = pll.min_pll_freq / 12; 228 if (output_freq >= pll [all...] |
/haiku/src/add-ons/kernel/drivers/graphics/radeon/ |
H A D | bios.c | 122 PLL_BLOCK pll, *pll_info; local 150 di->pll.ref_div = 0; 151 di->pll.max_pll_freq = RADEON_BIOS16(pll_start + 32); 152 di->pll.xclk = RADEON_BIOS16(pll_start + 72); 153 di->pll.min_pll_freq = RADEON_BIOS16(pll_start + 78); 154 di->pll.ref_freq = RADEON_BIOS16(pll_start + 82); 159 di->pll.ref_freq, di->pll.ref_div, di->pll.xclk, 160 di->pll [all...] |
H A D | radeon_driver.h | 118 general_pll_info pll; member in struct:device_info
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H A D | init.c | 274 si->pll = di->pll;
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/haiku/src/add-ons/accelerants/matrox/engine/ |
H A D | tvp3026.c | 21 #define WAIT_FOR_PLL_LOCK( pll, on_error) do { \ 28 int status = DXIR (pll ## PLLDATA); \ 34 LOG(2,("mil2 %s PLL locked in %fms for %d loops\n", #pll, delay, tmo)); \ 36 LOG(8,("mil2 %s PLL not locked in %fms for %d loops\n", #pll, delay, tmo)); \
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/haiku/src/add-ons/kernel/drivers/graphics/ati/ |
H A D | driver.cpp | 489 R128_PLLParams& pll = si.r128PLLParams; local 490 pll.reference_freq = 2950; 491 pll.reference_div = 65; 492 pll.min_pll_freq = 12500; 493 pll.max_pll_freq = 25000; 494 pll.xclk = 10300; 534 pll.reference_freq = BIOS16(pllInfoBlock + 0x0e); 535 pll.reference_div = BIOS16(pllInfoBlock + 0x10); 536 pll.min_pll_freq = BIOS32(pllInfoBlock + 0x12); 537 pll [all...] |
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar9002/ |
H A D | ar9280_attach.c | 109 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); local 118 pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; 120 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 122 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 124 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 127 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 129 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 131 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); 133 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 135 pll | [all...] |
/haiku/src/add-ons/media/media-add-ons/radeon/ |
H A D | Tuner.cpp | 51 int pll; member in struct:__anon2575::__anon2576 224 kTunerTable[index].bands[band].pll |
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H A D | Radeon.cpp | 320 refFreq = fSharedInfo->pll.ref_freq; 321 refDiv = fSharedInfo->pll.ref_div; 322 minFreq = fSharedInfo->pll.min_pll_freq; 323 maxFreq = fSharedInfo->pll.max_pll_freq; 324 xclock = fSharedInfo->pll.xclk;
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