Searched refs:impactv_regs (Results 1 - 5 of 5) sorted by relevance
/haiku/src/add-ons/accelerants/radeon/ |
H A D | theatre_out.c | 21 // mapping of offset in impactv_regs to register address 24 uint16 offset; // offset in impactv_regs 32 { THEATRE_VIP_MASTER_CNTL, offsetof( impactv_regs, tv_master_cntl ) }, 33 { THEATRE_VIP_TVO_DATA_DELAY_A, offsetof( impactv_regs, tv_data_delay_a ) }, 34 { THEATRE_VIP_TVO_DATA_DELAY_B, offsetof( impactv_regs, tv_data_delay_b ) }, 36 { THEATRE_VIP_CLKOUT_CNTL, offsetof( impactv_regs, tv_clkout_cntl ) }, 37 { THEATRE_VIP_PLL_CNTL0, offsetof( impactv_regs, tv_pll_cntl1 ) }, 39 { THEATRE_VIP_HRESTART, offsetof( impactv_regs, tv_hrestart ) }, 40 { THEATRE_VIP_VRESTART, offsetof( impactv_regs, tv_vrestart ) }, 41 { THEATRE_VIP_FRESTART, offsetof( impactv_regs, tv_frestar [all...] |
H A D | internal_tv_out.c | 22 // mapping of offset in impactv_regs to register address 25 uint16 offset; // offset in impactv_regs 33 { RADEON_TV_MASTER_CNTL, offsetof( impactv_regs, tv_master_cntl ) }, 34 { RADEON_TV_HRESTART, offsetof( impactv_regs, tv_hrestart ) }, 35 { RADEON_TV_VRESTART, offsetof( impactv_regs, tv_vrestart ) }, 36 { RADEON_TV_FRESTART, offsetof( impactv_regs, tv_frestart ) }, 37 { RADEON_TV_FTOTAL, offsetof( impactv_regs, tv_ftotal ) }, 43 { RADEON_TV_PLL_CNTL, offsetof( impactv_regs, tv_tv_pll_cntl ) }, 44 { RADEON_TV_PLL_CNTL1, offsetof( impactv_regs, tv_pll_cntl1 ) }, 45 { RADEON_TV_PLL_FINE_CNTL, offsetof( impactv_regs, tv_pll_fine_cnt [all...] |
H A D | set_mode.h | 170 } impactv_regs; typedef in typeref:struct:__anon1241 268 impactv_params *params, impactv_regs *values, int crtc_idx, 271 accelerator_info *ai, impactv_write_FIFO write, impactv_regs *values, bool internal_encoder ); 273 accelerator_info *ai, impactv_write_FIFO write, impactv_regs *values ); 277 void Radeon_TheatreProgramTVRegisters( accelerator_info *ai, impactv_regs *values ); 278 void Radeon_TheatreReadTVRegisters( accelerator_info *ai, impactv_regs *values ); 283 void Radeon_InternalTVOutProgramRegisters( accelerator_info *ai, impactv_regs *values ); 284 void Radeon_InternalTVOutReadRegisters( accelerator_info *ai, impactv_regs *values );
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H A D | impactv.c | 418 impactv_params *params, impactv_regs *values, int crtc_idx, 742 impactv_regs *values, bool internal_encoder ) 764 impactv_regs *values ) 789 accelerator_info *ai, impactv_write_FIFO write, impactv_regs *values, bool internal_encoder ) 810 accelerator_info *ai, impactv_write_FIFO write, impactv_regs *values )
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H A D | SetDisplayMode.c | 120 impactv_regs impactv_values;
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