Searched refs:fp2_gen_cntl (Results 1 - 3 of 3) sorted by relevance

/haiku/src/add-ons/accelerants/radeon/
H A Dflat_panel.c123 values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL );
169 values->fp2_gen_cntl &= (0xFFFF0000);
232 values->fp2_gen_cntl |= RADEON_FP2_FPON | RADEON_FP_PANEL_FORMAT;
233 values->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
236 //values->fp2_gen_cntl |= (1 << 22) | (1 << 28);
239 values->fp2_gen_cntl |= RADEON_FP2_DV0_EN;
242 SHOW_FLOW( 2, "after: fp_gen_cntl=%08lx, fp2_gen_cntl=%08lx, horz=%08lx, vert=%08lx, lvds_gen_cntl=%08lx",
243 values->fp_gen_cntl, values->fp2_gen_cntl, values->fp_horz_stretch, values->fp_vert_stretch,
262 OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
264 OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
[all...]
H A Dmonitor_routing.c75 values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL );
406 values->fp2_gen_cntl &= ~RADEON_FP2_SOURCE_SEL_CRTC2;
407 values->fp2_gen_cntl |=
412 values->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
413 values->fp2_gen_cntl |=
481 OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
H A Dset_mode.h106 uint32 fp2_gen_cntl; member in struct:__anon1240
202 uint32 fp2_gen_cntl; member in struct:__anon1242

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