Searched refs:crtc (Results 1 - 25 of 37) sorted by relevance

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/haiku/src/add-ons/accelerants/intel_810/
H A Di810_mode.cpp110 uint8 crtc[25]; local
111 crtc[0x00] = hTotal;
112 crtc[0x01] = hDisp_e;
113 crtc[0x02] = hBlank_s;
114 crtc[0x03] = (hBlank_e & 0x1f) | 0x80;
115 crtc[0x04] = hSync_s;
116 crtc[0x05] = ((hSync_e & 0x1f) | ((hBlank_e & 0x20) << 2));
117 crtc[0x06] = vTotal;
118 crtc[0x07] = (((vTotal & 0x100) >> 8)
127 crtc[
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/haiku/src/add-ons/accelerants/3dfx/
H A D3dfx_mode.cpp213 // Argument crtc will contain registers cr00 to cr18; thus, it must
238 uint8 crtc[25]; local
240 crtc[0x00] = hTotal;
241 crtc[0x01] = hDisp_e;
242 crtc[0x02] = hBlank_s;
243 crtc[0x03] = (hBlank_e & 0x1f) | 0x80;
244 crtc[0x04] = hSync_s;
245 crtc[0x05] = ((hSync_e & 0x1f) | ((hBlank_e & 0x20) << 2));
246 crtc[0x06] = vTotal;
247 crtc[
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/haiku/src/add-ons/accelerants/s3/
H A Dmode.cpp17 InitCrtcTimingValues(const DisplayModeEx& mode, int horzScaleFactor, uint8 crtc[], argument
22 // is a hexadecimal number. Argument crtc will contain registers cr00 to
45 crtc[0x00] = hTotal;
46 crtc[0x01] = hDisp_e;
47 crtc[0x02] = hBlank_s;
48 crtc[0x03] = (hBlank_e & 0x1f) | 0x80;
49 crtc[0x04] = hSync_s;
50 crtc[0x05] = ((hSync_e & 0x1f) | ((hBlank_e & 0x20) << 2));
51 crtc[0x06] = vTotal;
52 crtc[
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H A Dtrio64_mode.cpp174 uint8 crtc[25], cr3b, cr3c, cr5d, cr5e; local
176 InitCrtcTimingValues(mode, (mode.bpp > 8) ? 2 : 1, crtc, cr3b, cr3c, cr5d, cr5e);
177 crtc[0x17] = 0xe3;
181 for (int k = 0; k < (int)B_COUNT_OF(crtc); k++) {
182 WriteCrtcReg(k, crtc[k]);
H A Daccel.h166 void InitCrtcTimingValues(const DisplayModeEx& mode, int horzScaleFactor, uint8 crtc[],
/haiku/src/add-ons/kernel/drivers/graphics/radeon/
H A Dirq.c36 && si->crtc[0].vblank >= 0) {
41 if (get_sem_count(si->crtc[0].vblank, &blocked ) == B_OK && blocked < 0) {
42 release_sem_etc(si->crtc[0].vblank, -blocked, B_DO_NOT_RESCHEDULE);
48 && si->crtc[1].vblank >= 0) {
53 if (get_sem_count(si->crtc[1].vblank, &blocked) == B_OK && blocked < 0) {
54 release_sem_etc(si->crtc[1].vblank, -blocked, B_DO_NOT_RESCHEDULE);
212 si->crtc[0].vblank = create_sem(0, buffer);
213 if (si->crtc[0].vblank < 0) {
214 result = si->crtc[0].vblank;
218 si->crtc[
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H A Dbios.c301 int crtc = 0, id[2]; local
306 if (crtc < 2) {
309 if ( crtc == 1 ) {
323 id[crtc] = (portinfo>>8) & 0xf;
324 ptr_entity->port_info[crtc].dac_type = (portinfo & 0xf) - 1;
325 ptr_entity->port_info[crtc].connector_type = (portinfo>>4) & 0xf;
327 ptr_entity->port_info[crtc].tmds_type = tmds_int;
329 ptr_entity->port_info[crtc].tmds_type = tmds_ext;
332 if( tmp0 && id[crtc] ) {
333 switch (RADEON_BIOS16(tmp0 + 4 + 27 * id[crtc]) *
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H A Dinit.c265 si->crtc[0].crtc_idx = 0;
266 si->crtc[0].flatpanel_port = 0;
267 si->crtc[1].crtc_idx = 1;
268 si->crtc[1].flatpanel_port = 1;
/haiku/src/add-ons/accelerants/radeon/
H A DCursor.c154 crtc_info *crtc = &ai->si->crtc[crtc_idx]; local
159 x -= crtc->rel_x;
160 y -= crtc->rel_y;
167 prev_state = crtc->cursor_on_screen;
168 crtc->cursor_on_screen = true;
172 if( y > crtc->mode.timing.v_display ||
173 x > crtc->mode.timing.h_display ||
176 crtc->cursor_on_screen = false;
179 if( prev_state != crtc
223 crtc_info *crtc = &ai->si->crtc[crtc_idx]; local
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H A Dcrtc.c55 uint16 Radeon_GetHSyncFudge( crtc_info *crtc, int datatype ) argument
61 if( (crtc->chosen_displays & (dd_dvi | dd_dvi_ext | dd_lvds )) != 0 )
69 void Radeon_CalcCRTCRegisters( accelerator_info *ai, crtc_info *crtc, argument
78 hsync_fudge = Radeon_GetHSyncFudge( crtc, vc->datatype );
80 if( crtc->crtc_idx == 0 ) {
131 static void moveOneDisplay( accelerator_info *ai, crtc_info *crtc )
136 offset = (vc->mode.v_display_start + crtc->rel_y) * vc->pitch +
137 (vc->mode.h_display_start + crtc->rel_x) * vc->bpp +
141 offset, crtc->crtc_idx );
143 OUTREG( ai->regs, crtc
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H A Dmultimon.c58 int num_usable_crtcs = vc->assigned_crtc[0] && si->crtc[0].chosen_displays != dd_none;
61 num_usable_crtcs += vc->assigned_crtc[1] && si->crtc[1].chosen_displays != dd_none;
99 si->crtc[0].rel_x = 0;
100 si->crtc[0].rel_y = 0;
104 si->crtc[1].rel_x = 0;
105 si->crtc[1].rel_y = 0;
126 si->crtc[1].rel_x = x;
127 si->crtc[1].rel_y = y;
129 si->crtc[0].rel_x = x;
130 si->crtc[
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H A DSetDisplayMode.c40 accelerator_info *ai, crtc_info *crtc, display_mode *mode, impactv_params *tv_params );
107 accelerator_info *ai, crtc_info *crtc, display_mode *mode, impactv_params *tv_params )
126 crtc->mode = *mode;
129 mode = &crtc->mode;
131 disp_devices = crtc->chosen_displays;
132 fp_info = &si->flatpanels[crtc->flatpanel_port];
205 if( crtc->crtc_idx == 0 )
222 Radeon_CalcCRTCRegisters( ai, crtc, mode, &crtc_values );
228 crtc->crtc_idx, internal_tv_encoder, vc->tv_standard, disp_devices );
246 if( crtc
106 Radeon_SetMode( accelerator_info *ai, crtc_info *crtc, display_mode *mode, impactv_params *tv_params ) argument
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H A Ddpms.c293 crtc_info *crtc = &ai->si->crtc[crtc_idx]; local
317 if( crtc_idx == 0 || 1/* && (crtc->active_displays & dd_crt) != 0 */)
320 if( crtc_idx == 1 || (crtc->active_displays & (dd_tv_crt | dd_ctv | dd_stv)) != 0 )
324 if( (crtc->active_displays & (dd_ctv | dd_stv)) != 0 )
327 if( (crtc->active_displays & dd_lvds) != 0 )
330 if( (crtc->active_displays & dd_dvi) != 0 )
333 if( (crtc->active_displays & dd_dvi_ext) != 0 )
H A Doverlay.c96 if( si->crtc[crtc_idx].mode.timing.pixel_clock < 175000 )
537 crtc_info *crtc = &si->crtc[crtc_idx]; local
568 if( crtc->mode.timing.pixel_clock < 175000 )
616 dest_left -= vc->mode.h_display_start + crtc->rel_x;
617 dest_top -= vc->mode.v_display_start + crtc->rel_y;
618 dest_right -= vc->mode.h_display_start + crtc->rel_x;
619 dest_bottom -= vc->mode.v_display_start + crtc->rel_y;
632 crtc->mode.timing.h_display, crtc
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H A Dset_mode.h206 // crtc.c
207 uint16 Radeon_GetHSyncFudge( crtc_info *crtc, int datatype );
208 void Radeon_CalcCRTCRegisters( accelerator_info *ai, crtc_info *crtc,
238 void Radeon_CalcFPRegisters( accelerator_info *ai, crtc_info *crtc,
240 void Radeon_ProgramFPRegisters( accelerator_info *ai, crtc_info *crtc,
H A Dflat_panel.c145 // calculcate flat panel crtc registers;
148 accelerator_info *ai, crtc_info *crtc,
216 if( (crtc->chosen_displays & dd_lvds) != 0 ) {
250 accelerator_info *ai, crtc_info *crtc,
287 if( (crtc->chosen_displays & dd_lvds) != 0 ) {
147 Radeon_CalcFPRegisters( accelerator_info *ai, crtc_info *crtc, fp_info *fp_port, crtc_regs *crtc_values, fp_regs *values ) argument
249 Radeon_ProgramFPRegisters( accelerator_info *ai, crtc_info *crtc, fp_info *fp_port, fp_regs *values ) argument
H A DProposeDisplayMode.c144 Radeon_ProposeDisplayMode(shared_info *si, crtc_info *crtc, argument
155 fp_info *flatpanel = &si->flatpanels[crtc->flatpanel_port];
157 SHOW_FLOW( 4, "CRTC %d, DVI %d", (crtc == &si->crtc[0]) ? 0 : 1, crtc->flatpanel_port );
179 if( (crtc->chosen_displays & (dd_lvds | dd_dvi)) != 0 ) {
191 if( (crtc->chosen_displays & dd_dvi_ext) != 0 ) {
214 h_sync_fudge = Radeon_GetHSyncFudge( crtc, format );
490 if( Radeon_ProposeDisplayMode( si, &si->crtc[0],
501 if( Radeon_ProposeDisplayMode( si, &si->crtc[
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H A Dmonitor_routing.c86 display_devices[0] = ai->si->crtc[0].chosen_displays;
91 display_devices[1] = ai->si->crtc[1].chosen_displays;
671 &si->crtc[0].chosen_displays, &si->crtc[1].chosen_displays );
673 /* si->crtc[0].chosen_displays = dd_none;
674 si->crtc[1].chosen_displays = dd_tv_crt;*/
676 /*vc->used_crtc[0] = si->crtc[0].chosen_displays != dd_none;
677 vc->used_crtc[1] = si->crtc[1].chosen_displays != dd_none;*/
681 vc->assigned_crtc[0] ? "assigned" : "not assigned", si->crtc[0].chosen_displays,
682 vc->assigned_crtc[0] ? "assigned" : "not assigned", si->crtc[
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H A DGetModeInfo.c153 return ai->si->crtc[crtcIndex].vblank;
/haiku/src/add-ons/accelerants/radeon_hd/
H A Dmode.cpp95 uint8_t crtc = 0; local
97 if (gDisplay[crtc]->preferredMode.virtual_width > 0
98 && gDisplay[crtc]->preferredMode.virtual_height > 0) {
100 __func__, crtc);
101 memcpy(preferredMode, &gDisplay[crtc]->preferredMode,
102 sizeof(gDisplay[crtc]->preferredMode));
207 // *** crtc and encoder prep
212 // *** Set up encoder -> crtc routing
/haiku/headers/private/graphics/nvidia/
H A DDriverInterface.h436 bool crtc; /* location of overlay unit */ member in struct:__anon21::__anon29
459 bool crtc; /* adressed CRTC */ member in struct:__anon31
/haiku/src/add-ons/accelerants/skeleton/engine/
H A Dbes.c67 if (si->overlay.crtc)
352 status_t eng_bes_to_crtc(bool crtc) argument
356 if (crtc)
362 si->overlay.crtc = !si->crtc_switch_mode;
370 si->overlay.crtc = si->crtc_switch_mode;
/haiku/src/add-ons/accelerants/nvidia/engine/
H A Dnv_bes.c67 if (si->overlay.crtc)
352 status_t nv_bes_to_crtc(bool crtc) argument
356 if (crtc)
362 si->overlay.crtc = !si->crtc_switch_mode;
370 si->overlay.crtc = si->crtc_switch_mode;
/haiku/src/add-ons/accelerants/via/engine/
H A Dbes.c142 if (si->overlay.crtc)
475 status_t eng_bes_to_crtc(bool crtc) argument
479 if (crtc)
485 si->overlay.crtc = !si->crtc_switch_mode;
493 si->overlay.crtc = si->crtc_switch_mode;
/haiku/headers/private/graphics/skeleton/
H A DDriverInterface.h296 bool crtc; /* location of overlay unit */ member in struct:__anon937::__anon944

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