Searched refs:adress (Results 1 - 20 of 20) sorted by relevance

/haiku/src/add-ons/accelerants/skeleton/engine/
H A Dinfo.c38 static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab);
39 static status_t exec_type2_script(uint8* rom, uint16 adress, int16* size, PinsTables tabs, uint16 ram_tab);
40 static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, PinsTables tabs, uint16 ram_tab, bool* exec);
72 /* find the PINS struct adress */
304 uint16 adress; local
359 adress = *((uint16*)(&(rom[index])));
360 if (!adress)
366 while (adress && (result == B_OK))
368 result = exec_type2_script(rom, adress, &size, tabs, ram_tab);
371 adress
410 exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab) argument
910 exec_type2_script(uint8* rom, uint16 adress, int16* size, PinsTables tabs, uint16 ram_tab) argument
923 exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, PinsTables tabs, uint16 ram_tab, bool* exec) argument
[all...]
/haiku/src/add-ons/accelerants/nvidia/engine/
H A Dnv_info.c38 static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab);
39 static status_t exec_type2_script(uint8* rom, uint16 adress, int16* size, PinsTables tabs, uint16 ram_tab);
40 static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, PinsTables tabs, uint16 ram_tab, bool* exec);
72 /* find the PINS struct adress */
316 uint16 adress; local
371 adress = *((uint16*)(&(rom[index])));
372 if (!adress)
378 while (adress && (result == B_OK))
380 result = exec_type2_script(rom, adress, &size, tabs, ram_tab);
383 adress
422 exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab) argument
997 exec_type2_script(uint8* rom, uint16 adress, int16* size, PinsTables tabs, uint16 ram_tab) argument
1010 exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, PinsTables tabs, uint16 ram_tab, bool* exec) argument
[all...]
H A Dnv_brooktreetv.c113 buffer[0] = si->ps.tv_encoder.adress + WR;
132 see if a (possible) BT/CX chip resides at the given adress.
135 static uint8 BT_check (uint8 bus, uint8 adress) argument
139 buffer[0] = adress + WR;
143 * after writing adress $A0 (setting EN_XCLK)!!!
169 buffer[0] = si->ps.tv_encoder.adress + WR;
188 i2c_writebyte(si->ps.tv_encoder.bus, si->ps.tv_encoder.adress + RD);
227 /* try primary adress on bus */
231 si->ps.tv_encoder.adress = PRADR;
236 /* try secondary adress o
[all...]
/haiku/src/add-ons/accelerants/neomagic/
H A DOverlay.c71 uint32 adress, adress2, temp32; /* used to calculate buffer adresses */ local
177 /* calculate first free RAM adress in card:
184 LOG(4,("Overlay: first free cardRAM virtual adress $%08x\n", adress2));
191 /* calculate virtual memory adress that would be needed for a new bitmap */
192 adress = (((uint32)((uint8*)si->framebuffer)) + (si->ps.memory_size * 1024));
194 if(si->settings.hardcursor) adress -= si->ps.curmem_size;
195 LOG(4,("Overlay: last free cardRAM virtual adress $%08x\n", (adress - 1)));
198 adress -= si->overlay.myBufInfo[cnt].size;
204 /* Check if we need to modify the buffers starting adress an
[all...]
/haiku/src/add-ons/accelerants/via/
H A DOverlay.c73 uintptr_t adress, adress2, temp32; /* used to calculate buffer adresses */ local
172 /* calculate first free RAM adress in card:
178 LOG(4,("Overlay: first free cardRAM virtual adress $%08x\n", adress2));
185 /* calculate virtual memory adress that would be needed for a new bitmap */
196 adress = (((uintptr_t)((uint8*)si->framebuffer)) + si->ps.memory_size);
199 adress -= si->overlay.myBufInfo[cnt].size;
205 /* Check if we need to modify the buffers starting adress and thus the size */
207 temp32 = (adress - ((uintptr_t)((vuint32 *)si->framebuffer)));
213 /* update the (already calculated) adress to get it aligned */
214 adress
[all...]
/haiku/src/add-ons/accelerants/nvidia/
H A DOverlay.c76 uintptr_t adress, adress2, temp32; /* used to calculate buffer adresses */ local
207 /* calculate first free RAM adress in card:
213 LOG(4, ("Overlay: first free cardRAM virtual adress $%08x\n", adress2));
220 /* calculate virtual memory adress that would be needed for a new bitmap */
231 adress = (((uintptr_t)((uint8*)si->framebuffer)) + si->ps.memory_size);
235 adress -= PRE_NV40_OFFSET;
237 adress -= NV40_PLUS_OFFSET;
241 adress -= si->overlay.myBufInfo[cnt].size;
247 /* Check if we need to modify the buffers starting adress and thus the size */
249 temp32 = (adress
[all...]
/haiku/src/add-ons/accelerants/skeleton/
H A DOverlay.c74 uint32 adress, adress2, temp32; /* used to calculate buffer adresses */ local
183 /* calculate first free RAM adress in card:
189 LOG(4,("Overlay: first free cardRAM virtual adress $%08x\n", adress2));
196 /* calculate virtual memory adress that would be needed for a new bitmap */
207 adress = (((uint32)((uint8*)si->framebuffer)) + si->ps.memory_size);
210 adress -= si->overlay.myBufInfo[cnt].size;
216 /* Check if we need to modify the buffers starting adress and thus the size */
218 temp32 = (adress - ((uint32)((vuint32 *)si->framebuffer)));
224 /* update the (already calculated) adress to get it aligned */
225 adress
[all...]
/haiku/src/add-ons/accelerants/matrox/
H A DOverlay.c82 uintptr_t adress, adress2, temp32; /* used to calculate buffer adresses */ local
245 /* calculate first free RAM adress in card:
251 LOG(4, ("Overlay: first free cardRAM virtual adress $%08x\n", adress2));
258 /* calculate virtual memory adress that would be needed for a new bitmap */
269 adress = (((uintptr_t)((uint8*)si->framebuffer)) + (si->ps.memory_size * 1024 * 1024));
272 adress -= si->overlay.myBufInfo[cnt].size;
278 /* Check if we need to modify the buffers starting adress and thus the size */
280 temp32 = (adress - ((uintptr_t)((vuint32 *)si->framebuffer)));
286 /* update the (already calculated) adress to get it aligned */
287 adress
[all...]
/haiku/headers/private/graphics/neomagic/
H A Dnm_macros.h323 #define ISAWB(A,B)(nm_isa_access.adress=NMISA8_##A, nm_isa_access.data = (uint8)B, nm_isa_access.size = 1, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access)))
324 #define ISAWW(A,B)(nm_isa_access.adress=NMISA16_##A, nm_isa_access.data = B, nm_isa_access.size = 2, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access)))
325 #define ISARB(A) (nm_isa_access.adress=NMISA8_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), (uint8)nm_isa_access.data)
326 #define ISARW(A) (nm_isa_access.adress=NMISA16_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), nm_isa_access.data)
H A DDriverInterface.h245 uint16 adress; /* Offset to read/write */ member in struct:__anon806
/haiku/headers/private/graphics/nvidia/
H A DDriverInterface.h344 uint32 put; /* last 32-bit-word adress given to engine to exec. to */
345 uint32 current; /* first free 32-bit-word adress in buffer */
355 uint32 mem_low; /* ptr to first free mem adress: cardmem local offset */
356 uint32 mem_high; /* ptr to last free mem adress: cardmem local offset */
388 uint8 adress; /* I2C adress on which TVout chip resides */ member in struct:__anon21::__anon27::__anon28
496 uint16 adress; /* Offset to read/write */ member in struct:__anon36
H A Dnv_macros.h897 #define ISAWB(A,B)(nv_isa_access.adress=A, nv_isa_access.data = (uint8)B, nv_isa_access.size = 1, ioctl(fd,NV_ISA_OUT, &nv_isa_access,sizeof(nv_isa_access)))
898 #define ISAWW(A,B)(nv_isa_access.adress=A, nv_isa_access.data = B, nv_isa_access.size = 2, ioctl(fd,NV_ISA_OUT, &nv_isa_access,sizeof(nv_isa_access)))
899 #define ISARB(A) (nv_isa_access.adress=A, ioctl(fd,NV_ISA_IN, &nv_isa_access,sizeof(nv_isa_access)), (uint8)nv_isa_access.data)
900 #define ISARW(A) (nv_isa_access.adress=A, ioctl(fd,NV_ISA_IN, &nv_isa_access,sizeof(nv_isa_access)), nv_isa_access.data)
/haiku/headers/private/graphics/skeleton/
H A DDriverInterface.h355 uint16 adress; /* Offset to read/write */ member in struct:__anon951
H A Dmacros.h750 #define ISAWB(A,B)(eng_isa_access.adress=A, eng_isa_access.data = (uint8)B, eng_isa_access.size = 1, ioctl(fd,ENG_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access)))
751 #define ISAWW(A,B)(eng_isa_access.adress=A, eng_isa_access.data = B, eng_isa_access.size = 2, ioctl(fd,ENG_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access)))
752 #define ISARB(A) (eng_isa_access.adress=A, ioctl(fd,ENG_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), (uint8)eng_isa_access.data)
753 #define ISARW(A) (eng_isa_access.adress=A, ioctl(fd,ENG_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), eng_isa_access.data)
/haiku/headers/private/graphics/via/
H A Dmacros.h813 #define ISAWB(A,B)(eng_isa_access.adress=A, eng_isa_access.data = (uint8)B, eng_isa_access.size = 1, ioctl(fd,ENG_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access)))
814 #define ISAWW(A,B)(eng_isa_access.adress=A, eng_isa_access.data = B, eng_isa_access.size = 2, ioctl(fd,ENG_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access)))
815 #define ISARB(A) (eng_isa_access.adress=A, ioctl(fd,ENG_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), (uint8)eng_isa_access.data)
816 #define ISARW(A) (eng_isa_access.adress=A, ioctl(fd,ENG_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), eng_isa_access.data)
H A DDriverInterface.h366 uint16 adress; /* Offset to read/write */ member in struct:__anon18
/haiku/src/add-ons/kernel/drivers/graphics/neomagic/
H A Ddriver.c419 /* get ROM memory mapped base adress - this is defined in the PCI standard */
423 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */
449 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */
934 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data);
936 isa_bus->write_io_16(io_isa->adress, io_isa->data);
944 io_isa->data = isa_bus->read_io_8(io_isa->adress);
946 io_isa->data = isa_bus->read_io_16(io_isa->adress);
/haiku/src/add-ons/kernel/drivers/graphics/via/
H A Ddriver.c411 /* get ROM memory mapped base adress - this is defined in the PCI standard */
415 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */
441 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */
930 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data);
932 isa_bus->write_io_16(io_isa->adress, io_isa->data);
959 io_isa->data = isa_bus->read_io_8(io_isa->adress);
961 io_isa->data = isa_bus->read_io_16(io_isa->adress);
/haiku/src/add-ons/kernel/drivers/graphics/skeleton/
H A Ddriver.c402 /* get ROM memory mapped base adress - this is defined in the PCI standard */
406 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */
432 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */
942 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data);
944 isa_bus->write_io_16(io_isa->adress, io_isa->data);
971 io_isa->data = isa_bus->read_io_8(io_isa->adress);
973 io_isa->data = isa_bus->read_io_16(io_isa->adress);
/haiku/src/add-ons/kernel/drivers/graphics/nvidia/
H A Ddriver.c603 /* get ROM memory mapped base adress - this is defined in the PCI standard */
610 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */
639 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */
715 * don't attempt to adress more later on */
953 /* we (also) need the physical adress our DMA buffer is at, as this needs to be
954 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC
1009 /* don't attempt to adress memory not mapped by the kerneldriver */
1018 /* don't attempt to adress memory not mapped by the kerneldriver */
1332 isa_bus->write_io_8(io_isa.adress, (uint8)io_isa.data);
1334 isa_bus->write_io_16(io_isa.adress, io_is
[all...]

Completed in 689 milliseconds